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teensy-cores/teensy3/core_pins.h

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原始文件 Blame 歷史記錄 

  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be 

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows 

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _core_pins_h_

  32. #define _core_pins_h_

  33. 

  34. #include "mk20dx128.h"

  35. #include "pins_arduino.h"

  36. 

  37. 

  38. #define HIGH		1

  39. #define LOW		0

  40. #define INPUT		0

  41. #define OUTPUT		1

  42. #define INPUT_PULLUP	2

  43. #define LSBFIRST	0

  44. #define MSBFIRST	1

  45. #define _BV(n)		(1<<(n))

  46. #define CHANGE		4

  47. #define FALLING		2

  48. #define RISING		3

  49. 

  50. // Pin				Arduino

  51. //  0	B16			RXD

  52. //  1	B17			TXD

  53. //  2	D0			

  54. //  3	A12	FTM1_CH0	

  55. //  4	A13	FTM1_CH1	

  56. //  5	D7	FTM0_CH7	OC0B/T1

  57. //  6	D4	FTM0_CH4	OC0A

  58. //  7	D2			

  59. //  8	D3			ICP1

  60. //  9	C3	FTM0_CH2	OC1A

  61. // 10	C4	FTM0_CH3	SS/OC1B

  62. // 11	C6			MOSI/OC2A

  63. // 12	C7			MISO

  64. // 13	C5			SCK	

  65. // 14	D1			

  66. // 15	C0			

  67. // 16	B0	(FTM1_CH0)	

  68. // 17	B1	(FTM1_CH1)	

  69. // 18	B3			SDA

  70. // 19	B2			SCL

  71. // 20	D5	FTM0_CH5	

  72. // 21	D6	FTM0_CH6	

  73. // 22	C1	FTM0_CH0	

  74. // 23	C2	FTM0_CH1	

  75. // 24	A5	(FTM0_CH2)	

  76. // 25	B19

  77. // 26	E1

  78. // 27	C9

  79. // 28	C8

  80. // 29	C10

  81. // 30	C11

  82. // 31	E0

  83. // 32	B18

  84. // 33	A4	(FTM0_CH1)

  85. // (34)	analog only

  86. // (35)	analog only

  87. // (36)	analog only

  88. // (37)	analog only

  89. 

  90. // not available to user:

  91. //	A0	FTM0_CH5	SWD Clock

  92. //	A1	FTM0_CH6	USB ID

  93. //	A2	FTM0_CH7	SWD Trace

  94. //	A3	FTM0_CH0	SWD Data

  95. 

  96. #define CORE_NUM_TOTAL_PINS     34

  97. #define CORE_NUM_DIGITAL        34

  98. #define CORE_NUM_ANALOG         14

  99. #define CORE_NUM_PWM            10

  100. #define CORE_NUM_INTERRUPT      34

  101. 

  102. #define CORE_PIN0_BIT		16

  103. #define CORE_PIN1_BIT		17

  104. #define CORE_PIN2_BIT		0

  105. #define CORE_PIN3_BIT		12

  106. #define CORE_PIN4_BIT		13

  107. #define CORE_PIN5_BIT		7

  108. #define CORE_PIN6_BIT		4

  109. #define CORE_PIN7_BIT		2

  110. #define CORE_PIN8_BIT		3

  111. #define CORE_PIN9_BIT		3

  112. #define CORE_PIN10_BIT		4

  113. #define CORE_PIN11_BIT		6

  114. #define CORE_PIN12_BIT		7

  115. #define CORE_PIN13_BIT		5

  116. #define CORE_PIN14_BIT		1

  117. #define CORE_PIN15_BIT		0

  118. #define CORE_PIN16_BIT		0

  119. #define CORE_PIN17_BIT		1

  120. #define CORE_PIN18_BIT		3

  121. #define CORE_PIN19_BIT		2

  122. #define CORE_PIN20_BIT		5

  123. #define CORE_PIN21_BIT		6

  124. #define CORE_PIN22_BIT		1

  125. #define CORE_PIN23_BIT		2

  126. #define CORE_PIN24_BIT		5

  127. #define CORE_PIN25_BIT		19

  128. #define CORE_PIN26_BIT		1

  129. #define CORE_PIN27_BIT		9

  130. #define CORE_PIN28_BIT		8

  131. #define CORE_PIN29_BIT		10

  132. #define CORE_PIN30_BIT		11

  133. #define CORE_PIN31_BIT		0

  134. #define CORE_PIN32_BIT		18

  135. #define CORE_PIN33_BIT		4

  136. 

  137. #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))

  138. #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))

  139. #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))

  140. #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))

  141. #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))

  142. #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))

  143. #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))

  144. #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))

  145. #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))

  146. #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))

  147. #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))

  148. #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))

  149. #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))

  150. #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))

  151. #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))

  152. #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))

  153. #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))

  154. #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))

  155. #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))

  156. #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))

  157. #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))

  158. #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))

  159. #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))

  160. #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))

  161. #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))

  162. #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))

  163. #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))

  164. #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))

  165. #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))

  166. #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))

  167. #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))

  168. #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))

  169. #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))

  170. #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))

  171. 

  172. #define CORE_PIN0_PORTREG	GPIOB_PDOR

  173. #define CORE_PIN1_PORTREG	GPIOB_PDOR

  174. #define CORE_PIN2_PORTREG	GPIOD_PDOR

  175. #define CORE_PIN3_PORTREG	GPIOA_PDOR

  176. #define CORE_PIN4_PORTREG	GPIOA_PDOR

  177. #define CORE_PIN5_PORTREG	GPIOD_PDOR

  178. #define CORE_PIN6_PORTREG	GPIOD_PDOR

  179. #define CORE_PIN7_PORTREG	GPIOD_PDOR

  180. #define CORE_PIN8_PORTREG	GPIOD_PDOR

  181. #define CORE_PIN9_PORTREG	GPIOC_PDOR

  182. #define CORE_PIN10_PORTREG	GPIOC_PDOR

  183. #define CORE_PIN11_PORTREG	GPIOC_PDOR

  184. #define CORE_PIN12_PORTREG	GPIOC_PDOR

  185. #define CORE_PIN13_PORTREG	GPIOC_PDOR

  186. #define CORE_PIN14_PORTREG	GPIOD_PDOR

  187. #define CORE_PIN15_PORTREG	GPIOC_PDOR

  188. #define CORE_PIN16_PORTREG	GPIOB_PDOR

  189. #define CORE_PIN17_PORTREG	GPIOB_PDOR

  190. #define CORE_PIN18_PORTREG	GPIOB_PDOR

  191. #define CORE_PIN19_PORTREG	GPIOB_PDOR

  192. #define CORE_PIN20_PORTREG	GPIOD_PDOR

  193. #define CORE_PIN21_PORTREG	GPIOD_PDOR

  194. #define CORE_PIN22_PORTREG	GPIOC_PDOR

  195. #define CORE_PIN23_PORTREG	GPIOC_PDOR

  196. #define CORE_PIN24_PORTREG	GPIOA_PDOR

  197. #define CORE_PIN25_PORTREG	GPIOB_PDOR

  198. #define CORE_PIN26_PORTREG	GPIOE_PDOR

  199. #define CORE_PIN27_PORTREG	GPIOC_PDOR

  200. #define CORE_PIN28_PORTREG	GPIOC_PDOR

  201. #define CORE_PIN29_PORTREG	GPIOC_PDOR

  202. #define CORE_PIN30_PORTREG	GPIOC_PDOR

  203. #define CORE_PIN31_PORTREG	GPIOE_PDOR

  204. #define CORE_PIN32_PORTREG	GPIOB_PDOR

  205. #define CORE_PIN33_PORTREG	GPIOA_PDOR

  206. 

  207. #define CORE_PIN0_PORTSET	GPIOB_PSOR

  208. #define CORE_PIN1_PORTSET	GPIOB_PSOR

  209. #define CORE_PIN2_PORTSET	GPIOD_PSOR

  210. #define CORE_PIN3_PORTSET	GPIOA_PSOR

  211. #define CORE_PIN4_PORTSET	GPIOA_PSOR

  212. #define CORE_PIN5_PORTSET	GPIOD_PSOR

  213. #define CORE_PIN6_PORTSET	GPIOD_PSOR

  214. #define CORE_PIN7_PORTSET	GPIOD_PSOR

  215. #define CORE_PIN8_PORTSET	GPIOD_PSOR

  216. #define CORE_PIN9_PORTSET	GPIOC_PSOR

  217. #define CORE_PIN10_PORTSET	GPIOC_PSOR

  218. #define CORE_PIN11_PORTSET	GPIOC_PSOR

  219. #define CORE_PIN12_PORTSET	GPIOC_PSOR

  220. #define CORE_PIN13_PORTSET	GPIOC_PSOR

  221. #define CORE_PIN14_PORTSET	GPIOD_PSOR

  222. #define CORE_PIN15_PORTSET	GPIOC_PSOR

  223. #define CORE_PIN16_PORTSET	GPIOB_PSOR

  224. #define CORE_PIN17_PORTSET	GPIOB_PSOR

  225. #define CORE_PIN18_PORTSET	GPIOB_PSOR

  226. #define CORE_PIN19_PORTSET	GPIOB_PSOR

  227. #define CORE_PIN20_PORTSET	GPIOD_PSOR

  228. #define CORE_PIN21_PORTSET	GPIOD_PSOR

  229. #define CORE_PIN22_PORTSET	GPIOC_PSOR

  230. #define CORE_PIN23_PORTSET	GPIOC_PSOR

  231. #define CORE_PIN24_PORTSET	GPIOA_PSOR

  232. #define CORE_PIN25_PORTSET	GPIOB_PSOR

  233. #define CORE_PIN26_PORTSET	GPIOE_PSOR

  234. #define CORE_PIN27_PORTSET	GPIOC_PSOR

  235. #define CORE_PIN28_PORTSET	GPIOC_PSOR

  236. #define CORE_PIN29_PORTSET	GPIOC_PSOR

  237. #define CORE_PIN30_PORTSET	GPIOC_PSOR

  238. #define CORE_PIN31_PORTSET	GPIOE_PSOR

  239. #define CORE_PIN32_PORTSET	GPIOB_PSOR

  240. #define CORE_PIN33_PORTSET	GPIOA_PSOR

  241. 

  242. #define CORE_PIN0_PORTCLEAR	GPIOB_PCOR

  243. #define CORE_PIN1_PORTCLEAR	GPIOB_PCOR

  244. #define CORE_PIN2_PORTCLEAR	GPIOD_PCOR

  245. #define CORE_PIN3_PORTCLEAR	GPIOA_PCOR

  246. #define CORE_PIN4_PORTCLEAR	GPIOA_PCOR

  247. #define CORE_PIN5_PORTCLEAR	GPIOD_PCOR

  248. #define CORE_PIN6_PORTCLEAR	GPIOD_PCOR

  249. #define CORE_PIN7_PORTCLEAR	GPIOD_PCOR

  250. #define CORE_PIN8_PORTCLEAR	GPIOD_PCOR

  251. #define CORE_PIN9_PORTCLEAR	GPIOC_PCOR

  252. #define CORE_PIN10_PORTCLEAR	GPIOC_PCOR

  253. #define CORE_PIN11_PORTCLEAR	GPIOC_PCOR

  254. #define CORE_PIN12_PORTCLEAR	GPIOC_PCOR

  255. #define CORE_PIN13_PORTCLEAR	GPIOC_PCOR

  256. #define CORE_PIN14_PORTCLEAR	GPIOD_PCOR

  257. #define CORE_PIN15_PORTCLEAR	GPIOC_PCOR

  258. #define CORE_PIN16_PORTCLEAR	GPIOB_PCOR

  259. #define CORE_PIN17_PORTCLEAR	GPIOB_PCOR

  260. #define CORE_PIN18_PORTCLEAR	GPIOB_PCOR

  261. #define CORE_PIN19_PORTCLEAR	GPIOB_PCOR

  262. #define CORE_PIN20_PORTCLEAR	GPIOD_PCOR

  263. #define CORE_PIN21_PORTCLEAR	GPIOD_PCOR

  264. #define CORE_PIN22_PORTCLEAR	GPIOC_PCOR

  265. #define CORE_PIN23_PORTCLEAR	GPIOC_PCOR

  266. #define CORE_PIN24_PORTCLEAR	GPIOA_PCOR

  267. #define CORE_PIN25_PORTCLEAR	GPIOB_PCOR

  268. #define CORE_PIN26_PORTCLEAR	GPIOE_PCOR

  269. #define CORE_PIN27_PORTCLEAR	GPIOC_PCOR

  270. #define CORE_PIN28_PORTCLEAR	GPIOC_PCOR

  271. #define CORE_PIN29_PORTCLEAR	GPIOC_PCOR

  272. #define CORE_PIN30_PORTCLEAR	GPIOC_PCOR

  273. #define CORE_PIN31_PORTCLEAR	GPIOE_PCOR

  274. #define CORE_PIN32_PORTCLEAR	GPIOB_PCOR

  275. #define CORE_PIN33_PORTCLEAR	GPIOA_PCOR

  276. 

  277. #define CORE_PIN0_DDRREG	GPIOB_PDDR

  278. #define CORE_PIN1_DDRREG	GPIOB_PDDR

  279. #define CORE_PIN2_DDRREG	GPIOD_PDDR

  280. #define CORE_PIN3_DDRREG	GPIOA_PDDR

  281. #define CORE_PIN4_DDRREG	GPIOA_PDDR

  282. #define CORE_PIN5_DDRREG	GPIOD_PDDR

  283. #define CORE_PIN6_DDRREG	GPIOD_PDDR

  284. #define CORE_PIN7_DDRREG	GPIOD_PDDR

  285. #define CORE_PIN8_DDRREG	GPIOD_PDDR

  286. #define CORE_PIN9_DDRREG	GPIOC_PDDR

  287. #define CORE_PIN10_DDRREG	GPIOC_PDDR

  288. #define CORE_PIN11_DDRREG	GPIOC_PDDR

  289. #define CORE_PIN12_DDRREG	GPIOC_PDDR

  290. #define CORE_PIN13_DDRREG	GPIOC_PDDR

  291. #define CORE_PIN14_DDRREG	GPIOD_PDDR

  292. #define CORE_PIN15_DDRREG	GPIOC_PDDR

  293. #define CORE_PIN16_DDRREG	GPIOB_PDDR

  294. #define CORE_PIN17_DDRREG	GPIOB_PDDR

  295. #define CORE_PIN18_DDRREG	GPIOB_PDDR

  296. #define CORE_PIN19_DDRREG	GPIOB_PDDR

  297. #define CORE_PIN20_DDRREG	GPIOD_PDDR

  298. #define CORE_PIN21_DDRREG	GPIOD_PDDR

  299. #define CORE_PIN22_DDRREG	GPIOC_PDDR

  300. #define CORE_PIN23_DDRREG	GPIOC_PDDR

  301. #define CORE_PIN24_DDRREG	GPIOA_PDDR

  302. #define CORE_PIN25_DDRREG	GPIOB_PDDR

  303. #define CORE_PIN26_DDRREG	GPIOE_PDDR

  304. #define CORE_PIN27_DDRREG	GPIOC_PDDR

  305. #define CORE_PIN28_DDRREG	GPIOC_PDDR

  306. #define CORE_PIN29_DDRREG	GPIOC_PDDR

  307. #define CORE_PIN30_DDRREG	GPIOC_PDDR

  308. #define CORE_PIN31_DDRREG	GPIOE_PDDR

  309. #define CORE_PIN32_DDRREG	GPIOB_PDDR

  310. #define CORE_PIN33_DDRREG	GPIOA_PDDR

  311. 

  312. #define CORE_PIN0_PINREG	GPIOB_PDIR

  313. #define CORE_PIN1_PINREG	GPIOB_PDIR

  314. #define CORE_PIN2_PINREG	GPIOD_PDIR

  315. #define CORE_PIN3_PINREG	GPIOA_PDIR

  316. #define CORE_PIN4_PINREG	GPIOA_PDIR

  317. #define CORE_PIN5_PINREG	GPIOD_PDIR

  318. #define CORE_PIN6_PINREG	GPIOD_PDIR

  319. #define CORE_PIN7_PINREG	GPIOD_PDIR

  320. #define CORE_PIN8_PINREG	GPIOD_PDIR

  321. #define CORE_PIN9_PINREG	GPIOC_PDIR

  322. #define CORE_PIN10_PINREG	GPIOC_PDIR

  323. #define CORE_PIN11_PINREG	GPIOC_PDIR

  324. #define CORE_PIN12_PINREG	GPIOC_PDIR

  325. #define CORE_PIN13_PINREG	GPIOC_PDIR

  326. #define CORE_PIN14_PINREG	GPIOD_PDIR

  327. #define CORE_PIN15_PINREG	GPIOC_PDIR

  328. #define CORE_PIN16_PINREG	GPIOB_PDIR

  329. #define CORE_PIN17_PINREG	GPIOB_PDIR

  330. #define CORE_PIN18_PINREG	GPIOB_PDIR

  331. #define CORE_PIN19_PINREG	GPIOB_PDIR

  332. #define CORE_PIN20_PINREG	GPIOD_PDIR

  333. #define CORE_PIN21_PINREG	GPIOD_PDIR

  334. #define CORE_PIN22_PINREG	GPIOC_PDIR

  335. #define CORE_PIN23_PINREG	GPIOC_PDIR

  336. #define CORE_PIN24_PINREG	GPIOA_PDIR

  337. #define CORE_PIN25_PINREG	GPIOB_PDIR

  338. #define CORE_PIN26_PINREG	GPIOE_PDIR

  339. #define CORE_PIN27_PINREG	GPIOC_PDIR

  340. #define CORE_PIN28_PINREG	GPIOC_PDIR

  341. #define CORE_PIN29_PINREG	GPIOC_PDIR

  342. #define CORE_PIN30_PINREG	GPIOC_PDIR

  343. #define CORE_PIN31_PINREG	GPIOE_PDIR

  344. #define CORE_PIN32_PINREG	GPIOB_PDIR

  345. #define CORE_PIN33_PINREG	GPIOA_PDIR

  346. 

  347. #define CORE_PIN0_CONFIG	PORTB_PCR16

  348. #define CORE_PIN1_CONFIG	PORTB_PCR17

  349. #define CORE_PIN2_CONFIG	PORTD_PCR0

  350. #define CORE_PIN3_CONFIG	PORTA_PCR12

  351. #define CORE_PIN4_CONFIG	PORTA_PCR13

  352. #define CORE_PIN5_CONFIG	PORTD_PCR7

  353. #define CORE_PIN6_CONFIG	PORTD_PCR4

  354. #define CORE_PIN7_CONFIG	PORTD_PCR2

  355. #define CORE_PIN8_CONFIG	PORTD_PCR3

  356. #define CORE_PIN9_CONFIG	PORTC_PCR3

  357. #define CORE_PIN10_CONFIG	PORTC_PCR4

  358. #define CORE_PIN11_CONFIG	PORTC_PCR6

  359. #define CORE_PIN12_CONFIG	PORTC_PCR7

  360. #define CORE_PIN13_CONFIG	PORTC_PCR5

  361. #define CORE_PIN14_CONFIG	PORTD_PCR1

  362. #define CORE_PIN15_CONFIG	PORTC_PCR0

  363. #define CORE_PIN16_CONFIG	PORTB_PCR0

  364. #define CORE_PIN17_CONFIG	PORTB_PCR1

  365. #define CORE_PIN18_CONFIG	PORTB_PCR3

  366. #define CORE_PIN19_CONFIG	PORTB_PCR2

  367. #define CORE_PIN20_CONFIG	PORTD_PCR5

  368. #define CORE_PIN21_CONFIG	PORTD_PCR6

  369. #define CORE_PIN22_CONFIG	PORTC_PCR1

  370. #define CORE_PIN23_CONFIG	PORTC_PCR2

  371. #define CORE_PIN24_CONFIG	PORTA_PCR5

  372. #define CORE_PIN25_CONFIG	PORTB_PCR19

  373. #define CORE_PIN26_CONFIG	PORTE_PCR1

  374. #define CORE_PIN27_CONFIG	PORTC_PCR9

  375. #define CORE_PIN28_CONFIG	PORTC_PCR8

  376. #define CORE_PIN29_CONFIG	PORTC_PCR10

  377. #define CORE_PIN30_CONFIG	PORTC_PCR11

  378. #define CORE_PIN31_CONFIG	PORTE_PCR0

  379. #define CORE_PIN32_CONFIG	PORTB_PCR18

  380. #define CORE_PIN33_CONFIG	PORTA_PCR4

  381. 

  382. #define CORE_ADC0_PIN		14

  383. #define CORE_ADC1_PIN		15

  384. #define CORE_ADC2_PIN		16

  385. #define CORE_ADC3_PIN		17

  386. #define CORE_ADC4_PIN		18

  387. #define CORE_ADC5_PIN		19

  388. #define CORE_ADC6_PIN		20

  389. #define CORE_ADC7_PIN		21

  390. #define CORE_ADC8_PIN		22

  391. #define CORE_ADC9_PIN		23

  392. #define CORE_ADC10_PIN		34

  393. #define CORE_ADC11_PIN		35

  394. #define CORE_ADC12_PIN		36

  395. #define CORE_ADC13_PIN		37

  396. 

  397. #define CORE_RXD0_PIN		0

  398. #define CORE_TXD0_PIN		1

  399. #define CORE_RXD1_PIN		9

  400. #define CORE_TXD1_PIN		10

  401. #define CORE_RXD2_PIN		7

  402. #define CORE_TXD2_PIN		8

  403. 

  404. #define CORE_INT0_PIN		0

  405. #define CORE_INT1_PIN		1

  406. #define CORE_INT2_PIN		2

  407. #define CORE_INT3_PIN		3

  408. #define CORE_INT4_PIN		4

  409. #define CORE_INT5_PIN		5

  410. #define CORE_INT6_PIN		6

  411. #define CORE_INT7_PIN		7

  412. #define CORE_INT8_PIN		8

  413. #define CORE_INT9_PIN		9

  414. #define CORE_INT10_PIN		10

  415. #define CORE_INT11_PIN		11

  416. #define CORE_INT12_PIN		12

  417. #define CORE_INT13_PIN		13

  418. #define CORE_INT14_PIN		14

  419. #define CORE_INT15_PIN		15

  420. #define CORE_INT16_PIN		16

  421. #define CORE_INT17_PIN		17

  422. #define CORE_INT18_PIN		18

  423. #define CORE_INT19_PIN		19

  424. #define CORE_INT20_PIN		20

  425. #define CORE_INT21_PIN		21

  426. #define CORE_INT22_PIN		22

  427. #define CORE_INT23_PIN		23

  428. #define CORE_INT24_PIN		24

  429. #define CORE_INT25_PIN		25

  430. #define CORE_INT26_PIN		26

  431. #define CORE_INT27_PIN		27

  432. #define CORE_INT28_PIN		28

  433. #define CORE_INT29_PIN		29

  434. #define CORE_INT30_PIN		30

  435. #define CORE_INT31_PIN		31

  436. #define CORE_INT32_PIN		32

  437. #define CORE_INT33_PIN		33

  438. #define CORE_INT_EVERY_PIN	1

  439. 

  440. 

  441. 

  442. 

  443. #ifdef __cplusplus

  444. extern "C" {

  445. #endif

  446. 

  447. void digitalWrite(uint8_t pin, uint8_t val);

  448. static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));

  449. static inline void digitalWriteFast(uint8_t pin, uint8_t val)

  450. {

  451. 	if (__builtin_constant_p(pin)) {

  452. 		if (val) {

  453. 			if (pin == 0) {

  454. 				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;

  455. 			} else if (pin == 1) {

  456. 				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;

  457. 			} else if (pin == 2) {

  458. 				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;

  459. 			} else if (pin == 3) {

  460. 				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;

  461. 			} else if (pin == 4) {

  462. 				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;

  463. 			} else if (pin == 5) {

  464. 				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;

  465. 			} else if (pin == 6) {

  466. 				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;

  467. 			} else if (pin == 7) {

  468. 				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;

  469. 			} else if (pin == 8) {

  470. 				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;

  471. 			} else if (pin == 9) {

  472. 				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;

  473. 			} else if (pin == 10) {

  474. 				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;

  475. 			} else if (pin == 11) {

  476. 				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;

  477. 			} else if (pin == 12) {

  478. 				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;

  479. 			} else if (pin == 13) {

  480. 				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;

  481. 			} else if (pin == 14) {

  482. 				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;

  483. 			} else if (pin == 15) {

  484. 				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;

  485. 			} else if (pin == 16) {

  486. 				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;

  487. 			} else if (pin == 17) {

  488. 				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;

  489. 			} else if (pin == 18) {

  490. 				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;

  491. 			} else if (pin == 19) {

  492. 				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;

  493. 			} else if (pin == 20) {

  494. 				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;

  495. 			} else if (pin == 21) {

  496. 				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;

  497. 			} else if (pin == 22) {

  498. 				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;

  499. 			} else if (pin == 23) {

  500. 				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;

  501. 			} else if (pin == 24) {

  502. 				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;

  503. 			} else if (pin == 25) {

  504. 				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;

  505. 			} else if (pin == 26) {

  506. 				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;

  507. 			} else if (pin == 27) {

  508. 				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;

  509. 			} else if (pin == 28) {

  510. 				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;

  511. 			} else if (pin == 29) {

  512. 				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;

  513. 			} else if (pin == 30) {

  514. 				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;

  515. 			} else if (pin == 31) {

  516. 				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;

  517. 			} else if (pin == 32) {

  518. 				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;

  519. 			} else if (pin == 33) {

  520. 				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;

  521. 			}

  522. 		} else {

  523. 			if (pin == 0) {

  524. 				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;

  525. 			} else if (pin == 1) {

  526. 				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;

  527. 			} else if (pin == 2) {

  528. 				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;

  529. 			} else if (pin == 3) {

  530. 				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;

  531. 			} else if (pin == 4) {

  532. 				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;

  533. 			} else if (pin == 5) {

  534. 				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;

  535. 			} else if (pin == 6) {

  536. 				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;

  537. 			} else if (pin == 7) {

  538. 				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;

  539. 			} else if (pin == 8) {

  540. 				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;

  541. 			} else if (pin == 9) {

  542. 				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;

  543. 			} else if (pin == 10) {

  544. 				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;

  545. 			} else if (pin == 11) {

  546. 				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;

  547. 			} else if (pin == 12) {

  548. 				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;

  549. 			} else if (pin == 13) {

  550. 				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;

  551. 			} else if (pin == 14) {

  552. 				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;

  553. 			} else if (pin == 15) {

  554. 				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;

  555. 			} else if (pin == 16) {

  556. 				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;

  557. 			} else if (pin == 17) {

  558. 				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;

  559. 			} else if (pin == 18) {

  560. 				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;

  561. 			} else if (pin == 19) {

  562. 				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;

  563. 			} else if (pin == 20) {

  564. 				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;

  565. 			} else if (pin == 21) {

  566. 				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;

  567. 			} else if (pin == 22) {

  568. 				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;

  569. 			} else if (pin == 23) {

  570. 				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;

  571. 			} else if (pin == 24) {

  572. 				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;

  573. 			} else if (pin == 25) {

  574. 				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;

  575. 			} else if (pin == 26) {

  576. 				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;

  577. 			} else if (pin == 27) {

  578. 				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;

  579. 			} else if (pin == 28) {

  580. 				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;

  581. 			} else if (pin == 29) {

  582. 				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;

  583. 			} else if (pin == 30) {

  584. 				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;

  585. 			} else if (pin == 31) {

  586. 				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;

  587. 			} else if (pin == 32) {

  588. 				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;

  589. 			} else if (pin == 33) {

  590. 				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;

  591. 			}

  592. 		}

  593. 	} else {

  594. 		if (val) {

  595. 			*portSetRegister(pin) = 1;

  596. 		} else {

  597. 			*portClearRegister(pin) = 1;

  598. 		}

  599. 	}

  600. }

  601. 

  602. uint8_t digitalRead(uint8_t pin);

  603. static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));

  604. static inline uint8_t digitalReadFast(uint8_t pin)

  605. {

  606. 	if (__builtin_constant_p(pin)) {

  607. 		if (pin == 0) {

  608. 			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;

  609. 		} else if (pin == 1) {

  610. 			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;

  611. 		} else if (pin == 2) {

  612. 			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;

  613. 		} else if (pin == 3) {

  614. 			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;

  615. 		} else if (pin == 4) {

  616. 			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;

  617. 		} else if (pin == 5) {

  618. 			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;

  619. 		} else if (pin == 6) {

  620. 			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;

  621. 		} else if (pin == 7) {

  622. 			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;

  623. 		} else if (pin == 8) {

  624. 			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;

  625. 		} else if (pin == 9) {

  626. 			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;

  627. 		} else if (pin == 10) {

  628. 			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;

  629. 		} else if (pin == 11) {

  630. 			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;

  631. 		} else if (pin == 12) {

  632. 			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;

  633. 		} else if (pin == 13) {

  634. 			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;

  635. 		} else if (pin == 14) {

  636. 			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;

  637. 		} else if (pin == 15) {

  638. 			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;

  639. 		} else if (pin == 16) {

  640. 			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;

  641. 		} else if (pin == 17) {

  642. 			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;

  643. 		} else if (pin == 18) {

  644. 			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;

  645. 		} else if (pin == 19) {

  646. 			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;

  647. 		} else if (pin == 20) {

  648. 			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;

  649. 		} else if (pin == 21) {

  650. 			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;

  651. 		} else if (pin == 22) {

  652. 			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;

  653. 		} else if (pin == 23) {

  654. 			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;

  655. 		} else if (pin == 24) {

  656. 			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;

  657. 		} else if (pin == 25) {

  658. 			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;

  659. 		} else if (pin == 26) {

  660. 			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;

  661. 		} else if (pin == 27) {

  662. 			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;

  663. 		} else if (pin == 28) {

  664. 			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;

  665. 		} else if (pin == 29) {

  666. 			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;

  667. 		} else if (pin == 30) {

  668. 			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;

  669. 		} else if (pin == 31) {

  670. 			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;

  671. 		} else if (pin == 32) {

  672. 			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;

  673. 		} else if (pin == 33) {

  674. 			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;

  675. 		} else {

  676. 			return 0;

  677. 		}

  678. 	} else {

  679. 		return *portInputRegister(pin);

  680. 	}

  681. }

  682. 

  683. 

  684. void pinMode(uint8_t pin, uint8_t mode);

  685. void init_pins(void);

  686. void analogWrite(uint8_t pin, int val);

  687. void analogWriteRes(uint32_t bits);

  688. static inline void analogWriteResolution(uint32_t bits) { analogWriteRes(bits); }

  689. void analogWriteFrequency(uint8_t pin, uint32_t frequency);

  690. void attachInterrupt(uint8_t pin, void (*function)(void), int mode);

  691. void detachInterrupt(uint8_t pin);

  692. void _init_Teensyduino_internal_(void);

  693. 

  694. int analogRead(uint8_t pin);

  695. void analogReference(uint8_t type);

  696. void analogReadRes(unsigned int bits);

  697. static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }

  698. void analogReadAveraging(unsigned int num);

  699. void analog_init(void);

  700. 

  701. #define DEFAULT         0

  702. #define INTERNAL        2

  703. #define INTERNAL1V2     2

  704. #define INTERNAL1V1     2

  705. #define EXTERNAL        0

  706. 

  707. int touchRead(uint8_t pin);

  708. 

  709. 

  710. static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  711. extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));

  712. extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  713. extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  714. 

  715. static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  716. {

  717.         if (__builtin_constant_p(bitOrder)) {

  718.                 if (bitOrder == LSBFIRST) {

  719.                         shiftOut_lsbFirst(dataPin, clockPin, value);

  720.                 } else {

  721.                         shiftOut_msbFirst(dataPin, clockPin, value);

  722.                 }

  723.         } else {

  724.                 _shiftOut(dataPin, clockPin, bitOrder, value);

  725.         }

  726. }

  727. 

  728. static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  729. extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));

  730. extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  731. extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  732. 

  733. static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  734. {

  735.         if (__builtin_constant_p(bitOrder)) {

  736.                 if (bitOrder == LSBFIRST) {

  737.                         return shiftIn_lsbFirst(dataPin, clockPin);

  738.                 } else {

  739.                         return shiftIn_msbFirst(dataPin, clockPin);

  740.                 }

  741.         } else {

  742.                 return _shiftIn(dataPin, clockPin, bitOrder);

  743.         }

  744. }

  745. 

  746. void _reboot_Teensyduino_(void) __attribute__((noreturn));

  747. void _restart_Teensyduino_(void) __attribute__((noreturn));

  748. 

  749. void yield(void);

  750. 

  751. void delay(uint32_t msec);

  752. 

  753. extern volatile uint32_t systick_millis_count;

  754. 

  755. static inline uint32_t millis(void) __attribute__((always_inline, unused));

  756. static inline uint32_t millis(void)

  757. {

  758. 	volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic;

  759. 	return ret;

  760. }

  761. 

  762. uint32_t micros(void);

  763. 

  764. static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));

  765. static inline void delayMicroseconds(uint32_t usec)

  766. {

  767. #if F_CPU == 96000000

  768. 	uint32_t n = usec << 5;

  769. #elif F_CPU == 48000000

  770. 	uint32_t n = usec << 4;

  771. #elif F_CPU == 24000000

  772. 	uint32_t n = usec << 3;

  773. #endif

  774. 	if (usec == 0) return;

  775. 	asm volatile(

  776. 		"L_%=_delayMicroseconds:"		"\n\t"

  777. 		"subs   %0, #1"				"\n\t"

  778. 		"bne    L_%=_delayMicroseconds"		"\n"

  779. 		: "+r" (n) :

  780. 	);

  781. }

  782. 

  783. #ifdef __cplusplus

  784. }

  785. #endif

  786. 

  787. 

  788. 

  789. 

  790. 

  791. 

  792. 

  793. 

  794. #ifdef __cplusplus

  795. extern "C" {

  796. #endif

  797. unsigned long rtc_get(void);

  798. void rtc_set(unsigned long t);

  799. void rtc_compensate(int adjust);

  800. #ifdef __cplusplus

  801. }

  802. class teensy3_clock_class

  803. {

  804. public:

  805. 	static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }

  806. 	static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }

  807. 	static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }

  808. };

  809. extern teensy3_clock_class Teensy3Clock;

  810. #endif

  811. 

  812. 

  813. 

  814. 

  815. #endif