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teensy-cores/teensy3/analog.c

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2017 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #include "core_pins.h"

  32. //#include "HardwareSerial.h"

  33. 

  34. static uint8_t calibrating;

  35. static uint8_t analog_right_shift = 0;

  36. static uint8_t analog_config_bits = 10;

  37. static uint8_t analog_num_average = 4;

  38. static uint8_t analog_reference_internal = 0;

  39. 

  40. // the alternate clock is connected to OSCERCLK (16 MHz).

  41. // datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode

  42. // datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode

  43. #if F_BUS == 128000000

  44.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 8 MHz

  45.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 16 MHz

  46.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 16 MHz

  47.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 16 MHz

  48. #elif F_BUS == 120000000

  49.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7.5 MHz

  50.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz

  51.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz

  52.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz

  53. #elif F_BUS == 108000000

  54.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7 MHz

  55.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz

  56.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz

  57.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz

  58. #elif F_BUS == 96000000

  59.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz

  60.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz

  61.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz

  62.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 24 MHz

  63. #elif F_BUS == 90000000

  64.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz

  65.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz

  66.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz

  67.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 22.5 MHz

  68. #elif F_BUS == 80000000

  69.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz

  70.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz

  71.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz

  72.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 20 MHz			

  73. #elif F_BUS == 72000000

  74.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 9 MHz

  75.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz

  76.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz

  77.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz

  78. #elif F_BUS == 64000000

  79.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 8 MHz

  80.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz

  81.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz

  82.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz

  83. #elif F_BUS == 60000000

  84.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz

  85.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz

  86.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz

  87.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz

  88. #elif F_BUS == 56000000 || F_BUS == 54000000

  89.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz

  90.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz

  91.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz

  92.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz

  93. #elif F_BUS == 48000000

  94.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz

  95.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz

  96.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz

  97.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 24 MHz

  98. #elif F_BUS == 40000000

  99.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz

  100.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz

  101.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz

  102.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 20 MHz

  103. #elif F_BUS == 36000000

  104.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 9 MHz

  105.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz

  106.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz

  107.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz

  108. #elif F_BUS == 24000000

  109.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz

  110.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz

  111.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz

  112.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz

  113. #elif F_BUS == 16000000

  114.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  115.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  116.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  117.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 16 MHz

  118. #elif F_BUS == 8000000

  119.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  120.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  121.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  122.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz

  123. #elif F_BUS == 4000000

  124.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  125.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  126.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  127.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz

  128. #elif F_BUS == 2000000

  129.   #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  130.   #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  131.   #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  132.   #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz

  133. #else

  134. #error "F_BUS must be 128, 120, 108, 96, 90, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 4 or 2 MHz"

  135. #endif

  136. 

  137. void analog_init(void)

  138. {

  139. 	uint32_t num;

  140. 

  141. 	#if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  142. 	VREF_TRM = 0x60;

  143. 	VREF_SC = 0xE1;		// enable 1.2 volt ref

  144. 	#endif

  145. 

  146. 	if (analog_config_bits == 8) {

  147. 		ADC0_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);

  148. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  149. 		#ifdef HAS_KINETIS_ADC1

  150. 		ADC1_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);

  151. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  152. 		#endif

  153. 	} else if (analog_config_bits == 10) {

  154. 		ADC0_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;

  155. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  156. 		#ifdef HAS_KINETIS_ADC1

  157. 		ADC1_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;

  158. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);

  159. 		#endif

  160. 	} else if (analog_config_bits == 12) {

  161. 		ADC0_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;

  162. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  163. 		#ifdef HAS_KINETIS_ADC1

  164. 		ADC1_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;

  165. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  166. 		#endif

  167. 	} else {

  168. 		ADC0_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;

  169. 		ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  170. 		#ifdef HAS_KINETIS_ADC1

  171. 		ADC1_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;

  172. 		ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);

  173. 		#endif

  174. 	}

  175. 

  176. 	#if defined(__MK20DX128__)

  177. 	if (analog_reference_internal) {

  178. 		ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref

  179. 	} else {

  180. 		ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref

  181. 	}

  182. 	#elif defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  183. 	if (analog_reference_internal) {

  184. 		ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref

  185. 		ADC1_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref

  186. 	} else {

  187. 		ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref

  188. 		ADC1_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref

  189. 	}

  190. 	#elif defined(__MKL26Z64__)

  191. 	if (analog_reference_internal) {

  192. 		ADC0_SC2 = ADC_SC2_REFSEL(0); // external AREF

  193. 	} else {

  194. 		ADC0_SC2 = ADC_SC2_REFSEL(1); // vcc

  195. 	}

  196. 	#endif

  197. 

  198. 	num = analog_num_average;

  199. 	if (num <= 1) {

  200. 		ADC0_SC3 = ADC_SC3_CAL;  // begin cal

  201. 		#ifdef HAS_KINETIS_ADC1

  202. 		ADC1_SC3 = ADC_SC3_CAL;  // begin cal

  203. 		#endif

  204. 	} else if (num <= 4) {

  205. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  206. 		#ifdef HAS_KINETIS_ADC1

  207. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  208. 		#endif

  209. 	} else if (num <= 8) {

  210. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  211. 		#ifdef HAS_KINETIS_ADC1

  212. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  213. 		#endif

  214. 	} else if (num <= 16) {

  215. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  216. 		#ifdef HAS_KINETIS_ADC1

  217. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  218. 		#endif

  219. 	} else {

  220. 		ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  221. 		#ifdef HAS_KINETIS_ADC1

  222. 		ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  223. 		#endif

  224. 	}

  225. 	calibrating = 1;

  226. }

  227. 

  228. static void wait_for_cal(void)

  229. {

  230. 	uint16_t sum;

  231. 

  232. 	//serial_print("wait_for_cal\n");

  233. #if defined(HAS_KINETIS_ADC0) && defined(HAS_KINETIS_ADC1)

  234. 	while ((ADC0_SC3 & ADC_SC3_CAL) || (ADC1_SC3 & ADC_SC3_CAL)) {

  235. 		// wait

  236. 	}

  237. #elif defined(HAS_KINETIS_ADC0)

  238. 	while (ADC0_SC3 & ADC_SC3_CAL) {

  239. 		// wait

  240. 	}

  241. #endif

  242. 	__disable_irq();

  243. 	if (calibrating) {

  244. 		//serial_print("\n");

  245. 		sum = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;

  246. 		sum = (sum / 2) | 0x8000;

  247. 		ADC0_PG = sum;

  248. 		//serial_print("ADC0_PG = ");

  249. 		//serial_phex16(sum);

  250. 		//serial_print("\n");

  251. 		sum = ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;

  252. 		sum = (sum / 2) | 0x8000;

  253. 		ADC0_MG = sum;

  254. 		//serial_print("ADC0_MG = ");

  255. 		//serial_phex16(sum);

  256. 		//serial_print("\n");

  257. #ifdef HAS_KINETIS_ADC1

  258. 		sum = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;

  259. 		sum = (sum / 2) | 0x8000;

  260. 		ADC1_PG = sum;

  261. 		sum = ADC1_CLMS + ADC1_CLM4 + ADC1_CLM3 + ADC1_CLM2 + ADC1_CLM1 + ADC1_CLM0;

  262. 		sum = (sum / 2) | 0x8000;

  263. 		ADC1_MG = sum;

  264. #endif

  265. 		calibrating = 0;

  266. 	}

  267. 	__enable_irq();

  268. }

  269. 

  270. // ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC.

  271. //   VREFH/VREFL - connected as the primary reference option

  272. //   1.2 V VREF_OUT - connected as the VALT reference option

  273. 

  274. #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  275. #define DEFAULT         0

  276. #define INTERNAL        2

  277. #define INTERNAL1V2     2

  278. #define INTERNAL1V1     2

  279. #define EXTERNAL        0

  280. 

  281. #elif defined(__MKL26Z64__)

  282. #define DEFAULT         0

  283. #define INTERNAL        0

  284. #define EXTERNAL        1

  285. #endif

  286. 

  287. void analogReference(uint8_t type)

  288. {

  289. 	if (type) {

  290. 		// internal reference requested

  291. 		if (!analog_reference_internal) {

  292. 			analog_reference_internal = 1;

  293. 			if (calibrating) {

  294. 				ADC0_SC3 = 0; // cancel cal

  295. #ifdef HAS_KINETIS_ADC1

  296. 				ADC1_SC3 = 0; // cancel cal

  297. #endif

  298. 			}

  299. 			analog_init();

  300. 		}

  301. 	} else {

  302. 		// vcc or external reference requested

  303. 		if (analog_reference_internal) {

  304. 			analog_reference_internal = 0;

  305. 			if (calibrating) {

  306. 				ADC0_SC3 = 0; // cancel cal

  307. #ifdef HAS_KINETIS_ADC1

  308. 				ADC1_SC3 = 0; // cancel cal

  309. #endif

  310. 			}

  311. 			analog_init();

  312. 		}

  313. 	}

  314. }

  315. 

  316. 

  317. void analogReadRes(unsigned int bits)

  318. {

  319. 	unsigned int config;

  320. 

  321. 	if (bits >= 13) {

  322. 		if (bits > 16) bits = 16;

  323. 		config = 16;

  324. 	} else if (bits >= 11) {

  325. 		config = 12;

  326. 	} else if (bits >= 9) {

  327. 		config = 10;

  328. 	} else {

  329. 		config = 8;

  330. 	}

  331. 	analog_right_shift = config - bits;

  332. 	if (config != analog_config_bits) {

  333. 		analog_config_bits = config;

  334. 		if (calibrating) {

  335. 			ADC0_SC3 = 0; // cancel cal

  336. 			#ifdef HAS_KINETIS_ADC1

  337. 			ADC1_SC3 = 0;

  338. 			#endif

  339. 		}

  340. 		analog_init();

  341. 	}

  342. }

  343. 

  344. void analogReadAveraging(unsigned int num)

  345. {

  346. 

  347. 	if (calibrating) wait_for_cal();

  348. 	if (num <= 1) {

  349. 		num = 0;

  350. 		ADC0_SC3 = 0;

  351. 	} else if (num <= 4) {

  352. 		num = 4;

  353. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  354. #ifdef HAS_KINETIS_ADC1

  355. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);

  356. #endif

  357. 	} else if (num <= 8) {

  358. 		num = 8;

  359. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  360. #ifdef HAS_KINETIS_ADC1

  361. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);

  362. #endif

  363. 	} else if (num <= 16) {

  364. 		num = 16;

  365. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  366. #ifdef HAS_KINETIS_ADC1

  367. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);

  368. #endif

  369. 	} else {

  370. 		num = 32;

  371. 		ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  372. #ifdef HAS_KINETIS_ADC1

  373. 		ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);

  374. #endif

  375. 	}

  376. 	analog_num_average = num;

  377. }

  378. 

  379. // The SC1A register is used for both software and hardware trigger modes of operation.

  380. 

  381. #if defined(__MK20DX128__)

  382. static const uint8_t pin2sc1a[] = {

  383. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 0, 19, 3, 21, // 0-13 -> A0-A13

  384. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9

  385. 	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // 24-33 are digital only

  386. 	0, 19, 3, 21, // 34-37 are A10-A13

  387. 	26,           // 38 is temp sensor

  388. 	22,           // 39 is vref

  389. 	23            // 40 is unused analog pin

  390. };

  391. #elif defined(__MK20DX256__)

  392. static const uint8_t pin2sc1a[] = {

  393. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 0, 19, 3, 19+128, // 0-13 -> A0-A13

  394. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9

  395. 	255, 255, // 24-25 are digital only

  396. 	5+192, 5+128, 4+128, 6+128, 7+128, 4+192, // 26-31 are A15-A20

  397. 	255, 255, // 32-33 are digital only

  398. 	0, 19, 3, 19+128, // 34-37 are A10-A13

  399. 	26,     // 38 is temp sensor,

  400. 	18+128, // 39 is vref

  401. 	23      // 40 is A14

  402. };

  403. #elif defined(__MKL26Z64__)

  404. static const uint8_t pin2sc1a[] = {

  405. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 11, 0, 4+64, 23, // 0-12 -> A0-A12

  406. 	255, // 13 is digital only (no A13 alias)

  407. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 11, 0, 4+64, 23, // 14-26 are A0-A12

  408. 	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // 27-37 unused

  409. 	26, // 38=temperature

  410. 	27  // 39=bandgap ref (PMC_REGSC |= PMC_REGSC_BGBE)

  411. };

  412. #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)

  413. static const uint8_t pin2sc1a[] = {

  414. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 3, 19+128, 14+128, 15+128, // 0-13 -> A0-A13

  415. 	5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9

  416. 	255, 255, 255, 255, 255, 255, 255, // 24-30 are digital only

  417. 	14+128, 15+128, 17, 18, 4+128, 5+128, 6+128, 7+128, 17+128,  // 31-39 are A12-A20

  418. 	255, 255, 255, 255, 255, 255, 255, 255, 255,  // 40-48 are digital only

  419. 	10+128, 11+128, // 49-50 are A23-A24

  420. 	255, 255, 255, 255, 255, 255, 255, // 51-57 are digital only

  421. 	255, 255, 255, 255, 255, 255, // 58-63 (sd card pins) are digital only

  422. 	3, 19+128, // 64-65 are A10-A11

  423. 	23, 23+128,// 66-67 are A21-A22 (DAC pins)

  424. 	1, 1+128,  // 68-69 are A25-A26 (unused USB host port on Teensy 3.5)

  425. 	26,        // 70 is Temperature Sensor

  426. 	18+128     // 71 is Vref

  427. };

  428. #endif

  429. 

  430. 

  431. 

  432. // TODO: perhaps this should store the NVIC priority, so it works recursively?

  433. static volatile uint8_t analogReadBusyADC0 = 0;

  434. #ifdef HAS_KINETIS_ADC1

  435. static volatile uint8_t analogReadBusyADC1 = 0;

  436. #endif

  437. 

  438. int analogRead(uint8_t pin)

  439. {

  440. 	int result;

  441. 	uint8_t channel;

  442. 

  443. 	//serial_phex(pin);

  444. 	//serial_print(" ");

  445. 

  446. 	if (pin >= sizeof(pin2sc1a)) return 0;

  447. 	channel = pin2sc1a[pin];

  448. 	if (channel == 255) return 0;

  449. 

  450. 	if (calibrating) wait_for_cal();

  451. 

  452. #ifdef HAS_KINETIS_ADC1

  453. 	if (channel & 0x80) goto beginADC1;

  454. #endif

  455. 

  456. 	__disable_irq();

  457. startADC0:

  458. 	//serial_print("startADC0\n");

  459. #if defined(__MKL26Z64__)

  460. 	if (channel & 0x40) {

  461. 		ADC0_CFG2 &= ~ADC_CFG2_MUXSEL;

  462. 		channel &= 0x3F;

  463. 	} else {

  464. 		ADC0_CFG2 |= ADC_CFG2_MUXSEL;

  465. 	}

  466. #endif

  467. 	ADC0_SC1A = channel;

  468. 	analogReadBusyADC0 = 1;

  469. 	__enable_irq();

  470. 	while (1) {

  471. 		__disable_irq();

  472. 		if ((ADC0_SC1A & ADC_SC1_COCO)) {

  473. 			result = ADC0_RA;

  474. 			analogReadBusyADC0 = 0;

  475. 			__enable_irq();

  476. 			result >>= analog_right_shift;

  477. 			return result;

  478. 		}

  479. 		// detect if analogRead was used from an interrupt

  480. 		// if so, our analogRead got canceled, so it must

  481. 		// be restarted.

  482. 		if (!analogReadBusyADC0) goto startADC0;

  483. 		__enable_irq();

  484. 		yield();

  485. 	}

  486. 

  487. #ifdef HAS_KINETIS_ADC1

  488. beginADC1:

  489. 	__disable_irq();

  490. startADC1:

  491. 	//serial_print("startADC1\n");

  492. 	// ADC1_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b.

  493. 	if (channel & 0x40) {

  494. 		ADC1_CFG2 &= ~ADC_CFG2_MUXSEL;

  495. 	} else {

  496. 		ADC1_CFG2 |= ADC_CFG2_MUXSEL;

  497. 	}

  498. 	ADC1_SC1A = channel & 0x3F;

  499. 	analogReadBusyADC1 = 1;

  500. 	__enable_irq();

  501. 	while (1) {

  502. 		__disable_irq();

  503. 		if ((ADC1_SC1A & ADC_SC1_COCO)) {

  504. 			result = ADC1_RA;

  505. 			analogReadBusyADC1 = 0;

  506. 			__enable_irq();

  507. 			result >>= analog_right_shift;

  508. 			return result;

  509. 		}

  510. 		// detect if analogRead was used from an interrupt

  511. 		// if so, our analogRead got canceled, so it must

  512. 		// be restarted.

  513. 		if (!analogReadBusyADC1) goto startADC1;

  514. 		__enable_irq();

  515. 		yield();

  516. 	}

  517. #endif

  518. }

  519. 

  520. typedef int16_t __attribute__((__may_alias__)) aliased_int16_t;

  521. 

  522. void analogWriteDAC0(int val)

  523. {

  524. #if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)

  525. 	SIM_SCGC2 |= SIM_SCGC2_DAC0;

  526. 	if (analog_reference_internal) {

  527. 		DAC0_C0 = DAC_C0_DACEN;  // 1.2V ref is DACREF_1

  528. 	} else {

  529. 		DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2

  530. 	}

  531. 	__asm__ ("usat    %[value], #12, %[value]\n\t" : [value] "+r" (val));  // 0 <= val <= 4095

  532. 

  533. 	*(volatile aliased_int16_t *)&(DAC0_DAT0L) = val;

  534. #elif defined(__MKL26Z64__)

  535. 	SIM_SCGC6 |= SIM_SCGC6_DAC0;

  536. 	if (analog_reference_internal == 0) {

  537. 		// use 3.3V VDDA power as the reference (this is the default)

  538. 		DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS | DAC_C0_DACSWTRG; // 3.3V VDDA

  539. 	} else {

  540. 		// use whatever voltage is on the AREF pin

  541. 		DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACSWTRG; // 3.3V VDDA

  542. 	}

  543. 	if (val < 0) val = 0;

  544. 	else if (val > 4095) val = 4095;

  545. 

  546. 	*(volatile aliased_int16_t *)&(DAC0_DAT0L) = val;

  547. #endif

  548. }

  549. 

  550. 

  551. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  552. void analogWriteDAC1(int val)

  553. {

  554. 	SIM_SCGC2 |= SIM_SCGC2_DAC1;

  555. 	if (analog_reference_internal) {

  556. 		DAC1_C0 = DAC_C0_DACEN;  // 1.2V ref is DACREF_1

  557. 	} else {

  558. 		DAC1_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2

  559. 	}

  560. 	__asm__ ("usat    %[value], #12, %[value]\n\t" : [value] "+r" (val));  // 0 <= val <= 4095

  561. 

  562. 	*(volatile aliased_int16_t *)&(DAC1_DAT0L) = val;

  563. }

  564. #endif

  565. 

  566. 

  567. 

  568. 

  569. 

  570. 

  571. 

  572. 

  573. 

  574. 

  575. 

  576. 

  577. 

  578.