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teensy-cores/teensy4/digital.c

250 line
9.5KB
原始文件 Blame 歷史記錄 

  1. 

  2. #include "core_pins.h"

  3. 

  4. /*

  5. struct digital_pin_bitband_and_config_table_struct {

  6.         volatile uint32_t *reg;

  7.         volatile uint32_t *mux;

  8.         volatile uint32_t *pad;

  9.         uint32_t mask;

  10. };

  11. extern const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM[];

  12. #define digitalPinToPort(pin)    (pin)

  13. #define digitalPinToBitMask(pin) (digital_pin_to_info_PGM[(pin)].mask)

  14. #define portOutputRegister(pin)  ((digital_pin_to_info_PGM[(pin)].reg))

  15. #define portSetRegister(pin)     ((digital_pin_to_info_PGM[(pin)].reg + 0x21))

  16. #define portClearRegister(pin)   ((digital_pin_to_info_PGM[(pin)].reg + 0x22))

  17. #define portToggleRegister(pin)  ((digital_pin_to_info_PGM[(pin)].reg + 0x23))

  18. #define portInputRegister(pin)   ((digital_pin_to_info_PGM[(pin)].reg + 2))

  19. #define portModeRegister(pin)    ((digital_pin_to_info_PGM[(pin)].reg + 1))

  20. #define portConfigRegister(pin)  ((digital_pin_to_info_PGM[(pin)].max))

  21. #define digitalPinToPortReg(pin) (portOutputRegister(pin))

  22. */

  23. 

  24. const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM[] = {

  25. 	{&CORE_PIN0_PORTREG, &CORE_PIN0_CONFIG, &CORE_PIN0_PADCONFIG, CORE_PIN0_BITMASK},

  26. 	{&CORE_PIN1_PORTREG, &CORE_PIN1_CONFIG, &CORE_PIN1_PADCONFIG, CORE_PIN1_BITMASK},

  27. 	{&CORE_PIN2_PORTREG, &CORE_PIN2_CONFIG, &CORE_PIN2_PADCONFIG, CORE_PIN2_BITMASK},

  28. 	{&CORE_PIN3_PORTREG, &CORE_PIN3_CONFIG, &CORE_PIN3_PADCONFIG, CORE_PIN3_BITMASK},

  29. 	{&CORE_PIN4_PORTREG, &CORE_PIN4_CONFIG, &CORE_PIN4_PADCONFIG, CORE_PIN4_BITMASK},

  30. 	{&CORE_PIN5_PORTREG, &CORE_PIN5_CONFIG, &CORE_PIN5_PADCONFIG, CORE_PIN5_BITMASK},

  31. 	{&CORE_PIN6_PORTREG, &CORE_PIN6_CONFIG, &CORE_PIN6_PADCONFIG, CORE_PIN6_BITMASK},

  32. 	{&CORE_PIN7_PORTREG, &CORE_PIN7_CONFIG, &CORE_PIN7_PADCONFIG, CORE_PIN7_BITMASK},

  33. 	{&CORE_PIN8_PORTREG, &CORE_PIN8_CONFIG, &CORE_PIN8_PADCONFIG, CORE_PIN8_BITMASK},

  34. 	{&CORE_PIN9_PORTREG, &CORE_PIN9_CONFIG, &CORE_PIN9_PADCONFIG, CORE_PIN9_BITMASK},

  35. 	{&CORE_PIN10_PORTREG, &CORE_PIN10_CONFIG, &CORE_PIN10_PADCONFIG, CORE_PIN10_BITMASK},

  36. 	{&CORE_PIN11_PORTREG, &CORE_PIN11_CONFIG, &CORE_PIN11_PADCONFIG, CORE_PIN11_BITMASK},

  37. 	{&CORE_PIN12_PORTREG, &CORE_PIN12_CONFIG, &CORE_PIN12_PADCONFIG, CORE_PIN12_BITMASK},

  38. 	{&CORE_PIN13_PORTREG, &CORE_PIN13_CONFIG, &CORE_PIN13_PADCONFIG, CORE_PIN13_BITMASK},

  39. 	{&CORE_PIN14_PORTREG, &CORE_PIN14_CONFIG, &CORE_PIN14_PADCONFIG, CORE_PIN14_BITMASK},

  40. 	{&CORE_PIN15_PORTREG, &CORE_PIN15_CONFIG, &CORE_PIN15_PADCONFIG, CORE_PIN15_BITMASK},

  41. 	{&CORE_PIN16_PORTREG, &CORE_PIN16_CONFIG, &CORE_PIN16_PADCONFIG, CORE_PIN16_BITMASK},

  42. 	{&CORE_PIN17_PORTREG, &CORE_PIN17_CONFIG, &CORE_PIN17_PADCONFIG, CORE_PIN17_BITMASK},

  43. 	{&CORE_PIN18_PORTREG, &CORE_PIN18_CONFIG, &CORE_PIN18_PADCONFIG, CORE_PIN18_BITMASK},

  44. 	{&CORE_PIN19_PORTREG, &CORE_PIN19_CONFIG, &CORE_PIN19_PADCONFIG, CORE_PIN19_BITMASK},

  45. 	{&CORE_PIN20_PORTREG, &CORE_PIN20_CONFIG, &CORE_PIN20_PADCONFIG, CORE_PIN20_BITMASK},

  46. 	{&CORE_PIN21_PORTREG, &CORE_PIN21_CONFIG, &CORE_PIN21_PADCONFIG, CORE_PIN21_BITMASK},

  47. 	{&CORE_PIN22_PORTREG, &CORE_PIN22_CONFIG, &CORE_PIN22_PADCONFIG, CORE_PIN22_BITMASK},

  48. 	{&CORE_PIN23_PORTREG, &CORE_PIN23_CONFIG, &CORE_PIN23_PADCONFIG, CORE_PIN23_BITMASK},

  49. 	{&CORE_PIN24_PORTREG, &CORE_PIN24_CONFIG, &CORE_PIN24_PADCONFIG, CORE_PIN24_BITMASK},

  50. 	{&CORE_PIN25_PORTREG, &CORE_PIN25_CONFIG, &CORE_PIN25_PADCONFIG, CORE_PIN25_BITMASK},

  51. 	{&CORE_PIN26_PORTREG, &CORE_PIN26_CONFIG, &CORE_PIN26_PADCONFIG, CORE_PIN26_BITMASK},

  52. 	{&CORE_PIN27_PORTREG, &CORE_PIN27_CONFIG, &CORE_PIN27_PADCONFIG, CORE_PIN27_BITMASK},

  53. 	{&CORE_PIN28_PORTREG, &CORE_PIN28_CONFIG, &CORE_PIN28_PADCONFIG, CORE_PIN28_BITMASK},

  54. 	{&CORE_PIN29_PORTREG, &CORE_PIN29_CONFIG, &CORE_PIN29_PADCONFIG, CORE_PIN29_BITMASK},

  55. 	{&CORE_PIN30_PORTREG, &CORE_PIN30_CONFIG, &CORE_PIN30_PADCONFIG, CORE_PIN30_BITMASK},

  56. 	{&CORE_PIN31_PORTREG, &CORE_PIN31_CONFIG, &CORE_PIN31_PADCONFIG, CORE_PIN31_BITMASK},

  57. 	{&CORE_PIN32_PORTREG, &CORE_PIN32_CONFIG, &CORE_PIN32_PADCONFIG, CORE_PIN32_BITMASK},

  58. 	{&CORE_PIN33_PORTREG, &CORE_PIN33_CONFIG, &CORE_PIN33_PADCONFIG, CORE_PIN33_BITMASK},

  59. #if defined(__IMXRT1062__)

  60. 	{&CORE_PIN34_PORTREG, &CORE_PIN34_CONFIG, &CORE_PIN34_PADCONFIG, CORE_PIN34_BITMASK},

  61. 	{&CORE_PIN35_PORTREG, &CORE_PIN35_CONFIG, &CORE_PIN35_PADCONFIG, CORE_PIN35_BITMASK},

  62. 	{&CORE_PIN36_PORTREG, &CORE_PIN36_CONFIG, &CORE_PIN36_PADCONFIG, CORE_PIN36_BITMASK},

  63. 	{&CORE_PIN37_PORTREG, &CORE_PIN37_CONFIG, &CORE_PIN37_PADCONFIG, CORE_PIN37_BITMASK},

  64. 	{&CORE_PIN38_PORTREG, &CORE_PIN38_CONFIG, &CORE_PIN38_PADCONFIG, CORE_PIN38_BITMASK},

  65. 	{&CORE_PIN39_PORTREG, &CORE_PIN39_CONFIG, &CORE_PIN39_PADCONFIG, CORE_PIN39_BITMASK},

  66. #endif

  67. 	};

  68. 

  69. void digitalWrite(uint8_t pin, uint8_t val)

  70. {

  71. 	const struct digital_pin_bitband_and_config_table_struct *p;

  72. 	uint32_t pinmode, mask;

  73. 

  74. 	if (pin >= CORE_NUM_DIGITAL) return;

  75. 	p = digital_pin_to_info_PGM + pin;

  76. 	pinmode = *(p->reg + 1);

  77. 	mask = p->mask;

  78. 	if (pinmode & mask) {

  79. 		// pin is configured for output mode

  80. 		if (val) {

  81. 			*(p->reg + 0x21) = mask; // set register

  82. 		} else {

  83. 			*(p->reg + 0x22) = mask; // clear register

  84. 		}

  85. 	} else {

  86. 		// pin is configured for input mode

  87. 		// writing controls pullup resistor

  88. 

  89. 		// TODO....

  90. 	}

  91. }

  92. 

  93. uint8_t digitalRead(uint8_t pin)

  94. {

  95. 	const struct digital_pin_bitband_and_config_table_struct *p;

  96. 

  97. 	if (pin >= CORE_NUM_DIGITAL) return 0;

  98. 	p = digital_pin_to_info_PGM + pin;

  99. 	return (*(p->reg + 2) & p->mask) ? 1 : 0;

  100. }

  101. 

  102. void pinMode(uint8_t pin, uint8_t mode)

  103. {

  104. 	const struct digital_pin_bitband_and_config_table_struct *p;

  105. 

  106. 	if (pin >= CORE_NUM_DIGITAL) return;

  107. 	p = digital_pin_to_info_PGM + pin;

  108. 	if (mode == OUTPUT || mode == OUTPUT_OPENDRAIN) {

  109. 		*(p->reg + 1) |= p->mask; // TODO: atomic

  110. 		if (mode == OUTPUT) {

  111. 			*(p->pad) = IOMUXC_PAD_DSE(7);

  112. 		} else { // OUTPUT_OPENDRAIN

  113. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_ODE;

  114. 		}

  115. 	} else {

  116. 		*(p->reg + 1) &= ~(p->mask); // TODO: atomic

  117. 		if (mode == INPUT) {

  118. 			*(p->pad) = IOMUXC_PAD_DSE(7);

  119. 		} else if (mode == INPUT_PULLUP) {

  120. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(3) | IOMUXC_PAD_HYS;

  121. 		} else if (mode == INPUT_PULLDOWN) {

  122. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_PKE | IOMUXC_PAD_PUE | IOMUXC_PAD_PUS(0) | IOMUXC_PAD_HYS;

  123. 		} else { // INPUT_DISABLE

  124. 			*(p->pad) = IOMUXC_PAD_DSE(7) | IOMUXC_PAD_HYS;

  125. 		}

  126. 	}

  127. 	*(p->mux) = 5 | 0x10;

  128. }

  129. 

  130. void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  131. {

  132.         if (bitOrder == LSBFIRST) {

  133.                 shiftOut_lsbFirst(dataPin, clockPin, value);

  134.         } else {

  135.                 shiftOut_msbFirst(dataPin, clockPin, value);

  136.         }

  137. }

  138. 

  139. void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)

  140. {

  141.         uint8_t mask;

  142.         for (mask=0x01; mask; mask <<= 1) {

  143.                 digitalWrite(dataPin, value & mask);

  144.                 digitalWrite(clockPin, HIGH);

  145.                 digitalWrite(clockPin, LOW);

  146.         }

  147. }

  148. 

  149. void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)

  150. {

  151.         uint8_t mask;

  152.         for (mask=0x80; mask; mask >>= 1) {

  153.                 digitalWrite(dataPin, value & mask);

  154.                 digitalWrite(clockPin, HIGH);

  155.                 digitalWrite(clockPin, LOW);

  156.         }

  157. }

  158. 

  159. uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  160. {

  161.         if (bitOrder == LSBFIRST) {

  162.                 return shiftIn_lsbFirst(dataPin, clockPin);

  163.         } else {

  164.                 return shiftIn_msbFirst(dataPin, clockPin);

  165.         }

  166. }

  167. 

  168. uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin)

  169. {

  170.         uint8_t mask, value=0;

  171.         for (mask=0x01; mask; mask <<= 1) {

  172.                 digitalWrite(clockPin, HIGH);

  173.                 if (digitalRead(dataPin)) value |= mask;

  174.                 digitalWrite(clockPin, LOW);

  175.         }

  176.         return value;

  177. }

  178. 

  179. uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin)

  180. {

  181.         uint8_t mask, value=0;

  182.         for (mask=0x80; mask; mask >>= 1) {

  183.                 digitalWrite(clockPin, HIGH);

  184.                 if (digitalRead(dataPin)) value |= mask;

  185.                 digitalWrite(clockPin, LOW);

  186.         }

  187.         return value;

  188. }

  189. 

  190. //(*portInputRegister(pin) & digitalPinToBitMask(pin))

  191. uint32_t pulseIn_high(uint8_t pin, uint32_t timeout)

  192. {

  193. 	const struct digital_pin_bitband_and_config_table_struct *p;

  194. 	p = digital_pin_to_info_PGM + pin;

  195. 

  196. 	uint32_t usec_start, usec_stop;

  197. 

  198. 	// wait for any previous pulse to end

  199. 	usec_start = micros();

  200. 	while ((*(p->reg + 2) & p->mask)) {

  201. 		if (micros()-usec_start > timeout) return 0;

  202. 	}

  203. 	// wait for the pulse to start

  204. 	usec_start = micros();

  205. 	while (!(*(p->reg + 2) & p->mask)) {

  206. 		if (micros()-usec_start > timeout) return 0;

  207. 	}

  208. 	usec_start = micros();

  209. 	// wait for the pulse to stop

  210. 	while ((*(p->reg + 2) & p->mask)) {

  211. 		if (micros()-usec_start > timeout) return 0;

  212. 	}

  213. 	usec_stop = micros();

  214. 	return usec_stop - usec_start;

  215. }

  216. 

  217. uint32_t pulseIn_low(uint8_t pin, uint32_t timeout)

  218. {

  219. 	const struct digital_pin_bitband_and_config_table_struct *p;

  220. 	p = digital_pin_to_info_PGM + pin;

  221. 

  222. 	uint32_t usec_start, usec_stop;

  223. 

  224. 	// wait for any previous pulse to end

  225. 	usec_start = micros();

  226. 	while (!(*(p->reg + 2) & p->mask)) {

  227. 		if (micros() - usec_start > timeout) return 0;

  228. 	}

  229. 	// wait for the pulse to start

  230. 	usec_start = micros();

  231. 	while ((*(p->reg + 2) & p->mask)) {

  232. 		if (micros() - usec_start > timeout) return 0;

  233. 	}

  234. 	usec_start = micros();

  235. 	// wait for the pulse to stop

  236. 	while (!(*(p->reg + 2) & p->mask)) {

  237. 		if (micros() - usec_start > timeout) return 0;

  238. 	}

  239. 	usec_stop = micros();

  240. 	return usec_stop - usec_start;

  241. }

  242. 

  243. // TODO: an inline version should handle the common case where state is const

  244. uint32_t pulseIn(uint8_t pin, uint8_t state, uint32_t timeout)

  245. {

  246. 	if (pin >= CORE_NUM_DIGITAL) return 0;

  247. 	if (state) return pulseIn_high(pin, timeout);

  248. 	return pulseIn_low(pin, timeout);

  249. }