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teensy-cores/teensy/core_pins.h

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  1. #ifndef _core_pins_h_

  2. #define _core_pins_h_

  3. 

  4. #include <avr/io.h>

  5. 

  6. #if (GCC_VERSION >= 40300) && (GCC_VERSION < 40302)

  7. #error "Buggy GCC 4.3.0 compiler, please upgrade!"

  8. #endif

  9. 

  10. 

  11. // This will speed up digitalWrite slightly, but it

  12. // adds to your code size.  However, if you don't

  13. // have many digitalWrites, or most are compile time

  14. // constant inputs, then this might be worthwhile

  15. //#define DIGITAL_WRITE_EXPENSIVE_INLINE_OPTIMIZATION

  16. 

  17. // This removes checking in digitalWrite for pin numbers

  18. // beyond the maximum number of pins.  Your program

  19. // WILL CRASH is digitalWrite is called with a pin number

  20. // too large, when this is enabled.  However, if you don't

  21. // make such mistakes, you'll get a minor speedup.

  22. //#define DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK

  23. 

  24. #define HIGH 0x1

  25. #define LOW  0x0

  26. 

  27. #define INPUT 0x0

  28. #define OUTPUT 0x1

  29. #define INPUT_PULLUP 0x2

  30. 

  31. #define LSBFIRST 0

  32. #define MSBFIRST 1

  33. 

  34. #ifndef _BV

  35. #define _BV(n) (1<<(n))

  36. #endif

  37. 

  38. ////////////////////////////////////

  39. // Teensy 2.0

  40. ////////////////////////////////////

  41. #if defined(__AVR_ATmega32U4__)

  42. #define CORE_NUM_TOTAL_PINS	25

  43. #define CORE_NUM_DIGITAL	13

  44. #define CORE_NUM_ANALOG		12

  45. #define CORE_NUM_PWM		7

  46. #define CORE_NUM_INTERRUPT	4

  47. #define PIN_B0		0

  48. #define PIN_B1		1

  49. #define PIN_B2		2

  50. #define PIN_B3		3

  51. #define PIN_B7		4

  52. #define PIN_D0		5

  53. #define PIN_D1		6

  54. #define PIN_D2		7

  55. #define PIN_D3		8

  56. #define PIN_C6		9

  57. #define PIN_C7		10

  58. #define PIN_D6		11

  59. #define PIN_D7		12

  60. #define PIN_B4		13

  61. #define PIN_B5		14

  62. #define PIN_B6		15

  63. #define PIN_F7		16

  64. #define PIN_F6		17

  65. #define PIN_F5		18

  66. #define PIN_F4		19

  67. #define PIN_F1		20

  68. #define PIN_F0		21

  69. #define PIN_D4		22

  70. #define PIN_D5		23

  71. #define PIN_E6		24

  72. #define CORE_PIN0_BIT		0

  73. #define CORE_PIN1_BIT		1

  74. #define CORE_PIN2_BIT		2

  75. #define CORE_PIN3_BIT		3

  76. #define CORE_PIN4_BIT		7

  77. #define CORE_PIN5_BIT		0

  78. #define CORE_PIN6_BIT		1

  79. #define CORE_PIN7_BIT		2

  80. #define CORE_PIN8_BIT		3

  81. #define CORE_PIN9_BIT		6

  82. #define CORE_PIN10_BIT		7

  83. #define CORE_PIN11_BIT		6

  84. #define CORE_PIN12_BIT		7

  85. #define CORE_PIN13_BIT		4

  86. #define CORE_PIN14_BIT		5

  87. #define CORE_PIN15_BIT		6

  88. #define CORE_PIN16_BIT		7

  89. #define CORE_PIN17_BIT		6

  90. #define CORE_PIN18_BIT		5

  91. #define CORE_PIN19_BIT		4

  92. #define CORE_PIN20_BIT		1

  93. #define CORE_PIN21_BIT		0

  94. #define CORE_PIN22_BIT		4

  95. #define CORE_PIN23_BIT		5

  96. #define CORE_PIN24_BIT		6

  97. #define CORE_PIN0_BITMASK	_BV(CORE_PIN0_BIT)

  98. #define CORE_PIN1_BITMASK	_BV(CORE_PIN1_BIT)

  99. #define CORE_PIN2_BITMASK	_BV(CORE_PIN2_BIT)

  100. #define CORE_PIN3_BITMASK	_BV(CORE_PIN3_BIT)

  101. #define CORE_PIN4_BITMASK	_BV(CORE_PIN4_BIT)

  102. #define CORE_PIN5_BITMASK	_BV(CORE_PIN5_BIT)

  103. #define CORE_PIN6_BITMASK	_BV(CORE_PIN6_BIT)

  104. #define CORE_PIN7_BITMASK	_BV(CORE_PIN7_BIT)

  105. #define CORE_PIN8_BITMASK	_BV(CORE_PIN8_BIT)

  106. #define CORE_PIN9_BITMASK	_BV(CORE_PIN9_BIT)

  107. #define CORE_PIN10_BITMASK	_BV(CORE_PIN10_BIT)

  108. #define CORE_PIN11_BITMASK	_BV(CORE_PIN11_BIT)

  109. #define CORE_PIN12_BITMASK	_BV(CORE_PIN12_BIT)

  110. #define CORE_PIN13_BITMASK	_BV(CORE_PIN13_BIT)

  111. #define CORE_PIN14_BITMASK	_BV(CORE_PIN14_BIT)

  112. #define CORE_PIN15_BITMASK	_BV(CORE_PIN15_BIT)

  113. #define CORE_PIN16_BITMASK	_BV(CORE_PIN16_BIT)

  114. #define CORE_PIN17_BITMASK	_BV(CORE_PIN17_BIT)

  115. #define CORE_PIN18_BITMASK	_BV(CORE_PIN18_BIT)

  116. #define CORE_PIN19_BITMASK	_BV(CORE_PIN19_BIT)

  117. #define CORE_PIN20_BITMASK	_BV(CORE_PIN20_BIT)

  118. #define CORE_PIN21_BITMASK	_BV(CORE_PIN21_BIT)

  119. #define CORE_PIN22_BITMASK	_BV(CORE_PIN22_BIT)

  120. #define CORE_PIN23_BITMASK	_BV(CORE_PIN23_BIT)

  121. #define CORE_PIN24_BITMASK	_BV(CORE_PIN24_BIT)

  122. #define CORE_PIN0_PORTREG	PORTB

  123. #define CORE_PIN1_PORTREG	PORTB

  124. #define CORE_PIN2_PORTREG	PORTB

  125. #define CORE_PIN3_PORTREG	PORTB

  126. #define CORE_PIN4_PORTREG	PORTB

  127. #define CORE_PIN5_PORTREG	PORTD

  128. #define CORE_PIN6_PORTREG	PORTD

  129. #define CORE_PIN7_PORTREG	PORTD

  130. #define CORE_PIN8_PORTREG	PORTD

  131. #define CORE_PIN9_PORTREG	PORTC

  132. #define CORE_PIN10_PORTREG	PORTC

  133. #define CORE_PIN11_PORTREG	PORTD

  134. #define CORE_PIN12_PORTREG	PORTD

  135. #define CORE_PIN13_PORTREG	PORTB

  136. #define CORE_PIN14_PORTREG	PORTB

  137. #define CORE_PIN15_PORTREG	PORTB

  138. #define CORE_PIN16_PORTREG	PORTF

  139. #define CORE_PIN17_PORTREG	PORTF

  140. #define CORE_PIN18_PORTREG	PORTF

  141. #define CORE_PIN19_PORTREG	PORTF

  142. #define CORE_PIN20_PORTREG	PORTF

  143. #define CORE_PIN21_PORTREG	PORTF

  144. #define CORE_PIN22_PORTREG	PORTD

  145. #define CORE_PIN23_PORTREG	PORTD

  146. #define CORE_PIN24_PORTREG	PORTE

  147. #define CORE_PIN0_DDRREG	DDRB

  148. #define CORE_PIN1_DDRREG	DDRB

  149. #define CORE_PIN2_DDRREG	DDRB

  150. #define CORE_PIN3_DDRREG	DDRB

  151. #define CORE_PIN4_DDRREG	DDRB

  152. #define CORE_PIN5_DDRREG	DDRD

  153. #define CORE_PIN6_DDRREG	DDRD

  154. #define CORE_PIN7_DDRREG	DDRD

  155. #define CORE_PIN8_DDRREG	DDRD

  156. #define CORE_PIN9_DDRREG	DDRC

  157. #define CORE_PIN10_DDRREG	DDRC

  158. #define CORE_PIN11_DDRREG	DDRD

  159. #define CORE_PIN12_DDRREG	DDRD

  160. #define CORE_PIN13_DDRREG	DDRB

  161. #define CORE_PIN14_DDRREG	DDRB

  162. #define CORE_PIN15_DDRREG	DDRB

  163. #define CORE_PIN16_DDRREG	DDRF

  164. #define CORE_PIN17_DDRREG	DDRF

  165. #define CORE_PIN18_DDRREG	DDRF

  166. #define CORE_PIN19_DDRREG	DDRF

  167. #define CORE_PIN20_DDRREG	DDRF

  168. #define CORE_PIN21_DDRREG	DDRF

  169. #define CORE_PIN22_DDRREG	DDRD

  170. #define CORE_PIN23_DDRREG	DDRD

  171. #define CORE_PIN24_DDRREG	DDRE

  172. #define CORE_PIN0_PINREG	PINB

  173. #define CORE_PIN1_PINREG	PINB

  174. #define CORE_PIN2_PINREG	PINB

  175. #define CORE_PIN3_PINREG	PINB

  176. #define CORE_PIN4_PINREG	PINB

  177. #define CORE_PIN5_PINREG	PIND

  178. #define CORE_PIN6_PINREG	PIND

  179. #define CORE_PIN7_PINREG	PIND

  180. #define CORE_PIN8_PINREG	PIND

  181. #define CORE_PIN9_PINREG	PINC

  182. #define CORE_PIN10_PINREG	PINC

  183. #define CORE_PIN11_PINREG	PIND

  184. #define CORE_PIN12_PINREG	PIND

  185. #define CORE_PIN13_PINREG	PINB

  186. #define CORE_PIN14_PINREG	PINB

  187. #define CORE_PIN15_PINREG	PINB

  188. #define CORE_PIN16_PINREG	PINF

  189. #define CORE_PIN17_PINREG	PINF

  190. #define CORE_PIN18_PINREG	PINF

  191. #define CORE_PIN19_PINREG	PINF

  192. #define CORE_PIN20_PINREG	PINF

  193. #define CORE_PIN21_PINREG	PINF

  194. #define CORE_PIN22_PINREG	PIND

  195. #define CORE_PIN23_PINREG	PIND

  196. #define CORE_PIN24_PINREG	PINE

  197. #define CORE_ADC0_PIN		PIN_F0

  198. #define CORE_ADC1_PIN		PIN_F1

  199. #define CORE_ADC4_PIN		PIN_F4

  200. #define CORE_ADC5_PIN		PIN_F5

  201. #define CORE_ADC6_PIN		PIN_F6

  202. #define CORE_ADC7_PIN		PIN_F7

  203. #define CORE_ADC8_PIN		PIN_D4

  204. #define CORE_ADC9_PIN		PIN_D6

  205. #define CORE_ADC10_PIN		PIN_D7

  206. #define CORE_ADC11_PIN		PIN_B4

  207. #define CORE_ADC12_PIN		PIN_B5

  208. #define CORE_ADC13_PIN		PIN_B6

  209. #define CORE_RXD1_PIN           PIN_D2

  210. #define CORE_TXD1_PIN           PIN_D3

  211. #define CORE_XCK1_PIN           PIN_D5

  212. #define CORE_SDA0_PIN           PIN_D1

  213. #define CORE_SCL0_PIN           PIN_D0

  214. #define CORE_INT0_PIN           PIN_D0

  215. #define CORE_INT1_PIN           PIN_D1

  216. #define CORE_INT2_PIN           PIN_D2

  217. #define CORE_INT3_PIN           PIN_D3

  218. #define CORE_SS0_PIN            PIN_B0

  219. #define CORE_MOSI0_PIN          PIN_B2

  220. #define CORE_MISO0_PIN          PIN_B3

  221. #define CORE_SCLK0_PIN          PIN_B1

  222. #define CORE_T0_PIN             PIN_D7

  223. #define CORE_T1_PIN             PIN_D6

  224. #define CORE_ICP1_PIN           PIN_D4

  225. #define CORE_ICP3_PIN           PIN_C7

  226. #define CORE_OC0A_PIN           PIN_B7

  227. #define CORE_OC0B_PIN           PIN_D0

  228. #define CORE_OC1A_PIN           PIN_B5

  229. #define CORE_OC1B_PIN           PIN_B6

  230. #define CORE_OC1C_PIN           PIN_B7

  231. #define CORE_OC3A_PIN           PIN_C6

  232. #define CORE_OC4A_PIN           PIN_C7

  233. #define CORE_OC4AN_PIN          PIN_C6

  234. #define CORE_OC4B_PIN           PIN_B6

  235. #define CORE_OC4BN_PIN          PIN_B5

  236. #define CORE_OC4D_PIN           PIN_D7

  237. #define CORE_OC4DN_PIN          PIN_D6

  238. #define CORE_PCINT0_PIN		PIN_B0

  239. #define CORE_PCINT1_PIN		PIN_B1

  240. #define CORE_PCINT2_PIN		PIN_B2

  241. #define CORE_PCINT3_PIN		PIN_B3

  242. #define CORE_PCINT4_PIN		PIN_B4

  243. #define CORE_PCINT5_PIN		PIN_B5

  244. #define CORE_PCINT6_PIN		PIN_B6

  245. #define CORE_PCINT7_PIN		PIN_B7

  246. #define CORE_LED0_PIN		PIN_D6

  247. #define CORE_PWM0_PIN		CORE_OC1C_PIN	// B7  4

  248. #define CORE_PWM1_PIN		CORE_OC0B_PIN	// D0  5

  249. #define CORE_PWM2_PIN		CORE_OC3A_PIN	// C6  9

  250. #define CORE_PWM3_PIN		CORE_OC4A_PIN	// C7  10

  251. #define CORE_PWM4_PIN		CORE_OC4D_PIN	// D7  12

  252. #define CORE_PWM5_PIN		CORE_OC1A_PIN	// B5  14

  253. #define CORE_PWM6_PIN		CORE_OC1B_PIN	// B6  15

  254. #define CORE_ANALOG0_PIN	PIN_F0	// 21  ADC0

  255. #define CORE_ANALOG1_PIN	PIN_F1	// 20  ADC1

  256. #define CORE_ANALOG2_PIN	PIN_F4	// 19  ADC4

  257. #define CORE_ANALOG3_PIN	PIN_F5	// 18  ADC5

  258. #define CORE_ANALOG4_PIN	PIN_F6	// 17  ADC6

  259. #define CORE_ANALOG5_PIN	PIN_F7	// 16  ADC7

  260. #define CORE_ANALOG6_PIN	PIN_B6	// 15  ADC13

  261. #define CORE_ANALOG7_PIN	PIN_B5	// 14  ADC12

  262. #define CORE_ANALOG8_PIN	PIN_B4	// 13  ADC11

  263. #define CORE_ANALOG9_PIN	PIN_D7	// 12  ADC10

  264. #define CORE_ANALOG10_PIN	PIN_D6  // 11  ADC9

  265. #define CORE_ANALOG11_PIN	PIN_D4	// 22  ADC8

  266. 

  267. 

  268. ////////////////////////////////////

  269. // Teensy 1.0

  270. ////////////////////////////////////

  271. #elif defined(__AVR_AT90USB162__)

  272. #define CORE_NUM_TOTAL_PINS	21

  273. #define CORE_NUM_DIGITAL	21

  274. #define CORE_NUM_ANALOG		0

  275. #define CORE_NUM_PWM		4

  276. #define CORE_NUM_INTERRUPT	8

  277. #define PIN_D0		0

  278. #define PIN_D1		1

  279. #define PIN_D2		2

  280. #define PIN_D3		3

  281. #define PIN_D4		4

  282. #define PIN_D5		5

  283. #define PIN_D6		6

  284. #define PIN_D7		7

  285. #define PIN_SS		8

  286. #define PIN_SCLK	9

  287. #define PIN_MOSI	10

  288. #define PIN_MISO	11

  289. #define PIN_B0		8

  290. #define PIN_B1		9

  291. #define PIN_B2		10

  292. #define PIN_B3		11

  293. #define PIN_B4		12

  294. #define PIN_B5		13

  295. #define PIN_B6		14

  296. #define PIN_B7		15

  297. #define PIN_C7		16

  298. #define PIN_C6		17

  299. #define PIN_C5		18

  300. #define PIN_C4		19

  301. #define PIN_C2		20

  302. #define CORE_PIN0_BIT		0

  303. #define CORE_PIN1_BIT		1

  304. #define CORE_PIN2_BIT		2

  305. #define CORE_PIN3_BIT		3

  306. #define CORE_PIN4_BIT		4

  307. #define CORE_PIN5_BIT		5

  308. #define CORE_PIN6_BIT		6

  309. #define CORE_PIN7_BIT		7

  310. #define CORE_PIN8_BIT		0

  311. #define CORE_PIN9_BIT		1

  312. #define CORE_PIN10_BIT		2

  313. #define CORE_PIN11_BIT		3

  314. #define CORE_PIN12_BIT		4

  315. #define CORE_PIN13_BIT		5

  316. #define CORE_PIN14_BIT		6

  317. #define CORE_PIN15_BIT		7

  318. #define CORE_PIN16_BIT		7

  319. #define CORE_PIN17_BIT		6

  320. #define CORE_PIN18_BIT		5

  321. #define CORE_PIN19_BIT		4

  322. #define CORE_PIN20_BIT		2

  323. #define CORE_PIN0_BITMASK	_BV(CORE_PIN0_BIT)

  324. #define CORE_PIN1_BITMASK	_BV(CORE_PIN1_BIT)

  325. #define CORE_PIN2_BITMASK	_BV(CORE_PIN2_BIT)

  326. #define CORE_PIN3_BITMASK	_BV(CORE_PIN3_BIT)

  327. #define CORE_PIN4_BITMASK	_BV(CORE_PIN4_BIT)

  328. #define CORE_PIN5_BITMASK	_BV(CORE_PIN5_BIT)

  329. #define CORE_PIN6_BITMASK	_BV(CORE_PIN6_BIT)

  330. #define CORE_PIN7_BITMASK	_BV(CORE_PIN7_BIT)

  331. #define CORE_PIN8_BITMASK	_BV(CORE_PIN8_BIT)

  332. #define CORE_PIN9_BITMASK	_BV(CORE_PIN9_BIT)

  333. #define CORE_PIN10_BITMASK	_BV(CORE_PIN10_BIT)

  334. #define CORE_PIN11_BITMASK	_BV(CORE_PIN11_BIT)

  335. #define CORE_PIN12_BITMASK	_BV(CORE_PIN12_BIT)

  336. #define CORE_PIN13_BITMASK	_BV(CORE_PIN13_BIT)

  337. #define CORE_PIN14_BITMASK	_BV(CORE_PIN14_BIT)

  338. #define CORE_PIN15_BITMASK	_BV(CORE_PIN15_BIT)

  339. #define CORE_PIN16_BITMASK	_BV(CORE_PIN16_BIT)

  340. #define CORE_PIN17_BITMASK	_BV(CORE_PIN17_BIT)

  341. #define CORE_PIN18_BITMASK	_BV(CORE_PIN18_BIT)

  342. #define CORE_PIN19_BITMASK	_BV(CORE_PIN19_BIT)

  343. #define CORE_PIN20_BITMASK	_BV(CORE_PIN20_BIT)

  344. #define CORE_PIN0_PORTREG	PORTD

  345. #define CORE_PIN1_PORTREG	PORTD

  346. #define CORE_PIN2_PORTREG	PORTD

  347. #define CORE_PIN3_PORTREG	PORTD

  348. #define CORE_PIN4_PORTREG	PORTD

  349. #define CORE_PIN5_PORTREG	PORTD

  350. #define CORE_PIN6_PORTREG	PORTD

  351. #define CORE_PIN7_PORTREG	PORTD

  352. #define CORE_PIN8_PORTREG	PORTB

  353. #define CORE_PIN9_PORTREG	PORTB

  354. #define CORE_PIN10_PORTREG	PORTB

  355. #define CORE_PIN11_PORTREG	PORTB

  356. #define CORE_PIN12_PORTREG	PORTB

  357. #define CORE_PIN13_PORTREG	PORTB

  358. #define CORE_PIN14_PORTREG	PORTB

  359. #define CORE_PIN15_PORTREG	PORTB

  360. #define CORE_PIN16_PORTREG	PORTC

  361. #define CORE_PIN17_PORTREG	PORTC

  362. #define CORE_PIN18_PORTREG	PORTC

  363. #define CORE_PIN19_PORTREG	PORTC

  364. #define CORE_PIN20_PORTREG	PORTC

  365. #define CORE_PIN0_DDRREG	DDRD

  366. #define CORE_PIN1_DDRREG	DDRD

  367. #define CORE_PIN2_DDRREG	DDRD

  368. #define CORE_PIN3_DDRREG	DDRD

  369. #define CORE_PIN4_DDRREG	DDRD

  370. #define CORE_PIN5_DDRREG	DDRD

  371. #define CORE_PIN6_DDRREG	DDRD

  372. #define CORE_PIN7_DDRREG	DDRD

  373. #define CORE_PIN8_DDRREG	DDRB

  374. #define CORE_PIN9_DDRREG	DDRB

  375. #define CORE_PIN10_DDRREG	DDRB

  376. #define CORE_PIN11_DDRREG	DDRB

  377. #define CORE_PIN12_DDRREG	DDRB

  378. #define CORE_PIN13_DDRREG	DDRB

  379. #define CORE_PIN14_DDRREG	DDRB

  380. #define CORE_PIN15_DDRREG	DDRB

  381. #define CORE_PIN16_DDRREG	DDRC

  382. #define CORE_PIN17_DDRREG	DDRC

  383. #define CORE_PIN18_DDRREG	DDRC

  384. #define CORE_PIN19_DDRREG	DDRC

  385. #define CORE_PIN20_DDRREG	DDRC

  386. #define CORE_PIN0_PINREG	PIND

  387. #define CORE_PIN1_PINREG	PIND

  388. #define CORE_PIN2_PINREG	PIND

  389. #define CORE_PIN3_PINREG	PIND

  390. #define CORE_PIN4_PINREG	PIND

  391. #define CORE_PIN5_PINREG	PIND

  392. #define CORE_PIN6_PINREG	PIND

  393. #define CORE_PIN7_PINREG	PIND

  394. #define CORE_PIN8_PINREG	PINB

  395. #define CORE_PIN9_PINREG	PINB

  396. #define CORE_PIN10_PINREG	PINB

  397. #define CORE_PIN11_PINREG	PINB

  398. #define CORE_PIN12_PINREG	PINB

  399. #define CORE_PIN13_PINREG	PINB

  400. #define CORE_PIN14_PINREG	PINB

  401. #define CORE_PIN15_PINREG	PINB

  402. #define CORE_PIN16_PINREG	PINC

  403. #define CORE_PIN17_PINREG	PINC

  404. #define CORE_PIN18_PINREG	PINC

  405. #define CORE_PIN19_PINREG	PINC

  406. #define CORE_PIN20_PINREG	PINC

  407. #define CORE_T1_PIN		PIN_B4

  408. #define CORE_ICP1_PIN		PIN_C7

  409. #define CORE_OC0A_PIN		PIN_B7

  410. #define CORE_OC0B_PIN		PIN_D0

  411. #define CORE_OC1A_PIN		PIN_C6

  412. #define CORE_OC1B_PIN		PIN_C5

  413. #define CORE_OC1C_PIN		PIN_B7

  414. #define CORE_RXD1_PIN		PIN_D2

  415. #define CORE_TXD1_PIN		PIN_D3

  416. #define CORE_XCK1_PIN		PIN_D5

  417. #define CORE_INT0_PIN		PIN_D0

  418. #define CORE_INT1_PIN		PIN_D1

  419. #define CORE_INT2_PIN		PIN_D2

  420. #define CORE_INT3_PIN		PIN_D3

  421. #define CORE_INT4_PIN		PIN_C2

  422. #define CORE_INT5_PIN		PIN_D4

  423. #define CORE_INT6_PIN		PIN_D6

  424. #define CORE_INT7_PIN		PIN_D7

  425. #define CORE_SS0_PIN		PIN_B0

  426. #define CORE_MOSI0_PIN		PIN_B2

  427. #define CORE_MISO0_PIN		PIN_B3

  428. #define CORE_SCLK0_PIN		PIN_B1

  429. #define CORE_AIN0_PIN		PIN_D1

  430. #define CORE_AIN1_PIN		PIN_D2

  431. #define CORE_PCINT0_PIN		PIN_B0

  432. #define CORE_PCINT1_PIN		PIN_B1

  433. #define CORE_PCINT2_PIN		PIN_B2

  434. #define CORE_PCINT3_PIN		PIN_B3

  435. #define CORE_PCINT4_PIN		PIN_B4

  436. #define CORE_PCINT5_PIN		PIN_B5

  437. #define CORE_PCINT6_PIN		PIN_B6

  438. #define CORE_PCINT7_PIN		PIN_B7

  439. #define CORE_PCINT8_PIN		PIN_C6

  440. #define CORE_PCINT9_PIN		PIN_C5

  441. #define CORE_PCINT10_PIN	PIN_C4

  442. #define CORE_PCINT11_PIN	PIN_C2

  443. #define CORE_PCINT12_PIN	PIN_D5

  444. #define CORE_LED0_PIN		PIN_D6

  445. #define CORE_PWM0_PIN		CORE_OC0B_PIN	// D0, 0

  446. #define CORE_PWM1_PIN		CORE_OC1C_PIN	// B7, 15

  447. #define CORE_PWM2_PIN		CORE_OC1A_PIN	// C6, 17

  448. #define CORE_PWM3_PIN		CORE_OC1B_PIN	// C5, 18

  449. 

  450. 

  451. ////////////////////////////////////

  452. // Teensy++ 1.0 & 2.0

  453. ////////////////////////////////////

  454. #elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  455. #define CORE_NUM_TOTAL_PINS	46

  456. #define CORE_NUM_DIGITAL	38

  457. #define CORE_NUM_ANALOG		8

  458. #define CORE_NUM_PWM		9

  459. #define CORE_NUM_INTERRUPT	8

  460. #define PIN_D0		0

  461. #define PIN_D1		1

  462. #define PIN_D2		2

  463. #define PIN_D3		3

  464. #define PIN_D4		4

  465. #define PIN_D5		5

  466. #define PIN_D6		6

  467. #define PIN_D7		7

  468. #define PIN_E0		8

  469. #define PIN_E1		9

  470. #define PIN_C0		10

  471. #define PIN_C1		11

  472. #define PIN_C2		12

  473. #define PIN_C3		13

  474. #define PIN_C4		14

  475. #define PIN_C5		15

  476. #define PIN_C6		16

  477. #define PIN_C7		17

  478. #define PIN_E6		18

  479. #define PIN_E7		19

  480. #define PIN_SS		20

  481. #define PIN_SCLK	21

  482. #define PIN_MOSI	22

  483. #define PIN_MISO	23

  484. #define PIN_B0		20

  485. #define PIN_B1		21

  486. #define PIN_B2		22

  487. #define PIN_B3		23

  488. #define PIN_B4		24

  489. #define PIN_B5		25

  490. #define PIN_B6		26

  491. #define PIN_B7		27

  492. #define PIN_A0		28

  493. #define PIN_A1		29

  494. #define PIN_A2		30

  495. #define PIN_A3		31

  496. #define PIN_A4		32

  497. #define PIN_A5		33

  498. #define PIN_A6		34

  499. #define PIN_A7		35

  500. #define PIN_E4		36

  501. #define PIN_E5		37

  502. #define PIN_F0		38

  503. #define PIN_F1		39

  504. #define PIN_F2		40

  505. #define PIN_F3		41

  506. #define PIN_F4		42

  507. #define PIN_F5		43

  508. #define PIN_F6		44

  509. #define PIN_F7		45

  510. #define CORE_PIN0_BIT		0

  511. #define CORE_PIN1_BIT		1

  512. #define CORE_PIN2_BIT		2

  513. #define CORE_PIN3_BIT		3

  514. #define CORE_PIN4_BIT		4

  515. #define CORE_PIN5_BIT		5

  516. #define CORE_PIN6_BIT		6

  517. #define CORE_PIN7_BIT		7

  518. #define CORE_PIN8_BIT		0

  519. #define CORE_PIN9_BIT		1

  520. #define CORE_PIN10_BIT		0

  521. #define CORE_PIN11_BIT		1

  522. #define CORE_PIN12_BIT		2

  523. #define CORE_PIN13_BIT		3

  524. #define CORE_PIN14_BIT		4

  525. #define CORE_PIN15_BIT		5

  526. #define CORE_PIN16_BIT		6

  527. #define CORE_PIN17_BIT		7

  528. #define CORE_PIN18_BIT		6

  529. #define CORE_PIN19_BIT		7

  530. #define CORE_PIN20_BIT		0

  531. #define CORE_PIN21_BIT		1

  532. #define CORE_PIN22_BIT		2

  533. #define CORE_PIN23_BIT		3

  534. #define CORE_PIN24_BIT		4

  535. #define CORE_PIN25_BIT		5

  536. #define CORE_PIN26_BIT		6

  537. #define CORE_PIN27_BIT		7

  538. #define CORE_PIN28_BIT		0

  539. #define CORE_PIN29_BIT		1

  540. #define CORE_PIN30_BIT		2

  541. #define CORE_PIN31_BIT		3

  542. #define CORE_PIN32_BIT		4

  543. #define CORE_PIN33_BIT		5

  544. #define CORE_PIN34_BIT		6

  545. #define CORE_PIN35_BIT		7

  546. #define CORE_PIN36_BIT		4

  547. #define CORE_PIN37_BIT		5

  548. #define CORE_PIN38_BIT		0

  549. #define CORE_PIN39_BIT		1

  550. #define CORE_PIN40_BIT		2

  551. #define CORE_PIN41_BIT		3

  552. #define CORE_PIN42_BIT		4

  553. #define CORE_PIN43_BIT		5

  554. #define CORE_PIN44_BIT		6

  555. #define CORE_PIN45_BIT		7

  556. #define CORE_PIN0_BITMASK	_BV(CORE_PIN0_BIT)

  557. #define CORE_PIN1_BITMASK	_BV(CORE_PIN1_BIT)

  558. #define CORE_PIN2_BITMASK	_BV(CORE_PIN2_BIT)

  559. #define CORE_PIN3_BITMASK	_BV(CORE_PIN3_BIT)

  560. #define CORE_PIN4_BITMASK	_BV(CORE_PIN4_BIT)

  561. #define CORE_PIN5_BITMASK	_BV(CORE_PIN5_BIT)

  562. #define CORE_PIN6_BITMASK	_BV(CORE_PIN6_BIT)

  563. #define CORE_PIN7_BITMASK	_BV(CORE_PIN7_BIT)

  564. #define CORE_PIN8_BITMASK	_BV(CORE_PIN8_BIT)

  565. #define CORE_PIN9_BITMASK	_BV(CORE_PIN9_BIT)

  566. #define CORE_PIN10_BITMASK	_BV(CORE_PIN10_BIT)

  567. #define CORE_PIN11_BITMASK	_BV(CORE_PIN11_BIT)

  568. #define CORE_PIN12_BITMASK	_BV(CORE_PIN12_BIT)

  569. #define CORE_PIN13_BITMASK	_BV(CORE_PIN13_BIT)

  570. #define CORE_PIN14_BITMASK	_BV(CORE_PIN14_BIT)

  571. #define CORE_PIN15_BITMASK	_BV(CORE_PIN15_BIT)

  572. #define CORE_PIN16_BITMASK	_BV(CORE_PIN16_BIT)

  573. #define CORE_PIN17_BITMASK	_BV(CORE_PIN17_BIT)

  574. #define CORE_PIN18_BITMASK	_BV(CORE_PIN18_BIT)

  575. #define CORE_PIN19_BITMASK	_BV(CORE_PIN19_BIT)

  576. #define CORE_PIN20_BITMASK	_BV(CORE_PIN20_BIT)

  577. #define CORE_PIN21_BITMASK	_BV(CORE_PIN21_BIT)

  578. #define CORE_PIN22_BITMASK	_BV(CORE_PIN22_BIT)

  579. #define CORE_PIN23_BITMASK	_BV(CORE_PIN23_BIT)

  580. #define CORE_PIN24_BITMASK	_BV(CORE_PIN24_BIT)

  581. #define CORE_PIN25_BITMASK	_BV(CORE_PIN25_BIT)

  582. #define CORE_PIN26_BITMASK	_BV(CORE_PIN26_BIT)

  583. #define CORE_PIN27_BITMASK	_BV(CORE_PIN27_BIT)

  584. #define CORE_PIN28_BITMASK	_BV(CORE_PIN28_BIT)

  585. #define CORE_PIN29_BITMASK	_BV(CORE_PIN29_BIT)

  586. #define CORE_PIN30_BITMASK	_BV(CORE_PIN30_BIT)

  587. #define CORE_PIN31_BITMASK	_BV(CORE_PIN31_BIT)

  588. #define CORE_PIN32_BITMASK	_BV(CORE_PIN32_BIT)

  589. #define CORE_PIN33_BITMASK	_BV(CORE_PIN33_BIT)

  590. #define CORE_PIN34_BITMASK	_BV(CORE_PIN34_BIT)

  591. #define CORE_PIN35_BITMASK	_BV(CORE_PIN35_BIT)

  592. #define CORE_PIN36_BITMASK	_BV(CORE_PIN36_BIT)

  593. #define CORE_PIN37_BITMASK	_BV(CORE_PIN37_BIT)

  594. #define CORE_PIN38_BITMASK	_BV(CORE_PIN38_BIT)

  595. #define CORE_PIN39_BITMASK	_BV(CORE_PIN39_BIT)

  596. #define CORE_PIN40_BITMASK	_BV(CORE_PIN40_BIT)

  597. #define CORE_PIN41_BITMASK	_BV(CORE_PIN41_BIT)

  598. #define CORE_PIN42_BITMASK	_BV(CORE_PIN42_BIT)

  599. #define CORE_PIN43_BITMASK	_BV(CORE_PIN43_BIT)

  600. #define CORE_PIN44_BITMASK	_BV(CORE_PIN44_BIT)

  601. #define CORE_PIN45_BITMASK	_BV(CORE_PIN45_BIT)

  602. #define CORE_PIN0_PORTREG	PORTD

  603. #define CORE_PIN1_PORTREG	PORTD

  604. #define CORE_PIN2_PORTREG	PORTD

  605. #define CORE_PIN3_PORTREG	PORTD

  606. #define CORE_PIN4_PORTREG	PORTD

  607. #define CORE_PIN5_PORTREG	PORTD

  608. #define CORE_PIN6_PORTREG	PORTD

  609. #define CORE_PIN7_PORTREG	PORTD

  610. #define CORE_PIN8_PORTREG	PORTE

  611. #define CORE_PIN9_PORTREG	PORTE

  612. #define CORE_PIN10_PORTREG	PORTC

  613. #define CORE_PIN11_PORTREG	PORTC

  614. #define CORE_PIN12_PORTREG	PORTC

  615. #define CORE_PIN13_PORTREG	PORTC

  616. #define CORE_PIN14_PORTREG	PORTC

  617. #define CORE_PIN15_PORTREG	PORTC

  618. #define CORE_PIN16_PORTREG	PORTC

  619. #define CORE_PIN17_PORTREG	PORTC

  620. #define CORE_PIN18_PORTREG	PORTE

  621. #define CORE_PIN19_PORTREG	PORTE

  622. #define CORE_PIN20_PORTREG	PORTB

  623. #define CORE_PIN21_PORTREG	PORTB

  624. #define CORE_PIN22_PORTREG	PORTB

  625. #define CORE_PIN23_PORTREG	PORTB

  626. #define CORE_PIN24_PORTREG	PORTB

  627. #define CORE_PIN25_PORTREG	PORTB

  628. #define CORE_PIN26_PORTREG	PORTB

  629. #define CORE_PIN27_PORTREG	PORTB

  630. #define CORE_PIN28_PORTREG	PORTA

  631. #define CORE_PIN29_PORTREG	PORTA

  632. #define CORE_PIN30_PORTREG	PORTA

  633. #define CORE_PIN31_PORTREG	PORTA

  634. #define CORE_PIN32_PORTREG	PORTA

  635. #define CORE_PIN33_PORTREG	PORTA

  636. #define CORE_PIN34_PORTREG	PORTA

  637. #define CORE_PIN35_PORTREG	PORTA

  638. #define CORE_PIN36_PORTREG	PORTE

  639. #define CORE_PIN37_PORTREG	PORTE

  640. #define CORE_PIN38_PORTREG	PORTF

  641. #define CORE_PIN39_PORTREG	PORTF

  642. #define CORE_PIN40_PORTREG	PORTF

  643. #define CORE_PIN41_PORTREG	PORTF

  644. #define CORE_PIN42_PORTREG	PORTF

  645. #define CORE_PIN43_PORTREG	PORTF

  646. #define CORE_PIN44_PORTREG	PORTF

  647. #define CORE_PIN45_PORTREG	PORTF

  648. #define CORE_PIN0_DDRREG	DDRD

  649. #define CORE_PIN1_DDRREG	DDRD

  650. #define CORE_PIN2_DDRREG	DDRD

  651. #define CORE_PIN3_DDRREG	DDRD

  652. #define CORE_PIN4_DDRREG	DDRD

  653. #define CORE_PIN5_DDRREG	DDRD

  654. #define CORE_PIN6_DDRREG	DDRD

  655. #define CORE_PIN7_DDRREG	DDRD

  656. #define CORE_PIN8_DDRREG	DDRE

  657. #define CORE_PIN9_DDRREG	DDRE

  658. #define CORE_PIN10_DDRREG	DDRC

  659. #define CORE_PIN11_DDRREG	DDRC

  660. #define CORE_PIN12_DDRREG	DDRC

  661. #define CORE_PIN13_DDRREG	DDRC

  662. #define CORE_PIN14_DDRREG	DDRC

  663. #define CORE_PIN15_DDRREG	DDRC

  664. #define CORE_PIN16_DDRREG	DDRC

  665. #define CORE_PIN17_DDRREG	DDRC

  666. #define CORE_PIN18_DDRREG	DDRE

  667. #define CORE_PIN19_DDRREG	DDRE

  668. #define CORE_PIN20_DDRREG	DDRB

  669. #define CORE_PIN21_DDRREG	DDRB

  670. #define CORE_PIN22_DDRREG	DDRB

  671. #define CORE_PIN23_DDRREG	DDRB

  672. #define CORE_PIN24_DDRREG	DDRB

  673. #define CORE_PIN25_DDRREG	DDRB

  674. #define CORE_PIN26_DDRREG	DDRB

  675. #define CORE_PIN27_DDRREG	DDRB

  676. #define CORE_PIN28_DDRREG	DDRA

  677. #define CORE_PIN29_DDRREG	DDRA

  678. #define CORE_PIN30_DDRREG	DDRA

  679. #define CORE_PIN31_DDRREG	DDRA

  680. #define CORE_PIN32_DDRREG	DDRA

  681. #define CORE_PIN33_DDRREG	DDRA

  682. #define CORE_PIN34_DDRREG	DDRA

  683. #define CORE_PIN35_DDRREG	DDRA

  684. #define CORE_PIN36_DDRREG	DDRE

  685. #define CORE_PIN37_DDRREG	DDRE

  686. #define CORE_PIN38_DDRREG	DDRF

  687. #define CORE_PIN39_DDRREG	DDRF

  688. #define CORE_PIN40_DDRREG	DDRF

  689. #define CORE_PIN41_DDRREG	DDRF

  690. #define CORE_PIN42_DDRREG	DDRF

  691. #define CORE_PIN43_DDRREG	DDRF

  692. #define CORE_PIN44_DDRREG	DDRF

  693. #define CORE_PIN45_DDRREG	DDRF

  694. #define CORE_PIN0_PINREG	PIND

  695. #define CORE_PIN1_PINREG	PIND

  696. #define CORE_PIN2_PINREG	PIND

  697. #define CORE_PIN3_PINREG	PIND

  698. #define CORE_PIN4_PINREG	PIND

  699. #define CORE_PIN5_PINREG	PIND

  700. #define CORE_PIN6_PINREG	PIND

  701. #define CORE_PIN7_PINREG	PIND

  702. #define CORE_PIN8_PINREG	PINE

  703. #define CORE_PIN9_PINREG	PINE

  704. #define CORE_PIN10_PINREG	PINC

  705. #define CORE_PIN11_PINREG	PINC

  706. #define CORE_PIN12_PINREG	PINC

  707. #define CORE_PIN13_PINREG	PINC

  708. #define CORE_PIN14_PINREG	PINC

  709. #define CORE_PIN15_PINREG	PINC

  710. #define CORE_PIN16_PINREG	PINC

  711. #define CORE_PIN17_PINREG	PINC

  712. #define CORE_PIN18_PINREG	PINE

  713. #define CORE_PIN19_PINREG	PINE

  714. #define CORE_PIN20_PINREG	PINB

  715. #define CORE_PIN21_PINREG	PINB

  716. #define CORE_PIN22_PINREG	PINB

  717. #define CORE_PIN23_PINREG	PINB

  718. #define CORE_PIN24_PINREG	PINB

  719. #define CORE_PIN25_PINREG	PINB

  720. #define CORE_PIN26_PINREG	PINB

  721. #define CORE_PIN27_PINREG	PINB

  722. #define CORE_PIN28_PINREG	PINA

  723. #define CORE_PIN29_PINREG	PINA

  724. #define CORE_PIN30_PINREG	PINA

  725. #define CORE_PIN31_PINREG	PINA

  726. #define CORE_PIN32_PINREG	PINA

  727. #define CORE_PIN33_PINREG	PINA

  728. #define CORE_PIN34_PINREG	PINA

  729. #define CORE_PIN35_PINREG	PINA

  730. #define CORE_PIN36_PINREG	PINE

  731. #define CORE_PIN37_PINREG	PINE

  732. #define CORE_PIN38_PINREG	PINF

  733. #define CORE_PIN39_PINREG	PINF

  734. #define CORE_PIN40_PINREG	PINF

  735. #define CORE_PIN41_PINREG	PINF

  736. #define CORE_PIN42_PINREG	PINF

  737. #define CORE_PIN43_PINREG	PINF

  738. #define CORE_PIN44_PINREG	PINF

  739. #define CORE_PIN45_PINREG	PINF

  740. #define CORE_ADC0_PIN		PIN_F0

  741. #define CORE_ADC1_PIN		PIN_F1

  742. #define CORE_ADC2_PIN		PIN_F2

  743. #define CORE_ADC3_PIN		PIN_F3

  744. #define CORE_ADC4_PIN		PIN_F4

  745. #define CORE_ADC5_PIN		PIN_F5

  746. #define CORE_ADC6_PIN		PIN_F6

  747. #define CORE_ADC7_PIN		PIN_F7

  748. #define CORE_RXD1_PIN           PIN_D2

  749. #define CORE_TXD1_PIN           PIN_D3

  750. #define CORE_XCK1_PIN           PIN_D5

  751. #define CORE_SDA0_PIN           PIN_D1

  752. #define CORE_SCL0_PIN           PIN_D0

  753. #define CORE_INT0_PIN           PIN_D0

  754. #define CORE_INT1_PIN           PIN_D1

  755. #define CORE_INT2_PIN           PIN_D2

  756. #define CORE_INT3_PIN           PIN_D3

  757. #define CORE_INT4_PIN           PIN_E4

  758. #define CORE_INT5_PIN           PIN_E5

  759. #define CORE_INT6_PIN           PIN_E6

  760. #define CORE_INT7_PIN           PIN_E7

  761. #define CORE_SS0_PIN            PIN_B0

  762. #define CORE_MOSI0_PIN          PIN_B2

  763. #define CORE_MISO0_PIN          PIN_B3

  764. #define CORE_SCLK0_PIN          PIN_B1

  765. #define CORE_T0_PIN             PIN_D7

  766. #define CORE_T1_PIN             PIN_D6

  767. #define CORE_ICP1_PIN           PIN_D4

  768. #define CORE_ICP3_PIN           PIN_C7

  769. #define CORE_OC0A_PIN           PIN_B7

  770. #define CORE_OC0B_PIN           PIN_D0

  771. #define CORE_OC1A_PIN           PIN_B5

  772. #define CORE_OC1B_PIN           PIN_B6

  773. #define CORE_OC1C_PIN           PIN_B7

  774. #define CORE_OC2A_PIN           PIN_B4

  775. #define CORE_OC2B_PIN           PIN_D1

  776. #define CORE_OC3A_PIN           PIN_C6

  777. #define CORE_OC3B_PIN           PIN_C5

  778. #define CORE_OC3C_PIN           PIN_C4

  779. #define CORE_PCINT0_PIN		PIN_B0

  780. #define CORE_PCINT1_PIN		PIN_B1

  781. #define CORE_PCINT2_PIN		PIN_B2

  782. #define CORE_PCINT3_PIN		PIN_B3

  783. #define CORE_PCINT4_PIN		PIN_B4

  784. #define CORE_PCINT5_PIN		PIN_B5

  785. #define CORE_PCINT6_PIN		PIN_B6

  786. #define CORE_PCINT7_PIN		PIN_B7

  787. #define CORE_LED0_PIN		PIN_D6

  788. #define CORE_PWM0_PIN		CORE_OC0B_PIN	// D0, 0

  789. #define CORE_PWM1_PIN		CORE_OC2B_PIN	// D1, 1

  790. #define CORE_PWM2_PIN		CORE_OC3C_PIN	// C4, 14

  791. #define CORE_PWM3_PIN		CORE_OC3B_PIN	// C5, 15

  792. #define CORE_PWM4_PIN		CORE_OC3A_PIN	// C6, 16

  793. #define CORE_PWM5_PIN		CORE_OC2A_PIN	// B4, 24

  794. #define CORE_PWM6_PIN		CORE_OC1A_PIN	// B5, 25

  795. #define CORE_PWM7_PIN		CORE_OC1B_PIN	// B6, 26

  796. #define CORE_PWM8_PIN		CORE_OC1C_PIN	// B7, 27

  797. #define CORE_ANALOG0_PIN	PIN_F0

  798. #define CORE_ANALOG1_PIN	PIN_F1

  799. #define CORE_ANALOG2_PIN	PIN_F2

  800. #define CORE_ANALOG3_PIN	PIN_F3

  801. #define CORE_ANALOG4_PIN	PIN_F4

  802. #define CORE_ANALOG5_PIN	PIN_F5

  803. #define CORE_ANALOG6_PIN	PIN_F6

  804. #define CORE_ANALOG7_PIN	PIN_F7

  805. 

  806. #endif

  807. 

  808. 

  809. #define CORE_BIT(pin) CORE_PIN_CONCATENATE(pin, BIT)

  810. #define CORE_BITMASK(pin) CORE_PIN_CONCATENATE(pin, BITMASK)

  811. #define CORE_PORTREG(pin) CORE_PIN_CONCATENATE(pin, PORTREG)

  812. #define CORE_DDRREG(pin) CORE_PIN_CONCATENATE(pin, DDRREG)

  813. #define CORE_PINREG(pin) CORE_PIN_CONCATENATE(pin, PINREG)

  814. #define CORE_PIN_CONCATENATE(pin, reg) (CORE_PIN ## pin ## _ ## reg)

  815. 

  816. #ifdef __cplusplus

  817. extern "C"{

  818. #endif

  819. 

  820. 

  821. extern void _digitalWrite(void);

  822. extern void _digitalWrite_HIGH(void);

  823. extern void _digitalWrite_LOW(void);

  824. 

  825. static inline void digitalWrite(uint8_t, uint8_t) __attribute__((always_inline, unused));

  826. static inline void digitalWrite(uint8_t pin, uint8_t val)

  827. {

  828. 	if (__builtin_constant_p(pin)) {

  829. 		if (val) {

  830. 			if (pin == 0) {

  831. 				CORE_PIN0_PORTREG |= CORE_PIN0_BITMASK;

  832. 			} else if (pin == 1) {

  833. 				CORE_PIN1_PORTREG |= CORE_PIN1_BITMASK;

  834. 			} else if (pin == 2) {

  835. 				CORE_PIN2_PORTREG |= CORE_PIN2_BITMASK;

  836. 			} else if (pin == 3) {

  837. 				CORE_PIN3_PORTREG |= CORE_PIN3_BITMASK;

  838. 			} else if (pin == 4) {

  839. 				CORE_PIN4_PORTREG |= CORE_PIN4_BITMASK;

  840. 			} else if (pin == 5) {

  841. 				CORE_PIN5_PORTREG |= CORE_PIN5_BITMASK;

  842. 			} else if (pin == 6) {

  843. 				CORE_PIN6_PORTREG |= CORE_PIN6_BITMASK;

  844. 			} else if (pin == 7) {

  845. 				CORE_PIN7_PORTREG |= CORE_PIN7_BITMASK;

  846. 			} else if (pin == 8) {

  847. 				CORE_PIN8_PORTREG |= CORE_PIN8_BITMASK;

  848. 			} else if (pin == 9) {

  849. 				CORE_PIN9_PORTREG |= CORE_PIN9_BITMASK;

  850. 			} else if (pin == 10) {

  851. 				CORE_PIN10_PORTREG |= CORE_PIN10_BITMASK;

  852. 			} else if (pin == 11) {

  853. 				CORE_PIN11_PORTREG |= CORE_PIN11_BITMASK;

  854. 			} else if (pin == 12) {

  855. 				CORE_PIN12_PORTREG |= CORE_PIN12_BITMASK;

  856. 			} else if (pin == 13) {

  857. 				CORE_PIN13_PORTREG |= CORE_PIN13_BITMASK;

  858. 			} else if (pin == 14) {

  859. 				CORE_PIN14_PORTREG |= CORE_PIN14_BITMASK;

  860. 			} else if (pin == 15) {

  861. 				CORE_PIN15_PORTREG |= CORE_PIN15_BITMASK;

  862. 			} else if (pin == 16) {

  863. 				CORE_PIN16_PORTREG |= CORE_PIN16_BITMASK;

  864. 			} else if (pin == 17) {

  865. 				CORE_PIN17_PORTREG |= CORE_PIN17_BITMASK;

  866. 			} else if (pin == 18) {

  867. 				CORE_PIN18_PORTREG |= CORE_PIN18_BITMASK;

  868. 			} else if (pin == 19) {

  869. 				CORE_PIN19_PORTREG |= CORE_PIN19_BITMASK;

  870. 			} else if (pin == 20) {

  871. 				CORE_PIN20_PORTREG |= CORE_PIN20_BITMASK;

  872. 			}

  873. 			#if CORE_NUM_TOTAL_PINS > 21

  874. 			  else if (pin == 21) {

  875. 				CORE_PIN21_PORTREG |= CORE_PIN21_BITMASK;

  876. 			} else if (pin == 22) {

  877. 				CORE_PIN22_PORTREG |= CORE_PIN22_BITMASK;

  878. 			} else if (pin == 23) {

  879. 				CORE_PIN23_PORTREG |= CORE_PIN23_BITMASK;

  880. 			} else if (pin == 24) {

  881. 				CORE_PIN24_PORTREG |= CORE_PIN24_BITMASK;

  882. 			}

  883. 			#endif

  884. 			#if CORE_NUM_TOTAL_PINS > 25

  885. 			  else if (pin == 25) {

  886. 				CORE_PIN25_PORTREG |= CORE_PIN25_BITMASK;

  887. 			} else if (pin == 26) {

  888. 				CORE_PIN26_PORTREG |= CORE_PIN26_BITMASK;

  889. 			} else if (pin == 27) {

  890. 				CORE_PIN27_PORTREG |= CORE_PIN27_BITMASK;

  891. 			} else if (pin == 28) {

  892. 				CORE_PIN28_PORTREG |= CORE_PIN28_BITMASK;

  893. 			} else if (pin == 29) {

  894. 				CORE_PIN29_PORTREG |= CORE_PIN29_BITMASK;

  895. 			} else if (pin == 30) {

  896. 				CORE_PIN30_PORTREG |= CORE_PIN30_BITMASK;

  897. 			} else if (pin == 31) {

  898. 				CORE_PIN31_PORTREG |= CORE_PIN31_BITMASK;

  899. 			} else if (pin == 32) {

  900. 				CORE_PIN32_PORTREG |= CORE_PIN32_BITMASK;

  901. 			} else if (pin == 33) {

  902. 				CORE_PIN33_PORTREG |= CORE_PIN33_BITMASK;

  903. 			} else if (pin == 34) {

  904. 				CORE_PIN34_PORTREG |= CORE_PIN34_BITMASK;

  905. 			} else if (pin == 35) {

  906. 				CORE_PIN35_PORTREG |= CORE_PIN35_BITMASK;

  907. 			} else if (pin == 36) {

  908. 				CORE_PIN36_PORTREG |= CORE_PIN36_BITMASK;

  909. 			} else if (pin == 37) {

  910. 				CORE_PIN37_PORTREG |= CORE_PIN37_BITMASK;

  911. 			} else if (pin == 38) {

  912. 				CORE_PIN38_PORTREG |= CORE_PIN38_BITMASK;

  913. 			} else if (pin == 39) {

  914. 				CORE_PIN39_PORTREG |= CORE_PIN39_BITMASK;

  915. 			} else if (pin == 40) {

  916. 				CORE_PIN40_PORTREG |= CORE_PIN40_BITMASK;

  917. 			} else if (pin == 41) {

  918. 				CORE_PIN41_PORTREG |= CORE_PIN41_BITMASK;

  919. 			} else if (pin == 42) {

  920. 				CORE_PIN42_PORTREG |= CORE_PIN42_BITMASK;

  921. 			} else if (pin == 43) {

  922. 				CORE_PIN43_PORTREG |= CORE_PIN43_BITMASK;

  923. 			} else if (pin == 44) {

  924. 				CORE_PIN44_PORTREG |= CORE_PIN44_BITMASK;

  925. 			} else if (pin == 45) {

  926. 				CORE_PIN45_PORTREG |= CORE_PIN45_BITMASK;

  927. 			}

  928. 			#endif

  929. 		} else {

  930. 			if (pin == 0) {

  931. 				CORE_PIN0_PORTREG &= ~CORE_PIN0_BITMASK;

  932. 			} else if (pin == 1) {

  933. 				CORE_PIN1_PORTREG &= ~CORE_PIN1_BITMASK;

  934. 			} else if (pin == 2) {

  935. 				CORE_PIN2_PORTREG &= ~CORE_PIN2_BITMASK;

  936. 			} else if (pin == 3) {

  937. 				CORE_PIN3_PORTREG &= ~CORE_PIN3_BITMASK;

  938. 			} else if (pin == 4) {

  939. 				CORE_PIN4_PORTREG &= ~CORE_PIN4_BITMASK;

  940. 			} else if (pin == 5) {

  941. 				CORE_PIN5_PORTREG &= ~CORE_PIN5_BITMASK;

  942. 			} else if (pin == 6) {

  943. 				CORE_PIN6_PORTREG &= ~CORE_PIN6_BITMASK;

  944. 			} else if (pin == 7) {

  945. 				CORE_PIN7_PORTREG &= ~CORE_PIN7_BITMASK;

  946. 			} else if (pin == 8) {

  947. 				CORE_PIN8_PORTREG &= ~CORE_PIN8_BITMASK;

  948. 			} else if (pin == 9) {

  949. 				CORE_PIN9_PORTREG &= ~CORE_PIN9_BITMASK;

  950. 			} else if (pin == 10) {

  951. 				CORE_PIN10_PORTREG &= ~CORE_PIN10_BITMASK;

  952. 			} else if (pin == 11) {

  953. 				CORE_PIN11_PORTREG &= ~CORE_PIN11_BITMASK;

  954. 			} else if (pin == 12) {

  955. 				CORE_PIN12_PORTREG &= ~CORE_PIN12_BITMASK;

  956. 			} else if (pin == 13) {

  957. 				CORE_PIN13_PORTREG &= ~CORE_PIN13_BITMASK;

  958. 			} else if (pin == 14) {

  959. 				CORE_PIN14_PORTREG &= ~CORE_PIN14_BITMASK;

  960. 			} else if (pin == 15) {

  961. 				CORE_PIN15_PORTREG &= ~CORE_PIN15_BITMASK;

  962. 			} else if (pin == 16) {

  963. 				CORE_PIN16_PORTREG &= ~CORE_PIN16_BITMASK;

  964. 			} else if (pin == 17) {

  965. 				CORE_PIN17_PORTREG &= ~CORE_PIN17_BITMASK;

  966. 			} else if (pin == 18) {

  967. 				CORE_PIN18_PORTREG &= ~CORE_PIN18_BITMASK;

  968. 			} else if (pin == 19) {

  969. 				CORE_PIN19_PORTREG &= ~CORE_PIN19_BITMASK;

  970. 			} else if (pin == 20) {

  971. 				CORE_PIN20_PORTREG &= ~CORE_PIN20_BITMASK;

  972. 			}

  973. 			#if CORE_NUM_TOTAL_PINS > 21

  974. 			  else if (pin == 21) {

  975. 				CORE_PIN21_PORTREG &= ~CORE_PIN21_BITMASK;

  976. 			} else if (pin == 22) {

  977. 				CORE_PIN22_PORTREG &= ~CORE_PIN22_BITMASK;

  978. 			} else if (pin == 23) {

  979. 				CORE_PIN23_PORTREG &= ~CORE_PIN23_BITMASK;

  980. 			} else if (pin == 24) {

  981. 				CORE_PIN24_PORTREG &= ~CORE_PIN24_BITMASK;

  982. 			}

  983. 			#endif

  984. 			#if CORE_NUM_TOTAL_PINS > 25

  985. 			  else if (pin == 25) {

  986. 				CORE_PIN25_PORTREG &= ~CORE_PIN25_BITMASK;

  987. 			} else if (pin == 26) {

  988. 				CORE_PIN26_PORTREG &= ~CORE_PIN26_BITMASK;

  989. 			} else if (pin == 27) {

  990. 				CORE_PIN27_PORTREG &= ~CORE_PIN27_BITMASK;

  991. 			} else if (pin == 28) {

  992. 				CORE_PIN28_PORTREG &= ~CORE_PIN28_BITMASK;

  993. 			} else if (pin == 29) {

  994. 				CORE_PIN29_PORTREG &= ~CORE_PIN29_BITMASK;

  995. 			} else if (pin == 30) {

  996. 				CORE_PIN30_PORTREG &= ~CORE_PIN30_BITMASK;

  997. 			} else if (pin == 31) {

  998. 				CORE_PIN31_PORTREG &= ~CORE_PIN31_BITMASK;

  999. 			} else if (pin == 32) {

  1000. 				CORE_PIN32_PORTREG &= ~CORE_PIN32_BITMASK;

  1001. 			} else if (pin == 33) {

  1002. 				CORE_PIN33_PORTREG &= ~CORE_PIN33_BITMASK;

  1003. 			} else if (pin == 34) {

  1004. 				CORE_PIN34_PORTREG &= ~CORE_PIN34_BITMASK;

  1005. 			} else if (pin == 35) {

  1006. 				CORE_PIN35_PORTREG &= ~CORE_PIN35_BITMASK;

  1007. 			} else if (pin == 36) {

  1008. 				CORE_PIN36_PORTREG &= ~CORE_PIN36_BITMASK;

  1009. 			} else if (pin == 37) {

  1010. 				CORE_PIN37_PORTREG &= ~CORE_PIN37_BITMASK;

  1011. 			} else if (pin == 38) {

  1012. 				CORE_PIN38_PORTREG &= ~CORE_PIN38_BITMASK;

  1013. 			} else if (pin == 39) {

  1014. 				CORE_PIN39_PORTREG &= ~CORE_PIN39_BITMASK;

  1015. 			} else if (pin == 40) {

  1016. 				CORE_PIN40_PORTREG &= ~CORE_PIN40_BITMASK;

  1017. 			} else if (pin == 41) {

  1018. 				CORE_PIN41_PORTREG &= ~CORE_PIN41_BITMASK;

  1019. 			} else if (pin == 42) {

  1020. 				CORE_PIN42_PORTREG &= ~CORE_PIN42_BITMASK;

  1021. 			} else if (pin == 43) {

  1022. 				CORE_PIN43_PORTREG &= ~CORE_PIN43_BITMASK;

  1023. 			} else if (pin == 44) {

  1024. 				CORE_PIN44_PORTREG &= ~CORE_PIN44_BITMASK;

  1025. 			} else if (pin == 45) {

  1026. 				CORE_PIN45_PORTREG &= ~CORE_PIN45_BITMASK;

  1027. 			}

  1028. 			#endif

  1029. 		}

  1030. 		if (pin == CORE_OC0B_PIN) {

  1031. 			_SFR_BYTE(TCCR0A) &= ~(1<<COM0B1);

  1032. 		} else if (pin == CORE_OC1A_PIN) {

  1033. 			TCCR1A &= ~(1<<COM1A1);

  1034. 		} else if (pin == CORE_OC1B_PIN) {

  1035. 			TCCR1A &= ~(1<<COM1B1);

  1036. 		} else if (pin == CORE_OC1C_PIN) {

  1037. 			TCCR1A &= ~(1<<COM1C1);

  1038. 		}

  1039. 		#if defined(__AVR_ATmega32U4__)

  1040. 		  else if (pin == CORE_OC3A_PIN) {

  1041. 			TCCR3A &= ~(1<<COM3A1);

  1042. 		} else if (pin == CORE_OC4A_PIN) {

  1043. 			TCCR4A &= ~(1<<COM4A1);

  1044. 		} else if (pin == CORE_OC4D_PIN) {

  1045. 			TCCR4C &= ~(1<<COM4D1);

  1046. 		}

  1047. 		#endif

  1048. 		#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  1049. 		  else if (pin == CORE_OC2A_PIN) {

  1050. 			TCCR2A &= ~(1<<COM2A1);

  1051. 		} else if (pin == CORE_OC2B_PIN) {

  1052. 			TCCR2A &= ~(1<<COM2B1);

  1053. 		} else if (pin == CORE_OC3A_PIN) {

  1054. 			TCCR3A &= ~(1<<COM3A1);

  1055. 		} else if (pin == CORE_OC3B_PIN) {

  1056. 			TCCR3A &= ~(1<<COM3B1);

  1057. 		} else if (pin == CORE_OC3C_PIN) {

  1058. 			TCCR3A &= ~(1<<COM3C1);

  1059. 		}

  1060. 		#endif

  1061. 	} else {

  1062. 		if (__builtin_constant_p(val)) {

  1063. 			if (val) {

  1064. 				uint16_t tmp = (pin);

  1065. 				asm volatile(

  1066. 					#if defined(DIGITAL_WRITE_EXPENSIVE_INLINE_OPTIMIZATION)

  1067. 					#if !defined(DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK)

  1068. 					"cpi	r30, %1"					"\n\t"

  1069. 					"brsh	L%=end1"					"\n\t"

  1070. 					#endif

  1071. 					"lsl	r30"						"\n\t"

  1072. 					//"clr	r31"						"\n\t"

  1073. 					"subi	r30, lo8(-(pm(_digitalWrite_HIGH_TABLE)))"	"\n\t"

  1074. 					"sbci	r31, hi8(-(pm(_digitalWrite_HIGH_TABLE)))"	"\n\t"

  1075. 					"icall"							"\n\t"

  1076. 					"L%=end1:"						"\n"

  1077. 					#else

  1078. 					"call _digitalWrite_HIGH"

  1079. 					#endif

  1080. 					: "+z" (tmp)

  1081. 					: "I" (CORE_NUM_TOTAL_PINS)

  1082. 				);

  1083. 			} else {

  1084. 				uint16_t tmp = (pin);

  1085. 				asm volatile(

  1086. 					#if defined(DIGITAL_WRITE_EXPENSIVE_INLINE_OPTIMIZATION)

  1087. 					#if !defined(DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK)

  1088. 					"cpi	r30, %1"					"\n\t"

  1089. 					"brsh	L%=end2"					"\n\t"

  1090. 					#endif

  1091. 					"lsl	r30"						"\n\t"

  1092. 					//"clr	r31"						"\n\t"

  1093. 					"subi	r30, lo8(-(pm(_digitalWrite_LOW_TABLE)))"	"\n\t"

  1094. 					"sbci	r31, hi8(-(pm(_digitalWrite_LOW_TABLE)))"	"\n\t"

  1095. 					"icall"							"\n\t"

  1096. 					"L%=end2:"						"\n"

  1097. 					#else

  1098. 					"call _digitalWrite_LOW"

  1099. 					#endif

  1100. 					: "+z" (tmp)

  1101. 					: "I" (CORE_NUM_TOTAL_PINS)

  1102. 				);

  1103. 			}

  1104. 		} else {

  1105. 			uint16_t tmp1 = (pin);

  1106. 			uint8_t tmp2 = (val);

  1107. 			asm volatile(

  1108. 				#if defined(DIGITAL_WRITE_EXPENSIVE_INLINE_OPTIMIZATION)

  1109. 				#if !defined(DIGITAL_WRITE_RISKY_OMIT_OVERFLOW_CHECK)

  1110. 				"cpi	%0, %2"						"\n\t"

  1111. 				"brsh	L%=end3"					"\n\t"

  1112. 				#endif

  1113. 				"lsl	r30"						"\n\t"

  1114. 				//"clr	r31"						"\n\t"

  1115. 				"tst	%1"						"\n\t"

  1116. 				"breq	L%=low"						"\n\t"

  1117. 				"subi	r30, lo8(-(pm(_digitalWrite_HIGH_TABLE)))"	"\n\t"

  1118. 				"sbci	r31, hi8(-(pm(_digitalWrite_HIGH_TABLE)))"	"\n\t"

  1119. 				"icall"							"\n\t"

  1120. 				"rjmp	L%=end3"					"\n\t"

  1121. 				"L%=low:"						"\n\t"

  1122. 				"subi	r30, lo8(-(pm(_digitalWrite_LOW_TABLE)))"	"\n\t"

  1123. 				"sbci	r31, hi8(-(pm(_digitalWrite_LOW_TABLE)))"	"\n\t"

  1124. 				"icall"							"\n\t"

  1125. 				"L%=end3:"						"\n\t"

  1126. 				: "+z" (tmp1)

  1127. 				: "d" (tmp2), "I" (CORE_NUM_TOTAL_PINS)

  1128. 				#else

  1129. 				"mov __tmp_reg__, %1"  "\n\t"

  1130. 				"call _digitalWrite"

  1131. 				: "+z" (tmp1)

  1132. 				: "r" (tmp2)

  1133. 				#endif

  1134. 			);

  1135. 		}

  1136. 	}

  1137. }

  1138. 

  1139. extern void _digitalRead(void) __attribute__((noinline));

  1140. 

  1141. static inline uint8_t digitalRead(uint8_t) __attribute__((always_inline, unused));

  1142. static inline uint8_t digitalRead(uint8_t pin)

  1143. {

  1144. 	if (__builtin_constant_p(pin)) {

  1145. 		if (pin == 0) {

  1146. 			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;

  1147. 		} else if (pin == 1) {

  1148. 			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;

  1149. 		} else if (pin == 2) {

  1150. 			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;

  1151. 		} else if (pin == 3) {

  1152. 			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;

  1153. 		} else if (pin == 4) {

  1154. 			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;

  1155. 		} else if (pin == 5) {

  1156. 			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;

  1157. 		} else if (pin == 6) {

  1158. 			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;

  1159. 		} else if (pin == 7) {

  1160. 			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;

  1161. 		} else if (pin == 8) {

  1162. 			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;

  1163. 		} else if (pin == 9) {

  1164. 			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;

  1165. 		} else if (pin == 10) {

  1166. 			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;

  1167. 		} else if (pin == 11) {

  1168. 			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;

  1169. 		} else if (pin == 12) {

  1170. 			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;

  1171. 		} else if (pin == 13) {

  1172. 			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;

  1173. 		} else if (pin == 14) {

  1174. 			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;

  1175. 		} else if (pin == 15) {

  1176. 			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;

  1177. 		} else if (pin == 16) {

  1178. 			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;

  1179. 		} else if (pin == 17) {

  1180. 			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;

  1181. 		} else if (pin == 18) {

  1182. 			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;

  1183. 		} else if (pin == 19) {

  1184. 			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;

  1185. 		} else if (pin == 20) {

  1186. 			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;

  1187. 		}

  1188. 		#if CORE_NUM_TOTAL_PINS > 21

  1189. 		  else if (pin == 21) {

  1190. 			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;

  1191. 		} else if (pin == 22) {

  1192. 			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;

  1193. 		} else if (pin == 23) {

  1194. 			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;

  1195. 		} else if (pin == 24) {

  1196. 			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;

  1197. 		}

  1198. 		#endif

  1199. 		#if CORE_NUM_TOTAL_PINS > 25

  1200. 		  else if (pin == 25) {

  1201. 			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;

  1202. 		} else if (pin == 26) {

  1203. 			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;

  1204. 		} else if (pin == 27) {

  1205. 			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;

  1206. 		} else if (pin == 28) {

  1207. 			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;

  1208. 		} else if (pin == 29) {

  1209. 			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;

  1210. 		} else if (pin == 30) {

  1211. 			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;

  1212. 		} else if (pin == 31) {

  1213. 			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;

  1214. 		} else if (pin == 32) {

  1215. 			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;

  1216. 		} else if (pin == 33) {

  1217. 			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;

  1218. 		} else if (pin == 34) {

  1219. 			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;

  1220. 		} else if (pin == 35) {

  1221. 			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;

  1222. 		} else if (pin == 36) {

  1223. 			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;

  1224. 		} else if (pin == 37) {

  1225. 			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;

  1226. 		} else if (pin == 38) {

  1227. 			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;

  1228. 		} else if (pin == 39) {

  1229. 			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;

  1230. 		} else if (pin == 40) {

  1231. 			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;

  1232. 		} else if (pin == 41) {

  1233. 			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;

  1234. 		} else if (pin == 42) {

  1235. 			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;

  1236. 		} else if (pin == 43) {

  1237. 			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;

  1238. 		} else if (pin == 44) {

  1239. 			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;

  1240. 		} else if (pin == 45) {

  1241. 			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;

  1242. 		}

  1243. 		#endif

  1244. 		  else {

  1245. 			return 0;

  1246. 		}

  1247. 	} else {

  1248. 		uint16_t tmp = (pin);

  1249. 		asm volatile(

  1250. 			"call _digitalRead"

  1251. 			: "+z" (tmp)

  1252. 			:);

  1253. 		return (uint8_t)tmp;

  1254. 	}

  1255. }

  1256. 

  1257. extern void _pinMode(uint8_t pin, uint8_t mode) __attribute__((noinline));

  1258. extern void _pinMode_output(uint8_t pin) __attribute__((noinline));

  1259. extern void _pinMode_input(uint8_t pin) __attribute__((noinline));

  1260. extern void _pinMode_input_pullup(uint8_t pin) __attribute__((noinline));

  1261. 

  1262. static inline void pinMode(uint8_t, uint8_t) __attribute__((always_inline, unused));

  1263. static inline void pinMode(uint8_t pin, uint8_t mode)

  1264. {

  1265. 	if (__builtin_constant_p(pin) && __builtin_constant_p(mode)) {

  1266. 		if (mode == OUTPUT) {

  1267. 			if (pin == 0) {

  1268. 				CORE_PIN0_DDRREG |= CORE_PIN0_BITMASK;

  1269. 			} else if (pin == 1) {

  1270. 				CORE_PIN1_DDRREG |= CORE_PIN1_BITMASK;

  1271. 			} else if (pin == 2) {

  1272. 				CORE_PIN2_DDRREG |= CORE_PIN2_BITMASK;

  1273. 			} else if (pin == 3) {

  1274. 				CORE_PIN3_DDRREG |= CORE_PIN3_BITMASK;

  1275. 			} else if (pin == 4) {

  1276. 				CORE_PIN4_DDRREG |= CORE_PIN4_BITMASK;

  1277. 			} else if (pin == 5) {

  1278. 				CORE_PIN5_DDRREG |= CORE_PIN5_BITMASK;

  1279. 			} else if (pin == 6) {

  1280. 				CORE_PIN6_DDRREG |= CORE_PIN6_BITMASK;

  1281. 			} else if (pin == 7) {

  1282. 				CORE_PIN7_DDRREG |= CORE_PIN7_BITMASK;

  1283. 			} else if (pin == 8) {

  1284. 				CORE_PIN8_DDRREG |= CORE_PIN8_BITMASK;

  1285. 			} else if (pin == 9) {

  1286. 				CORE_PIN9_DDRREG |= CORE_PIN9_BITMASK;

  1287. 			} else if (pin == 10) {

  1288. 				CORE_PIN10_DDRREG |= CORE_PIN10_BITMASK;

  1289. 			} else if (pin == 11) {

  1290. 				CORE_PIN11_DDRREG |= CORE_PIN11_BITMASK;

  1291. 			} else if (pin == 12) {

  1292. 				CORE_PIN12_DDRREG |= CORE_PIN12_BITMASK;

  1293. 			} else if (pin == 13) {

  1294. 				CORE_PIN13_DDRREG |= CORE_PIN13_BITMASK;

  1295. 			} else if (pin == 14) {

  1296. 				CORE_PIN14_DDRREG |= CORE_PIN14_BITMASK;

  1297. 			} else if (pin == 15) {

  1298. 				CORE_PIN15_DDRREG |= CORE_PIN15_BITMASK;

  1299. 			} else if (pin == 16) {

  1300. 				CORE_PIN16_DDRREG |= CORE_PIN16_BITMASK;

  1301. 			} else if (pin == 17) {

  1302. 				CORE_PIN17_DDRREG |= CORE_PIN17_BITMASK;

  1303. 			} else if (pin == 18) {

  1304. 				CORE_PIN18_DDRREG |= CORE_PIN18_BITMASK;

  1305. 			} else if (pin == 19) {

  1306. 				CORE_PIN19_DDRREG |= CORE_PIN19_BITMASK;

  1307. 			} else if (pin == 20) {

  1308. 				CORE_PIN20_DDRREG |= CORE_PIN20_BITMASK;

  1309. 			}

  1310. 			#if CORE_NUM_TOTAL_PINS > 21

  1311. 			  else if (pin == 21) {

  1312. 				CORE_PIN21_DDRREG |= CORE_PIN21_BITMASK;

  1313. 			} else if (pin == 22) {

  1314. 				CORE_PIN22_DDRREG |= CORE_PIN22_BITMASK;

  1315. 			} else if (pin == 23) {

  1316. 				CORE_PIN23_DDRREG |= CORE_PIN23_BITMASK;

  1317. 			} else if (pin == 24) {

  1318. 				CORE_PIN24_DDRREG |= CORE_PIN24_BITMASK;

  1319. 			}

  1320. 			#endif

  1321. 			#if CORE_NUM_TOTAL_PINS > 25

  1322. 			  else if (pin == 25) {

  1323. 				CORE_PIN25_DDRREG |= CORE_PIN25_BITMASK;

  1324. 			} else if (pin == 26) {

  1325. 				CORE_PIN26_DDRREG |= CORE_PIN26_BITMASK;

  1326. 			} else if (pin == 27) {

  1327. 				CORE_PIN27_DDRREG |= CORE_PIN27_BITMASK;

  1328. 			} else if (pin == 28) {

  1329. 				CORE_PIN28_DDRREG |= CORE_PIN28_BITMASK;

  1330. 			} else if (pin == 29) {

  1331. 				CORE_PIN29_DDRREG |= CORE_PIN29_BITMASK;

  1332. 			} else if (pin == 30) {

  1333. 				CORE_PIN30_DDRREG |= CORE_PIN30_BITMASK;

  1334. 			} else if (pin == 31) {

  1335. 				CORE_PIN31_DDRREG |= CORE_PIN31_BITMASK;

  1336. 			} else if (pin == 32) {

  1337. 				CORE_PIN32_DDRREG |= CORE_PIN32_BITMASK;

  1338. 			} else if (pin == 33) {

  1339. 				CORE_PIN33_DDRREG |= CORE_PIN33_BITMASK;

  1340. 			} else if (pin == 34) {

  1341. 				CORE_PIN34_DDRREG |= CORE_PIN34_BITMASK;

  1342. 			} else if (pin == 35) {

  1343. 				CORE_PIN35_DDRREG |= CORE_PIN35_BITMASK;

  1344. 			} else if (pin == 36) {

  1345. 				CORE_PIN36_DDRREG |= CORE_PIN36_BITMASK;

  1346. 			} else if (pin == 37) {

  1347. 				CORE_PIN37_DDRREG |= CORE_PIN37_BITMASK;

  1348. 			} else if (pin == 38) {

  1349. 				CORE_PIN38_DDRREG |= CORE_PIN38_BITMASK;

  1350. 			} else if (pin == 39) {

  1351. 				CORE_PIN39_DDRREG |= CORE_PIN39_BITMASK;

  1352. 			} else if (pin == 40) {

  1353. 				CORE_PIN40_DDRREG |= CORE_PIN40_BITMASK;

  1354. 			} else if (pin == 41) {

  1355. 				CORE_PIN41_DDRREG |= CORE_PIN41_BITMASK;

  1356. 			} else if (pin == 42) {

  1357. 				CORE_PIN42_DDRREG |= CORE_PIN42_BITMASK;

  1358. 			} else if (pin == 43) {

  1359. 				CORE_PIN43_DDRREG |= CORE_PIN43_BITMASK;

  1360. 			} else if (pin == 44) {

  1361. 				CORE_PIN44_DDRREG |= CORE_PIN44_BITMASK;

  1362. 			} else if (pin == 45) {

  1363. 				CORE_PIN45_DDRREG |= CORE_PIN45_BITMASK;

  1364. 			}

  1365. 			#endif

  1366. 		} else if (mode == INPUT_PULLUP) {

  1367. 			if (pin == 0) {

  1368. 				CORE_PIN0_DDRREG  &= ~CORE_PIN0_BITMASK;

  1369. 				CORE_PIN0_PORTREG |=  CORE_PIN0_BITMASK;

  1370. 			} else if (pin == 1) {

  1371. 				CORE_PIN1_DDRREG  &= ~CORE_PIN1_BITMASK;

  1372. 				CORE_PIN1_PORTREG |=  CORE_PIN1_BITMASK;

  1373. 			} else if (pin == 2) {

  1374. 				CORE_PIN2_DDRREG  &= ~CORE_PIN2_BITMASK;

  1375. 				CORE_PIN2_PORTREG |=  CORE_PIN2_BITMASK;

  1376. 			} else if (pin == 3) {

  1377. 				CORE_PIN3_DDRREG  &= ~CORE_PIN3_BITMASK;

  1378. 				CORE_PIN3_PORTREG |=  CORE_PIN3_BITMASK;

  1379. 			} else if (pin == 4) {

  1380. 				CORE_PIN4_DDRREG  &= ~CORE_PIN4_BITMASK;

  1381. 				CORE_PIN4_PORTREG |=  CORE_PIN4_BITMASK;

  1382. 			} else if (pin == 5) {

  1383. 				CORE_PIN5_DDRREG  &= ~CORE_PIN5_BITMASK;

  1384. 				CORE_PIN5_PORTREG |=  CORE_PIN5_BITMASK;

  1385. 			} else if (pin == 6) {

  1386. 				CORE_PIN6_DDRREG  &= ~CORE_PIN6_BITMASK;

  1387. 				CORE_PIN6_PORTREG |=  CORE_PIN6_BITMASK;

  1388. 			} else if (pin == 7) {

  1389. 				CORE_PIN7_DDRREG  &= ~CORE_PIN7_BITMASK;

  1390. 				CORE_PIN7_PORTREG |=  CORE_PIN7_BITMASK;

  1391. 			} else if (pin == 8) {

  1392. 				CORE_PIN8_DDRREG  &= ~CORE_PIN8_BITMASK;

  1393. 				CORE_PIN8_PORTREG |=  CORE_PIN8_BITMASK;

  1394. 			} else if (pin == 9) {

  1395. 				CORE_PIN9_DDRREG  &= ~CORE_PIN9_BITMASK;

  1396. 				CORE_PIN9_PORTREG |=  CORE_PIN9_BITMASK;

  1397. 			} else if (pin == 10) {

  1398. 				CORE_PIN10_DDRREG  &= ~CORE_PIN10_BITMASK;

  1399. 				CORE_PIN10_PORTREG |=  CORE_PIN10_BITMASK;

  1400. 			} else if (pin == 11) {

  1401. 				CORE_PIN11_DDRREG  &= ~CORE_PIN11_BITMASK;

  1402. 				CORE_PIN11_PORTREG |=  CORE_PIN11_BITMASK;

  1403. 			} else if (pin == 12) {

  1404. 				CORE_PIN12_DDRREG  &= ~CORE_PIN12_BITMASK;

  1405. 				CORE_PIN12_PORTREG |=  CORE_PIN12_BITMASK;

  1406. 			} else if (pin == 13) {

  1407. 				CORE_PIN13_DDRREG  &= ~CORE_PIN13_BITMASK;

  1408. 				CORE_PIN13_PORTREG |=  CORE_PIN13_BITMASK;

  1409. 			} else if (pin == 14) {

  1410. 				CORE_PIN14_DDRREG  &= ~CORE_PIN14_BITMASK;

  1411. 				CORE_PIN14_PORTREG |=  CORE_PIN14_BITMASK;

  1412. 			} else if (pin == 15) {

  1413. 				CORE_PIN15_DDRREG  &= ~CORE_PIN15_BITMASK;

  1414. 				CORE_PIN15_PORTREG |=  CORE_PIN15_BITMASK;

  1415. 			} else if (pin == 16) {

  1416. 				CORE_PIN16_DDRREG  &= ~CORE_PIN16_BITMASK;

  1417. 				CORE_PIN16_PORTREG |=  CORE_PIN16_BITMASK;

  1418. 			} else if (pin == 17) {

  1419. 				CORE_PIN17_DDRREG  &= ~CORE_PIN17_BITMASK;

  1420. 				CORE_PIN17_PORTREG |=  CORE_PIN17_BITMASK;

  1421. 			} else if (pin == 18) {

  1422. 				CORE_PIN18_DDRREG  &= ~CORE_PIN18_BITMASK;

  1423. 				CORE_PIN18_PORTREG |=  CORE_PIN18_BITMASK;

  1424. 			} else if (pin == 19) {

  1425. 				CORE_PIN19_DDRREG  &= ~CORE_PIN19_BITMASK;

  1426. 				CORE_PIN19_PORTREG |=  CORE_PIN19_BITMASK;

  1427. 			} else if (pin == 20) {

  1428. 				CORE_PIN20_DDRREG  &= ~CORE_PIN20_BITMASK;

  1429. 				CORE_PIN20_PORTREG |=  CORE_PIN20_BITMASK;

  1430. 			}

  1431. 			#if CORE_NUM_TOTAL_PINS > 21

  1432. 			  else if (pin == 21) {

  1433. 				CORE_PIN21_DDRREG  &= ~CORE_PIN21_BITMASK;

  1434. 				CORE_PIN21_PORTREG |=  CORE_PIN21_BITMASK;

  1435. 			} else if (pin == 22) {

  1436. 				CORE_PIN22_DDRREG  &= ~CORE_PIN22_BITMASK;

  1437. 				CORE_PIN22_PORTREG |=  CORE_PIN22_BITMASK;

  1438. 			} else if (pin == 23) {

  1439. 				CORE_PIN23_DDRREG  &= ~CORE_PIN23_BITMASK;

  1440. 				CORE_PIN23_PORTREG |=  CORE_PIN23_BITMASK;

  1441. 			} else if (pin == 24) {

  1442. 				CORE_PIN24_DDRREG  &= ~CORE_PIN24_BITMASK;

  1443. 				CORE_PIN24_PORTREG |=  CORE_PIN24_BITMASK;

  1444. 			}

  1445. 			#endif

  1446. 			#if CORE_NUM_TOTAL_PINS > 25

  1447. 			  else if (pin == 25) {

  1448. 				CORE_PIN25_DDRREG  &= ~CORE_PIN25_BITMASK;

  1449. 				CORE_PIN25_PORTREG |=  CORE_PIN25_BITMASK;

  1450. 			} else if (pin == 26) {

  1451. 				CORE_PIN26_DDRREG  &= ~CORE_PIN26_BITMASK;

  1452. 				CORE_PIN26_PORTREG |=  CORE_PIN26_BITMASK;

  1453. 			} else if (pin == 27) {

  1454. 				CORE_PIN27_DDRREG  &= ~CORE_PIN27_BITMASK;

  1455. 				CORE_PIN27_PORTREG |=  CORE_PIN27_BITMASK;

  1456. 			} else if (pin == 28) {

  1457. 				CORE_PIN28_DDRREG  &= ~CORE_PIN28_BITMASK;

  1458. 				CORE_PIN28_PORTREG |=  CORE_PIN28_BITMASK;

  1459. 			} else if (pin == 29) {

  1460. 				CORE_PIN29_DDRREG  &= ~CORE_PIN29_BITMASK;

  1461. 				CORE_PIN29_PORTREG |=  CORE_PIN29_BITMASK;

  1462. 			} else if (pin == 30) {

  1463. 				CORE_PIN30_DDRREG  &= ~CORE_PIN30_BITMASK;

  1464. 				CORE_PIN30_PORTREG |=  CORE_PIN30_BITMASK;

  1465. 			} else if (pin == 31) {

  1466. 				CORE_PIN31_DDRREG  &= ~CORE_PIN31_BITMASK;

  1467. 				CORE_PIN31_PORTREG |=  CORE_PIN31_BITMASK;

  1468. 			} else if (pin == 32) {

  1469. 				CORE_PIN32_DDRREG  &= ~CORE_PIN32_BITMASK;

  1470. 				CORE_PIN32_PORTREG |=  CORE_PIN32_BITMASK;

  1471. 			} else if (pin == 33) {

  1472. 				CORE_PIN33_DDRREG  &= ~CORE_PIN33_BITMASK;

  1473. 				CORE_PIN33_PORTREG |=  CORE_PIN33_BITMASK;

  1474. 			} else if (pin == 34) {

  1475. 				CORE_PIN34_DDRREG  &= ~CORE_PIN34_BITMASK;

  1476. 				CORE_PIN34_PORTREG |=  CORE_PIN34_BITMASK;

  1477. 			} else if (pin == 35) {

  1478. 				CORE_PIN35_DDRREG  &= ~CORE_PIN35_BITMASK;

  1479. 				CORE_PIN35_PORTREG |=  CORE_PIN35_BITMASK;

  1480. 			} else if (pin == 36) {

  1481. 				CORE_PIN36_DDRREG  &= ~CORE_PIN36_BITMASK;

  1482. 				CORE_PIN36_PORTREG |=  CORE_PIN36_BITMASK;

  1483. 			} else if (pin == 37) {

  1484. 				CORE_PIN37_DDRREG  &= ~CORE_PIN37_BITMASK;

  1485. 				CORE_PIN37_PORTREG |=  CORE_PIN37_BITMASK;

  1486. 			} else if (pin == 38) {

  1487. 				CORE_PIN38_DDRREG  &= ~CORE_PIN38_BITMASK;

  1488. 				CORE_PIN38_PORTREG |=  CORE_PIN38_BITMASK;

  1489. 			} else if (pin == 39) {

  1490. 				CORE_PIN39_DDRREG  &= ~CORE_PIN39_BITMASK;

  1491. 				CORE_PIN39_PORTREG |=  CORE_PIN39_BITMASK;

  1492. 			} else if (pin == 40) {

  1493. 				CORE_PIN40_DDRREG  &= ~CORE_PIN40_BITMASK;

  1494. 				CORE_PIN40_PORTREG |=  CORE_PIN40_BITMASK;

  1495. 			} else if (pin == 41) {

  1496. 				CORE_PIN41_DDRREG  &= ~CORE_PIN41_BITMASK;

  1497. 				CORE_PIN41_PORTREG |=  CORE_PIN41_BITMASK;

  1498. 			} else if (pin == 42) {

  1499. 				CORE_PIN42_DDRREG  &= ~CORE_PIN42_BITMASK;

  1500. 				CORE_PIN42_PORTREG |=  CORE_PIN42_BITMASK;

  1501. 			} else if (pin == 43) {

  1502. 				CORE_PIN43_DDRREG  &= ~CORE_PIN43_BITMASK;

  1503. 				CORE_PIN43_PORTREG |=  CORE_PIN43_BITMASK;

  1504. 			} else if (pin == 44) {

  1505. 				CORE_PIN44_DDRREG  &= ~CORE_PIN44_BITMASK;

  1506. 				CORE_PIN44_PORTREG |=  CORE_PIN44_BITMASK;

  1507. 			} else if (pin == 45) {

  1508. 				CORE_PIN45_DDRREG  &= ~CORE_PIN45_BITMASK;

  1509. 				CORE_PIN45_PORTREG |=  CORE_PIN45_BITMASK;

  1510. 			}

  1511. 			#endif

  1512. 		} else {

  1513. 			if (pin == 0) {

  1514. 				CORE_PIN0_DDRREG  &= ~CORE_PIN0_BITMASK;

  1515. 				CORE_PIN0_PORTREG &= ~CORE_PIN0_BITMASK;

  1516. 			} else if (pin == 1) {

  1517. 				CORE_PIN1_DDRREG  &= ~CORE_PIN1_BITMASK;

  1518. 				CORE_PIN1_PORTREG &= ~CORE_PIN1_BITMASK;

  1519. 			} else if (pin == 2) {

  1520. 				CORE_PIN2_DDRREG  &= ~CORE_PIN2_BITMASK;

  1521. 				CORE_PIN2_PORTREG &= ~CORE_PIN2_BITMASK;

  1522. 			} else if (pin == 3) {

  1523. 				CORE_PIN3_DDRREG  &= ~CORE_PIN3_BITMASK;

  1524. 				CORE_PIN3_PORTREG &= ~CORE_PIN3_BITMASK;

  1525. 			} else if (pin == 4) {

  1526. 				CORE_PIN4_DDRREG  &= ~CORE_PIN4_BITMASK;

  1527. 				CORE_PIN4_PORTREG &= ~CORE_PIN4_BITMASK;

  1528. 			} else if (pin == 5) {

  1529. 				CORE_PIN5_DDRREG  &= ~CORE_PIN5_BITMASK;

  1530. 				CORE_PIN5_PORTREG &= ~CORE_PIN5_BITMASK;

  1531. 			} else if (pin == 6) {

  1532. 				CORE_PIN6_DDRREG  &= ~CORE_PIN6_BITMASK;

  1533. 				CORE_PIN6_PORTREG &= ~CORE_PIN6_BITMASK;

  1534. 			} else if (pin == 7) {

  1535. 				CORE_PIN7_DDRREG  &= ~CORE_PIN7_BITMASK;

  1536. 				CORE_PIN7_PORTREG &= ~CORE_PIN7_BITMASK;

  1537. 			} else if (pin == 8) {

  1538. 				CORE_PIN8_DDRREG  &= ~CORE_PIN8_BITMASK;

  1539. 				CORE_PIN8_PORTREG &= ~CORE_PIN8_BITMASK;

  1540. 			} else if (pin == 9) {

  1541. 				CORE_PIN9_DDRREG  &= ~CORE_PIN9_BITMASK;

  1542. 				CORE_PIN9_PORTREG &= ~CORE_PIN9_BITMASK;

  1543. 			} else if (pin == 10) {

  1544. 				CORE_PIN10_DDRREG  &= ~CORE_PIN10_BITMASK;

  1545. 				CORE_PIN10_PORTREG &= ~CORE_PIN10_BITMASK;

  1546. 			} else if (pin == 11) {

  1547. 				CORE_PIN11_DDRREG  &= ~CORE_PIN11_BITMASK;

  1548. 				CORE_PIN11_PORTREG &= ~CORE_PIN11_BITMASK;

  1549. 			} else if (pin == 12) {

  1550. 				CORE_PIN12_DDRREG  &= ~CORE_PIN12_BITMASK;

  1551. 				CORE_PIN12_PORTREG &= ~CORE_PIN12_BITMASK;

  1552. 			} else if (pin == 13) {

  1553. 				CORE_PIN13_DDRREG  &= ~CORE_PIN13_BITMASK;

  1554. 				CORE_PIN13_PORTREG &= ~CORE_PIN13_BITMASK;

  1555. 			} else if (pin == 14) {

  1556. 				CORE_PIN14_DDRREG  &= ~CORE_PIN14_BITMASK;

  1557. 				CORE_PIN14_PORTREG &= ~CORE_PIN14_BITMASK;

  1558. 			} else if (pin == 15) {

  1559. 				CORE_PIN15_DDRREG  &= ~CORE_PIN15_BITMASK;

  1560. 				CORE_PIN15_PORTREG &= ~CORE_PIN15_BITMASK;

  1561. 			} else if (pin == 16) {

  1562. 				CORE_PIN16_DDRREG  &= ~CORE_PIN16_BITMASK;

  1563. 				CORE_PIN16_PORTREG &= ~CORE_PIN16_BITMASK;

  1564. 			} else if (pin == 17) {

  1565. 				CORE_PIN17_DDRREG  &= ~CORE_PIN17_BITMASK;

  1566. 				CORE_PIN17_PORTREG &= ~CORE_PIN17_BITMASK;

  1567. 			} else if (pin == 18) {

  1568. 				CORE_PIN18_DDRREG  &= ~CORE_PIN18_BITMASK;

  1569. 				CORE_PIN18_PORTREG &= ~CORE_PIN18_BITMASK;

  1570. 			} else if (pin == 19) {

  1571. 				CORE_PIN19_DDRREG  &= ~CORE_PIN19_BITMASK;

  1572. 				CORE_PIN19_PORTREG &= ~CORE_PIN19_BITMASK;

  1573. 			} else if (pin == 20) {

  1574. 				CORE_PIN20_DDRREG  &= ~CORE_PIN20_BITMASK;

  1575. 				CORE_PIN20_PORTREG &= ~CORE_PIN20_BITMASK;

  1576. 			}

  1577. 			#if CORE_NUM_TOTAL_PINS > 21

  1578. 			  else if (pin == 21) {

  1579. 				CORE_PIN21_DDRREG  &= ~CORE_PIN21_BITMASK;

  1580. 				CORE_PIN21_PORTREG &= ~CORE_PIN21_BITMASK;

  1581. 			} else if (pin == 22) {

  1582. 				CORE_PIN22_DDRREG  &= ~CORE_PIN22_BITMASK;

  1583. 				CORE_PIN22_PORTREG &= ~CORE_PIN22_BITMASK;

  1584. 			} else if (pin == 23) {

  1585. 				CORE_PIN23_DDRREG  &= ~CORE_PIN23_BITMASK;

  1586. 				CORE_PIN23_PORTREG &= ~CORE_PIN23_BITMASK;

  1587. 			} else if (pin == 24) {

  1588. 				CORE_PIN24_DDRREG  &= ~CORE_PIN24_BITMASK;

  1589. 				CORE_PIN24_PORTREG &= ~CORE_PIN24_BITMASK;

  1590. 			}

  1591. 			#endif

  1592. 			#if CORE_NUM_TOTAL_PINS > 25

  1593. 			  else if (pin == 25) {

  1594. 				CORE_PIN25_DDRREG  &= ~CORE_PIN25_BITMASK;

  1595. 				CORE_PIN25_PORTREG &= ~CORE_PIN25_BITMASK;

  1596. 			} else if (pin == 26) {

  1597. 				CORE_PIN26_DDRREG  &= ~CORE_PIN26_BITMASK;

  1598. 				CORE_PIN26_PORTREG &= ~CORE_PIN26_BITMASK;

  1599. 			} else if (pin == 27) {

  1600. 				CORE_PIN27_DDRREG  &= ~CORE_PIN27_BITMASK;

  1601. 				CORE_PIN27_PORTREG &= ~CORE_PIN27_BITMASK;

  1602. 			} else if (pin == 28) {

  1603. 				CORE_PIN28_DDRREG  &= ~CORE_PIN28_BITMASK;

  1604. 				CORE_PIN28_PORTREG &= ~CORE_PIN28_BITMASK;

  1605. 			} else if (pin == 29) {

  1606. 				CORE_PIN29_DDRREG  &= ~CORE_PIN29_BITMASK;

  1607. 				CORE_PIN29_PORTREG &= ~CORE_PIN29_BITMASK;

  1608. 			} else if (pin == 30) {

  1609. 				CORE_PIN30_DDRREG  &= ~CORE_PIN30_BITMASK;

  1610. 				CORE_PIN30_PORTREG &= ~CORE_PIN30_BITMASK;

  1611. 			} else if (pin == 31) {

  1612. 				CORE_PIN31_DDRREG  &= ~CORE_PIN31_BITMASK;

  1613. 				CORE_PIN31_PORTREG &= ~CORE_PIN31_BITMASK;

  1614. 			} else if (pin == 32) {

  1615. 				CORE_PIN32_DDRREG  &= ~CORE_PIN32_BITMASK;

  1616. 				CORE_PIN32_PORTREG &= ~CORE_PIN32_BITMASK;

  1617. 			} else if (pin == 33) {

  1618. 				CORE_PIN33_DDRREG  &= ~CORE_PIN33_BITMASK;

  1619. 				CORE_PIN33_PORTREG &= ~CORE_PIN33_BITMASK;

  1620. 			} else if (pin == 34) {

  1621. 				CORE_PIN34_DDRREG  &= ~CORE_PIN34_BITMASK;

  1622. 				CORE_PIN34_PORTREG &= ~CORE_PIN34_BITMASK;

  1623. 			} else if (pin == 35) {

  1624. 				CORE_PIN35_DDRREG  &= ~CORE_PIN35_BITMASK;

  1625. 				CORE_PIN35_PORTREG &= ~CORE_PIN35_BITMASK;

  1626. 			} else if (pin == 36) {

  1627. 				CORE_PIN36_DDRREG  &= ~CORE_PIN36_BITMASK;

  1628. 				CORE_PIN36_PORTREG &= ~CORE_PIN36_BITMASK;

  1629. 			} else if (pin == 37) {

  1630. 				CORE_PIN37_DDRREG  &= ~CORE_PIN37_BITMASK;

  1631. 				CORE_PIN37_PORTREG &= ~CORE_PIN37_BITMASK;

  1632. 			} else if (pin == 38) {

  1633. 				CORE_PIN38_DDRREG  &= ~CORE_PIN38_BITMASK;

  1634. 				CORE_PIN38_PORTREG &= ~CORE_PIN38_BITMASK;

  1635. 			} else if (pin == 39) {

  1636. 				CORE_PIN39_DDRREG  &= ~CORE_PIN39_BITMASK;

  1637. 				CORE_PIN39_PORTREG &= ~CORE_PIN39_BITMASK;

  1638. 			} else if (pin == 40) {

  1639. 				CORE_PIN40_DDRREG  &= ~CORE_PIN40_BITMASK;

  1640. 				CORE_PIN40_PORTREG &= ~CORE_PIN40_BITMASK;

  1641. 			} else if (pin == 41) {

  1642. 				CORE_PIN41_DDRREG  &= ~CORE_PIN41_BITMASK;

  1643. 				CORE_PIN41_PORTREG &= ~CORE_PIN41_BITMASK;

  1644. 			} else if (pin == 42) {

  1645. 				CORE_PIN42_DDRREG  &= ~CORE_PIN42_BITMASK;

  1646. 				CORE_PIN42_PORTREG &= ~CORE_PIN42_BITMASK;

  1647. 			} else if (pin == 43) {

  1648. 				CORE_PIN43_DDRREG  &= ~CORE_PIN43_BITMASK;

  1649. 				CORE_PIN43_PORTREG &= ~CORE_PIN43_BITMASK;

  1650. 			} else if (pin == 44) {

  1651. 				CORE_PIN44_DDRREG  &= ~CORE_PIN44_BITMASK;

  1652. 				CORE_PIN44_PORTREG &= ~CORE_PIN44_BITMASK;

  1653. 			} else if (pin == 45) {

  1654. 				CORE_PIN45_DDRREG  &= ~CORE_PIN45_BITMASK;

  1655. 				CORE_PIN45_PORTREG &= ~CORE_PIN45_BITMASK;

  1656. 			}

  1657. 			#endif

  1658. 		}

  1659. 		#if defined(__AVR_ATmega32U4__)

  1660. 		if (mode == INPUT || mode == INPUT_PULLUP) {

  1661. 			if (pin == 11) {

  1662. 				DIDR2 &= ~0x02;

  1663. 			} else if (pin == 12) {

  1664. 				DIDR2 &= ~0x04;

  1665. 			} else if (pin == 13) {

  1666. 				DIDR2 &= ~0x08;

  1667. 			} else if (pin == 14) {

  1668. 				DIDR2 &= ~0x10;

  1669. 			} else if (pin == 15) {

  1670. 				DIDR2 &= ~0x20;

  1671. 			} else if (pin == 16) {

  1672. 				DIDR0 &= ~0x80;

  1673. 			} else if (pin == 17) {

  1674. 				DIDR0 &= ~0x40;

  1675. 			} else if (pin == 18) {

  1676. 				DIDR0 &= ~0x20;

  1677. 			} else if (pin == 19) {

  1678. 				DIDR0 &= ~0x10;

  1679. 			} else if (pin == 20) {

  1680. 				DIDR0 &= ~0x02;

  1681. 			} else if (pin == 21) {

  1682. 				DIDR0 &= ~0x01;

  1683. 			} else if (pin == 22) {

  1684. 				DIDR2 &= ~0x01;

  1685. 			}

  1686. 		}

  1687. 		#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  1688. 		if (mode == INPUT || mode == INPUT_PULLUP) {

  1689. 			if (pin == 38) {

  1690. 				DIDR0 &= ~0x01;

  1691. 			} else if (pin == 39) {

  1692. 				DIDR0 &= ~0x02;

  1693. 			} else if (pin == 40) {

  1694. 				DIDR0 &= ~0x04;

  1695. 			} else if (pin == 41) {

  1696. 				DIDR0 &= ~0x08;

  1697. 			} else if (pin == 42) {

  1698. 				DIDR0 &= ~0x10;

  1699. 			} else if (pin == 43) {

  1700. 				DIDR0 &= ~0x20;

  1701. 			} else if (pin == 44) {

  1702. 				DIDR0 &= ~0x40;

  1703. 			} else if (pin == 45) {

  1704. 				DIDR0 &= ~0x80;

  1705. 			}

  1706. 		}

  1707. 		#endif

  1708. 	} else if (__builtin_constant_p(mode)) {

  1709. 		if (mode == OUTPUT) {

  1710. 			_pinMode_output(pin);

  1711. 		} else if (mode == INPUT_PULLUP) {

  1712. 			_pinMode_input_pullup(pin);

  1713. 		} else {

  1714. 			_pinMode_input(pin);

  1715. 		}

  1716. 	} else {

  1717. 		_pinMode(pin, mode);

  1718. 	}

  1719. }

  1720. 

  1721. extern void _init_Teensyduino_internal_(void);

  1722. extern int analogRead(uint8_t);

  1723. 

  1724. extern void _analogWrite(uint8_t pin, int val) __attribute__((noinline));

  1725. 

  1726. static inline void analogWrite(uint8_t, int) __attribute__((always_inline, unused));

  1727. static inline void analogWrite(uint8_t pin, int val)

  1728. {

  1729. 	if (__builtin_constant_p(pin)) {

  1730. 		if (pin == CORE_OC0B_PIN) {	// TIMER0B

  1731. 			CORE_DDRREG(CORE_OC0B_PIN) |= CORE_BITMASK(CORE_OC0B_PIN);

  1732. 			if (val) {

  1733. 				OCR0B = val;

  1734. 				_SFR_BYTE(TCCR0A) |= (1<<COM0B1);

  1735. 			} else {

  1736. 				CORE_PORTREG(CORE_OC0B_PIN) &= ~CORE_BITMASK(CORE_OC0B_PIN);

  1737. 				_SFR_BYTE(TCCR0A) &= ~(1<<COM0B1);

  1738. 			}

  1739. 		} else if (pin == CORE_OC1A_PIN) { //TIMER1A

  1740. 			CORE_DDRREG(CORE_OC1A_PIN) |= CORE_BITMASK(CORE_OC1A_PIN);

  1741. 			OCR1A = val;

  1742. 			TCCR1A |= (1<<COM1A1);

  1743. 		} else if (pin == CORE_OC1B_PIN) { //TIMER1B

  1744. 			CORE_DDRREG(CORE_OC1B_PIN) |= CORE_BITMASK(CORE_OC1B_PIN);

  1745. 			OCR1B = val;

  1746. 			TCCR1A |= (1<<COM1B1);

  1747. 		} else if (pin == CORE_OC1C_PIN) { //TIMER1C

  1748. 			CORE_DDRREG(CORE_OC1C_PIN) |= CORE_BITMASK(CORE_OC1C_PIN);

  1749. 			OCR1C = val;

  1750. 			TCCR1A |= (1<<COM1C1);

  1751. 		}

  1752. #if defined(__AVR_ATmega32U4__)

  1753. 		  else if (pin == CORE_OC3A_PIN) { //TIMER3A

  1754. 			CORE_DDRREG(CORE_OC3A_PIN) |= CORE_BITMASK(CORE_OC3A_PIN);

  1755. 			OCR3A = val;

  1756. 			TCCR3A |= (1<<COM3A1);

  1757. 		} else if (pin == CORE_OC4A_PIN) { //TIMER4A

  1758. 			CORE_DDRREG(CORE_OC4A_PIN) |= CORE_BITMASK(CORE_OC4A_PIN);

  1759. 			OCR4A = val;

  1760. 			TCCR4A |= (1<<COM4A1);

  1761. 		} else if (pin == CORE_OC4D_PIN) { //TIMER4D

  1762. 			CORE_DDRREG(CORE_OC4D_PIN) |= CORE_BITMASK(CORE_OC4D_PIN);

  1763. 			OCR4D = val;

  1764. 			TCCR4C |= (1<<COM4D1);

  1765. 		}

  1766. #endif

  1767. #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)

  1768. 		  else if (pin == CORE_OC2A_PIN) { //TIMER2A

  1769. 			CORE_DDRREG(CORE_OC2A_PIN) |= CORE_BITMASK(CORE_OC2A_PIN);

  1770. 			OCR2A = val;

  1771. 			TCCR2A |= (1<<COM2A1);

  1772. 		} else if (pin == CORE_OC2B_PIN) { //TIMER2B

  1773. 			CORE_DDRREG(CORE_OC2B_PIN) |= CORE_BITMASK(CORE_OC2B_PIN);

  1774. 			OCR2B = val;

  1775. 			TCCR2A |= (1<<COM2B1);

  1776. 		} else if (pin == CORE_OC3A_PIN) { //TIMER3A

  1777. 			CORE_DDRREG(CORE_OC3A_PIN) |= CORE_BITMASK(CORE_OC3A_PIN);

  1778. 			OCR3A = val;

  1779. 			TCCR3A |= (1<<COM3A1);

  1780. 		} else if (pin == CORE_OC3B_PIN) { //TIMER3B

  1781. 			CORE_DDRREG(CORE_OC3B_PIN) |= CORE_BITMASK(CORE_OC3B_PIN);

  1782. 			OCR3B = val;

  1783. 			TCCR3A |= (1<<COM3B1);

  1784. 		} else if (pin == CORE_OC3C_PIN) { //TIMER3C

  1785. 			CORE_DDRREG(CORE_OC3C_PIN) |= CORE_BITMASK(CORE_OC3C_PIN);

  1786. 			OCR3C = val;

  1787. 			TCCR3A |= (1<<COM3C1);

  1788. 		}

  1789. #endif

  1790. 		  else {

  1791. 			if (pin < CORE_NUM_TOTAL_PINS) {

  1792. 				pinMode(pin, OUTPUT);

  1793. 				if (val < 128) {

  1794. 					digitalWrite(pin, LOW);

  1795. 				} else {

  1796. 					digitalWrite(pin, HIGH);

  1797. 				}

  1798. 			}

  1799. 		}

  1800. 	} else {

  1801. 		_analogWrite(pin, val);

  1802. 	}

  1803. }

  1804. 

  1805. static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  1806. extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));

  1807. extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  1808. extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  1809. 

  1810. static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  1811. {

  1812. 	if (__builtin_constant_p(bitOrder)) {

  1813. 		if (bitOrder == LSBFIRST) {

  1814. 			shiftOut_lsbFirst(dataPin, clockPin, value);

  1815. 		} else {

  1816. 			shiftOut_msbFirst(dataPin, clockPin, value);

  1817. 		}

  1818. 	} else {

  1819. 		_shiftOut(dataPin, clockPin, bitOrder, value);

  1820. 	}

  1821. }

  1822. 

  1823. static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  1824. extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));

  1825. extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  1826. extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  1827. 

  1828. static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  1829. {

  1830. 	if (__builtin_constant_p(bitOrder)) {

  1831. 		if (bitOrder == LSBFIRST) {

  1832. 			return shiftIn_lsbFirst(dataPin, clockPin);

  1833. 		} else {

  1834. 			return shiftIn_msbFirst(dataPin, clockPin);

  1835. 		}

  1836. 	} else {

  1837. 		return _shiftIn(dataPin, clockPin, bitOrder);

  1838. 	}

  1839. }

  1840. 

  1841. void _reboot_Teensyduino_(void) __attribute__((noreturn));

  1842. void _restart_Teensyduino_(void) __attribute__((noreturn));

  1843. 

  1844. 

  1845. #if defined(__AVR_AT90USB162__)

  1846. #define analogReference(mode)

  1847. #else

  1848. extern uint8_t w_analog_reference;

  1849. static inline void analogReference(uint8_t mode)

  1850. {

  1851. 	w_analog_reference = (mode << 6);

  1852. }

  1853. #endif

  1854. 

  1855. void yield(void);

  1856. 

  1857. extern void delay(uint32_t);

  1858. 

  1859. extern volatile uint32_t timer0_millis_count;

  1860. 

  1861. static inline uint32_t millis(void) __attribute__((always_inline, unused));

  1862. static inline uint32_t millis(void)

  1863. {

  1864. 	uint32_t out;

  1865. 	asm volatile(

  1866. 		"in	__tmp_reg__, __SREG__"		"\n\t"

  1867. 		"cli"					"\n\t"

  1868. 		"lds	%A0, timer0_millis_count"	"\n\t"

  1869. 		"lds	%B0, timer0_millis_count+1"	"\n\t"

  1870. 		"lds	%C0, timer0_millis_count+2"	"\n\t"

  1871. 		"lds	%D0, timer0_millis_count+3"	"\n\t"

  1872. 		"out	__SREG__, __tmp_reg__"

  1873. 		: "=r" (out) : : "r0"

  1874. 	);

  1875. 	return out;

  1876. }

  1877. 

  1878. extern uint32_t _micros(void) __attribute__((noinline));

  1879. 

  1880. static inline uint32_t micros(void) __attribute__((always_inline, unused));

  1881. static inline uint32_t micros(void)

  1882. {

  1883. 	register uint32_t out asm("r22");

  1884. 	asm volatile("call _micros" : "=d" (out) : : "r0");

  1885. 	return out;

  1886. }

  1887. 

  1888. 

  1889. static inline void delayMicroseconds(uint16_t) __attribute__((always_inline, unused));

  1890. static inline void delayMicroseconds(uint16_t usec)

  1891. {

  1892. 	if (__builtin_constant_p(usec)) {

  1893. 		#if F_CPU == 16000000L

  1894. 		uint16_t tmp = usec * 4;

  1895. 		#elif F_CPU == 8000000L

  1896. 		uint16_t tmp = usec * 2;

  1897. 		#elif F_CPU == 4000000L

  1898. 		uint16_t tmp = usec;

  1899. 		#elif F_CPU == 2000000L

  1900. 		uint16_t tmp = usec / 2;

  1901. 		if (usec == 1) {

  1902. 			asm volatile("rjmp L%=\nL%=:\n" ::);

  1903. 		}

  1904. 		#elif F_CPU == 1000000L

  1905. 		uint16_t tmp = usec / 4;

  1906. 		if (usec == 1) {

  1907. 			asm volatile("nop\n");

  1908. 		} else if (usec == 2) {

  1909. 			asm volatile("rjmp L%=\nL%=:\n" ::);

  1910. 		} else if (usec == 3) {

  1911. 			asm volatile("rjmp L%=\nL%=:\n" ::);

  1912. 			asm volatile("nop\n");

  1913. 		}

  1914. 		#else

  1915. 		#error "Clock must be 16, 8, 4, 2 or 1 MHz"

  1916. 		#endif

  1917. 		if (tmp > 0) {

  1918. 			if (tmp < 256) {

  1919. 				uint8_t tmp2 = tmp;

  1920. 				asm volatile(

  1921. 				"L_%=_loop:"				// 1 to load

  1922. 					"subi	%0, 1"		"\n\t"	// 2

  1923. 					"brne	L_%=_loop"	"\n\t"	// 2 (1 on last)

  1924. 					: "=d" (tmp2)

  1925. 					: "0" (tmp2)

  1926. 				);

  1927. 			} else {

  1928. 				asm volatile(

  1929. 				"L_%=_loop:"				// 2 to load

  1930. 					"sbiw	%A0, 1"		"\n\t"	// 2

  1931. 					"brne	L_%=_loop"	"\n\t"	// 2 (1 on last)

  1932. 					: "=w" (tmp)

  1933. 					: "0" (tmp)

  1934. 				);

  1935. 			}

  1936. 		}

  1937. 	} else {

  1938. 		asm volatile(

  1939. 		#if F_CPU == 16000000L

  1940. 			"sbiw	%A0, 2"			"\n\t"	// 2

  1941. 			"brcs	L_%=_end"		"\n\t"	// 1

  1942. 			"breq	L_%=_end"		"\n\t"	// 1

  1943. 			"lsl	%A0"			"\n\t"	// 1

  1944. 			"rol	%B0"			"\n\t"	// 1

  1945. 			"lsl	%A0"			"\n\t"	// 1

  1946. 			"rol	%B0"			"\n\t"	// 1  overhead: (8)/4 = 2us

  1947. 		#elif F_CPU == 8000000L

  1948. 			"sbiw	%A0, 3"			"\n\t"	// 2

  1949. 			"brcs	L_%=_end"		"\n\t"	// 1

  1950. 			"breq	L_%=_end"		"\n\t"	// 1

  1951. 			"lsl	%A0"			"\n\t"	// 1

  1952. 			"rol	%B0"			"\n\t"	// 1  overhead: (6)/2 = 3 us

  1953. 		#elif F_CPU == 4000000L

  1954. 			"sbiw	%A0, 4"			"\n\t"	// 2

  1955. 			"brcs	L_%=_end"		"\n\t"	// 1

  1956. 			"breq	L_%=_end"		"\n\t"	// 1  overhead: (4) = 4 us

  1957. 		#elif F_CPU == 2000000L

  1958. 			"sbiw	%A0, 12"		"\n\t"	// 2

  1959. 			"brcs	L_%=_end"		"\n\t"	// 1

  1960. 			"breq	L_%=_end"		"\n\t"	// 1

  1961. 			"lsr	%B0"			"\n\t"	// 1

  1962. 			"ror	%A0"			"\n\t"	// 1  overhead: (6)*2 = 12 us

  1963. 		#elif F_CPU == 1000000L

  1964. 			"sbiw	%A0, 32"		"\n\t"	// 2

  1965. 			"brcs	L_%=_end"		"\n\t"	// 1

  1966. 			"breq	L_%=_end"		"\n\t"	// 1

  1967. 			"lsr	%B0"			"\n\t"	// 1

  1968. 			"ror	%A0"			"\n\t"	// 1

  1969. 			"lsr	%B0"			"\n\t"	// 1

  1970. 			"ror	%A0"			"\n\t"	// 1  overhead: (8)*4 = 32 us

  1971. 		#endif

  1972. 		"L_%=_loop:"

  1973. 			"sbiw	%A0, 1"			"\n\t"	// 2

  1974. 			"brne	L_%=_loop"		"\n\t"	// 2

  1975. 		"L_%=_end:"

  1976. 			: "=w" (usec)

  1977. 			: "0" (usec)

  1978. 		);

  1979. 	}

  1980. }

  1981. 

  1982. 

  1983. 

  1984. 

  1985. #ifdef __cplusplus

  1986. } // extern "C"

  1987. #endif

  1988. #endif