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  1. /* Teensyduino Core Library
  2. * http://www.pjrc.com/teensy/
  3. * Copyright (c) 2017 PJRC.COM, LLC.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * 1. The above copyright notice and this permission notice shall be
  14. * included in all copies or substantial portions of the Software.
  15. *
  16. * 2. If the Software is incorporated into a build system that allows
  17. * selection among a list of target devices, then similar target
  18. * devices manufactured by PJRC.COM must be included in the list of
  19. * target devices and selectable in the same manner.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  24. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  25. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  26. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  27. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  28. * SOFTWARE.
  29. */
  30. #include "core_pins.h"
  31. //#include "HardwareSerial.h"
  32. static uint8_t calibrating;
  33. static uint8_t analog_right_shift = 0;
  34. static uint8_t analog_config_bits = 10;
  35. static uint8_t analog_num_average = 4;
  36. static uint8_t analog_reference_internal = 0;
  37. // the alternate clock is connected to OSCERCLK (16 MHz).
  38. // datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode
  39. // datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode
  40. #if F_BUS == 120000000
  41. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7.5 MHz
  42. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz
  43. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz
  44. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 15 MHz
  45. #elif F_BUS == 108000000
  46. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(3) + ADC_CFG1_ADICLK(1) // 7 MHz
  47. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz
  48. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz
  49. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 14 MHz
  50. #elif F_BUS == 96000000
  51. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz
  52. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz
  53. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 12 MHz
  54. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 24 MHz
  55. #elif F_BUS == 90000000
  56. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz
  57. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz
  58. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 11.25 MHz
  59. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 22.5 MHz
  60. #elif F_BUS == 80000000
  61. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz
  62. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz
  63. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 10 MHz
  64. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 20 MHz
  65. #elif F_BUS == 72000000
  66. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 9 MHz
  67. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz
  68. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz
  69. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 18 MHz
  70. #elif F_BUS == 64000000
  71. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 8 MHz
  72. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz
  73. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz
  74. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 16 MHz
  75. #elif F_BUS == 60000000
  76. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz
  77. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
  78. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
  79. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
  80. #elif F_BUS == 56000000 || F_BUS == 54000000
  81. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz
  82. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
  83. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
  84. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
  85. #elif F_BUS == 48000000
  86. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
  87. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
  88. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
  89. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 24 MHz
  90. #elif F_BUS == 40000000
  91. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
  92. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
  93. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
  94. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 20 MHz
  95. #elif F_BUS == 36000000
  96. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 9 MHz
  97. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
  98. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
  99. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
  100. #elif F_BUS == 24000000
  101. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
  102. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
  103. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
  104. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz
  105. #elif F_BUS == 16000000
  106. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  107. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  108. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  109. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 16 MHz
  110. #elif F_BUS == 8000000
  111. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  112. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  113. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  114. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
  115. #elif F_BUS == 4000000
  116. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  117. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  118. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  119. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
  120. #elif F_BUS == 2000000
  121. #define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  122. #define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  123. #define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  124. #define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
  125. #else
  126. #error "F_BUS must be 120, 108, 96, 90, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 4 or 2 MHz"
  127. #endif
  128. void analog_init(void)
  129. {
  130. uint32_t num;
  131. #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
  132. VREF_TRM = 0x60;
  133. VREF_SC = 0xE1; // enable 1.2 volt ref
  134. #endif
  135. if (analog_config_bits == 8) {
  136. ADC0_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
  137. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  138. #ifdef HAS_KINETIS_ADC1
  139. ADC1_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
  140. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  141. #endif
  142. } else if (analog_config_bits == 10) {
  143. ADC0_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
  144. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  145. #ifdef HAS_KINETIS_ADC1
  146. ADC1_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
  147. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
  148. #endif
  149. } else if (analog_config_bits == 12) {
  150. ADC0_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
  151. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  152. #ifdef HAS_KINETIS_ADC1
  153. ADC1_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
  154. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  155. #endif
  156. } else {
  157. ADC0_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
  158. ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  159. #ifdef HAS_KINETIS_ADC1
  160. ADC1_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
  161. ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
  162. #endif
  163. }
  164. #if defined(__MK20DX128__)
  165. if (analog_reference_internal) {
  166. ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
  167. } else {
  168. ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
  169. }
  170. #elif defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
  171. if (analog_reference_internal) {
  172. ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
  173. ADC1_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
  174. } else {
  175. ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
  176. ADC1_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
  177. }
  178. #elif defined(__MKL26Z64__)
  179. if (analog_reference_internal) {
  180. ADC0_SC2 = ADC_SC2_REFSEL(0); // external AREF
  181. } else {
  182. ADC0_SC2 = ADC_SC2_REFSEL(1); // vcc
  183. }
  184. #endif
  185. num = analog_num_average;
  186. if (num <= 1) {
  187. ADC0_SC3 = ADC_SC3_CAL; // begin cal
  188. #ifdef HAS_KINETIS_ADC1
  189. ADC1_SC3 = ADC_SC3_CAL; // begin cal
  190. #endif
  191. } else if (num <= 4) {
  192. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
  193. #ifdef HAS_KINETIS_ADC1
  194. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
  195. #endif
  196. } else if (num <= 8) {
  197. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
  198. #ifdef HAS_KINETIS_ADC1
  199. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
  200. #endif
  201. } else if (num <= 16) {
  202. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
  203. #ifdef HAS_KINETIS_ADC1
  204. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
  205. #endif
  206. } else {
  207. ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
  208. #ifdef HAS_KINETIS_ADC1
  209. ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
  210. #endif
  211. }
  212. calibrating = 1;
  213. }
  214. static void wait_for_cal(void)
  215. {
  216. uint16_t sum;
  217. //serial_print("wait_for_cal\n");
  218. #if defined(HAS_KINETIS_ADC0) && defined(HAS_KINETIS_ADC1)
  219. while ((ADC0_SC3 & ADC_SC3_CAL) || (ADC1_SC3 & ADC_SC3_CAL)) {
  220. // wait
  221. }
  222. #elif defined(HAS_KINETIS_ADC0)
  223. while (ADC0_SC3 & ADC_SC3_CAL) {
  224. // wait
  225. }
  226. #endif
  227. __disable_irq();
  228. if (calibrating) {
  229. //serial_print("\n");
  230. sum = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
  231. sum = (sum / 2) | 0x8000;
  232. ADC0_PG = sum;
  233. //serial_print("ADC0_PG = ");
  234. //serial_phex16(sum);
  235. //serial_print("\n");
  236. sum = ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;
  237. sum = (sum / 2) | 0x8000;
  238. ADC0_MG = sum;
  239. //serial_print("ADC0_MG = ");
  240. //serial_phex16(sum);
  241. //serial_print("\n");
  242. #ifdef HAS_KINETIS_ADC1
  243. sum = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;
  244. sum = (sum / 2) | 0x8000;
  245. ADC1_PG = sum;
  246. sum = ADC1_CLMS + ADC1_CLM4 + ADC1_CLM3 + ADC1_CLM2 + ADC1_CLM1 + ADC1_CLM0;
  247. sum = (sum / 2) | 0x8000;
  248. ADC1_MG = sum;
  249. #endif
  250. calibrating = 0;
  251. }
  252. __enable_irq();
  253. }
  254. // ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC.
  255. // VREFH/VREFL - connected as the primary reference option
  256. // 1.2 V VREF_OUT - connected as the VALT reference option
  257. #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
  258. #define DEFAULT 0
  259. #define INTERNAL 2
  260. #define INTERNAL1V2 2
  261. #define INTERNAL1V1 2
  262. #define EXTERNAL 0
  263. #elif defined(__MKL26Z64__)
  264. #define DEFAULT 0
  265. #define INTERNAL 0
  266. #define EXTERNAL 1
  267. #endif
  268. void analogReference(uint8_t type)
  269. {
  270. if (type) {
  271. // internal reference requested
  272. if (!analog_reference_internal) {
  273. analog_reference_internal = 1;
  274. if (calibrating) {
  275. ADC0_SC3 = 0; // cancel cal
  276. #ifdef HAS_KINETIS_ADC1
  277. ADC1_SC3 = 0; // cancel cal
  278. #endif
  279. }
  280. analog_init();
  281. }
  282. } else {
  283. // vcc or external reference requested
  284. if (analog_reference_internal) {
  285. analog_reference_internal = 0;
  286. if (calibrating) {
  287. ADC0_SC3 = 0; // cancel cal
  288. #ifdef HAS_KINETIS_ADC1
  289. ADC1_SC3 = 0; // cancel cal
  290. #endif
  291. }
  292. analog_init();
  293. }
  294. }
  295. }
  296. void analogReadRes(unsigned int bits)
  297. {
  298. unsigned int config;
  299. if (bits >= 13) {
  300. if (bits > 16) bits = 16;
  301. config = 16;
  302. } else if (bits >= 11) {
  303. config = 12;
  304. } else if (bits >= 9) {
  305. config = 10;
  306. } else {
  307. config = 8;
  308. }
  309. analog_right_shift = config - bits;
  310. if (config != analog_config_bits) {
  311. analog_config_bits = config;
  312. if (calibrating) {
  313. ADC0_SC3 = 0; // cancel cal
  314. #ifdef HAS_KINETIS_ADC1
  315. ADC1_SC3 = 0;
  316. #endif
  317. }
  318. analog_init();
  319. }
  320. }
  321. void analogReadAveraging(unsigned int num)
  322. {
  323. if (calibrating) wait_for_cal();
  324. if (num <= 1) {
  325. num = 0;
  326. ADC0_SC3 = 0;
  327. } else if (num <= 4) {
  328. num = 4;
  329. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);
  330. #ifdef HAS_KINETIS_ADC1
  331. ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);
  332. #endif
  333. } else if (num <= 8) {
  334. num = 8;
  335. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);
  336. #ifdef HAS_KINETIS_ADC1
  337. ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);
  338. #endif
  339. } else if (num <= 16) {
  340. num = 16;
  341. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);
  342. #ifdef HAS_KINETIS_ADC1
  343. ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);
  344. #endif
  345. } else {
  346. num = 32;
  347. ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);
  348. #ifdef HAS_KINETIS_ADC1
  349. ADC1_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);
  350. #endif
  351. }
  352. analog_num_average = num;
  353. }
  354. // The SC1A register is used for both software and hardware trigger modes of operation.
  355. #if defined(__MK20DX128__)
  356. static const uint8_t pin2sc1a[] = {
  357. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 0, 19, 3, 21, // 0-13 -> A0-A13
  358. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9
  359. 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // 24-33 are digital only
  360. 0, 19, 3, 21, // 34-37 are A10-A13
  361. 26, // 38 is temp sensor
  362. 22, // 39 is vref
  363. 23 // 40 is unused analog pin
  364. };
  365. #elif defined(__MK20DX256__)
  366. static const uint8_t pin2sc1a[] = {
  367. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 0, 19, 3, 19+128, // 0-13 -> A0-A13
  368. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9
  369. 255, 255, // 24-25 are digital only
  370. 5+192, 5+128, 4+128, 6+128, 7+128, 4+192, // 26-31 are A15-A20
  371. 255, 255, // 32-33 are digital only
  372. 0, 19, 3, 19+128, // 34-37 are A10-A13
  373. 26, // 38 is temp sensor,
  374. 18+128, // 39 is vref
  375. 23 // 40 is A14
  376. };
  377. #elif defined(__MKL26Z64__)
  378. static const uint8_t pin2sc1a[] = {
  379. 5, 14, 8, 9, 13, 12, 6, 7, 15, 11, 0, 4+64, 23, // 0-12 -> A0-A12
  380. 255, // 13 is digital only (no A13 alias)
  381. 5, 14, 8, 9, 13, 12, 6, 7, 15, 11, 0, 4+64, 23, // 14-26 are A0-A12
  382. 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // 27-37 unused
  383. 26, // 38=temperature
  384. 27 // 39=bandgap ref (PMC_REGSC |= PMC_REGSC_BGBE)
  385. };
  386. #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
  387. static const uint8_t pin2sc1a[] = {
  388. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4, 3, 19+128, 14+128, 15+128, // 0-13 -> A0-A13
  389. 5, 14, 8, 9, 13, 12, 6, 7, 15, 4, // 14-23 are A0-A9
  390. 255, 255, 255, 255, 255, 255, 255, // 24-30 are digital only
  391. 14+128, 15+128, 17, 18, 4+128, 5+128, 6+128, 7+128, 17+128, // 31-39 are A12-A20
  392. 255, 255, 255, 255, 255, 255, 255, 255, 255, // 40-48 are digital only
  393. 10+128, 11+128, // 49-50 are A23-A24
  394. 255, 255, 255, 255, 255, 255, 255, // 51-57 are digital only
  395. 255, 255, 255, 255, 255, 255, // 58-63 (sd card pins) are digital only
  396. 3, 19+128, // 64-65 are A10-A11
  397. 23, 23+128,// 66-67 are A21-A22 (DAC pins)
  398. 1, 1+128, // 68-69 are A25-A26 (unused USB host port on Teensy 3.5)
  399. 26, // 70 is Temperature Sensor
  400. 18+128 // 71 is Vref
  401. };
  402. #endif
  403. // TODO: perhaps this should store the NVIC priority, so it works recursively?
  404. static volatile uint8_t analogReadBusyADC0 = 0;
  405. #ifdef HAS_KINETIS_ADC1
  406. static volatile uint8_t analogReadBusyADC1 = 0;
  407. #endif
  408. int analogRead(uint8_t pin)
  409. {
  410. int result;
  411. uint8_t channel;
  412. //serial_phex(pin);
  413. //serial_print(" ");
  414. if (pin >= sizeof(pin2sc1a)) return 0;
  415. channel = pin2sc1a[pin];
  416. if (channel == 255) return 0;
  417. if (calibrating) wait_for_cal();
  418. #ifdef HAS_KINETIS_ADC1
  419. if (channel & 0x80) goto beginADC1;
  420. #endif
  421. __disable_irq();
  422. startADC0:
  423. //serial_print("startADC0\n");
  424. #if defined(__MKL26Z64__)
  425. if (channel & 0x40) {
  426. ADC0_CFG2 &= ~ADC_CFG2_MUXSEL;
  427. channel &= 0x3F;
  428. } else {
  429. ADC0_CFG2 |= ADC_CFG2_MUXSEL;
  430. }
  431. #endif
  432. ADC0_SC1A = channel;
  433. analogReadBusyADC0 = 1;
  434. __enable_irq();
  435. while (1) {
  436. __disable_irq();
  437. if ((ADC0_SC1A & ADC_SC1_COCO)) {
  438. result = ADC0_RA;
  439. analogReadBusyADC0 = 0;
  440. __enable_irq();
  441. result >>= analog_right_shift;
  442. return result;
  443. }
  444. // detect if analogRead was used from an interrupt
  445. // if so, our analogRead got canceled, so it must
  446. // be restarted.
  447. if (!analogReadBusyADC0) goto startADC0;
  448. __enable_irq();
  449. yield();
  450. }
  451. #ifdef HAS_KINETIS_ADC1
  452. beginADC1:
  453. __disable_irq();
  454. startADC1:
  455. //serial_print("startADC1\n");
  456. // ADC1_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b.
  457. if (channel & 0x40) {
  458. ADC1_CFG2 &= ~ADC_CFG2_MUXSEL;
  459. } else {
  460. ADC1_CFG2 |= ADC_CFG2_MUXSEL;
  461. }
  462. ADC1_SC1A = channel & 0x3F;
  463. analogReadBusyADC1 = 1;
  464. __enable_irq();
  465. while (1) {
  466. __disable_irq();
  467. if ((ADC1_SC1A & ADC_SC1_COCO)) {
  468. result = ADC1_RA;
  469. analogReadBusyADC1 = 0;
  470. __enable_irq();
  471. result >>= analog_right_shift;
  472. return result;
  473. }
  474. // detect if analogRead was used from an interrupt
  475. // if so, our analogRead got canceled, so it must
  476. // be restarted.
  477. if (!analogReadBusyADC1) goto startADC1;
  478. __enable_irq();
  479. yield();
  480. }
  481. #endif
  482. }
  483. typedef int16_t __attribute__((__may_alias__)) aliased_int16_t;
  484. void analogWriteDAC0(int val)
  485. {
  486. #if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
  487. SIM_SCGC2 |= SIM_SCGC2_DAC0;
  488. if (analog_reference_internal) {
  489. DAC0_C0 = DAC_C0_DACEN; // 1.2V ref is DACREF_1
  490. } else {
  491. DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
  492. }
  493. if (val < 0) val = 0; // TODO: saturate instruction?
  494. else if (val > 4095) val = 4095;
  495. *(volatile aliased_int16_t *)&(DAC0_DAT0L) = val;
  496. #elif defined(__MKL26Z64__)
  497. SIM_SCGC6 |= SIM_SCGC6_DAC0;
  498. if (analog_reference_internal == 0) {
  499. // use 3.3V VDDA power as the reference (this is the default)
  500. DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS | DAC_C0_DACSWTRG; // 3.3V VDDA
  501. } else {
  502. // use whatever voltage is on the AREF pin
  503. DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACSWTRG; // 3.3V VDDA
  504. }
  505. if (val < 0) val = 0;
  506. else if (val > 4095) val = 4095;
  507. *(volatile aliased_int16_t *)&(DAC0_DAT0L) = val;
  508. #endif
  509. }
  510. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
  511. void analogWriteDAC1(int val)
  512. {
  513. SIM_SCGC2 |= SIM_SCGC2_DAC1;
  514. if (analog_reference_internal) {
  515. DAC1_C0 = DAC_C0_DACEN; // 1.2V ref is DACREF_1
  516. } else {
  517. DAC1_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
  518. }
  519. if (val < 0) val = 0; // TODO: saturate instruction?
  520. else if (val > 4095) val = 4095;
  521. *(volatile aliased_int16_t *)&(DAC1_DAT0L) = val;
  522. }
  523. #endif