visus
/
teensy-cores
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
786 Commits
1 Branch
Tree: e1676586f1
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'e1676586f1'
${ noResults }
teensy-cores/teensy3/SPIFIFO.h

338 lines
17KB
Raw Blame History 

  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2017 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _SPIFIFO_h_

  32. #define _SPIFIFO_h_

  33. 

  34. #include "avr_emulation.h"

  35. 

  36. #ifdef KINETISK

  37. 

  38. // The preferred way to set SPI speed is with SPI.beginTransaction()

  39. 

  40. #if F_BUS == 120000000

  41. #define HAS_SPIFIFO

  42. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(120 / 5) * ((1+1)/2)

  43. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(120 / 2) * ((1+0)/4) = 15 MHz

  44. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0))                //(120 / 5) * ((1+0)/2)

  45. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(120 / 5) * ((1+1)/6)

  46. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(2))                //(120 / 5) * ((1+0)/4)

  47. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4)) 		    //(120 / 5) * ((1+0)/6)

  48. 

  49. #elif F_BUS == 108000000

  50. #define HAS_SPIFIFO

  51. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(108 / 5) * ((1+1)/2) = 21.6 MHz

  52. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(108 / 2) * ((1+0)/4) = 13.5 MHz

  53. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(108 / 3) * ((1+1)/6)

  54. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(108 / 5) * ((1+1)/6) = 7.2 MHz

  55. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4))                //(108 / 3) * ((1+0)/6) 

  56. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(5) | SPI_CTAR_BR(2)) 		    //(108 / 7) * ((1+0)/4) = 3.86 MHz

  57. 

  58. #elif F_BUS == 96000000

  59. #define HAS_SPIFIFO

  60. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(96 / 2) * ((1+0)/2)

  61. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(96 / 2) * ((1+1)/6)

  62. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | SPI_CTAR_DBR) //(96 / 2) * ((1+1)/8)

  63. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(2))                //(96 / 3) * ((1+0)/4)

  64. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6))                //(96 / 2) * ((1+0)/8)

  65. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(6)) 		    //(96 / 3) * ((1+0)/8)

  66. 

  67. #elif F_BUS == 90000000

  68. #define HAS_SPIFIFO

  69. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(90 / 2) * ((1+0)/2) = 22.5 MHz

  70. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(90 / 2) * ((1+1)/6) = 15 MHz

  71. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | SPI_CTAR_DBR) //(90 / 2) * ((1+1)/8) = 11.25 MHz

  72. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4))                //(90 / 2) * ((1+0)/6) = 7.5 MHz

  73. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(90 / 5) * ((1+1)/6)

  74. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(6)) 		    //(90 / 3) * ((1+0)/8) = 3.75 MHz

  75. 

  76. #elif F_BUS == 80000000

  77. #define HAS_SPIFIFO

  78. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(80 / 2) * ((1+0)/2) = 20 MHz

  79. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(80 / 5) * ((1+1)/2)

  80. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(5) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(80 / 7) * ((1+1)/2) = 11.42 MHz

  81. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0))                //(80 / 5) * ((1+0)/2)

  82. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(5) | SPI_CTAR_BR(0))                //(80 / 7) * ((1+0)/2) = 5.7 MHz

  83. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(2)) 		    //(80 / 5) * ((1+0)/4)

  84. 

  85. #elif F_BUS == 72000000

  86. #define HAS_SPIFIFO

  87. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(72 / 3) * ((1+1)/2)

  88. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(72 / 2) * ((1+1)/6) = 12 MHz

  89. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(72 / 2) * ((1+1)/6)

  90. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | SPI_CTAR_DBR) //(72 / 3) * ((1+1)/6)

  91. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4))                //(72 / 2) * ((1+0)/6)

  92. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(4)) 		    //(72 / 3) * ((1+0)/6)

  93. 

  94. #elif F_BUS == 64000000

  95. #define HAS_SPIFIFO

  96. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(64 / 3) * ((1+1)/2) = 21.3 MHz

  97. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(64 / 2) * ((1+0)/2)

  98. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0)) 		    //(64 / 3) * ((1+0)/2) = 10.67 MHz

  99. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(64 / 2) * ((1+0)/4)

  100. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(4))                //(64 / 2) * ((1+0)/6) = 5.3 MHz

  101. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(6)) 		    //(64 / 2) * ((1+0)/8)

  102. 

  103. #elif F_BUS == 60000000

  104. #define HAS_SPIFIFO

  105. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 3) * ((1+1)/2) = 20 MHz

  106. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(60 / 2) * ((1+0)/2) = 15 MHz

  107. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/2)

  108. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1))                //(60 / 2) * ((1+0)/4) = 7.5 MHz

  109. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0))                //(60 / 5) * ((1+0)/2)

  110. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(60 / 5) * ((1+1)/6)

  111. 

  112. #elif F_BUS == 56000000

  113. #define HAS_SPIFIFO

  114. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 3) * ((1+1)/2) = 18.67

  115. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(56 / 2) * ((1+0)/2) = 14

  116. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 5) * ((1+1)/2) = 11.2

  117. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(56 / 7) * ((1+1)/2)

  118. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0))                //(56 / 5) * ((1+0)/2)

  119. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0))                //(56 / 7) * ((1+0)/2)

  120. 

  121. #elif F_BUS == 48000000

  122. #define HAS_SPIFIFO

  123. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/2)

  124. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(48 / 3) * ((1+1)/2)

  125. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(48 / 2) * ((1+0)/2)

  126. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(48 / 2) * ((1+1)/6)

  127. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1))                //(48 / 2) * ((1+0)/4)

  128. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2))                //(48 / 2) * ((1+0)/6)

  129. 

  130. #elif F_BUS == 40000000

  131. #define HAS_SPIFIFO

  132. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 2) * ((1+1)/2) = 20

  133. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 3) * ((1+1)/2) = 13.33

  134. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(40 / 2) * ((1+0)/2) = 10

  135. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(40 / 5) * ((1+1)/2)

  136. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(3) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(40 / 7) * ((1+1)/2) = 5.71

  137. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(1))                //(40 / 5) * ((1+0)/2)

  138. 

  139. #elif F_BUS == 36000000

  140. #define HAS_SPIFIFO

  141. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/2) = 18

  142. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12

  143. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/2) = 12

  144. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(36 / 5) * ((1+1)/2) = 7.2

  145. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 2) * ((1+1)/6)

  146. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(36 / 3) * ((1+1)/6)

  147. 

  148. #elif F_BUS == 24000000

  149. #define HAS_SPIFIFO

  150. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz

  151. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)  12 MHz

  152. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/2)

  153. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(24 / 3) * ((1+1)/2)

  154. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0))                //(24 / 2) * ((1+0)/2)

  155. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(2) | SPI_CTAR_DBR) //(24 / 2) * ((1+1)/6)

  156. 

  157. #elif F_BUS == 16000000

  158. #define HAS_SPIFIFO

  159. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  160. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  161. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  162. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  163. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  164. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_DBR) //(16 / 2) * ((1+1)/8) = 2 MHz

  165. 

  166. #elif F_BUS == 8000000

  167. #define HAS_SPIFIFO

  168. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  169. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  170. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  171. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  172. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  173. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_DBR) //(8 / 2) * ((1+1)/4) = 2 MHz

  174. 

  175. #elif F_BUS == 4000000

  176. #define HAS_SPIFIFO

  177. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  178. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  179. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  180. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  181. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  182. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 2 MHz

  183. 

  184. #elif F_BUS == 2000000

  185. #define HAS_SPIFIFO

  186. #define SPI_CLOCK_24MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  187. #define SPI_CLOCK_16MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  188. #define SPI_CLOCK_12MHz   (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  189. #define SPI_CLOCK_8MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  190. #define SPI_CLOCK_6MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  191. #define SPI_CLOCK_4MHz    (SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR) //(4 / 2) * ((1+1)/2) = 1 MHz

  192. 

  193. #endif // F_BUS

  194. 

  195. #endif // KINETISK

  196. 

  197. /*

  198. #! /usr/bin/perl

  199. $clock = 60;

  200. for $i (2, 3, 5, 7) {

  201.         for $j (0, 1) {

  202.                 for $k (2, 4, 6, 8, 16, 32) {

  203.                         $out = $clock / $i * (1 + $j) / $k;

  204.                         printf "%0.2f :  ", $out;

  205.                         print "$clock / $i * (1 + $j) / $k = $out\n";

  206.                 }

  207.         }

  208. }

  209. */

  210. 

  211. // sck = F_BUS / PBR * ((1+DBR)/BR)

  212. //  PBR = 2, 3, 5, 7

  213. //  DBR = 0, 1         -- zero preferred

  214. //  BR = 2, 4, 6, 8, 16, 32, 64, 128, 256, 512

  215. 

  216. 

  217. #ifdef HAS_SPIFIFO

  218. 

  219. #ifndef SPI_MODE0

  220. #define SPI_MODE0 0x00  // CPOL = 0, CPHA = 0

  221. #define SPI_MODE1 0x04  // CPOL = 0, CPHA = 1

  222. #define SPI_MODE2 0x08  // CPOL = 1, CPHA = 0

  223. #define SPI_MODE3 0x0C  // CPOL = 1, CPHA = 1

  224. #endif

  225. 

  226. #define SPI_CONTINUE 1

  227. 

  228. class SPIFIFOclass

  229. {

  230. public:

  231. 	inline void begin(uint8_t pin, uint32_t speed, uint32_t mode=SPI_MODE0) __attribute__((always_inline, deprecated)) {

  232. 		uint32_t p, ctar = speed;

  233. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  234. 

  235. 		KINETISK_SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);

  236. 		if (mode & 0x08) ctar |= SPI_CTAR_CPOL;

  237. 		if (mode & 0x04) {

  238. 			ctar |= SPI_CTAR_CPHA;

  239. 			ctar |= (ctar & 0x0F) << 8;

  240. 		} else {

  241. 			ctar |= (ctar & 0x0F) << 12;

  242. 		}

  243. 		KINETISK_SPI0.CTAR0 = ctar | SPI_CTAR_FMSZ(7);

  244. 		KINETISK_SPI0.CTAR1 = ctar | SPI_CTAR_FMSZ(15);

  245. 		if (pin == 10) {         // PTC4

  246. 			CORE_PIN10_CONFIG = PORT_PCR_MUX(2);

  247. 			p = 0x01;

  248. 		} else if (pin == 2) {   // PTD0

  249. 			CORE_PIN2_CONFIG = PORT_PCR_MUX(2);

  250. 			p = 0x01;

  251. 		} else if (pin == 9) {   // PTC3

  252. 			CORE_PIN9_CONFIG = PORT_PCR_MUX(2);

  253. 			p = 0x02;

  254. 		} else if (pin == 6) {   // PTD4

  255. 			CORE_PIN6_CONFIG = PORT_PCR_MUX(2);

  256. 			p = 0x02;

  257. 		} else if (pin == 20) {  // PTD5

  258. 			CORE_PIN20_CONFIG = PORT_PCR_MUX(2);

  259. 			p = 0x04;

  260. 		} else if (pin == 23) {  // PTC2

  261. 			CORE_PIN23_CONFIG = PORT_PCR_MUX(2);

  262. 			p = 0x04;

  263. 		} else if (pin == 21) {  // PTD6

  264. 			CORE_PIN21_CONFIG = PORT_PCR_MUX(2);

  265. 			p = 0x08;

  266. 		} else if (pin == 22) {  // PTC1

  267. 			CORE_PIN22_CONFIG = PORT_PCR_MUX(2);

  268. 			p = 0x08;

  269. 		} else if (pin == 15) {  // PTC0

  270. 			CORE_PIN15_CONFIG = PORT_PCR_MUX(2);

  271. 			p = 0x10;

  272. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  273. 		} else if (pin == 26) {  

  274. 			CORE_PIN26_CONFIG = PORT_PCR_MUX(2);

  275. 			p = 0x01;

  276. #endif

  277. 		} else {

  278. 			reg = portOutputRegister(pin);

  279. 			pinMode(pin, OUTPUT);

  280. 			*reg = 1;

  281. 			p = 0;

  282. 		}

  283. 		pcs = p;

  284. 		clear();

  285. 		SPCR.enable_pins();

  286. 	}

  287. 	inline void write(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {

  288. 		uint32_t pcsbits = pcs << 16;

  289. 		if (pcsbits) {

  290. 			KINETISK_SPI0.PUSHR = (b & 0xFF) | pcsbits | (cont ? SPI_PUSHR_CONT : 0);

  291. 			while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ; // wait if FIFO full

  292. 		} else {

  293. 			*reg = 0;

  294. 			KINETISK_SPI0.SR = SPI_SR_EOQF;

  295. 			KINETISK_SPI0.PUSHR = (b & 0xFF) | (cont ? 0 : SPI_PUSHR_EOQ);

  296. 			if (cont) {

  297. 				while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  298. 			} else {

  299. 				while (!(KINETISK_SPI0.SR & SPI_SR_EOQF)) ;

  300. 				*reg = 1;

  301. 			}

  302. 		}

  303. 	}

  304. 	inline void write16(uint32_t b, uint32_t cont=0) __attribute__((always_inline)) {

  305. 		uint32_t pcsbits = pcs << 16;

  306. 		if (pcsbits) {

  307. 			KINETISK_SPI0.PUSHR = (b & 0xFFFF) | (pcs << 16) |

  308. 				(cont ? SPI_PUSHR_CONT : 0) | SPI_PUSHR_CTAS(1);

  309. 			while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  310. 		} else {

  311. 			*reg = 0;

  312. 			KINETISK_SPI0.SR = SPI_SR_EOQF;

  313. 			KINETISK_SPI0.PUSHR = (b & 0xFFFF) | (cont ? 0 : SPI_PUSHR_EOQ) | SPI_PUSHR_CTAS(1);

  314. 			if (cont) {

  315. 				while (((KINETISK_SPI0.SR) & (15 << 12)) > (3 << 12)) ;

  316. 			} else {

  317. 				while (!(KINETISK_SPI0.SR & SPI_SR_EOQF)) ;

  318. 				*reg = 1;

  319. 			}

  320. 		}

  321. 	}

  322. 	inline uint32_t read(void) __attribute__((always_inline)) {

  323. 		while ((KINETISK_SPI0.SR & (15 << 4)) == 0) ;  // TODO, could wait forever

  324. 		return KINETISK_SPI0.POPR;

  325. 	}

  326. 	inline void clear(void) __attribute__((always_inline)) {

  327. 		KINETISK_SPI0.MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F) | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;

  328. 	}

  329. private:

  330. 	static uint8_t pcs;

  331. 	static volatile uint8_t *reg;

  332. };

  333. extern SPIFIFOclass SPIFIFO;

  334. 

  335. #endif // HAS_SPIFIFO

  336. 

  337. #endif