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teensy-cores/teensy3/mk20dx128.h

1778 lines
131KB
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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2013 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be 

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows 

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _mk20dx128_h_

  32. #define _mk20dx128_h_

  33. 

  34. //#define F_CPU 96000000

  35. //#define F_CPU 48000000

  36. //#define F_CPU 24000000

  37. //#define F_BUS 48000000

  38. //#define F_BUS 24000000

  39. //#define F_MEM 24000000

  40. 

  41. #if (F_CPU == 96000000)

  42.  #define F_BUS 48000000

  43.  #define F_MEM 24000000

  44. #elif (F_CPU == 48000000)

  45.  #define F_BUS 48000000

  46.  #define F_MEM 24000000

  47. #elif (F_CPU == 24000000)

  48.  #define F_BUS 24000000

  49.  #define F_MEM 24000000

  50. #endif

  51. 

  52. 

  53. #ifndef NULL

  54. #define NULL ((void *)0)

  55. #endif

  56. 

  57. #include <stdint.h>

  58. #ifdef __cplusplus

  59. extern "C" {

  60. #endif

  61. 

  62. // chapter 11: Port control and interrupts (PORT)

  63. #define PORTA_PCR0              *(volatile uint32_t *)0x40049000 // Pin Control Register n

  64. #define PORT_PCR_ISF			(uint32_t)0x01000000		// Interrupt Status Flag

  65. #define PORT_PCR_IRQC(n)		(uint32_t)(((n) & 15) << 16)	// Interrupt Configuration

  66. #define PORT_PCR_IRQC_MASK		(uint32_t)0x000F0000

  67. #define PORT_PCR_LK			(uint32_t)0x00008000		// Lock Register

  68. #define PORT_PCR_MUX(n)			(uint32_t)(((n) & 7) << 8)	// Pin Mux Control

  69. #define PORT_PCR_MUX_MASK		(uint32_t)0x00000700

  70. #define PORT_PCR_DSE			(uint32_t)0x00000040		// Drive Strength Enable

  71. #define PORT_PCR_ODE			(uint32_t)0x00000020		// Open Drain Enable

  72. #define PORT_PCR_PFE			(uint32_t)0x00000010		// Passive Filter Enable

  73. #define PORT_PCR_SRE			(uint32_t)0x00000004		// Slew Rate Enable

  74. #define PORT_PCR_PE			(uint32_t)0x00000002		// Pull Enable

  75. #define PORT_PCR_PS			(uint32_t)0x00000001		// Pull Select

  76. #define PORTA_PCR1              *(volatile uint32_t *)0x40049004 // Pin Control Register n

  77. #define PORTA_PCR2              *(volatile uint32_t *)0x40049008 // Pin Control Register n

  78. #define PORTA_PCR3              *(volatile uint32_t *)0x4004900C // Pin Control Register n

  79. #define PORTA_PCR4              *(volatile uint32_t *)0x40049010 // Pin Control Register n

  80. #define PORTA_PCR5              *(volatile uint32_t *)0x40049014 // Pin Control Register n

  81. #define PORTA_PCR6              *(volatile uint32_t *)0x40049018 // Pin Control Register n

  82. #define PORTA_PCR7              *(volatile uint32_t *)0x4004901C // Pin Control Register n

  83. #define PORTA_PCR8              *(volatile uint32_t *)0x40049020 // Pin Control Register n

  84. #define PORTA_PCR9              *(volatile uint32_t *)0x40049024 // Pin Control Register n

  85. #define PORTA_PCR10             *(volatile uint32_t *)0x40049028 // Pin Control Register n

  86. #define PORTA_PCR11             *(volatile uint32_t *)0x4004902C // Pin Control Register n

  87. #define PORTA_PCR12             *(volatile uint32_t *)0x40049030 // Pin Control Register n

  88. #define PORTA_PCR13             *(volatile uint32_t *)0x40049034 // Pin Control Register n

  89. #define PORTA_PCR14             *(volatile uint32_t *)0x40049038 // Pin Control Register n

  90. #define PORTA_PCR15             *(volatile uint32_t *)0x4004903C // Pin Control Register n

  91. #define PORTA_PCR16             *(volatile uint32_t *)0x40049040 // Pin Control Register n

  92. #define PORTA_PCR17             *(volatile uint32_t *)0x40049044 // Pin Control Register n

  93. #define PORTA_PCR18             *(volatile uint32_t *)0x40049048 // Pin Control Register n

  94. #define PORTA_PCR19             *(volatile uint32_t *)0x4004904C // Pin Control Register n

  95. #define PORTA_PCR20             *(volatile uint32_t *)0x40049050 // Pin Control Register n

  96. #define PORTA_PCR21             *(volatile uint32_t *)0x40049054 // Pin Control Register n

  97. #define PORTA_PCR22             *(volatile uint32_t *)0x40049058 // Pin Control Register n

  98. #define PORTA_PCR23             *(volatile uint32_t *)0x4004905C // Pin Control Register n

  99. #define PORTA_PCR24             *(volatile uint32_t *)0x40049060 // Pin Control Register n

  100. #define PORTA_PCR25             *(volatile uint32_t *)0x40049064 // Pin Control Register n

  101. #define PORTA_PCR26             *(volatile uint32_t *)0x40049068 // Pin Control Register n

  102. #define PORTA_PCR27             *(volatile uint32_t *)0x4004906C // Pin Control Register n

  103. #define PORTA_PCR28             *(volatile uint32_t *)0x40049070 // Pin Control Register n

  104. #define PORTA_PCR29             *(volatile uint32_t *)0x40049074 // Pin Control Register n

  105. #define PORTA_PCR30             *(volatile uint32_t *)0x40049078 // Pin Control Register n

  106. #define PORTA_PCR31             *(volatile uint32_t *)0x4004907C // Pin Control Register n

  107. #define PORTA_GPCLR             *(volatile uint32_t *)0x40049080 // Global Pin Control Low Register

  108. #define PORTA_GPCHR             *(volatile uint32_t *)0x40049084 // Global Pin Control High Register

  109. #define PORTA_ISFR              *(volatile uint32_t *)0x400490A0 // Interrupt Status Flag Register

  110. #define PORTB_PCR0              *(volatile uint32_t *)0x4004A000 // Pin Control Register n

  111. #define PORTB_PCR1              *(volatile uint32_t *)0x4004A004 // Pin Control Register n

  112. #define PORTB_PCR2              *(volatile uint32_t *)0x4004A008 // Pin Control Register n

  113. #define PORTB_PCR3              *(volatile uint32_t *)0x4004A00C // Pin Control Register n

  114. #define PORTB_PCR4              *(volatile uint32_t *)0x4004A010 // Pin Control Register n

  115. #define PORTB_PCR5              *(volatile uint32_t *)0x4004A014 // Pin Control Register n

  116. #define PORTB_PCR6              *(volatile uint32_t *)0x4004A018 // Pin Control Register n

  117. #define PORTB_PCR7              *(volatile uint32_t *)0x4004A01C // Pin Control Register n

  118. #define PORTB_PCR8              *(volatile uint32_t *)0x4004A020 // Pin Control Register n

  119. #define PORTB_PCR9              *(volatile uint32_t *)0x4004A024 // Pin Control Register n

  120. #define PORTB_PCR10             *(volatile uint32_t *)0x4004A028 // Pin Control Register n

  121. #define PORTB_PCR11             *(volatile uint32_t *)0x4004A02C // Pin Control Register n

  122. #define PORTB_PCR12             *(volatile uint32_t *)0x4004A030 // Pin Control Register n

  123. #define PORTB_PCR13             *(volatile uint32_t *)0x4004A034 // Pin Control Register n

  124. #define PORTB_PCR14             *(volatile uint32_t *)0x4004A038 // Pin Control Register n

  125. #define PORTB_PCR15             *(volatile uint32_t *)0x4004A03C // Pin Control Register n

  126. #define PORTB_PCR16             *(volatile uint32_t *)0x4004A040 // Pin Control Register n

  127. #define PORTB_PCR17             *(volatile uint32_t *)0x4004A044 // Pin Control Register n

  128. #define PORTB_PCR18             *(volatile uint32_t *)0x4004A048 // Pin Control Register n

  129. #define PORTB_PCR19             *(volatile uint32_t *)0x4004A04C // Pin Control Register n

  130. #define PORTB_PCR20             *(volatile uint32_t *)0x4004A050 // Pin Control Register n

  131. #define PORTB_PCR21             *(volatile uint32_t *)0x4004A054 // Pin Control Register n

  132. #define PORTB_PCR22             *(volatile uint32_t *)0x4004A058 // Pin Control Register n

  133. #define PORTB_PCR23             *(volatile uint32_t *)0x4004A05C // Pin Control Register n

  134. #define PORTB_PCR24             *(volatile uint32_t *)0x4004A060 // Pin Control Register n

  135. #define PORTB_PCR25             *(volatile uint32_t *)0x4004A064 // Pin Control Register n

  136. #define PORTB_PCR26             *(volatile uint32_t *)0x4004A068 // Pin Control Register n

  137. #define PORTB_PCR27             *(volatile uint32_t *)0x4004A06C // Pin Control Register n

  138. #define PORTB_PCR28             *(volatile uint32_t *)0x4004A070 // Pin Control Register n

  139. #define PORTB_PCR29             *(volatile uint32_t *)0x4004A074 // Pin Control Register n

  140. #define PORTB_PCR30             *(volatile uint32_t *)0x4004A078 // Pin Control Register n

  141. #define PORTB_PCR31             *(volatile uint32_t *)0x4004A07C // Pin Control Register n

  142. #define PORTB_GPCLR             *(volatile uint32_t *)0x4004A080 // Global Pin Control Low Register

  143. #define PORTB_GPCHR             *(volatile uint32_t *)0x4004A084 // Global Pin Control High Register

  144. #define PORTB_ISFR              *(volatile uint32_t *)0x4004A0A0 // Interrupt Status Flag Register

  145. #define PORTC_PCR0              *(volatile uint32_t *)0x4004B000 // Pin Control Register n

  146. #define PORTC_PCR1              *(volatile uint32_t *)0x4004B004 // Pin Control Register n

  147. #define PORTC_PCR2              *(volatile uint32_t *)0x4004B008 // Pin Control Register n

  148. #define PORTC_PCR3              *(volatile uint32_t *)0x4004B00C // Pin Control Register n

  149. #define PORTC_PCR4              *(volatile uint32_t *)0x4004B010 // Pin Control Register n

  150. #define PORTC_PCR5              *(volatile uint32_t *)0x4004B014 // Pin Control Register n

  151. #define PORTC_PCR6              *(volatile uint32_t *)0x4004B018 // Pin Control Register n

  152. #define PORTC_PCR7              *(volatile uint32_t *)0x4004B01C // Pin Control Register n

  153. #define PORTC_PCR8              *(volatile uint32_t *)0x4004B020 // Pin Control Register n

  154. #define PORTC_PCR9              *(volatile uint32_t *)0x4004B024 // Pin Control Register n

  155. #define PORTC_PCR10             *(volatile uint32_t *)0x4004B028 // Pin Control Register n

  156. #define PORTC_PCR11             *(volatile uint32_t *)0x4004B02C // Pin Control Register n

  157. #define PORTC_PCR12             *(volatile uint32_t *)0x4004B030 // Pin Control Register n

  158. #define PORTC_PCR13             *(volatile uint32_t *)0x4004B034 // Pin Control Register n

  159. #define PORTC_PCR14             *(volatile uint32_t *)0x4004B038 // Pin Control Register n

  160. #define PORTC_PCR15             *(volatile uint32_t *)0x4004B03C // Pin Control Register n

  161. #define PORTC_PCR16             *(volatile uint32_t *)0x4004B040 // Pin Control Register n

  162. #define PORTC_PCR17             *(volatile uint32_t *)0x4004B044 // Pin Control Register n

  163. #define PORTC_PCR18             *(volatile uint32_t *)0x4004B048 // Pin Control Register n

  164. #define PORTC_PCR19             *(volatile uint32_t *)0x4004B04C // Pin Control Register n

  165. #define PORTC_PCR20             *(volatile uint32_t *)0x4004B050 // Pin Control Register n

  166. #define PORTC_PCR21             *(volatile uint32_t *)0x4004B054 // Pin Control Register n

  167. #define PORTC_PCR22             *(volatile uint32_t *)0x4004B058 // Pin Control Register n

  168. #define PORTC_PCR23             *(volatile uint32_t *)0x4004B05C // Pin Control Register n

  169. #define PORTC_PCR24             *(volatile uint32_t *)0x4004B060 // Pin Control Register n

  170. #define PORTC_PCR25             *(volatile uint32_t *)0x4004B064 // Pin Control Register n

  171. #define PORTC_PCR26             *(volatile uint32_t *)0x4004B068 // Pin Control Register n

  172. #define PORTC_PCR27             *(volatile uint32_t *)0x4004B06C // Pin Control Register n

  173. #define PORTC_PCR28             *(volatile uint32_t *)0x4004B070 // Pin Control Register n

  174. #define PORTC_PCR29             *(volatile uint32_t *)0x4004B074 // Pin Control Register n

  175. #define PORTC_PCR30             *(volatile uint32_t *)0x4004B078 // Pin Control Register n

  176. #define PORTC_PCR31             *(volatile uint32_t *)0x4004B07C // Pin Control Register n

  177. #define PORTC_GPCLR             *(volatile uint32_t *)0x4004B080 // Global Pin Control Low Register

  178. #define PORTC_GPCHR             *(volatile uint32_t *)0x4004B084 // Global Pin Control High Register

  179. #define PORTC_ISFR              *(volatile uint32_t *)0x4004B0A0 // Interrupt Status Flag Register

  180. #define PORTD_PCR0              *(volatile uint32_t *)0x4004C000 // Pin Control Register n

  181. #define PORTD_PCR1              *(volatile uint32_t *)0x4004C004 // Pin Control Register n

  182. #define PORTD_PCR2              *(volatile uint32_t *)0x4004C008 // Pin Control Register n

  183. #define PORTD_PCR3              *(volatile uint32_t *)0x4004C00C // Pin Control Register n

  184. #define PORTD_PCR4              *(volatile uint32_t *)0x4004C010 // Pin Control Register n

  185. #define PORTD_PCR5              *(volatile uint32_t *)0x4004C014 // Pin Control Register n

  186. #define PORTD_PCR6              *(volatile uint32_t *)0x4004C018 // Pin Control Register n

  187. #define PORTD_PCR7              *(volatile uint32_t *)0x4004C01C // Pin Control Register n

  188. #define PORTD_PCR8              *(volatile uint32_t *)0x4004C020 // Pin Control Register n

  189. #define PORTD_PCR9              *(volatile uint32_t *)0x4004C024 // Pin Control Register n

  190. #define PORTD_PCR10             *(volatile uint32_t *)0x4004C028 // Pin Control Register n

  191. #define PORTD_PCR11             *(volatile uint32_t *)0x4004C02C // Pin Control Register n

  192. #define PORTD_PCR12             *(volatile uint32_t *)0x4004C030 // Pin Control Register n

  193. #define PORTD_PCR13             *(volatile uint32_t *)0x4004C034 // Pin Control Register n

  194. #define PORTD_PCR14             *(volatile uint32_t *)0x4004C038 // Pin Control Register n

  195. #define PORTD_PCR15             *(volatile uint32_t *)0x4004C03C // Pin Control Register n

  196. #define PORTD_PCR16             *(volatile uint32_t *)0x4004C040 // Pin Control Register n

  197. #define PORTD_PCR17             *(volatile uint32_t *)0x4004C044 // Pin Control Register n

  198. #define PORTD_PCR18             *(volatile uint32_t *)0x4004C048 // Pin Control Register n

  199. #define PORTD_PCR19             *(volatile uint32_t *)0x4004C04C // Pin Control Register n

  200. #define PORTD_PCR20             *(volatile uint32_t *)0x4004C050 // Pin Control Register n

  201. #define PORTD_PCR21             *(volatile uint32_t *)0x4004C054 // Pin Control Register n

  202. #define PORTD_PCR22             *(volatile uint32_t *)0x4004C058 // Pin Control Register n

  203. #define PORTD_PCR23             *(volatile uint32_t *)0x4004C05C // Pin Control Register n

  204. #define PORTD_PCR24             *(volatile uint32_t *)0x4004C060 // Pin Control Register n

  205. #define PORTD_PCR25             *(volatile uint32_t *)0x4004C064 // Pin Control Register n

  206. #define PORTD_PCR26             *(volatile uint32_t *)0x4004C068 // Pin Control Register n

  207. #define PORTD_PCR27             *(volatile uint32_t *)0x4004C06C // Pin Control Register n

  208. #define PORTD_PCR28             *(volatile uint32_t *)0x4004C070 // Pin Control Register n

  209. #define PORTD_PCR29             *(volatile uint32_t *)0x4004C074 // Pin Control Register n

  210. #define PORTD_PCR30             *(volatile uint32_t *)0x4004C078 // Pin Control Register n

  211. #define PORTD_PCR31             *(volatile uint32_t *)0x4004C07C // Pin Control Register n

  212. #define PORTD_GPCLR             *(volatile uint32_t *)0x4004C080 // Global Pin Control Low Register

  213. #define PORTD_GPCHR             *(volatile uint32_t *)0x4004C084 // Global Pin Control High Register

  214. #define PORTD_ISFR              *(volatile uint32_t *)0x4004C0A0 // Interrupt Status Flag Register

  215. #define PORTE_PCR0              *(volatile uint32_t *)0x4004D000 // Pin Control Register n

  216. #define PORTE_PCR1              *(volatile uint32_t *)0x4004D004 // Pin Control Register n

  217. #define PORTE_PCR2              *(volatile uint32_t *)0x4004D008 // Pin Control Register n

  218. #define PORTE_PCR3              *(volatile uint32_t *)0x4004D00C // Pin Control Register n

  219. #define PORTE_PCR4              *(volatile uint32_t *)0x4004D010 // Pin Control Register n

  220. #define PORTE_PCR5              *(volatile uint32_t *)0x4004D014 // Pin Control Register n

  221. #define PORTE_PCR6              *(volatile uint32_t *)0x4004D018 // Pin Control Register n

  222. #define PORTE_PCR7              *(volatile uint32_t *)0x4004D01C // Pin Control Register n

  223. #define PORTE_PCR8              *(volatile uint32_t *)0x4004D020 // Pin Control Register n

  224. #define PORTE_PCR9              *(volatile uint32_t *)0x4004D024 // Pin Control Register n

  225. #define PORTE_PCR10             *(volatile uint32_t *)0x4004D028 // Pin Control Register n

  226. #define PORTE_PCR11             *(volatile uint32_t *)0x4004D02C // Pin Control Register n

  227. #define PORTE_PCR12             *(volatile uint32_t *)0x4004D030 // Pin Control Register n

  228. #define PORTE_PCR13             *(volatile uint32_t *)0x4004D034 // Pin Control Register n

  229. #define PORTE_PCR14             *(volatile uint32_t *)0x4004D038 // Pin Control Register n

  230. #define PORTE_PCR15             *(volatile uint32_t *)0x4004D03C // Pin Control Register n

  231. #define PORTE_PCR16             *(volatile uint32_t *)0x4004D040 // Pin Control Register n

  232. #define PORTE_PCR17             *(volatile uint32_t *)0x4004D044 // Pin Control Register n

  233. #define PORTE_PCR18             *(volatile uint32_t *)0x4004D048 // Pin Control Register n

  234. #define PORTE_PCR19             *(volatile uint32_t *)0x4004D04C // Pin Control Register n

  235. #define PORTE_PCR20             *(volatile uint32_t *)0x4004D050 // Pin Control Register n

  236. #define PORTE_PCR21             *(volatile uint32_t *)0x4004D054 // Pin Control Register n

  237. #define PORTE_PCR22             *(volatile uint32_t *)0x4004D058 // Pin Control Register n

  238. #define PORTE_PCR23             *(volatile uint32_t *)0x4004D05C // Pin Control Register n

  239. #define PORTE_PCR24             *(volatile uint32_t *)0x4004D060 // Pin Control Register n

  240. #define PORTE_PCR25             *(volatile uint32_t *)0x4004D064 // Pin Control Register n

  241. #define PORTE_PCR26             *(volatile uint32_t *)0x4004D068 // Pin Control Register n

  242. #define PORTE_PCR27             *(volatile uint32_t *)0x4004D06C // Pin Control Register n

  243. #define PORTE_PCR28             *(volatile uint32_t *)0x4004D070 // Pin Control Register n

  244. #define PORTE_PCR29             *(volatile uint32_t *)0x4004D074 // Pin Control Register n

  245. #define PORTE_PCR30             *(volatile uint32_t *)0x4004D078 // Pin Control Register n

  246. #define PORTE_PCR31             *(volatile uint32_t *)0x4004D07C // Pin Control Register n

  247. #define PORTE_GPCLR             *(volatile uint32_t *)0x4004D080 // Global Pin Control Low Register

  248. #define PORTE_GPCHR             *(volatile uint32_t *)0x4004D084 // Global Pin Control High Register

  249. #define PORTE_ISFR              *(volatile uint32_t *)0x4004D0A0 // Interrupt Status Flag Register

  250. 

  251. // Chapter 12: System Integration Module (SIM)

  252. #define SIM_SOPT1               *(volatile uint32_t *)0x40047000 // System Options Register 1

  253. #define SIM_SOPT1CFG            *(volatile uint32_t *)0x40047004 // SOPT1 Configuration Register

  254. #define SIM_SOPT2               *(volatile uint32_t *)0x40048004 // System Options Register 2

  255. #define SIM_SOPT2_USBSRC		(uint32_t)0x00040000		// 0=USB_CLKIN, 1=FFL/PLL 

  256. #define SIM_SOPT2_PLLFLLSEL		(uint32_t)0x00010000		// 0=FLL, 1=PLL

  257. #define SIM_SOPT2_TRACECLKSEL		(uint32_t)0x00001000		// 0=MCGOUTCLK, 1=CPU

  258. #define SIM_SOPT2_PTD7PAD		(uint32_t)0x00000800		// 0=normal, 1=double drive PTD7

  259. #define SIM_SOPT2_CLKOUTSEL(n)		(uint32_t)(((n) & 7) << 5)	// Selects the clock to output on the CLKOUT pin.

  260. #define SIM_SOPT2_RTCCLKOUTSEL		(uint32_t)0x00000010		// RTC clock out select

  261. #define SIM_SOPT4               *(volatile uint32_t *)0x4004800C // System Options Register 4

  262. #define SIM_SOPT5               *(volatile uint32_t *)0x40048010 // System Options Register 5

  263. #define SIM_SOPT7               *(volatile uint32_t *)0x40048018 // System Options Register 7

  264. #define SIM_SDID                *(const    uint32_t *)0x40048024 // System Device Identification Register

  265. #define SIM_SCGC4               *(volatile uint32_t *)0x40048034 // System Clock Gating Control Register 4

  266. #define SIM_SCGC4_VREF			(uint32_t)0x00100000		// VREF Clock Gate Control

  267. #define SIM_SCGC4_CMP			(uint32_t)0x00080000		// Comparator Clock Gate Control

  268. #define SIM_SCGC4_USBOTG		(uint32_t)0x00040000		// USB Clock Gate Control

  269. #define SIM_SCGC4_UART2			(uint32_t)0x00001000		// UART2 Clock Gate Control

  270. #define SIM_SCGC4_UART1			(uint32_t)0x00000800		// UART1 Clock Gate Control

  271. #define SIM_SCGC4_UART0			(uint32_t)0x00000400		// UART0 Clock Gate Control

  272. #define SIM_SCGC4_I2C0			(uint32_t)0x00000040		// I2C0 Clock Gate Control

  273. #define SIM_SCGC4_CMT			(uint32_t)0x00000004		// CMT Clock Gate Control

  274. #define SIM_SCGC4_EWM			(uint32_t)0x00000002		// EWM Clock Gate Control

  275. #define SIM_SCGC5               *(volatile uint32_t *)0x40048038 // System Clock Gating Control Register 5

  276. #define SIM_SCGC5_PORTE			(uint32_t)0x00002000		// Port E Clock Gate Control

  277. #define SIM_SCGC5_PORTD			(uint32_t)0x00001000		// Port D Clock Gate Control

  278. #define SIM_SCGC5_PORTC			(uint32_t)0x00000800		// Port C Clock Gate Control

  279. #define SIM_SCGC5_PORTB			(uint32_t)0x00000400		// Port B Clock Gate Control

  280. #define SIM_SCGC5_PORTA			(uint32_t)0x00000200		// Port A Clock Gate Control

  281. #define SIM_SCGC5_TSI			(uint32_t)0x00000020		// Touch Sense Input TSI Clock Gate Control

  282. #define SIM_SCGC5_LPTIMER		(uint32_t)0x00000001		// Low Power Timer Access Control

  283. #define SIM_SCGC6               *(volatile uint32_t *)0x4004803C // System Clock Gating Control Register 6

  284. #define SIM_SCGC6_RTC			(uint32_t)0x20000000		// RTC Access

  285. #define SIM_SCGC6_ADC0			(uint32_t)0x08000000		// ADC0 Clock Gate Control

  286. #define SIM_SCGC6_FTM1			(uint32_t)0x02000000		// FTM1 Clock Gate Control

  287. #define SIM_SCGC6_FTM0			(uint32_t)0x01000000		// FTM0 Clock Gate Control

  288. #define SIM_SCGC6_PIT			(uint32_t)0x00800000		// PIT Clock Gate Control

  289. #define SIM_SCGC6_PDB			(uint32_t)0x00400000		// PDB Clock Gate Control

  290. #define SIM_SCGC6_USBDCD		(uint32_t)0x00200000		// USB DCD Clock Gate Control

  291. #define SIM_SCGC6_CRC			(uint32_t)0x00040000		// CRC Clock Gate Control

  292. #define SIM_SCGC6_I2S			(uint32_t)0x00008000		// I2S Clock Gate Control

  293. #define SIM_SCGC6_SPI0			(uint32_t)0x00001000		// SPI0 Clock Gate Control

  294. #define SIM_SCGC6_DMAMUX		(uint32_t)0x00000002		// DMA Mux Clock Gate Control

  295. #define SIM_SCGC6_FTFL			(uint32_t)0x00000001		// Flash Memory Clock Gate Control

  296. #define SIM_SCGC7               *(volatile uint32_t *)0x40048040 // System Clock Gating Control Register 7

  297. #define SIM_SCGC7_DMA			(uint32_t)0x00000020		// DMA Clock Gate Control

  298. #define SIM_CLKDIV1             *(volatile uint32_t *)0x40048044 // System Clock Divider Register 1

  299. #define SIM_CLKDIV1_OUTDIV1(n)		(uint32_t)(((n) & 0x0F) << 28)	// divide value for the core/system clock

  300. #define SIM_CLKDIV1_OUTDIV2(n)		(uint32_t)(((n) & 0x0F) << 24)	// divide value for the peripheral clock

  301. #define SIM_CLKDIV1_OUTDIV4(n)		(uint32_t)(((n) & 0x0F) << 16)	// divide value for the flash clock

  302. #define SIM_CLKDIV2             *(volatile uint32_t *)0x40048048 // System Clock Divider Register 2

  303. #define SIM_CLKDIV2_USBDIV(n)		(uint32_t)(((n) & 0x07) << 1)

  304. #define SIM_CLKDIV2_USBFRAC		(uint32_t)0x01

  305. #define SIM_FCFG1               *(const    uint32_t *)0x4004804C // Flash Configuration Register 1

  306. #define SIM_FCFG2               *(const    uint32_t *)0x40048050 // Flash Configuration Register 2

  307. #define SIM_UIDH                *(const    uint32_t *)0x40048054 // Unique Identification Register High

  308. #define SIM_UIDMH               *(const    uint32_t *)0x40048058 // Unique Identification Register Mid-High

  309. #define SIM_UIDML               *(const    uint32_t *)0x4004805C // Unique Identification Register Mid Low

  310. #define SIM_UIDL                *(const    uint32_t *)0x40048060 // Unique Identification Register Low

  311. 

  312. // Chapter 13: Reset Control Module (RCM)

  313. #define RCM_SRS0                *(volatile uint8_t  *)0x4007F000 // System Reset Status Register 0

  314. #define RCM_SRS1                *(volatile uint8_t  *)0x4007F001 // System Reset Status Register 1

  315. #define RCM_RPFC                *(volatile uint8_t  *)0x4007F004 // Reset Pin Filter Control Register

  316. #define RCM_RPFW                *(volatile uint8_t  *)0x4007F005 // Reset Pin Filter Width Register

  317. #define RCM_MR                  *(volatile uint8_t  *)0x4007F007 // Mode Register

  318. 

  319. // Chapter 14: System Mode Controller

  320. #define SMC_PMPROT              *(volatile uint8_t  *)0x4007E000 // Power Mode Protection Register

  321. #define SMC_PMPROT_AVLP			(uint8_t)0x20			// Allow very low power modes

  322. #define SMC_PMPROT_ALLS			(uint8_t)0x08			// Allow low leakage stop mode

  323. #define SMC_PMPROT_AVLLS		(uint8_t)0x02			// Allow very low leakage stop mode

  324. #define SMC_PMCTRL              *(volatile uint8_t  *)0x4007E001 // Power Mode Control Register

  325. #define SMC_PMCTRL_LPWUI		(uint8_t)0x80			// Low Power Wake Up on Interrupt

  326. #define SMC_PMCTRL_RUNM(n)		(uint8_t)(((n) & 0x03) << 5)	// Run Mode Control

  327. #define SMC_PMCTRL_STOPA		(uint8_t)0x08			// Stop Aborted

  328. #define SMC_PMCTRL_STOPM(n)		(uint8_t)((n) & 0x07)		// Stop Mode Control

  329. #define SMC_VLLSCTRL            *(volatile uint8_t  *)0x4007E002 // VLLS Control Register

  330. #define SMC_VLLSCTRL_PORPO		(uint8_t)0x20			// POR Power Option

  331. #define SMC_VLLSCTRL_VLLSM(n)		(uint8_t)((n) & 0x07)		// VLLS Mode Control

  332. #define SMC_PMSTAT              *(volatile uint8_t  *)0x4007E003 // Power Mode Status Register

  333. #define SMC_PMSTAT_RUN			(uint8_t)0x01			// Current power mode is RUN

  334. #define SMC_PMSTAT_STOP			(uint8_t)0x02			// Current power mode is STOP

  335. #define SMC_PMSTAT_VLPR			(uint8_t)0x04			// Current power mode is VLPR

  336. #define SMC_PMSTAT_VLPW			(uint8_t)0x08			// Current power mode is VLPW

  337. #define SMC_PMSTAT_VLPS			(uint8_t)0x10			// Current power mode is VLPS

  338. #define SMC_PMSTAT_LLS			(uint8_t)0x20			// Current power mode is LLS

  339. #define SMC_PMSTAT_VLLS			(uint8_t)0x40			// Current power mode is VLLS

  340. 

  341. // Chapter 15: Power Management Controller

  342. #define PMC_LVDSC1              *(volatile uint8_t  *)0x4007D000 // Low Voltage Detect Status And Control 1 register

  343. #define PMC_LVDSC1_LVDF			(uint8_t)0x80			// Low-Voltage Detect Flag

  344. #define PMC_LVDSC1_LVDACK		(uint8_t)0x40			// Low-Voltage Detect Acknowledge

  345. #define PMC_LVDSC1_LVDIE		(uint8_t)0x20			// Low-Voltage Detect Interrupt Enable

  346. #define PMC_LVDSC1_LVDRE		(uint8_t)0x10			// Low-Voltage Detect Reset Enable

  347. #define PMC_LVDSC1_LVDV(n)		(uint8_t)((n) & 0x03)		// Low-Voltage Detect Voltage Select

  348. #define PMC_LVDSC2              *(volatile uint8_t  *)0x4007D001 // Low Voltage Detect Status And Control 2 register

  349. #define PMC_LVDSC2_LVWF			(uint8_t)0x80			// Low-Voltage Warning Flag

  350. #define PMC_LVDSC2_LVWACK		(uint8_t)0x40			// Low-Voltage Warning Acknowledge

  351. #define PMC_LVDSC2_LVWIE		(uint8_t)0x20			// Low-Voltage Warning Interrupt Enable

  352. #define PMC_LVDSC2_LVWV(n)		(uint8_t)((n) & 0x03)		// Low-Voltage Warning Voltage Select

  353. #define PMC_REGSC               *(volatile uint8_t  *)0x4007D002 // Regulator Status And Control register

  354. #define PMC_REGSC_BGEN			(uint8_t)0x10			// Bandgap Enable In VLPx Operation

  355. #define PMC_REGSC_ACKISO		(uint8_t)0x08			// Acknowledge Isolation

  356. #define PMC_REGSC_REGONS		(uint8_t)0x04			// Regulator In Run Regulation Status

  357. #define PMC_REGSC_BGBE			(uint8_t)0x01			// Bandgap Buffer Enable

  358. 

  359. // Chapter 16: Low-Leakage Wakeup Unit (LLWU)

  360. #define LLWU_PE1                *(volatile uint8_t  *)0x4007C000 // LLWU Pin Enable 1 register

  361. #define LLWU_PE2                *(volatile uint8_t  *)0x4007C001 // LLWU Pin Enable 2 register

  362. #define LLWU_PE3                *(volatile uint8_t  *)0x4007C002 // LLWU Pin Enable 3 register

  363. #define LLWU_PE4                *(volatile uint8_t  *)0x4007C003 // LLWU Pin Enable 4 register

  364. #define LLWU_ME                 *(volatile uint8_t  *)0x4007C004 // LLWU Module Enable register

  365. #define LLWU_F1                 *(volatile uint8_t  *)0x4007C005 // LLWU Flag 1 register

  366. #define LLWU_F2                 *(volatile uint8_t  *)0x4007C006 // LLWU Flag 2 register

  367. #define LLWU_F3                 *(volatile uint8_t  *)0x4007C007 // LLWU Flag 3 register

  368. #define LLWU_FILT1              *(volatile uint8_t  *)0x4007C008 // LLWU Pin Filter 1 register

  369. #define LLWU_FILT2              *(volatile uint8_t  *)0x4007C009 // LLWU Pin Filter 2 register

  370. #define LLWU_RST                *(volatile uint8_t  *)0x4007C00A // LLWU Reset Enable register

  371. 

  372. // Chapter 17: Miscellaneous Control Module (MCM)

  373. #define MCM_PLASC               *(volatile uint16_t *)0xE0080008 // Crossbar Switch (AXBS) Slave Configuration

  374. #define MCM_PLAMC               *(volatile uint16_t *)0xE008000A // Crossbar Switch (AXBS) Master Configuration

  375. #define MCM_PLACR               *(volatile uint32_t *)0xE008000C // Crossbar Switch (AXBS) Control Register

  376. 

  377. // Chapter 20: Direct Memory Access Multiplexer (DMAMUX)

  378. #define DMAMUX0_CHCFG0          *(volatile uint8_t  *)0x40021000 // Channel Configuration register

  379. #define DMAMUX0_CHCFG1          *(volatile uint8_t  *)0x40021001 // Channel Configuration register

  380. #define DMAMUX0_CHCFG2          *(volatile uint8_t  *)0x40021002 // Channel Configuration register

  381. #define DMAMUX0_CHCFG3          *(volatile uint8_t  *)0x40021003 // Channel Configuration register

  382. #define DMAMUX0_CHCFG4          *(volatile uint8_t  *)0x40021004 // Channel Configuration register

  383. #define DMAMUX0_CHCFG5          *(volatile uint8_t  *)0x40021005 // Channel Configuration register

  384. #define DMAMUX0_CHCFG6          *(volatile uint8_t  *)0x40021006 // Channel Configuration register

  385. #define DMAMUX0_CHCFG7          *(volatile uint8_t  *)0x40021007 // Channel Configuration register

  386. #define DMAMUX0_CHCFG8          *(volatile uint8_t  *)0x40021008 // Channel Configuration register

  387. #define DMAMUX0_CHCFG9          *(volatile uint8_t  *)0x40021009 // Channel Configuration register

  388. #define DMAMUX0_CHCFG10         *(volatile uint8_t  *)0x4002100A // Channel Configuration register

  389. #define DMAMUX0_CHCFG11         *(volatile uint8_t  *)0x4002100B // Channel Configuration register

  390. #define DMAMUX0_CHCFG12         *(volatile uint8_t  *)0x4002100C // Channel Configuration register

  391. #define DMAMUX0_CHCFG13         *(volatile uint8_t  *)0x4002100D // Channel Configuration register

  392. #define DMAMUX0_CHCFG14         *(volatile uint8_t  *)0x4002100E // Channel Configuration register

  393. #define DMAMUX0_CHCFG15         *(volatile uint8_t  *)0x4002100F // Channel Configuration register

  394. #define DMAMUX_DISABLE			0

  395. #define DMAMUX_TRIG			64

  396. #define DMAMUX_ENABLE			128

  397. #define DMAMUX_SOURCE_UART0_RX		2

  398. #define DMAMUX_SOURCE_UART0_TX		3

  399. #define DMAMUX_SOURCE_UART1_RX		4

  400. #define DMAMUX_SOURCE_UART1_TX		5

  401. #define DMAMUX_SOURCE_UART2_RX		6

  402. #define DMAMUX_SOURCE_UART2_TX		7

  403. #define DMAMUX_SOURCE_I2S0_RX		14

  404. #define DMAMUX_SOURCE_I2S0_TX		15

  405. #define DMAMUX_SOURCE_SPI0_RX		16

  406. #define DMAMUX_SOURCE_SPI0_TX		17

  407. #define DMAMUX_SOURCE_I2C0		22

  408. #define DMAMUX_SOURCE_FTM0_CH0		24

  409. #define DMAMUX_SOURCE_FTM0_CH1		25

  410. #define DMAMUX_SOURCE_FTM0_CH2		26

  411. #define DMAMUX_SOURCE_FTM0_CH3		27

  412. #define DMAMUX_SOURCE_FTM0_CH4		28

  413. #define DMAMUX_SOURCE_FTM0_CH5		29

  414. #define DMAMUX_SOURCE_FTM0_CH6		30

  415. #define DMAMUX_SOURCE_FTM0_CH7		31

  416. #define DMAMUX_SOURCE_FTM1_CH0		32

  417. #define DMAMUX_SOURCE_FTM1_CH1		33

  418. #define DMAMUX_SOURCE_ADC0		40

  419. #define DMAMUX_SOURCE_CMP0		42

  420. #define DMAMUX_SOURCE_CMP1		43

  421. #define DMAMUX_SOURCE_CMT		47

  422. #define DMAMUX_SOURCE_PDB		48

  423. #define DMAMUX_SOURCE_PORTA		49

  424. #define DMAMUX_SOURCE_PORTB		50

  425. #define DMAMUX_SOURCE_PORTC		51

  426. #define DMAMUX_SOURCE_PORTD		52

  427. #define DMAMUX_SOURCE_PORTE		53

  428. #define DMAMUX_SOURCE_ALWAYS0		54

  429. #define DMAMUX_SOURCE_ALWAYS1		55

  430. #define DMAMUX_SOURCE_ALWAYS2		56

  431. #define DMAMUX_SOURCE_ALWAYS3		57

  432. #define DMAMUX_SOURCE_ALWAYS4		58

  433. #define DMAMUX_SOURCE_ALWAYS5		59

  434. #define DMAMUX_SOURCE_ALWAYS6		60

  435. #define DMAMUX_SOURCE_ALWAYS7		61

  436. #define DMAMUX_SOURCE_ALWAYS8		62

  437. #define DMAMUX_SOURCE_ALWAYS9		63

  438. 

  439. // Chapter 21: Direct Memory Access Controller (eDMA)

  440. #define DMA_CR                  *(volatile uint32_t *)0x40008000 // Control Register

  441. #define DMA_CR_CX                       ((uint32_t)(1<<17))     // Cancel Transfer

  442. #define DMA_CR_ECX                      ((uint32_t)(1<<16))     // Error Cancel Transfer

  443. #define DMA_CR_EMLM                     ((uint32_t)0x80)        // Enable Minor Loop Mapping

  444. #define DMA_CR_CLM                      ((uint32_t)0x40)        // Continuous Link Mode

  445. #define DMA_CR_HALT                     ((uint32_t)0x20)        // Halt DMA Operations

  446. #define DMA_CR_HOE                      ((uint32_t)0x10)        // Halt On Error

  447. #define DMA_CR_ERCA                     ((uint32_t)0x04)        // Enable Round Robin Channel Arbitration

  448. #define DMA_CR_EDBG                     ((uint32_t)0x02)        // Enable Debug

  449. #define DMA_ES                  *(volatile uint32_t *)0x40008004 // Error Status Register

  450. #define DMA_ERQ                 *(volatile uint32_t *)0x4000800C // Enable Request Register

  451. #define DMA_ERQ_ERQ0                    ((uint32_t)1<<0)        // Enable DMA Request 0

  452. #define DMA_ERQ_ERQ1                    ((uint32_t)1<<1)        // Enable DMA Request 1

  453. #define DMA_ERQ_ERQ2                    ((uint32_t)1<<2)        // Enable DMA Request 2

  454. #define DMA_ERQ_ERQ3                    ((uint32_t)1<<3)        // Enable DMA Request 3

  455. #define DMA_EEI                 *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register

  456. #define DMA_EEI_EEI0                    ((uint32_t)1<<0)        // Enable Error Interrupt 0

  457. #define DMA_EEI_EEI1                    ((uint32_t)1<<1)        // Enable Error Interrupt 1

  458. #define DMA_EEI_EEI2                    ((uint32_t)1<<2)        // Enable Error Interrupt 2

  459. #define DMA_EEI_EEI3                    ((uint32_t)1<<3)        // Enable Error Interrupt 3

  460. #define DMA_CEEI                *(volatile uint8_t  *)0x40008018 // Clear Enable Error Interrupt Register

  461. #define DMA_CEEI_CEEI(n)                ((uint8_t)(n & 3)<<0)   // Clear Enable Error Interrupt

  462. #define DMA_CEEI_CAEE                   ((uint8_t)1<<6)         // Clear All Enable Error Interrupts

  463. #define DMA_CEEI_NOP                    ((uint8_t)1<<7)         // NOP

  464. #define DMA_SEEI                *(volatile uint8_t  *)0x40008019 // Set Enable Error Interrupt Register

  465. #define DMA_SEEI_SEEI(n)                ((uint8_t)(n & 3)<<0)   // Set Enable Error Interrupt

  466. #define DMA_SEEI_SAEE                   ((uint8_t)1<<6)         // Set All Enable Error Interrupts

  467. #define DMA_SEEI_NOP                    ((uint8_t)1<<7)         // NOP

  468. #define DMA_CERQ                *(volatile uint8_t  *)0x4000801A // Clear Enable Request Register

  469. #define DMA_CERQ_CERQ(n)                ((uint8_t)(n & 3)<<0)   // Clear Enable Request

  470. #define DMA_CERQ_CAER                   ((uint8_t)1<<6)         // Clear All Enable Requests

  471. #define DMA_CERQ_NOP                    ((uint8_t)1<<7)         // NOP

  472. #define DMA_SERQ                *(volatile uint8_t  *)0x4000801B // Set Enable Request Register

  473. #define DMA_SERQ_SERQ(n)                ((uint8_t)(n & 3)<<0)   // Set Enable Request

  474. #define DMA_SERQ_SAER                   ((uint8_t)1<<6)         // Set All Enable Requests

  475. #define DMA_SERQ_NOP                    ((uint8_t)1<<7)         // NOP

  476. #define DMA_CDNE                *(volatile uint8_t  *)0x4000801C // Clear DONE Status Bit Register

  477. #define DMA_CDNE_CDNE(n)                ((uint8_t)(n & 3)<<0)   // Clear Done Bit

  478. #define DMA_CDNE_CADN                   ((uint8_t)1<<6)         // Clear All Done Bits

  479. #define DMA_CDNE_NOP                    ((uint8_t)1<<7)         // NOP

  480. #define DMA_SSRT                *(volatile uint8_t  *)0x4000801D // Set START Bit Register

  481. #define DMA_SSRT_SSRT(n)                ((uint8_t)(n & 3)<<0)   // Set Start Bit

  482. #define DMA_SSRT_SAST                   ((uint8_t)1<<6)         // Set All Start Bits

  483. #define DMA_SSRT_NOP                    ((uint8_t)1<<7)         // NOP

  484. #define DMA_CERR                *(volatile uint8_t  *)0x4000801E // Clear Error Register

  485. #define DMA_CERR_CERR(n)                ((uint8_t)(n & 3)<<0)   // Clear Error Indicator

  486. #define DMA_CERR_CAEI                   ((uint8_t)1<<6)         // Clear All Error Indicators

  487. #define DMA_CERR_NOP                    ((uint8_t)1<<7)         // NOP

  488. #define DMA_CINT                *(volatile uint8_t  *)0x4000801F // Clear Interrupt Request Register

  489. #define DMA_CINT_CINT(n)                ((uint8_t)(n & 3)<<0)   // Clear Interrupt Request

  490. #define DMA_CINT_CAIR                   ((uint8_t)1<<6)         // Clear All Interrupt Requests

  491. #define DMA_CINT_NOP                    ((uint8_t)1<<7)         // NOP

  492. #define DMA_INT                 *(volatile uint32_t *)0x40008024 // Interrupt Request Register

  493. #define DMA_INT_INT0                    ((uint32_t)1<<0)        // Interrupt Request 0

  494. #define DMA_INT_INT1                    ((uint32_t)1<<1)        // Interrupt Request 1

  495. #define DMA_INT_INT2                    ((uint32_t)1<<2)        // Interrupt Request 2

  496. #define DMA_INT_INT3                    ((uint32_t)1<<3)        // Interrupt Request 3

  497. #define DMA_ERR                 *(volatile uint32_t *)0x4000802C // Error Register

  498. #define DMA_ERR_ERR0                    ((uint32_t)1<<0)        // Error in Channel 0

  499. #define DMA_ERR_ERR1                    ((uint32_t)1<<1)        // Error in Channel 1

  500. #define DMA_ERR_ERR2                    ((uint32_t)1<<2)        // Error in Channel 2

  501. #define DMA_ERR_ERR3                    ((uint32_t)1<<3)        // Error in Channel 3

  502. #define DMA_HRS                 *(volatile uint32_t *)0x40008034 // Hardware Request Status Register

  503. #define DMA_HRS_HRS0                    ((uint32_t)1<<0)        // Hardware Request Status Channel 0

  504. #define DMA_HRS_HRS1                    ((uint32_t)1<<1)        // Hardware Request Status Channel 1

  505. #define DMA_HRS_HRS2                    ((uint32_t)1<<2)        // Hardware Request Status Channel 2

  506. #define DMA_HRS_HRS3                    ((uint32_t)1<<3)        // Hardware Request Status Channel 3

  507. #define DMA_DCHPRI3             *(volatile uint8_t  *)0x40008100 // Channel n Priority Register

  508. #define DMA_DCHPRI2             *(volatile uint8_t  *)0x40008101 // Channel n Priority Register

  509. #define DMA_DCHPRI1             *(volatile uint8_t  *)0x40008102 // Channel n Priority Register

  510. #define DMA_DCHPRI0             *(volatile uint8_t  *)0x40008103 // Channel n Priority Register

  511. #define DMA_DCHPRI_CHPRI(n)             ((uint8_t)(n & 3)<<0)   // Channel Arbitration Priority

  512. #define DMA_DCHPRI_DPA                  ((uint8_t)1<<6)         // Disable PreEmpt Ability

  513. #define DMA_DCHPRI_ECP                  ((uint8_t)1<<7)         // Enable PreEmption

  514. 

  515. 

  516. #define DMA_TCD_ATTR_SMOD(n)		(((n) & 0x1F) << 11)

  517. #define DMA_TCD_ATTR_SSIZE(n)		(((n) & 0x7) << 8)

  518. #define DMA_TCD_ATTR_DMOD(n)		(((n) & 0x1F) << 3)

  519. #define DMA_TCD_ATTR_DSIZE(n)		(((n) & 0x7) << 0)

  520. #define DMA_TCD_ATTR_SIZE_8BIT		0

  521. #define DMA_TCD_ATTR_SIZE_16BIT		1

  522. #define DMA_TCD_ATTR_SIZE_32BIT		2

  523. #define DMA_TCD_ATTR_SIZE_16BYTE	4

  524. #define DMA_TCD_ATTR_SIZE_32BYTE	5

  525. #define DMA_TCD_CSR_BWC(n)		(((n) & 0x3) << 14)

  526. #define DMA_TCD_CSR_MAJORLINKCH(n)	(((n) & 0x3) << 8)

  527. #define DMA_TCD_CSR_DONE		0x0080

  528. #define DMA_TCD_CSR_ACTIVE		0x0040

  529. #define DMA_TCD_CSR_MAJORELINK		0x0020

  530. #define DMA_TCD_CSR_ESG			0x0010

  531. #define DMA_TCD_CSR_DREQ		0x0008

  532. #define DMA_TCD_CSR_INTHALF		0x0004

  533. #define DMA_TCD_CSR_INTMAJOR		0x0002

  534. #define DMA_TCD_CSR_START		0x0001

  535. #define DMA_TCD_CITER_MASK                  ((uint16_t)0x7FFF)     // Loop count mask

  536. #define DMA_TCD_CITER_ELINK                 ((uint16_t)1<<15)      // Enable channel linking on minor-loop complete

  537. #define DMA_TCD_BITER_MASK                  ((uint16_t)0x7FFF)     // Loop count mask

  538. #define DMA_TCD_BITER_ELINK                 ((uint16_t)1<<15)      // Enable channel linking on minor-loop complete

  539. #define DMA_TCD_NBYTES_SMLOE                ((uint32_t)1<<31)               // Source Minor Loop Offset Enable

  540. #define DMA_TCD_NBYTES_DMLOE                ((uint32_t)1<<30)               // Destination Minor Loop Offset Enable

  541. #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n)    ((uint32_t)(n))                 // NBytes transfer count when minor loop disabled

  542. #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n)   ((uint32_t)(n & 0x1F))          // NBytes transfer count when minor loop enabled

  543. #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n)    ((uint32_t)(n & 0xFFFFF)<<10)   // Offset 

  544. 

  545. #define DMA_TCD0_SADDR          *(volatile const void * volatile *)0x40009000 // TCD Source Address

  546. #define DMA_TCD0_SOFF           *(volatile int16_t *)0x40009004  // TCD Signed Source Address Offset

  547. #define DMA_TCD0_ATTR           *(volatile uint16_t *)0x40009006 // TCD Transfer Attributes

  548. #define DMA_TCD0_NBYTES_MLNO    *(volatile uint32_t *)0x40009008 // TCD Minor Byte Count (Minor Loop Disabled)

  549. #define DMA_TCD0_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

  550. #define DMA_TCD0_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009008 // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

  551. #define DMA_TCD0_SLAST          *(volatile int32_t *)0x4000900C  // TCD Last Source Address Adjustment

  552. #define DMA_TCD0_DADDR          *(volatile void * volatile *)0x40009010 // TCD Destination Address

  553. #define DMA_TCD0_DOFF           *(volatile int16_t *)0x40009014  // TCD Signed Destination Address Offset

  554. #define DMA_TCD0_CITER_ELINKYES *(volatile uint16_t *)0x40009016 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  555. #define DMA_TCD0_CITER_ELINKNO  *(volatile uint16_t *)0x40009016 // ??

  556. #define DMA_TCD0_DLASTSGA       *(volatile int32_t *)0x40009018  // TCD Last Destination Address Adjustment/Scatter Gather Address

  557. #define DMA_TCD0_CSR            *(volatile uint16_t *)0x4000901C // TCD Control and Status

  558. #define DMA_TCD0_BITER_ELINKYES *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled

  559. #define DMA_TCD0_BITER_ELINKNO  *(volatile uint16_t *)0x4000901E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled

  560. 

  561. #define DMA_TCD1_SADDR          *(volatile const void * volatile *)0x40009020 // TCD Source Address

  562. #define DMA_TCD1_SOFF           *(volatile int16_t *)0x40009024  // TCD Signed Source Address Offset

  563. #define DMA_TCD1_ATTR           *(volatile uint16_t *)0x40009026 // TCD Transfer Attributes

  564. #define DMA_TCD1_NBYTES_MLNO    *(volatile uint32_t *)0x40009028 // TCD Minor Byte Count, Minor Loop Disabled

  565. #define DMA_TCD1_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled

  566. #define DMA_TCD1_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009028 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled

  567. #define DMA_TCD1_SLAST          *(volatile int32_t *)0x4000902C  // TCD Last Source Address Adjustment

  568. #define DMA_TCD1_DADDR          *(volatile void * volatile *)0x40009030 // TCD Destination Address

  569. #define DMA_TCD1_DOFF           *(volatile int16_t *)0x40009034  // TCD Signed Destination Address Offset

  570. #define DMA_TCD1_CITER_ELINKYES *(volatile uint16_t *)0x40009036 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  571. #define DMA_TCD1_CITER_ELINKNO  *(volatile uint16_t *)0x40009036 // ??

  572. #define DMA_TCD1_DLASTSGA       *(volatile int32_t *)0x40009038  // TCD Last Destination Address Adjustment/Scatter Gather Address

  573. #define DMA_TCD1_CSR            *(volatile uint16_t *)0x4000903C // TCD Control and Status

  574. #define DMA_TCD1_BITER_ELINKYES *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled

  575. #define DMA_TCD1_BITER_ELINKNO  *(volatile uint16_t *)0x4000903E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled

  576. 

  577. #define DMA_TCD2_SADDR          *(volatile const void * volatile *)0x40009040 // TCD Source Address

  578. #define DMA_TCD2_SOFF           *(volatile int16_t *)0x40009044  // TCD Signed Source Address Offset

  579. #define DMA_TCD2_ATTR           *(volatile uint16_t *)0x40009046 // TCD Transfer Attributes

  580. #define DMA_TCD2_NBYTES_MLNO    *(volatile uint32_t *)0x40009048 // TCD Minor Byte Count, Minor Loop Disabled

  581. #define DMA_TCD2_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled

  582. #define DMA_TCD2_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009048 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled

  583. #define DMA_TCD2_SLAST          *(volatile int32_t *)0x4000904C  // TCD Last Source Address Adjustment

  584. #define DMA_TCD2_DADDR          *(volatile void * volatile *)0x40009050 // TCD Destination Address

  585. #define DMA_TCD2_DOFF           *(volatile int16_t *)0x40009054  // TCD Signed Destination Address Offset

  586. #define DMA_TCD2_CITER_ELINKYES *(volatile uint16_t *)0x40009056 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  587. #define DMA_TCD2_CITER_ELINKNO  *(volatile uint16_t *)0x40009056 // ??

  588. #define DMA_TCD2_DLASTSGA       *(volatile int32_t *)0x40009058  // TCD Last Destination Address Adjustment/Scatter Gather Address

  589. #define DMA_TCD2_CSR            *(volatile uint16_t *)0x4000905C // TCD Control and Status

  590. #define DMA_TCD2_BITER_ELINKYES *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled

  591. #define DMA_TCD2_BITER_ELINKNO  *(volatile uint16_t *)0x4000905E // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled

  592. 

  593. #define DMA_TCD3_SADDR          *(volatile const void * volatile *)0x40009060 // TCD Source Address

  594. #define DMA_TCD3_SOFF           *(volatile int16_t *)0x40009064  // TCD Signed Source Address Offset

  595. #define DMA_TCD3_ATTR           *(volatile uint16_t *)0x40009066 // TCD Transfer Attributes

  596. #define DMA_TCD3_NBYTES_MLNO    *(volatile uint32_t *)0x40009068 // TCD Minor Byte Count, Minor Loop Disabled

  597. #define DMA_TCD3_NBYTES_MLOFFNO *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled

  598. #define DMA_TCD3_NBYTES_MLOFFYES *(volatile uint32_t *)0x40009068 // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled

  599. #define DMA_TCD3_SLAST          *(volatile int32_t *)0x4000906C  // TCD Last Source Address Adjustment

  600. #define DMA_TCD3_DADDR          *(volatile void * volatile *)0x40009070 // TCD Destination Address

  601. #define DMA_TCD3_DOFF           *(volatile int16_t *)0x40009074  // TCD Signed Destination Address Offset

  602. #define DMA_TCD3_CITER_ELINKYES *(volatile uint16_t *)0x40009076 // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled

  603. #define DMA_TCD3_CITER_ELINKNO  *(volatile uint16_t *)0x40009076 // ??

  604. #define DMA_TCD3_DLASTSGA       *(volatile int32_t *)0x40009078  // TCD Last Destination Address Adjustment/Scatter Gather Address

  605. #define DMA_TCD3_CSR            *(volatile uint16_t *)0x4000907C // TCD Control and Status

  606. #define DMA_TCD3_BITER_ELINKYES *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled

  607. #define DMA_TCD3_BITER_ELINKNO  *(volatile uint16_t *)0x4000907E // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled

  608. 

  609. // Chapter 22: External Watchdog Monitor (EWM)

  610. #define EWM_CTRL                *(volatile uint8_t  *)0x40061000 // Control Register

  611. #define EWM_SERV                *(volatile uint8_t  *)0x40061001 // Service Register

  612. #define EWM_CMPL                *(volatile uint8_t  *)0x40061002 // Compare Low Register

  613. #define EWM_CMPH                *(volatile uint8_t  *)0x40061003 // Compare High Register

  614. 

  615. // Chapter 23: Watchdog Timer (WDOG)

  616. #define WDOG_STCTRLH            *(volatile uint16_t *)0x40052000 // Watchdog Status and Control Register High

  617. #define WDOG_STCTRLH_DISTESTWDOG	(uint16_t)0x4000		// Allows the WDOG's functional test mode to be disabled permanently.

  618. #define WDOG_STCTRLH_BYTESEL(n)		(uint16_t)(((n) & 3) << 12)	// selects the byte to be tested when the watchdog is in the byte test mode.

  619. #define WDOG_STCTRLH_TESTSEL		(uint16_t)0x0800

  620. #define WDOG_STCTRLH_TESTWDOG		(uint16_t)0x0400

  621. #define WDOG_STCTRLH_WAITEN		(uint16_t)0x0080

  622. #define WDOG_STCTRLH_STOPEN		(uint16_t)0x0040

  623. #define WDOG_STCTRLH_DBGEN		(uint16_t)0x0020

  624. #define WDOG_STCTRLH_ALLOWUPDATE	(uint16_t)0x0010

  625. #define WDOG_STCTRLH_WINEN		(uint16_t)0x0008

  626. #define WDOG_STCTRLH_IRQRSTEN		(uint16_t)0x0004

  627. #define WDOG_STCTRLH_CLKSRC		(uint16_t)0x0002

  628. #define WDOG_STCTRLH_WDOGEN		(uint16_t)0x0001

  629. #define WDOG_STCTRLL            *(volatile uint16_t *)0x40052002 // Watchdog Status and Control Register Low

  630. #define WDOG_TOVALH             *(volatile uint16_t *)0x40052004 // Watchdog Time-out Value Register High

  631. #define WDOG_TOVALL             *(volatile uint16_t *)0x40052006 // Watchdog Time-out Value Register Low

  632. #define WDOG_WINH               *(volatile uint16_t *)0x40052008 // Watchdog Window Register High

  633. #define WDOG_WINL               *(volatile uint16_t *)0x4005200A // Watchdog Window Register Low

  634. #define WDOG_REFRESH            *(volatile uint16_t *)0x4005200C // Watchdog Refresh register

  635. #define WDOG_UNLOCK             *(volatile uint16_t *)0x4005200E // Watchdog Unlock register

  636. #define WDOG_UNLOCK_SEQ1		(uint16_t)0xC520

  637. #define WDOG_UNLOCK_SEQ2		(uint16_t)0xD928

  638. #define WDOG_TMROUTH            *(volatile uint16_t *)0x40052010 // Watchdog Timer Output Register High

  639. #define WDOG_TMROUTL            *(volatile uint16_t *)0x40052012 // Watchdog Timer Output Register Low

  640. #define WDOG_RSTCNT             *(volatile uint16_t *)0x40052014 // Watchdog Reset Count register

  641. #define WDOG_PRESC              *(volatile uint16_t *)0x40052016 // Watchdog Prescaler register

  642. 

  643. // Chapter 24: Multipurpose Clock Generator (MCG)

  644. #define MCG_C1                  *(volatile uint8_t  *)0x40064000 // MCG Control 1 Register

  645. #define MCG_C1_IREFSTEN			(uint8_t)0x01			// Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.

  646. #define MCG_C1_IRCLKEN			(uint8_t)0x02			// Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.

  647. #define MCG_C1_IREFS			(uint8_t)0x04			// Internal Reference Select, Selects the reference clock source for the FLL.

  648. #define MCG_C1_FRDIV(n)			(uint8_t)(((n) & 0x07) << 3)	// FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL

  649. #define MCG_C1_CLKS(n)			(uint8_t)(((n) & 0x03) << 6)	// Clock Source Select, Selects the clock source for MCGOUTCLK

  650. #define MCG_C2                  *(volatile uint8_t  *)0x40064001 // MCG Control 2 Register

  651. #define MCG_C2_IRCS			(uint8_t)0x01			// Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.

  652. #define MCG_C2_LP			(uint8_t)0x02			// Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.

  653. #define MCG_C2_EREFS			(uint8_t)0x04			// External Reference Select, Selects the source for the external reference clock. 

  654. #define MCG_C2_HGO0			(uint8_t)0x08			// High Gain Oscillator Select, Controls the crystal oscillator mode of operation

  655. #define MCG_C2_RANGE0(n)		(uint8_t)(((n) & 0x03) << 4)	// Frequency Range Select, Selects the frequency range for the crystal oscillator

  656. #define MCG_C2_LOCRE0			(uint8_t)0x80			// Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 

  657. #define MCG_C3                  *(volatile uint8_t  *)0x40064002 // MCG Control 3 Register

  658. #define MCG_C3_SCTRIM(n)		(uint8_t)(n)			// Slow Internal Reference Clock Trim Setting

  659. #define MCG_C4                  *(volatile uint8_t  *)0x40064003 // MCG Control 4 Register

  660. #define MCG_C4_SCFTRIM			(uint8_t)0x01			// Slow Internal Reference Clock Fine Trim

  661. #define MCG_C4_FCTRIM(n)		(uint8_t)(((n) & 0x0F) << 1)	// Fast Internal Reference Clock Trim Setting

  662. #define MCG_C4_DRST_DRS(n)		(uint8_t)(((n) & 0x03) << 5)	// DCO Range Select

  663. #define MCG_C4_DMX32			(uint8_t)0x80			// DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed

  664. #define MCG_C5                  *(volatile uint8_t  *)0x40064004 // MCG Control 5 Register

  665. #define MCG_C5_PRDIV0(n)		(uint8_t)((n) & 0x1F)		// PLL External Reference Divider

  666. #define MCG_C5_PLLSTEN0			(uint8_t)0x20			// PLL Stop Enable

  667. #define MCG_C5_PLLCLKEN0		(uint8_t)0x40			// PLL Clock Enable

  668. #define MCG_C6                  *(volatile uint8_t  *)0x40064005 // MCG Control 6 Register

  669. #define MCG_C6_VDIV0(n)			(uint8_t)((n) & 0x1F)		// VCO 0 Divider

  670. #define MCG_C6_CME0			(uint8_t)0x20			// Clock Monitor Enable

  671. #define MCG_C6_PLLS			(uint8_t)0x40			// PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. 

  672. #define MCG_C6_LOLIE0			(uint8_t)0x80			// Loss of Lock Interrrupt Enable

  673. #define MCG_S                   *(volatile uint8_t  *)0x40064006 // MCG Status Register

  674. #define MCG_S_IRCST			(uint8_t)0x01			// Internal Reference Clock Status

  675. #define MCG_S_OSCINIT0			(uint8_t)0x02			// OSC Initialization,  resets to 0, is set to 1 after the initialization cycles of the crystal oscillator

  676. #define MCG_S_CLKST(n)			(uint8_t)(((n) & 0x03) << 2)	// Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL

  677. #define MCG_S_CLKST_MASK		(uint8_t)0x0C

  678. #define MCG_S_IREFST			(uint8_t)0x10			// Internal Reference Status

  679. #define MCG_S_PLLST			(uint8_t)0x20			// PLL Select Status

  680. #define MCG_S_LOCK0			(uint8_t)0x40			// Lock Status, 0=PLL Unlocked, 1=PLL Locked

  681. #define MCG_S_LOLS0			(uint8_t)0x80			// Loss of Lock Status

  682. #define MCG_SC                  *(volatile uint8_t  *)0x40064008 // MCG Status and Control Register

  683. #define MCG_SC_LOCS0			(uint8_t)0x01			// OSC0 Loss of Clock Status

  684. #define MCG_SC_FCRDIV(n)		(uint8_t)(((n) & 0x07) << 1)	// Fast Clock Internal Reference Divider

  685. #define MCG_SC_FLTPRSRV			(uint8_t)0x10			// FLL Filter Preserve Enable

  686. #define MCG_SC_ATMF			(uint8_t)0x20			// Automatic Trim Machine Fail Flag

  687. #define MCG_SC_ATMS			(uint8_t)0x40			// Automatic Trim Machine Select

  688. #define MCG_SC_ATME			(uint8_t)0x80			// Automatic Trim Machine Enable

  689. #define MCG_ATCVH               *(volatile uint8_t  *)0x4006400A // MCG Auto Trim Compare Value High Register

  690. #define MCG_ATCVL               *(volatile uint8_t  *)0x4006400B // MCG Auto Trim Compare Value Low Register

  691. #define MCG_C7                  *(volatile uint8_t  *)0x4006400C // MCG Control 7 Register

  692. #define MCG_C8                  *(volatile uint8_t  *)0x4006400D // MCG Control 8 Register

  693. 

  694. // Chapter 25: Oscillator (OSC)

  695. #define OSC0_CR                 *(volatile uint8_t  *)0x40065000 // OSC Control Register

  696. #define OSC_SC16P			(uint8_t)0x01			// Oscillator 16 pF Capacitor Load Configure

  697. #define OSC_SC8P			(uint8_t)0x02			// Oscillator 8 pF Capacitor Load Configure

  698. #define OSC_SC4P			(uint8_t)0x04			// Oscillator 4 pF Capacitor Load Configure

  699. #define OSC_SC2P			(uint8_t)0x08			// Oscillator 2 pF Capacitor Load Configure

  700. #define OSC_EREFSTEN			(uint8_t)0x20			// External Reference Stop Enable, Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.

  701. #define OSC_ERCLKEN			(uint8_t)0x80			// External Reference Enable, Enables external reference clock (OSCERCLK).

  702. 

  703. // Chapter 27: Flash Memory Controller (FMC)

  704. #define FMC_PFAPR		*(volatile uint32_t *)0x4001F000	// Flash Access Protection

  705. #define FMC_PFB0CR		*(volatile uint32_t *)0x4001F004	// Flash Control

  706. #define FMC_TAGVDW0S0		*(volatile uint32_t *)0x4001F100	// Cache Tag Storage

  707. #define FMC_TAGVDW0S1		*(volatile uint32_t *)0x4001F104	// Cache Tag Storage

  708. #define FMC_TAGVDW1S0		*(volatile uint32_t *)0x4001F108	// Cache Tag Storage

  709. #define FMC_TAGVDW1S1		*(volatile uint32_t *)0x4001F10C	// Cache Tag Storage

  710. #define FMC_TAGVDW2S0		*(volatile uint32_t *)0x4001F110	// Cache Tag Storage

  711. #define FMC_TAGVDW2S1		*(volatile uint32_t *)0x4001F114	// Cache Tag Storage

  712. #define FMC_TAGVDW3S0		*(volatile uint32_t *)0x4001F118	// Cache Tag Storage

  713. #define FMC_TAGVDW3S1		*(volatile uint32_t *)0x4001F11C	// Cache Tag Storage

  714. #define FMC_DATAW0S0		*(volatile uint32_t *)0x4001F200	// Cache Data Storage

  715. #define FMC_DATAW0S1		*(volatile uint32_t *)0x4001F204	// Cache Data Storage

  716. #define FMC_DATAW1S0		*(volatile uint32_t *)0x4001F208	// Cache Data Storage

  717. #define FMC_DATAW1S1		*(volatile uint32_t *)0x4001F20C	// Cache Data Storage

  718. #define FMC_DATAW2S0		*(volatile uint32_t *)0x4001F210	// Cache Data Storage

  719. #define FMC_DATAW2S1		*(volatile uint32_t *)0x4001F214	// Cache Data Storage

  720. #define FMC_DATAW3S0		*(volatile uint32_t *)0x4001F218	// Cache Data Storage

  721. #define FMC_DATAW3S1		*(volatile uint32_t *)0x4001F21C	// Cache Data Storage

  722. 

  723. // Chapter 28: Flash Memory Module (FTFL)

  724. #define FTFL_FSTAT		*(volatile uint8_t  *)0x40020000      // Flash Status Register

  725. #define FTFL_FSTAT_CCIF			(uint8_t)0x80			// Command Complete Interrupt Flag

  726. #define FTFL_FSTAT_RDCOLERR		(uint8_t)0x40			// Flash Read Collision Error Flag

  727. #define FTFL_FSTAT_ACCERR		(uint8_t)0x20			// Flash Access Error Flag

  728. #define FTFL_FSTAT_FPVIOL		(uint8_t)0x10			// Flash Protection Violation Flag

  729. #define FTFL_FSTAT_MGSTAT0		(uint8_t)0x01			// Memory Controller Command Completion Status Flag

  730. #define FTFL_FCNFG		*(volatile uint8_t  *)0x40020001      // Flash Configuration Register

  731. #define FTFL_FCNFG_CCIE			(uint8_t)0x80			// Command Complete Interrupt Enable

  732. #define FTFL_FCNFG_RDCOLLIE		(uint8_t)0x40			// Read Collision Error Interrupt Enable

  733. #define FTFL_FCNFG_ERSAREQ		(uint8_t)0x20			// Erase All Request

  734. #define FTFL_FCNFG_ERSSUSP		(uint8_t)0x10			// Erase Suspend

  735. #define FTFL_FCNFG_PFLSH		(uint8_t)0x04			// Flash memory configuration

  736. #define FTFL_FCNFG_RAMRDY		(uint8_t)0x02			// RAM Ready

  737. #define FTFL_FCNFG_EEERDY		(uint8_t)0x01			// EEPROM Ready

  738. #define FTFL_FSEC               *(const    uint8_t  *)0x40020002      // Flash Security Register

  739. #define FTFL_FOPT               *(const    uint8_t  *)0x40020003      // Flash Option Register

  740. #define FTFL_FCCOB3             *(volatile uint8_t  *)0x40020004      // Flash Common Command Object Registers

  741. #define FTFL_FCCOB2             *(volatile uint8_t  *)0x40020005

  742. #define FTFL_FCCOB1             *(volatile uint8_t  *)0x40020006

  743. #define FTFL_FCCOB0             *(volatile uint8_t  *)0x40020007

  744. #define FTFL_FCCOB7             *(volatile uint8_t  *)0x40020008

  745. #define FTFL_FCCOB6             *(volatile uint8_t  *)0x40020009

  746. #define FTFL_FCCOB5             *(volatile uint8_t  *)0x4002000A

  747. #define FTFL_FCCOB4             *(volatile uint8_t  *)0x4002000B

  748. #define FTFL_FCCOBB             *(volatile uint8_t  *)0x4002000C

  749. #define FTFL_FCCOBA             *(volatile uint8_t  *)0x4002000D

  750. #define FTFL_FCCOB9             *(volatile uint8_t  *)0x4002000E

  751. #define FTFL_FCCOB8             *(volatile uint8_t  *)0x4002000F

  752. #define FTFL_FPROT3             *(volatile uint8_t  *)0x40020010      // Program Flash Protection Registers

  753. #define FTFL_FPROT2             *(volatile uint8_t  *)0x40020011      // Program Flash Protection Registers

  754. #define FTFL_FPROT1             *(volatile uint8_t  *)0x40020012      // Program Flash Protection Registers

  755. #define FTFL_FPROT0             *(volatile uint8_t  *)0x40020013      // Program Flash Protection Registers

  756. #define FTFL_FEPROT             *(volatile uint8_t  *)0x40020016      // EEPROM Protection Register

  757. #define FTFL_FDPROT             *(volatile uint8_t  *)0x40020017      // Data Flash Protection Register

  758. 

  759. // Chapter 30: Cyclic Redundancy Check (CRC)

  760. #define CRC_CRC                 *(volatile uint32_t *)0x40032000 // CRC Data register

  761. #define CRC_GPOLY               *(volatile uint32_t *)0x40032004 // CRC Polynomial register

  762. #define CRC_CTRL                *(volatile uint32_t *)0x40032008 // CRC Control register

  763. 

  764. // Chapter 31: Analog-to-Digital Converter (ADC)

  765. #define ADC0_SC1A               *(volatile uint32_t *)0x4003B000 // ADC status and control registers 1

  766. #define ADC0_SC1B               *(volatile uint32_t *)0x4003B004 // ADC status and control registers 1

  767. #define ADC_SC1_COCO			(uint32_t)0x80			// Conversion complete flag

  768. #define ADC_SC1_AIEN			(uint32_t)0x40			// Interrupt enable

  769. #define ADC_SC1_DIFF			(uint32_t)0x20			// Differential mode enable

  770. #define ADC_SC1_ADCH(n)			(uint32_t)((n) & 0x1F)		// Input channel select

  771. #define ADC0_CFG1               *(volatile uint32_t *)0x4003B008 // ADC configuration register 1

  772. #define ADC_CFG1_ADLPC			(uint32_t)0x80			// Low-power configuration

  773. #define ADC_CFG1_ADIV(n)		(uint32_t)(((n) & 3) << 5)	// Clock divide select, 0=direct, 1=div2, 2=div4, 3=div8

  774. #define ADC_CFG1_ADLSMP			(uint32_t)0x10			// Sample time configuration, 0=Short, 1=Long

  775. #define ADC_CFG1_MODE(n)		(uint32_t)(((n) & 3) << 2)	// Conversion mode, 0=8 bit, 1=12 bit, 2=10 bit, 3=16 bit

  776. #define ADC_CFG1_ADICLK(n)		(uint32_t)(((n) & 3) << 0)	// Input clock, 0=bus, 1=bus/2, 2=OSCERCLK, 3=async

  777. #define ADC0_CFG2               *(volatile uint32_t *)0x4003B00C // Configuration register 2

  778. #define ADC_CFG2_MUXSEL			(uint32_t)0x10			// 0=a channels, 1=b channels

  779. #define ADC_CFG2_ADACKEN		(uint32_t)0x08			// async clock enable

  780. #define ADC_CFG2_ADHSC			(uint32_t)0x04			// High speed configuration

  781. #define ADC_CFG2_ADLSTS(n)		(uint32_t)(((n) & 3) << 0)	// Sample time, 0=24 cycles, 1=12 cycles, 2=6 cycles, 3=2 cycles

  782. #define ADC0_RA                 *(volatile uint32_t *)0x4003B010 // ADC data result register

  783. #define ADC0_RB                 *(volatile uint32_t *)0x4003B014 // ADC data result register

  784. #define ADC0_CV1                *(volatile uint32_t *)0x4003B018 // Compare value registers

  785. #define ADC0_CV2                *(volatile uint32_t *)0x4003B01C // Compare value registers

  786. #define ADC0_SC2                *(volatile uint32_t *)0x4003B020 // Status and control register 2

  787. #define ADC_SC2_ADACT			(uint32_t)0x80			// Conversion active

  788. #define ADC_SC2_ADTRG			(uint32_t)0x40			// Conversion trigger select, 0=software, 1=hardware

  789. #define ADC_SC2_ACFE			(uint32_t)0x20			// Compare function enable

  790. #define ADC_SC2_ACFGT			(uint32_t)0x10			// Compare function greater than enable

  791. #define ADC_SC2_ACREN			(uint32_t)0x08			// Compare function range enable

  792. #define ADC_SC2_DMAEN			(uint32_t)0x04			// DMA enable

  793. #define ADC_SC2_REFSEL(n)		(uint32_t)(((n) & 3) << 0)	// Voltage reference, 0=vcc/external, 1=1.2 volts

  794. #define ADC0_SC3                *(volatile uint32_t *)0x4003B024 // Status and control register 3

  795. #define ADC_SC3_CAL			(uint32_t)0x80			// Calibration, 1=begin, stays set while cal in progress

  796. #define ADC_SC3_CALF			(uint32_t)0x40			// Calibration failed flag

  797. #define ADC_SC3_ADCO			(uint32_t)0x08			// Continuous conversion enable

  798. #define ADC_SC3_AVGE			(uint32_t)0x04			// Hardware average enable

  799. #define ADC_SC3_AVGS(n)			(uint32_t)(((n) & 3) << 0)	// avg select, 0=4 samples, 1=8 samples, 2=16 samples, 3=32 samples

  800. #define ADC0_OFS                *(volatile uint32_t *)0x4003B028 // ADC offset correction register

  801. #define ADC0_PG                 *(volatile uint32_t *)0x4003B02C // ADC plus-side gain register

  802. #define ADC0_MG                 *(volatile uint32_t *)0x4003B030 // ADC minus-side gain register

  803. #define ADC0_CLPD               *(volatile uint32_t *)0x4003B034 // ADC plus-side general calibration value register

  804. #define ADC0_CLPS               *(volatile uint32_t *)0x4003B038 // ADC plus-side general calibration value register

  805. #define ADC0_CLP4               *(volatile uint32_t *)0x4003B03C // ADC plus-side general calibration value register

  806. #define ADC0_CLP3               *(volatile uint32_t *)0x4003B040 // ADC plus-side general calibration value register

  807. #define ADC0_CLP2               *(volatile uint32_t *)0x4003B044 // ADC plus-side general calibration value register

  808. #define ADC0_CLP1               *(volatile uint32_t *)0x4003B048 // ADC plus-side general calibration value register

  809. #define ADC0_CLP0               *(volatile uint32_t *)0x4003B04C // ADC plus-side general calibration value register

  810. #define ADC0_CLMD               *(volatile uint32_t *)0x4003B054 // ADC minus-side general calibration value register

  811. #define ADC0_CLMS               *(volatile uint32_t *)0x4003B058 // ADC minus-side general calibration value register

  812. #define ADC0_CLM4               *(volatile uint32_t *)0x4003B05C // ADC minus-side general calibration value register

  813. #define ADC0_CLM3               *(volatile uint32_t *)0x4003B060 // ADC minus-side general calibration value register

  814. #define ADC0_CLM2               *(volatile uint32_t *)0x4003B064 // ADC minus-side general calibration value register

  815. #define ADC0_CLM1               *(volatile uint32_t *)0x4003B068 // ADC minus-side general calibration value register

  816. #define ADC0_CLM0               *(volatile uint32_t *)0x4003B06C // ADC minus-side general calibration value register

  817. //#define MCG_C2_RANGE0(n)		(uint8_t)(((n) & 0x03) << 4)	// Frequency Range Select, Selects the frequency range for the crystal oscillator

  818. //#define MCG_C2_LOCRE0			(uint8_t)0x80			// Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0 

  819. 

  820. // Chapter 32: Comparator (CMP)

  821. #define CMP0_CR0                *(volatile uint8_t  *)0x40073000 // CMP Control Register 0

  822. #define CMP0_CR1                *(volatile uint8_t  *)0x40073001 // CMP Control Register 1

  823. #define CMP0_FPR                *(volatile uint8_t  *)0x40073002 // CMP Filter Period Register

  824. #define CMP0_SCR                *(volatile uint8_t  *)0x40073003 // CMP Status and Control Register

  825. #define CMP0_DACCR              *(volatile uint8_t  *)0x40073004 // DAC Control Register

  826. #define CMP0_MUXCR              *(volatile uint8_t  *)0x40073005 // MUX Control Register

  827. #define CMP1_CR0                *(volatile uint8_t  *)0x40073008 // CMP Control Register 0

  828. #define CMP1_CR1                *(volatile uint8_t  *)0x40073009 // CMP Control Register 1

  829. #define CMP1_FPR                *(volatile uint8_t  *)0x4007300A // CMP Filter Period Register

  830. #define CMP1_SCR                *(volatile uint8_t  *)0x4007300B // CMP Status and Control Register

  831. #define CMP1_DACCR              *(volatile uint8_t  *)0x4007300C // DAC Control Register

  832. #define CMP1_MUXCR              *(volatile uint8_t  *)0x4007300D // MUX Control Register

  833. 

  834. // Chapter 33: Voltage Reference (VREFV1)

  835. #define VREF_TRM                *(volatile uint8_t  *)0x40074000 // VREF Trim Register

  836. #define VREF_SC                 *(volatile uint8_t  *)0x40074001 // VREF Status and Control Register

  837. 

  838. // Chapter 34: Programmable Delay Block (PDB)

  839. #define PDB0_SC                 *(volatile uint32_t *)0x40036000 // Status and Control Register

  840. #define PDB_SC_LDMOD(n)			(((n) & 3) << 18)	// Load Mode Select

  841. #define PDB_SC_PDBEIE			0x00020000		// Sequence Error Interrupt Enable

  842. #define PDB_SC_SWTRIG			0x00010000		// Software Trigger

  843. #define PDB_SC_DMAEN			0x00008000		// DMA Enable

  844. #define PDB_SC_PRESCALER(n)		(((n) & 7) << 12)	// Prescaler Divider Select

  845. #define PDB_SC_TRGSEL(n)		(((n) & 15) << 8)	// Trigger Input Source Select

  846. #define PDB_SC_PDBEN			0x00000080		// PDB Enable

  847. #define PDB_SC_PDBIF			0x00000040		// PDB Interrupt Flag

  848. #define PDB_SC_PDBIE			0x00000020		// PDB Interrupt Enable.

  849. #define PDB_SC_MULT(n)			(((n) & 3) << 2)	// Multiplication Factor

  850. #define PDB_SC_CONT			0x00000002		// Continuous Mode Enable

  851. #define PDB_SC_LDOK			0x00000001		// Load OK

  852. #define PDB0_MOD                *(volatile uint32_t *)0x40036004 // Modulus Register

  853. #define PDB0_CNT                *(volatile uint32_t *)0x40036008 // Counter Register

  854. #define PDB0_IDLY               *(volatile uint32_t *)0x4003600C // Interrupt Delay Register

  855. #define PDB0_CH0C1              *(volatile uint32_t *)0x40036010 // Channel n Control Register 1

  856. #define PDB0_CH0S               *(volatile uint32_t *)0x40036014 // Channel n Status Register

  857. #define PDB0_CH0DLY0            *(volatile uint32_t *)0x40036018 // Channel n Delay 0 Register

  858. #define PDB0_CH0DLY1            *(volatile uint32_t *)0x4003601C // Channel n Delay 1 Register

  859. #define PDB0_POEN               *(volatile uint32_t *)0x40036190 // Pulse-Out n Enable Register

  860. #define PDB0_PO0DLY             *(volatile uint32_t *)0x40036194 // Pulse-Out n Delay Register

  861. #define PDB0_PO1DLY             *(volatile uint32_t *)0x40036198 // Pulse-Out n Delay Register

  862. 

  863. // Chapter 35: FlexTimer Module (FTM)

  864. #define FTM0_SC                 *(volatile uint32_t *)0x40038000 // Status And Control

  865. #define FTM_SC_TOF			0x80				// Timer Overflow Flag

  866. #define FTM_SC_TOIE			0x40				// Timer Overflow Interrupt Enable

  867. #define FTM_SC_CPWMS			0x20				// Center-Aligned PWM Select

  868. #define FTM_SC_CLKS(n)			(((n) & 3) << 3)		// Clock Source Selection

  869. #define FTM_SC_PS(n)			(((n) & 7) << 0)		// Prescale Factor Selection

  870. #define FTM0_CNT                *(volatile uint32_t *)0x40038004 // Counter

  871. #define FTM0_MOD                *(volatile uint32_t *)0x40038008 // Modulo

  872. #define FTM0_C0SC		*(volatile uint32_t *)0x4003800C // Channel 0 Status And Control

  873. #define FTM0_C0V		*(volatile uint32_t *)0x40038010 // Channel 0 Value

  874. #define FTM0_C1SC		*(volatile uint32_t *)0x40038014 // Channel 1 Status And Control

  875. #define FTM0_C1V		*(volatile uint32_t *)0x40038018 // Channel 1 Value

  876. #define FTM0_C2SC		*(volatile uint32_t *)0x4003801C // Channel 2 Status And Control

  877. #define FTM0_C2V		*(volatile uint32_t *)0x40038020 // Channel 2 Value

  878. #define FTM0_C3SC		*(volatile uint32_t *)0x40038024 // Channel 3 Status And Control

  879. #define FTM0_C3V		*(volatile uint32_t *)0x40038028 // Channel 3 Value

  880. #define FTM0_C4SC		*(volatile uint32_t *)0x4003802C // Channel 4 Status And Control

  881. #define FTM0_C4V		*(volatile uint32_t *)0x40038030 // Channel 4 Value

  882. #define FTM0_C5SC		*(volatile uint32_t *)0x40038034 // Channel 5 Status And Control

  883. #define FTM0_C5V		*(volatile uint32_t *)0x40038038 // Channel 5 Value

  884. #define FTM0_C6SC		*(volatile uint32_t *)0x4003803C // Channel 6 Status And Control

  885. #define FTM0_C6V		*(volatile uint32_t *)0x40038040 // Channel 6 Value

  886. #define FTM0_C7SC		*(volatile uint32_t *)0x40038044 // Channel 7 Status And Control

  887. #define FTM0_C7V		*(volatile uint32_t *)0x40038048 // Channel 7 Value

  888. #define FTM0_CNTIN              *(volatile uint32_t *)0x4003804C // Counter Initial Value

  889. #define FTM0_STATUS             *(volatile uint32_t *)0x40038050 // Capture And Compare Status

  890. #define FTM0_MODE               *(volatile uint32_t *)0x40038054 // Features Mode Selection

  891. #define FTM_MODE_FAULTIE		0x80				// Fault Interrupt Enable

  892. #define FTM_MODE_FAULTM(n)		(((n) & 3) << 5)		// Fault Control Mode

  893. #define FTM_MODE_CAPTEST		0x10				// Capture Test Mode Enable

  894. #define FTM_MODE_PWMSYNC		0x08				// PWM Synchronization Mode

  895. #define FTM_MODE_WPDIS			0x04				// Write Protection Disable

  896. #define FTM_MODE_INIT			0x02				// Initialize The Channels Output

  897. #define FTM_MODE_FTMEN			0x01				// FTM Enable

  898. #define FTM0_SYNC               *(volatile uint32_t *)0x40038058 // Synchronization

  899. #define FTM_SYNC_SWSYNC			0x80				// 

  900. #define FTM_SYNC_TRIG2			0x40				// 

  901. #define FTM_SYNC_TRIG1			0x20				// 

  902. #define FTM_SYNC_TRIG0			0x10				// 

  903. #define FTM_SYNC_SYNCHOM		0x08				// 

  904. #define FTM_SYNC_REINIT			0x04				// 

  905. #define FTM_SYNC_CNTMAX			0x02				// 

  906. #define FTM_SYNC_CNTMIN			0x01				// 

  907. #define FTM0_OUTINIT            *(volatile uint32_t *)0x4003805C // Initial State For Channels Output

  908. #define FTM0_OUTMASK            *(volatile uint32_t *)0x40038060 // Output Mask

  909. #define FTM0_COMBINE            *(volatile uint32_t *)0x40038064 // Function For Linked Channels

  910. #define FTM0_DEADTIME           *(volatile uint32_t *)0x40038068 // Deadtime Insertion Control

  911. #define FTM0_EXTTRIG            *(volatile uint32_t *)0x4003806C // FTM External Trigger

  912. #define FTM0_POL                *(volatile uint32_t *)0x40038070 // Channels Polarity

  913. #define FTM0_FMS                *(volatile uint32_t *)0x40038074 // Fault Mode Status

  914. #define FTM0_FILTER             *(volatile uint32_t *)0x40038078 // Input Capture Filter Control

  915. #define FTM0_FLTCTRL            *(volatile uint32_t *)0x4003807C // Fault Control

  916. #define FTM0_QDCTRL             *(volatile uint32_t *)0x40038080 // Quadrature Decoder Control And Status

  917. #define FTM0_CONF               *(volatile uint32_t *)0x40038084 // Configuration

  918. #define FTM0_FLTPOL             *(volatile uint32_t *)0x40038088 // FTM Fault Input Polarity

  919. #define FTM0_SYNCONF            *(volatile uint32_t *)0x4003808C // Synchronization Configuration

  920. #define FTM0_INVCTRL            *(volatile uint32_t *)0x40038090 // FTM Inverting Control

  921. #define FTM0_SWOCTRL            *(volatile uint32_t *)0x40038094 // FTM Software Output Control

  922. #define FTM0_PWMLOAD            *(volatile uint32_t *)0x40038098 // FTM PWM Load

  923. #define FTM1_SC                 *(volatile uint32_t *)0x40039000 // Status And Control

  924. #define FTM1_CNT                *(volatile uint32_t *)0x40039004 // Counter

  925. #define FTM1_MOD                *(volatile uint32_t *)0x40039008 // Modulo

  926. #define FTM1_C0SC		*(volatile uint32_t *)0x4003900C // Channel 0 Status And Control

  927. #define FTM1_C0V		*(volatile uint32_t *)0x40039010 // Channel 0 Value

  928. #define FTM1_C1SC		*(volatile uint32_t *)0x40039014 // Channel 1 Status And Control

  929. #define FTM1_C1V		*(volatile uint32_t *)0x40039018 // Channel 1 Value

  930. #define FTM1_CNTIN              *(volatile uint32_t *)0x4003904C // Counter Initial Value

  931. #define FTM1_STATUS             *(volatile uint32_t *)0x40039050 // Capture And Compare Status

  932. #define FTM1_MODE               *(volatile uint32_t *)0x40039054 // Features Mode Selection

  933. #define FTM1_SYNC               *(volatile uint32_t *)0x40039058 // Synchronization

  934. #define FTM1_OUTINIT            *(volatile uint32_t *)0x4003905C // Initial State For Channels Output

  935. #define FTM1_OUTMASK            *(volatile uint32_t *)0x40039060 // Output Mask

  936. #define FTM1_COMBINE            *(volatile uint32_t *)0x40039064 // Function For Linked Channels

  937. #define FTM1_DEADTIME           *(volatile uint32_t *)0x40039068 // Deadtime Insertion Control

  938. #define FTM1_EXTTRIG            *(volatile uint32_t *)0x4003906C // FTM External Trigger

  939. #define FTM1_POL                *(volatile uint32_t *)0x40039070 // Channels Polarity

  940. #define FTM1_FMS                *(volatile uint32_t *)0x40039074 // Fault Mode Status

  941. #define FTM1_FILTER             *(volatile uint32_t *)0x40039078 // Input Capture Filter Control

  942. #define FTM1_FLTCTRL            *(volatile uint32_t *)0x4003907C // Fault Control

  943. #define FTM1_QDCTRL             *(volatile uint32_t *)0x40039080 // Quadrature Decoder Control And Status

  944. #define FTM1_CONF               *(volatile uint32_t *)0x40039084 // Configuration

  945. #define FTM1_FLTPOL             *(volatile uint32_t *)0x40039088 // FTM Fault Input Polarity

  946. #define FTM1_SYNCONF            *(volatile uint32_t *)0x4003908C // Synchronization Configuration

  947. #define FTM1_INVCTRL            *(volatile uint32_t *)0x40039090 // FTM Inverting Control

  948. #define FTM1_SWOCTRL            *(volatile uint32_t *)0x40039094 // FTM Software Output Control

  949. #define FTM1_PWMLOAD            *(volatile uint32_t *)0x40039098 // FTM PWM Load

  950. 

  951. // Chapter 36: Periodic Interrupt Timer (PIT)

  952. #define PIT_MCR                 *(volatile uint32_t *)0x40037000 // PIT Module Control Register

  953. #define PIT_LDVAL0              *(volatile uint32_t *)0x40037100 // Timer Load Value Register

  954. #define PIT_CVAL0               *(volatile uint32_t *)0x40037104 // Current Timer Value Register

  955. #define PIT_TCTRL0              *(volatile uint32_t *)0x40037108 // Timer Control Register

  956. #define PIT_TFLG0               *(volatile uint32_t *)0x4003710C // Timer Flag Register

  957. #define PIT_LDVAL1              *(volatile uint32_t *)0x40037110 // Timer Load Value Register

  958. #define PIT_CVAL1               *(volatile uint32_t *)0x40037114 // Current Timer Value Register

  959. #define PIT_TCTRL1              *(volatile uint32_t *)0x40037118 // Timer Control Register

  960. #define PIT_TFLG1               *(volatile uint32_t *)0x4003711C // Timer Flag Register

  961. #define PIT_LDVAL2              *(volatile uint32_t *)0x40037120 // Timer Load Value Register

  962. #define PIT_CVAL2               *(volatile uint32_t *)0x40037124 // Current Timer Value Register

  963. #define PIT_TCTRL2              *(volatile uint32_t *)0x40037128 // Timer Control Register

  964. #define PIT_TFLG2               *(volatile uint32_t *)0x4003712C // Timer Flag Register

  965. #define PIT_LDVAL3              *(volatile uint32_t *)0x40037130 // Timer Load Value Register

  966. #define PIT_CVAL3               *(volatile uint32_t *)0x40037134 // Current Timer Value Register

  967. #define PIT_TCTRL3              *(volatile uint32_t *)0x40037138 // Timer Control Register

  968. #define PIT_TFLG3               *(volatile uint32_t *)0x4003713C // Timer Flag Register

  969. 

  970. // Chapter 37: Low-Power Timer (LPTMR)

  971. #define LPTMR0_CSR              *(volatile uint32_t *)0x40040000 // Low Power Timer Control Status Register

  972. #define LPTMR0_PSR              *(volatile uint32_t *)0x40040004 // Low Power Timer Prescale Register

  973. #define LPTMR0_CMR              *(volatile uint32_t *)0x40040008 // Low Power Timer Compare Register

  974. #define LPTMR0_CNR              *(volatile uint32_t *)0x4004000C // Low Power Timer Counter Register

  975. 

  976. // Chapter 38: Carrier Modulator Transmitter (CMT)

  977. #define CMT_CGH1                *(volatile uint8_t  *)0x40062000 // CMT Carrier Generator High Data Register 1

  978. #define CMT_CGL1                *(volatile uint8_t  *)0x40062001 // CMT Carrier Generator Low Data Register 1

  979. #define CMT_CGH2                *(volatile uint8_t  *)0x40062002 // CMT Carrier Generator High Data Register 2

  980. #define CMT_CGL2                *(volatile uint8_t  *)0x40062003 // CMT Carrier Generator Low Data Register 2

  981. #define CMT_OC                  *(volatile uint8_t  *)0x40062004 // CMT Output Control Register

  982. #define CMT_MSC                 *(volatile uint8_t  *)0x40062005 // CMT Modulator Status and Control Register

  983. #define CMT_CMD1                *(volatile uint8_t  *)0x40062006 // CMT Modulator Data Register Mark High

  984. #define CMT_CMD2                *(volatile uint8_t  *)0x40062007 // CMT Modulator Data Register Mark Low

  985. #define CMT_CMD3                *(volatile uint8_t  *)0x40062008 // CMT Modulator Data Register Space High

  986. #define CMT_CMD4                *(volatile uint8_t  *)0x40062009 // CMT Modulator Data Register Space Low

  987. #define CMT_PPS                 *(volatile uint8_t  *)0x4006200A // CMT Primary Prescaler Register

  988. #define CMT_DMA                 *(volatile uint8_t  *)0x4006200B // CMT Direct Memory Access Register

  989. 

  990. // Chapter 39: Real Time Clock (RTC)

  991. #define RTC_TSR                 *(volatile uint32_t *)0x4003D000 // RTC Time Seconds Register

  992. #define RTC_TPR                 *(volatile uint32_t *)0x4003D004 // RTC Time Prescaler Register

  993. #define RTC_TAR                 *(volatile uint32_t *)0x4003D008 // RTC Time Alarm Register

  994. #define RTC_TCR                 *(volatile uint32_t *)0x4003D00C // RTC Time Compensation Register

  995. #define RTC_TCR_CIC(n)			(((n) & 255) << 24)		// Compensation Interval Counter

  996. #define RTC_TCR_TCV(n)			(((n) & 255) << 16)		// Time Compensation Value

  997. #define RTC_TCR_CIR(n)			(((n) & 255) << 8)		// Compensation Interval Register

  998. #define RTC_TCR_TCR(n)			(((n) & 255) << 0)		// Time Compensation Register

  999. #define RTC_CR                  *(volatile uint32_t *)0x4003D010 // RTC Control Register

  1000. #define RTC_CR_SC2P			(uint32_t)0x00002000		// 

  1001. #define RTC_CR_SC4P			(uint32_t)0x00001000		// 

  1002. #define RTC_CR_SC8P			(uint32_t)0x00000800		// 

  1003. #define RTC_CR_SC16P			(uint32_t)0x00000400		// 

  1004. #define RTC_CR_CLKO			(uint32_t)0x00000200		// 

  1005. #define RTC_CR_OSCE			(uint32_t)0x00000100		// 

  1006. #define RTC_CR_UM			(uint32_t)0x00000008		// 

  1007. #define RTC_CR_SUP			(uint32_t)0x00000004		// 

  1008. #define RTC_CR_WPE			(uint32_t)0x00000002		// 

  1009. #define RTC_CR_SWR			(uint32_t)0x00000001		// 

  1010. #define RTC_SR                  *(volatile uint32_t *)0x4003D014 // RTC Status Register

  1011. #define RTC_SR_TCE			(uint32_t)0x00000010		// 

  1012. #define RTC_SR_TAF			(uint32_t)0x00000004		// 

  1013. #define RTC_SR_TOF			(uint32_t)0x00000002		// 

  1014. #define RTC_SR_TIF			(uint32_t)0x00000001		// 

  1015. #define RTC_LR                  *(volatile uint32_t *)0x4003D018 // RTC Lock Register

  1016. #define RTC_IER                 *(volatile uint32_t *)0x4003D01C // RTC Interrupt Enable Register

  1017. #define RTC_WAR                 *(volatile uint32_t *)0x4003D800 // RTC Write Access Register

  1018. #define RTC_RAR                 *(volatile uint32_t *)0x4003D804 // RTC Read Access Register

  1019. 

  1020. // Chapter 40: Universal Serial Bus OTG Controller (USBOTG)

  1021. #define USB0_PERID              *(const    uint8_t  *)0x40072000 // Peripheral ID register

  1022. #define USB0_IDCOMP             *(const    uint8_t  *)0x40072004 // Peripheral ID Complement register

  1023. #define USB0_REV                *(const    uint8_t  *)0x40072008 // Peripheral Revision register

  1024. #define USB0_ADDINFO            *(volatile uint8_t  *)0x4007200C // Peripheral Additional Info register

  1025. #define USB0_OTGISTAT           *(volatile uint8_t  *)0x40072010 // OTG Interrupt Status register

  1026. #define USB_OTGISTAT_IDCHG		(uint8_t)0x80			//

  1027. #define USB_OTGISTAT_ONEMSEC		(uint8_t)0x40			//

  1028. #define USB_OTGISTAT_LINE_STATE_CHG	(uint8_t)0x20			//

  1029. #define USB_OTGISTAT_SESSVLDCHG		(uint8_t)0x08			//

  1030. #define USB_OTGISTAT_B_SESS_CHG		(uint8_t)0x04			//

  1031. #define USB_OTGISTAT_AVBUSCHG		(uint8_t)0x01			//

  1032. #define USB0_OTGICR             *(volatile uint8_t  *)0x40072014 // OTG Interrupt Control Register

  1033. #define USB_OTGICR_IDEN			(uint8_t)0x80			// 

  1034. #define USB_OTGICR_ONEMSECEN		(uint8_t)0x40			// 

  1035. #define USB_OTGICR_LINESTATEEN		(uint8_t)0x20			// 

  1036. #define USB_OTGICR_SESSVLDEN		(uint8_t)0x08			// 

  1037. #define USB_OTGICR_BSESSEN		(uint8_t)0x04			// 

  1038. #define USB_OTGICR_AVBUSEN		(uint8_t)0x01			// 

  1039. #define USB0_OTGSTAT            *(volatile uint8_t  *)0x40072018 // OTG Status register

  1040. #define USB_OTGSTAT_ID			(uint8_t)0x80			// 

  1041. #define USB_OTGSTAT_ONEMSECEN		(uint8_t)0x40			// 

  1042. #define USB_OTGSTAT_LINESTATESTABLE	(uint8_t)0x20			// 

  1043. #define USB_OTGSTAT_SESS_VLD		(uint8_t)0x08			// 

  1044. #define USB_OTGSTAT_BSESSEND		(uint8_t)0x04			// 

  1045. #define USB_OTGSTAT_AVBUSVLD		(uint8_t)0x01			// 

  1046. #define USB0_OTGCTL             *(volatile uint8_t  *)0x4007201C // OTG Control Register

  1047. #define USB_OTGCTL_DPHIGH		(uint8_t)0x80			// 

  1048. #define USB_OTGCTL_DPLOW		(uint8_t)0x20			// 

  1049. #define USB_OTGCTL_DMLOW		(uint8_t)0x10			// 

  1050. #define USB_OTGCTL_OTGEN		(uint8_t)0x04			// 

  1051. #define USB0_ISTAT              *(volatile uint8_t  *)0x40072080 // Interrupt Status Register

  1052. #define USB_ISTAT_STALL			(uint8_t)0x80			// 

  1053. #define USB_ISTAT_ATTACH		(uint8_t)0x40			// 

  1054. #define USB_ISTAT_RESUME		(uint8_t)0x20			// 

  1055. #define USB_ISTAT_SLEEP			(uint8_t)0x10			// 

  1056. #define USB_ISTAT_TOKDNE		(uint8_t)0x08			// 

  1057. #define USB_ISTAT_SOFTOK		(uint8_t)0x04			// 

  1058. #define USB_ISTAT_ERROR			(uint8_t)0x02			// 

  1059. #define USB_ISTAT_USBRST		(uint8_t)0x01			// 

  1060. #define USB0_INTEN              *(volatile uint8_t  *)0x40072084 // Interrupt Enable Register

  1061. #define USB_INTEN_STALLEN		(uint8_t)0x80			// 

  1062. #define USB_INTEN_ATTACHEN		(uint8_t)0x40			// 

  1063. #define USB_INTEN_RESUMEEN		(uint8_t)0x20			// 

  1064. #define USB_INTEN_SLEEPEN		(uint8_t)0x10			// 

  1065. #define USB_INTEN_TOKDNEEN		(uint8_t)0x08			// 

  1066. #define USB_INTEN_SOFTOKEN		(uint8_t)0x04			// 

  1067. #define USB_INTEN_ERROREN		(uint8_t)0x02			// 

  1068. #define USB_INTEN_USBRSTEN		(uint8_t)0x01			// 

  1069. #define USB0_ERRSTAT            *(volatile uint8_t  *)0x40072088 // Error Interrupt Status Register

  1070. #define USB_ERRSTAT_BTSERR		(uint8_t)0x80			// 

  1071. #define USB_ERRSTAT_DMAERR		(uint8_t)0x20			// 

  1072. #define USB_ERRSTAT_BTOERR		(uint8_t)0x10			// 

  1073. #define USB_ERRSTAT_DFN8		(uint8_t)0x08			// 

  1074. #define USB_ERRSTAT_CRC16		(uint8_t)0x04			// 

  1075. #define USB_ERRSTAT_CRC5EOF		(uint8_t)0x02			// 

  1076. #define USB_ERRSTAT_PIDERR		(uint8_t)0x01			// 

  1077. #define USB0_ERREN              *(volatile uint8_t  *)0x4007208C // Error Interrupt Enable Register

  1078. #define USB_ERREN_BTSERREN		(uint8_t)0x80			// 

  1079. #define USB_ERREN_DMAERREN		(uint8_t)0x20			// 

  1080. #define USB_ERREN_BTOERREN		(uint8_t)0x10			// 

  1081. #define USB_ERREN_DFN8EN		(uint8_t)0x08			// 

  1082. #define USB_ERREN_CRC16EN		(uint8_t)0x04			// 

  1083. #define USB_ERREN_CRC5EOFEN		(uint8_t)0x02			// 

  1084. #define USB_ERREN_PIDERREN		(uint8_t)0x01			// 

  1085. #define USB0_STAT               *(volatile uint8_t  *)0x40072090 // Status Register

  1086. #define USB_STAT_TX			(uint8_t)0x08			// 

  1087. #define USB_STAT_ODD			(uint8_t)0x04			// 

  1088. #define USB_STAT_ENDP(n)		(uint8_t)((n) >> 4)		// 

  1089. #define USB0_CTL                *(volatile uint8_t  *)0x40072094 // Control Register

  1090. #define USB_CTL_JSTATE			(uint8_t)0x80			// 

  1091. #define USB_CTL_SE0			(uint8_t)0x40			// 

  1092. #define USB_CTL_TXSUSPENDTOKENBUSY	(uint8_t)0x20			// 

  1093. #define USB_CTL_RESET			(uint8_t)0x10			// 

  1094. #define USB_CTL_HOSTMODEEN		(uint8_t)0x08			// 

  1095. #define USB_CTL_RESUME			(uint8_t)0x04			// 

  1096. #define USB_CTL_ODDRST			(uint8_t)0x02			// 

  1097. #define USB_CTL_USBENSOFEN		(uint8_t)0x01			// 

  1098. #define USB0_ADDR               *(volatile uint8_t  *)0x40072098 // Address Register

  1099. #define USB0_BDTPAGE1           *(volatile uint8_t  *)0x4007209C // BDT Page Register 1

  1100. #define USB0_FRMNUML            *(volatile uint8_t  *)0x400720A0 // Frame Number Register Low

  1101. #define USB0_FRMNUMH            *(volatile uint8_t  *)0x400720A4 // Frame Number Register High

  1102. #define USB0_TOKEN              *(volatile uint8_t  *)0x400720A8 // Token Register

  1103. #define USB0_SOFTHLD            *(volatile uint8_t  *)0x400720AC // SOF Threshold Register

  1104. #define USB0_BDTPAGE2           *(volatile uint8_t  *)0x400720B0 // BDT Page Register 2

  1105. #define USB0_BDTPAGE3           *(volatile uint8_t  *)0x400720B4 // BDT Page Register 3

  1106. #define USB0_ENDPT0             *(volatile uint8_t  *)0x400720C0 // Endpoint Control Register

  1107. #define USB_ENDPT_HOSTWOHUB		(uint8_t)0x80			// host only, enable low speed

  1108. #define USB_ENDPT_RETRYDIS		(uint8_t)0x40			// host only, set to disable NAK retry

  1109. #define USB_ENDPT_EPCTLDIS		(uint8_t)0x10			// 0=control, 1=bulk, interrupt, isync

  1110. #define USB_ENDPT_EPRXEN		(uint8_t)0x08			// enables the endpoint for RX transfers.

  1111. #define USB_ENDPT_EPTXEN		(uint8_t)0x04			// enables the endpoint for TX transfers.

  1112. #define USB_ENDPT_EPSTALL		(uint8_t)0x02			// set to stall endpoint

  1113. #define USB_ENDPT_EPHSHK		(uint8_t)0x01			// enable handshaking during a transaction, generally set unless Isochronous

  1114. #define USB0_ENDPT1             *(volatile uint8_t  *)0x400720C4 // Endpoint Control Register

  1115. #define USB0_ENDPT2             *(volatile uint8_t  *)0x400720C8 // Endpoint Control Register

  1116. #define USB0_ENDPT3             *(volatile uint8_t  *)0x400720CC // Endpoint Control Register

  1117. #define USB0_ENDPT4             *(volatile uint8_t  *)0x400720D0 // Endpoint Control Register

  1118. #define USB0_ENDPT5             *(volatile uint8_t  *)0x400720D4 // Endpoint Control Register

  1119. #define USB0_ENDPT6             *(volatile uint8_t  *)0x400720D8 // Endpoint Control Register

  1120. #define USB0_ENDPT7             *(volatile uint8_t  *)0x400720DC // Endpoint Control Register

  1121. #define USB0_ENDPT8             *(volatile uint8_t  *)0x400720E0 // Endpoint Control Register

  1122. #define USB0_ENDPT9             *(volatile uint8_t  *)0x400720E4 // Endpoint Control Register

  1123. #define USB0_ENDPT10            *(volatile uint8_t  *)0x400720E8 // Endpoint Control Register

  1124. #define USB0_ENDPT11            *(volatile uint8_t  *)0x400720EC // Endpoint Control Register

  1125. #define USB0_ENDPT12            *(volatile uint8_t  *)0x400720F0 // Endpoint Control Register

  1126. #define USB0_ENDPT13            *(volatile uint8_t  *)0x400720F4 // Endpoint Control Register

  1127. #define USB0_ENDPT14            *(volatile uint8_t  *)0x400720F8 // Endpoint Control Register

  1128. #define USB0_ENDPT15            *(volatile uint8_t  *)0x400720FC // Endpoint Control Register

  1129. #define USB0_USBCTRL            *(volatile uint8_t  *)0x40072100 // USB Control Register

  1130. #define USB_USBCTRL_SUSP		(uint8_t)0x80			// Places the USB transceiver into the suspend state.

  1131. #define USB_USBCTRL_PDE			(uint8_t)0x40			// Enables the weak pulldowns on the USB transceiver.

  1132. #define USB0_OBSERVE            *(volatile uint8_t  *)0x40072104 // USB OTG Observe Register

  1133. #define USB_OBSERVE_DPPU		(uint8_t)0x80			// 

  1134. #define USB_OBSERVE_DPPD		(uint8_t)0x40			// 

  1135. #define USB_OBSERVE_DMPD		(uint8_t)0x10			// 

  1136. #define USB0_CONTROL            *(volatile uint8_t  *)0x40072108 // USB OTG Control Register

  1137. #define USB_CONTROL_DPPULLUPNONOTG	(uint8_t)0x10			//  Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.

  1138. #define USB0_USBTRC0            *(volatile uint8_t  *)0x4007210C // USB Transceiver Control Register 0

  1139. #define USB_USBTRC_USBRESET		(uint8_t)0x80			//

  1140. #define USB_USBTRC_USBRESMEN		(uint8_t)0x20			//

  1141. #define USB_USBTRC_SYNC_DET		(uint8_t)0x02			//

  1142. #define USB_USBTRC_USB_RESUME_INT	(uint8_t)0x01			//

  1143. #define USB0_USBFRMADJUST       *(volatile uint8_t  *)0x40072114 // Frame Adjust Register

  1144. 

  1145. // Chapter 41: USB Device Charger Detection Module (USBDCD)

  1146. #define USBDCD_CONTROL          *(volatile uint32_t *)0x40035000 // Control register

  1147. #define USBDCD_CLOCK            *(volatile uint32_t *)0x40035004 // Clock register

  1148. #define USBDCD_STATUS           *(volatile uint32_t *)0x40035008 // Status register

  1149. #define USBDCD_TIMER0           *(volatile uint32_t *)0x40035010 // TIMER0 register

  1150. #define USBDCD_TIMER1           *(volatile uint32_t *)0x40035014 // TIMER1 register

  1151. #define USBDCD_TIMER2           *(volatile uint32_t *)0x40035018 // TIMER2 register

  1152. 

  1153. // Chapter 43: SPI (DSPI)

  1154. #define SPI0_MCR                *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register

  1155. #define SPI_MCR_MSTR			(uint32_t)0x80000000		// Master/Slave Mode Select

  1156. #define SPI_MCR_CONT_SCKE		(uint32_t)0x40000000		// 

  1157. #define SPI_MCR_DCONF(n)		(((n) & 3) << 28)		// 

  1158. #define SPI_MCR_FRZ			(uint32_t)0x08000000		// 

  1159. #define SPI_MCR_MTFE			(uint32_t)0x04000000		// 

  1160. #define SPI_MCR_ROOE			(uint32_t)0x01000000		// 

  1161. #define SPI_MCR_PCSIS(n)		(((n) & 0x1F) << 16)		//

  1162. #define SPI_MCR_DOZE			(uint32_t)0x00008000		// 

  1163. #define SPI_MCR_MDIS			(uint32_t)0x00004000		// 

  1164. #define SPI_MCR_DIS_TXF			(uint32_t)0x00002000		// 

  1165. #define SPI_MCR_DIS_RXF			(uint32_t)0x00001000		// 

  1166. #define SPI_MCR_CLR_TXF			(uint32_t)0x00000800		// 

  1167. #define SPI_MCR_CLR_RXF			(uint32_t)0x00000400		// 

  1168. #define SPI_MCR_SMPL_PT(n)		(((n) & 3) << 8)		//

  1169. #define SPI_MCR_HALT			(uint32_t)0x00000001		// 

  1170. #define SPI0_TCR                *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register

  1171. #define SPI0_CTAR0              *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode

  1172. #define SPI_CTAR_DBR			(uint32_t)0x80000000		// Double Baud Rate

  1173. #define SPI_CTAR_FMSZ(n)		(((n) & 15) << 27)		// Frame Size (+1)

  1174. #define SPI_CTAR_CPOL			(uint32_t)0x04000000		// Clock Polarity

  1175. #define SPI_CTAR_CPHA			(uint32_t)0x02000000		// Clock Phase

  1176. #define SPI_CTAR_LSBFE			(uint32_t)0x01000000		// LSB First

  1177. #define SPI_CTAR_PCSSCK(n)		(((n) & 3) << 22)		// PCS to SCK Delay Prescaler

  1178. #define SPI_CTAR_PASC(n)		(((n) & 3) << 20)		// After SCK Delay Prescaler

  1179. #define SPI_CTAR_PDT(n)			(((n) & 3) << 18)		// Delay after Transfer Prescaler

  1180. #define SPI_CTAR_PBR(n)			(((n) & 3) << 16)		// Baud Rate Prescaler

  1181. #define SPI_CTAR_CSSCK(n)		(((n) & 15) << 12)		// PCS to SCK Delay Scaler

  1182. #define SPI_CTAR_ASC(n)			(((n) & 15) << 8)		// After SCK Delay Scaler

  1183. #define SPI_CTAR_DT(n)			(((n) & 15) << 4)		// Delay After Transfer Scaler

  1184. #define SPI_CTAR_BR(n)			(((n) & 15) << 0)		// Baud Rate Scaler

  1185. #define SPI0_CTAR0_SLAVE        *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode

  1186. #define SPI0_CTAR1              *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode

  1187. #define SPI0_SR                 *(volatile uint32_t *)0x4002C02C // DSPI Status Register

  1188. #define SPI_SR_TCF			(uint32_t)0x80000000		// Transfer Complete Flag

  1189. #define SPI_SR_TXRXS			(uint32_t)0x40000000		// TX and RX Status

  1190. #define SPI_SR_EOQF			(uint32_t)0x10000000		// End of Queue Flag

  1191. #define SPI_SR_TFUF			(uint32_t)0x08000000		// Transmit FIFO Underflow Flag

  1192. #define SPI_SR_TFFF			(uint32_t)0x02000000		// Transmit FIFO Fill Flag

  1193. #define SPI_SR_RFOF			(uint32_t)0x00080000		// Receive FIFO Overflow Flag

  1194. #define SPI_SR_RFDF			(uint32_t)0x00020000		// Receive FIFO Drain Flag

  1195. #define SPI0_RSER               *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register

  1196. #define SPI_RSER_TCF_RE			(uint32_t)0x80000000		// Transmission Complete Request Enable

  1197. #define SPI_RSER_EOQF_RE		(uint32_t)0x10000000		// DSPI Finished Request Request Enable

  1198. #define SPI_RSER_TFUF_RE		(uint32_t)0x08000000		// Transmit FIFO Underflow Request Enable

  1199. #define SPI_RSER_TFFF_RE		(uint32_t)0x02000000		// Transmit FIFO Fill Request Enable

  1200. #define SPI_RSER_TFFF_DIRS		(uint32_t)0x01000000		// Transmit FIFO FIll Dma or Interrupt Request Select

  1201. #define SPI_RSER_RFOF_RE		(uint32_t)0x00080000		// Receive FIFO Overflow Request Enable

  1202. #define SPI_RSER_RFDF_RE		(uint32_t)0x00020000		// Receive FIFO Drain Request Enable

  1203. #define SPI_RSER_RFDF_DIRS		(uint32_t)0x00010000		// Receive FIFO Drain DMA or Interrupt Request Select

  1204. #define SPI0_PUSHR              *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode

  1205. #define SPI_PUSHR_CONT			(uint32_t)0x80000000		// 

  1206. #define SPI_PUSHR_CTAS(n)		(((n) & 7) << 28)		// 

  1207. #define SPI_PUSHR_EOQ			(uint32_t)0x08000000		// 

  1208. #define SPI_PUSHR_CTCNT			(uint32_t)0x04000000		// 

  1209. #define SPI_PUSHR_PCS(n)		(((n) & 31) << 16)		//

  1210. #define SPI0_PUSHR_SLAVE        *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode

  1211. #define SPI0_POPR               *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register

  1212. #define SPI0_TXFR0              *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers

  1213. #define SPI0_TXFR1              *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers

  1214. #define SPI0_TXFR2              *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers

  1215. #define SPI0_TXFR3              *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers

  1216. #define SPI0_RXFR0              *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers

  1217. #define SPI0_RXFR1              *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers

  1218. #define SPI0_RXFR2              *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers

  1219. #define SPI0_RXFR3              *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers

  1220. 

  1221. // Chapter 44: Inter-Integrated Circuit (I2C)

  1222. #define I2C0_A1                 *(volatile uint8_t  *)0x40066000 // I2C Address Register 1

  1223. #define I2C0_F                  *(volatile uint8_t  *)0x40066001 // I2C Frequency Divider register

  1224. #define I2C0_C1                 *(volatile uint8_t  *)0x40066002 // I2C Control Register 1

  1225. #define I2C_C1_IICEN			(uint8_t)0x80			// I2C Enable

  1226. #define I2C_C1_IICIE			(uint8_t)0x40			// I2C Interrupt Enable

  1227. #define I2C_C1_MST			(uint8_t)0x20			// Master Mode Select

  1228. #define I2C_C1_TX			(uint8_t)0x10			// Transmit Mode Select

  1229. #define I2C_C1_TXAK			(uint8_t)0x08			// Transmit Acknowledge Enable

  1230. #define I2C_C1_RSTA			(uint8_t)0x04			// Repeat START

  1231. #define I2C_C1_WUEN			(uint8_t)0x02			// Wakeup Enable

  1232. #define I2C_C1_DMAEN			(uint8_t)0x01			// DMA Enable

  1233. #define I2C0_S                  *(volatile uint8_t  *)0x40066003 // I2C Status register

  1234. #define I2C_S_TCF			(uint8_t)0x80			// Transfer Complete Flag

  1235. #define I2C_S_IAAS			(uint8_t)0x40			// Addressed As A Slave

  1236. #define I2C_S_BUSY			(uint8_t)0x20			// Bus Busy

  1237. #define I2C_S_ARBL			(uint8_t)0x10			// Arbitration Lost

  1238. #define I2C_S_RAM			(uint8_t)0x08			// Range Address Match

  1239. #define I2C_S_SRW			(uint8_t)0x04			// Slave Read/Write

  1240. #define I2C_S_IICIF			(uint8_t)0x02			// Interrupt Flag

  1241. #define I2C_S_RXAK			(uint8_t)0x01			// Receive Acknowledge

  1242. #define I2C0_D                  *(volatile uint8_t  *)0x40066004 // I2C Data I/O register

  1243. #define I2C0_C2                 *(volatile uint8_t  *)0x40066005 // I2C Control Register 2

  1244. #define I2C_C2_GCAEN			(uint8_t)0x80			// General Call Address Enable

  1245. #define I2C_C2_ADEXT			(uint8_t)0x40			// Address Extension

  1246. #define I2C_C2_HDRS			(uint8_t)0x20			// High Drive Select

  1247. #define I2C_C2_SBRC			(uint8_t)0x10			// Slave Baud Rate Control

  1248. #define I2C_C2_RMEN			(uint8_t)0x08			// Range Address Matching Enable

  1249. #define I2C_C2_AD(n)			((n) & 7)			// Slave Address, upper 3 bits

  1250. #define I2C0_FLT                *(volatile uint8_t  *)0x40066006 // I2C Programmable Input Glitch Filter register

  1251. #define I2C0_RA                 *(volatile uint8_t  *)0x40066007 // I2C Range Address register

  1252. #define I2C0_SMB                *(volatile uint8_t  *)0x40066008 // I2C SMBus Control and Status register

  1253. #define I2C0_A2                 *(volatile uint8_t  *)0x40066009 // I2C Address Register 2

  1254. #define I2C0_SLTH               *(volatile uint8_t  *)0x4006600A // I2C SCL Low Timeout Register High

  1255. #define I2C0_SLTL               *(volatile uint8_t  *)0x4006600B // I2C SCL Low Timeout Register Low

  1256. 

  1257. // Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)

  1258. #define UART0_BDH               *(volatile uint8_t  *)0x4006A000 // UART Baud Rate Registers: High

  1259. #define UART0_BDL               *(volatile uint8_t  *)0x4006A001 // UART Baud Rate Registers: Low

  1260. #define UART0_C1                *(volatile uint8_t  *)0x4006A002 // UART Control Register 1

  1261. #define UART_C1_LOOPS			(uint8_t)0x80			// When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input

  1262. #define UART_C1_UARTSWAI		(uint8_t)0x40			// UART Stops in Wait Mode

  1263. #define UART_C1_RSRC			(uint8_t)0x20			// When LOOPS is set, the RSRC field determines the source for the receiver shift register input

  1264. #define UART_C1_M			(uint8_t)0x10			// 9-bit or 8-bit Mode Select

  1265. #define UART_C1_WAKE			(uint8_t)0x08			// Determines which condition wakes the UART

  1266. #define UART_C1_ILT			(uint8_t)0x04			// Idle Line Type Select

  1267. #define UART_C1_PE			(uint8_t)0x02			// Parity Enable

  1268. #define UART_C1_PT			(uint8_t)0x01			// Parity Type, 0=even, 1=odd

  1269. #define UART0_C2                *(volatile uint8_t  *)0x4006A003 // UART Control Register 2

  1270. #define UART_C2_TIE			(uint8_t)0x80			// Transmitter Interrupt or DMA Transfer Enable.

  1271. #define UART_C2_TCIE			(uint8_t)0x40			// Transmission Complete Interrupt Enable

  1272. #define UART_C2_RIE			(uint8_t)0x20			// Receiver Full Interrupt or DMA Transfer Enable

  1273. #define UART_C2_ILIE			(uint8_t)0x10			// Idle Line Interrupt Enable

  1274. #define UART_C2_TE			(uint8_t)0x08			// Transmitter Enable

  1275. #define UART_C2_RE			(uint8_t)0x04			// Receiver Enable

  1276. #define UART_C2_RWU			(uint8_t)0x02			// Receiver Wakeup Control

  1277. #define UART_C2_SBK			(uint8_t)0x01			// Send Break

  1278. #define UART0_S1                *(volatile uint8_t  *)0x4006A004 // UART Status Register 1

  1279. #define UART_S1_TDRE			(uint8_t)0x80			// Transmit Data Register Empty Flag

  1280. #define UART_S1_TC			(uint8_t)0x40			// Transmit Complete Flag

  1281. #define UART_S1_RDRF			(uint8_t)0x20			// Receive Data Register Full Flag

  1282. #define UART_S1_IDLE			(uint8_t)0x10			// Idle Line Flag

  1283. #define UART_S1_OR			(uint8_t)0x08			// Receiver Overrun Flag

  1284. #define UART_S1_NF			(uint8_t)0x04			// Noise Flag

  1285. #define UART_S1_FE			(uint8_t)0x02			// Framing Error Flag

  1286. #define UART_S1_PF			(uint8_t)0x01			// Parity Error Flag

  1287. #define UART0_S2                *(volatile uint8_t  *)0x4006A005 // UART Status Register 2

  1288. #define UART0_C3                *(volatile uint8_t  *)0x4006A006 // UART Control Register 3

  1289. #define UART0_D                 *(volatile uint8_t  *)0x4006A007 // UART Data Register

  1290. #define UART0_MA1               *(volatile uint8_t  *)0x4006A008 // UART Match Address Registers 1

  1291. #define UART0_MA2               *(volatile uint8_t  *)0x4006A009 // UART Match Address Registers 2

  1292. #define UART0_C4                *(volatile uint8_t  *)0x4006A00A // UART Control Register 4

  1293. #define UART0_C5                *(volatile uint8_t  *)0x4006A00B // UART Control Register 5

  1294. #define UART0_ED                *(volatile uint8_t  *)0x4006A00C // UART Extended Data Register

  1295. #define UART0_MODEM             *(volatile uint8_t  *)0x4006A00D // UART Modem Register

  1296. #define UART0_IR                *(volatile uint8_t  *)0x4006A00E // UART Infrared Register

  1297. #define UART0_PFIFO             *(volatile uint8_t  *)0x4006A010 // UART FIFO Parameters

  1298. #define UART_PFIFO_TXFE			(uint8_t)0x80

  1299. #define UART_PFIFO_RXFE			(uint8_t)0x08

  1300. #define UART0_CFIFO             *(volatile uint8_t  *)0x4006A011 // UART FIFO Control Register

  1301. #define UART_CFIFO_TXFLUSH		(uint8_t)0x80			// 

  1302. #define UART_CFIFO_RXFLUSH		(uint8_t)0x40			// 

  1303. #define UART_CFIFO_RXOFE		(uint8_t)0x04			// 

  1304. #define UART_CFIFO_TXOFE		(uint8_t)0x02			// 

  1305. #define UART_CFIFO_RXUFE		(uint8_t)0x01			// 

  1306. #define UART0_SFIFO             *(volatile uint8_t  *)0x4006A012 // UART FIFO Status Register

  1307. #define UART_SFIFO_TXEMPT		(uint8_t)0x80

  1308. #define UART_SFIFO_RXEMPT		(uint8_t)0x40

  1309. #define UART_SFIFO_RXOF			(uint8_t)0x04

  1310. #define UART_SFIFO_TXOF			(uint8_t)0x02

  1311. #define UART_SFIFO_RXUF			(uint8_t)0x01

  1312. #define UART0_TWFIFO            *(volatile uint8_t  *)0x4006A013 // UART FIFO Transmit Watermark

  1313. #define UART0_TCFIFO            *(volatile uint8_t  *)0x4006A014 // UART FIFO Transmit Count

  1314. #define UART0_RWFIFO            *(volatile uint8_t  *)0x4006A015 // UART FIFO Receive Watermark

  1315. #define UART0_RCFIFO            *(volatile uint8_t  *)0x4006A016 // UART FIFO Receive Count

  1316. #define UART0_C7816             *(volatile uint8_t  *)0x4006A018 // UART 7816 Control Register

  1317. #define UART0_IE7816            *(volatile uint8_t  *)0x4006A019 // UART 7816 Interrupt Enable Register

  1318. #define UART0_IS7816            *(volatile uint8_t  *)0x4006A01A // UART 7816 Interrupt Status Register

  1319. #define UART0_WP7816T0          *(volatile uint8_t  *)0x4006A01B // UART 7816 Wait Parameter Register

  1320. #define UART0_WP7816T1          *(volatile uint8_t  *)0x4006A01B // UART 7816 Wait Parameter Register

  1321. #define UART0_WN7816            *(volatile uint8_t  *)0x4006A01C // UART 7816 Wait N Register

  1322. #define UART0_WF7816            *(volatile uint8_t  *)0x4006A01D // UART 7816 Wait FD Register

  1323. #define UART0_ET7816            *(volatile uint8_t  *)0x4006A01E // UART 7816 Error Threshold Register

  1324. #define UART0_TL7816            *(volatile uint8_t  *)0x4006A01F // UART 7816 Transmit Length Register

  1325. #define UART0_C6                *(volatile uint8_t  *)0x4006A021 // UART CEA709.1-B Control Register 6

  1326. #define UART0_PCTH              *(volatile uint8_t  *)0x4006A022 // UART CEA709.1-B Packet Cycle Time Counter High

  1327. #define UART0_PCTL              *(volatile uint8_t  *)0x4006A023 // UART CEA709.1-B Packet Cycle Time Counter Low

  1328. #define UART0_B1T               *(volatile uint8_t  *)0x4006A024 // UART CEA709.1-B Beta1 Timer

  1329. #define UART0_SDTH              *(volatile uint8_t  *)0x4006A025 // UART CEA709.1-B Secondary Delay Timer High

  1330. #define UART0_SDTL              *(volatile uint8_t  *)0x4006A026 // UART CEA709.1-B Secondary Delay Timer Low

  1331. #define UART0_PRE               *(volatile uint8_t  *)0x4006A027 // UART CEA709.1-B Preamble

  1332. #define UART0_TPL               *(volatile uint8_t  *)0x4006A028 // UART CEA709.1-B Transmit Packet Length

  1333. #define UART0_IE                *(volatile uint8_t  *)0x4006A029 // UART CEA709.1-B Interrupt Enable Register

  1334. #define UART0_WB                *(volatile uint8_t  *)0x4006A02A // UART CEA709.1-B WBASE

  1335. #define UART0_S3                *(volatile uint8_t  *)0x4006A02B // UART CEA709.1-B Status Register

  1336. #define UART0_S4                *(volatile uint8_t  *)0x4006A02C // UART CEA709.1-B Status Register

  1337. #define UART0_RPL               *(volatile uint8_t  *)0x4006A02D // UART CEA709.1-B Received Packet Length

  1338. #define UART0_RPREL             *(volatile uint8_t  *)0x4006A02E // UART CEA709.1-B Received Preamble Length

  1339. #define UART0_CPW               *(volatile uint8_t  *)0x4006A02F // UART CEA709.1-B Collision Pulse Width

  1340. #define UART0_RIDT              *(volatile uint8_t  *)0x4006A030 // UART CEA709.1-B Receive Indeterminate Time

  1341. #define UART0_TIDT              *(volatile uint8_t  *)0x4006A031 // UART CEA709.1-B Transmit Indeterminate Time

  1342. #define UART1_BDH               *(volatile uint8_t  *)0x4006B000 // UART Baud Rate Registers: High

  1343. #define UART1_BDL               *(volatile uint8_t  *)0x4006B001 // UART Baud Rate Registers: Low

  1344. #define UART1_C1                *(volatile uint8_t  *)0x4006B002 // UART Control Register 1

  1345. #define UART1_C2                *(volatile uint8_t  *)0x4006B003 // UART Control Register 2

  1346. #define UART1_S1                *(volatile uint8_t  *)0x4006B004 // UART Status Register 1

  1347. #define UART1_S2                *(volatile uint8_t  *)0x4006B005 // UART Status Register 2

  1348. #define UART1_C3                *(volatile uint8_t  *)0x4006B006 // UART Control Register 3

  1349. #define UART1_D                 *(volatile uint8_t  *)0x4006B007 // UART Data Register

  1350. #define UART1_MA1               *(volatile uint8_t  *)0x4006B008 // UART Match Address Registers 1

  1351. #define UART1_MA2               *(volatile uint8_t  *)0x4006B009 // UART Match Address Registers 2

  1352. #define UART1_C4                *(volatile uint8_t  *)0x4006B00A // UART Control Register 4

  1353. #define UART1_C5                *(volatile uint8_t  *)0x4006B00B // UART Control Register 5

  1354. #define UART1_ED                *(volatile uint8_t  *)0x4006B00C // UART Extended Data Register

  1355. #define UART1_MODEM             *(volatile uint8_t  *)0x4006B00D // UART Modem Register

  1356. #define UART1_IR                *(volatile uint8_t  *)0x4006B00E // UART Infrared Register

  1357. #define UART1_PFIFO             *(volatile uint8_t  *)0x4006B010 // UART FIFO Parameters

  1358. #define UART1_CFIFO             *(volatile uint8_t  *)0x4006B011 // UART FIFO Control Register

  1359. #define UART1_SFIFO             *(volatile uint8_t  *)0x4006B012 // UART FIFO Status Register

  1360. #define UART1_TWFIFO            *(volatile uint8_t  *)0x4006B013 // UART FIFO Transmit Watermark

  1361. #define UART1_TCFIFO            *(volatile uint8_t  *)0x4006B014 // UART FIFO Transmit Count

  1362. #define UART1_RWFIFO            *(volatile uint8_t  *)0x4006B015 // UART FIFO Receive Watermark

  1363. #define UART1_RCFIFO            *(volatile uint8_t  *)0x4006B016 // UART FIFO Receive Count

  1364. #define UART1_C7816             *(volatile uint8_t  *)0x4006B018 // UART 7816 Control Register

  1365. #define UART1_IE7816            *(volatile uint8_t  *)0x4006B019 // UART 7816 Interrupt Enable Register

  1366. #define UART1_IS7816            *(volatile uint8_t  *)0x4006B01A // UART 7816 Interrupt Status Register

  1367. #define UART1_WP7816T0          *(volatile uint8_t  *)0x4006B01B // UART 7816 Wait Parameter Register

  1368. #define UART1_WP7816T1          *(volatile uint8_t  *)0x4006B01B // UART 7816 Wait Parameter Register

  1369. #define UART1_WN7816            *(volatile uint8_t  *)0x4006B01C // UART 7816 Wait N Register

  1370. #define UART1_WF7816            *(volatile uint8_t  *)0x4006B01D // UART 7816 Wait FD Register

  1371. #define UART1_ET7816            *(volatile uint8_t  *)0x4006B01E // UART 7816 Error Threshold Register

  1372. #define UART1_TL7816            *(volatile uint8_t  *)0x4006B01F // UART 7816 Transmit Length Register

  1373. #define UART1_C6                *(volatile uint8_t  *)0x4006B021 // UART CEA709.1-B Control Register 6

  1374. #define UART1_PCTH              *(volatile uint8_t  *)0x4006B022 // UART CEA709.1-B Packet Cycle Time Counter High

  1375. #define UART1_PCTL              *(volatile uint8_t  *)0x4006B023 // UART CEA709.1-B Packet Cycle Time Counter Low

  1376. #define UART1_B1T               *(volatile uint8_t  *)0x4006B024 // UART CEA709.1-B Beta1 Timer

  1377. #define UART1_SDTH              *(volatile uint8_t  *)0x4006B025 // UART CEA709.1-B Secondary Delay Timer High

  1378. #define UART1_SDTL              *(volatile uint8_t  *)0x4006B026 // UART CEA709.1-B Secondary Delay Timer Low

  1379. #define UART1_PRE               *(volatile uint8_t  *)0x4006B027 // UART CEA709.1-B Preamble

  1380. #define UART1_TPL               *(volatile uint8_t  *)0x4006B028 // UART CEA709.1-B Transmit Packet Length

  1381. #define UART1_IE                *(volatile uint8_t  *)0x4006B029 // UART CEA709.1-B Interrupt Enable Register

  1382. #define UART1_WB                *(volatile uint8_t  *)0x4006B02A // UART CEA709.1-B WBASE

  1383. #define UART1_S3                *(volatile uint8_t  *)0x4006B02B // UART CEA709.1-B Status Register

  1384. #define UART1_S4                *(volatile uint8_t  *)0x4006B02C // UART CEA709.1-B Status Register

  1385. #define UART1_RPL               *(volatile uint8_t  *)0x4006B02D // UART CEA709.1-B Received Packet Length

  1386. #define UART1_RPREL             *(volatile uint8_t  *)0x4006B02E // UART CEA709.1-B Received Preamble Length

  1387. #define UART1_CPW               *(volatile uint8_t  *)0x4006B02F // UART CEA709.1-B Collision Pulse Width

  1388. #define UART1_RIDT              *(volatile uint8_t  *)0x4006B030 // UART CEA709.1-B Receive Indeterminate Time

  1389. #define UART1_TIDT              *(volatile uint8_t  *)0x4006B031 // UART CEA709.1-B Transmit Indeterminate Time

  1390. #define UART2_BDH               *(volatile uint8_t  *)0x4006C000 // UART Baud Rate Registers: High

  1391. #define UART2_BDL               *(volatile uint8_t  *)0x4006C001 // UART Baud Rate Registers: Low

  1392. #define UART2_C1                *(volatile uint8_t  *)0x4006C002 // UART Control Register 1

  1393. #define UART2_C2                *(volatile uint8_t  *)0x4006C003 // UART Control Register 2

  1394. #define UART2_S1                *(volatile uint8_t  *)0x4006C004 // UART Status Register 1

  1395. #define UART2_S2                *(volatile uint8_t  *)0x4006C005 // UART Status Register 2

  1396. #define UART2_C3                *(volatile uint8_t  *)0x4006C006 // UART Control Register 3

  1397. #define UART2_D                 *(volatile uint8_t  *)0x4006C007 // UART Data Register

  1398. #define UART2_MA1               *(volatile uint8_t  *)0x4006C008 // UART Match Address Registers 1

  1399. #define UART2_MA2               *(volatile uint8_t  *)0x4006C009 // UART Match Address Registers 2

  1400. #define UART2_C4                *(volatile uint8_t  *)0x4006C00A // UART Control Register 4

  1401. #define UART2_C5                *(volatile uint8_t  *)0x4006C00B // UART Control Register 5

  1402. #define UART2_ED                *(volatile uint8_t  *)0x4006C00C // UART Extended Data Register

  1403. #define UART2_MODEM             *(volatile uint8_t  *)0x4006C00D // UART Modem Register

  1404. #define UART2_IR                *(volatile uint8_t  *)0x4006C00E // UART Infrared Register

  1405. #define UART2_PFIFO             *(volatile uint8_t  *)0x4006C010 // UART FIFO Parameters

  1406. #define UART2_CFIFO             *(volatile uint8_t  *)0x4006C011 // UART FIFO Control Register

  1407. #define UART2_SFIFO             *(volatile uint8_t  *)0x4006C012 // UART FIFO Status Register

  1408. #define UART2_TWFIFO            *(volatile uint8_t  *)0x4006C013 // UART FIFO Transmit Watermark

  1409. #define UART2_TCFIFO            *(volatile uint8_t  *)0x4006C014 // UART FIFO Transmit Count

  1410. #define UART2_RWFIFO            *(volatile uint8_t  *)0x4006C015 // UART FIFO Receive Watermark

  1411. #define UART2_RCFIFO            *(volatile uint8_t  *)0x4006C016 // UART FIFO Receive Count

  1412. #define UART2_C7816             *(volatile uint8_t  *)0x4006C018 // UART 7816 Control Register

  1413. #define UART2_IE7816            *(volatile uint8_t  *)0x4006C019 // UART 7816 Interrupt Enable Register

  1414. #define UART2_IS7816            *(volatile uint8_t  *)0x4006C01A // UART 7816 Interrupt Status Register

  1415. #define UART2_WP7816T0          *(volatile uint8_t  *)0x4006C01B // UART 7816 Wait Parameter Register

  1416. #define UART2_WP7816T1          *(volatile uint8_t  *)0x4006C01B // UART 7816 Wait Parameter Register

  1417. #define UART2_WN7816            *(volatile uint8_t  *)0x4006C01C // UART 7816 Wait N Register

  1418. #define UART2_WF7816            *(volatile uint8_t  *)0x4006C01D // UART 7816 Wait FD Register

  1419. #define UART2_ET7816            *(volatile uint8_t  *)0x4006C01E // UART 7816 Error Threshold Register

  1420. #define UART2_TL7816            *(volatile uint8_t  *)0x4006C01F // UART 7816 Transmit Length Register

  1421. #define UART2_C6                *(volatile uint8_t  *)0x4006C021 // UART CEA709.1-B Control Register 6

  1422. #define UART2_PCTH              *(volatile uint8_t  *)0x4006C022 // UART CEA709.1-B Packet Cycle Time Counter High

  1423. #define UART2_PCTL              *(volatile uint8_t  *)0x4006C023 // UART CEA709.1-B Packet Cycle Time Counter Low

  1424. #define UART2_B1T               *(volatile uint8_t  *)0x4006C024 // UART CEA709.1-B Beta1 Timer

  1425. #define UART2_SDTH              *(volatile uint8_t  *)0x4006C025 // UART CEA709.1-B Secondary Delay Timer High

  1426. #define UART2_SDTL              *(volatile uint8_t  *)0x4006C026 // UART CEA709.1-B Secondary Delay Timer Low

  1427. #define UART2_PRE               *(volatile uint8_t  *)0x4006C027 // UART CEA709.1-B Preamble

  1428. #define UART2_TPL               *(volatile uint8_t  *)0x4006C028 // UART CEA709.1-B Transmit Packet Length

  1429. #define UART2_IE                *(volatile uint8_t  *)0x4006C029 // UART CEA709.1-B Interrupt Enable Register

  1430. #define UART2_WB                *(volatile uint8_t  *)0x4006C02A // UART CEA709.1-B WBASE

  1431. #define UART2_S3                *(volatile uint8_t  *)0x4006C02B // UART CEA709.1-B Status Register

  1432. #define UART2_S4                *(volatile uint8_t  *)0x4006C02C // UART CEA709.1-B Status Register

  1433. #define UART2_RPL               *(volatile uint8_t  *)0x4006C02D // UART CEA709.1-B Received Packet Length

  1434. #define UART2_RPREL             *(volatile uint8_t  *)0x4006C02E // UART CEA709.1-B Received Preamble Length

  1435. #define UART2_CPW               *(volatile uint8_t  *)0x4006C02F // UART CEA709.1-B Collision Pulse Width

  1436. #define UART2_RIDT              *(volatile uint8_t  *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time

  1437. #define UART2_TIDT              *(volatile uint8_t  *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time

  1438. 

  1439. // Chapter 46: Synchronous Audio Interface (SAI)

  1440. #define I2S0_TCSR               *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register

  1441. #define I2S_TCSR_TE                     (uint32_t)0x80000000    // Transmitter Enable

  1442. #define I2S_TCSR_STOPE                  (uint32_t)0x40000000    // Transmitter Enable in Stop mode

  1443. #define I2S_TCSR_DBGE                   (uint32_t)0x20000000    // Transmitter Enable in Debug mode

  1444. #define I2S_TCSR_BCE                    (uint32_t)0x10000000    // Bit Clock Enable

  1445. #define I2S_TCSR_FR                     (uint32_t)0x02000000    // FIFO Reset

  1446. #define I2S_TCSR_SR                     (uint32_t)0x01000000    // Software Reset

  1447. #define I2S_TCSR_WSF                    (uint32_t)0x00100000    // Word Start Flag

  1448. #define I2S_TCSR_SEF                    (uint32_t)0x00080000    // Sync Error Flag

  1449. #define I2S_TCSR_FEF                    (uint32_t)0x00040000    // FIFO Error Flag (underrun)

  1450. #define I2S_TCSR_FWF                    (uint32_t)0x00020000    // FIFO Warning Flag (empty)

  1451. #define I2S_TCSR_FRF                    (uint32_t)0x00010000    // FIFO Request Flag (Data Ready)

  1452. #define I2S_TCSR_WSIE                   (uint32_t)0x00001000    // Word Start Interrupt Enable

  1453. #define I2S_TCSR_SEIE                   (uint32_t)0x00000800    // Sync Error Interrupt Enable

  1454. #define I2S_TCSR_FEIE                   (uint32_t)0x00000400    // FIFO Error Interrupt Enable

  1455. #define I2S_TCSR_FWIE                   (uint32_t)0x00000200    // FIFO Warning Interrupt Enable

  1456. #define I2S_TCSR_FRIE                   (uint32_t)0x00000100    // FIFO Request Interrupt Enable

  1457. #define I2S_TCSR_FWDE                   (uint32_t)0x00000002    // FIFO Warning DMA Enable

  1458. #define I2S_TCSR_FRDE                   (uint32_t)0x00000001    // FIFO Request DMA Enable

  1459. #define I2S0_TCR1               *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register

  1460. #define I2S_TCR1_TFW(n)                 ((uint32_t)n & 0x03)          // Transmit FIFO watermark

  1461. #define I2S0_TCR2               *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register

  1462. #define I2S_TCR2_DIV(n)                 ((uint32_t)n & 0xff)          // Bit clock divide by (DIV+1)*2

  1463. #define I2S_TCR2_BCD                    ((uint32_t)1<<24)             // Bit clock direction

  1464. #define I2S_TCR2_BCP                    ((uint32_t)1<<25)             // Bit clock polarity

  1465. #define I2S_TCR2_MSEL(n)                ((uint32_t)(n & 3)<<26)       // MCLK select, 0=bus clock, 1=I2S0_MCLK

  1466. #define I2S_TCR2_BCI                    ((uint32_t)1<<28)             // Bit clock input

  1467. #define I2S_TCR2_BCS                    ((uint32_t)1<<29)             // Bit clock swap

  1468. #define I2S_TCR2_SYNC(n)                ((uint32_t)(n & 3)<<30)       // 0=async 1=sync with receiver

  1469. #define I2S0_TCR3               *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register

  1470. #define I2S_TCR3_WDFL(n)                ((uint32_t)n & 0x0f)          // word flag configuration

  1471. #define I2S_TCR3_TCE                    ((uint32_t)0x10000)           // transmit channel enable

  1472. #define I2S0_TCR4               *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register

  1473. #define I2S_TCR4_FSD                    ((uint32_t)1)                 // Frame Sync Direction

  1474. #define I2S_TCR4_FSP                    ((uint32_t)2)                 // Frame Sync Polarity

  1475. #define I2S_TCR4_FSE                    ((uint32_t)8)                 // Frame Sync Early

  1476. #define I2S_TCR4_MF                     ((uint32_t)0x10)              // MSB First

  1477. #define I2S_TCR4_SYWD(n)                ((uint32_t)(n & 0x1f)<<8)     // Sync Width

  1478. #define I2S_TCR4_FRSZ(n)                ((uint32_t)(n & 0x0f)<<16)    // Frame Size

  1479. #define I2S0_TCR5               *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register

  1480. #define I2S_TCR5_FBT(n)                 ((uint32_t)(n & 0x1f)<<8)     // First Bit Shifted

  1481. #define I2S_TCR5_W0W(n)                 ((uint32_t)(n & 0x1f)<<16)    // Word 0 Width

  1482. #define I2S_TCR5_WNW(n)                 ((uint32_t)(n & 0x1f)<<24)    // Word N Width

  1483. #define I2S0_TDR0               *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register

  1484. #define I2S0_TFR0               *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register

  1485. #define I2S_TFR_RFP(n)                  ((uint32_t)n & 7)             // read FIFO pointer

  1486. #define I2S_TFR_WFP(n)                  ((uint32_t)(n & 7)<<16)       // write FIFO pointer

  1487. #define I2S0_TMR                *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register

  1488. #define I2S_TMR_TWM(n)                  ((uint32_t)n & 0xFFFFFFFF)

  1489. #define I2S0_RCSR               *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register

  1490. #define I2S_RCSR_RE                     (uint32_t)0x80000000    // Receiver Enable

  1491. #define I2S_RCSR_STOPE                  (uint32_t)0x40000000    // Receiver Enable in Stop mode

  1492. #define I2S_RCSR_DBGE                   (uint32_t)0x20000000    // Receiver Enable in Debug mode

  1493. #define I2S_RCSR_BCE                    (uint32_t)0x10000000    // Bit Clock Enable

  1494. #define I2S_RCSR_FR                     (uint32_t)0x02000000    // FIFO Reset

  1495. #define I2S_RCSR_SR                     (uint32_t)0x01000000    // Software Reset

  1496. #define I2S_RCSR_WSF                    (uint32_t)0x00100000    // Word Start Flag

  1497. #define I2S_RCSR_SEF                    (uint32_t)0x00080000    // Sync Error Flag

  1498. #define I2S_RCSR_FEF                    (uint32_t)0x00040000    // FIFO Error Flag (underrun)

  1499. #define I2S_RCSR_FWF                    (uint32_t)0x00020000    // FIFO Warning Flag (empty)

  1500. #define I2S_RCSR_FRF                    (uint32_t)0x00010000    // FIFO Request Flag (Data Ready)

  1501. #define I2S_RCSR_WSIE                   (uint32_t)0x00001000    // Word Start Interrupt Enable

  1502. #define I2S_RCSR_SEIE                   (uint32_t)0x00000800    // Sync Error Interrupt Enable

  1503. #define I2S_RCSR_FEIE                   (uint32_t)0x00000400    // FIFO Error Interrupt Enable

  1504. #define I2S_RCSR_FWIE                   (uint32_t)0x00000200    // FIFO Warning Interrupt Enable

  1505. #define I2S_RCSR_FRIE                   (uint32_t)0x00000100    // FIFO Request Interrupt Enable

  1506. #define I2S_RCSR_FWDE                   (uint32_t)0x00000002    // FIFO Warning DMA Enable

  1507. #define I2S_RCSR_FRDE                   (uint32_t)0x00000001    // FIFO Request DMA Enable

  1508. #define I2S0_RCR1               *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register

  1509. #define I2S_RCR1_RFW(n)                 ((uint32_t)n & 0x03)          // Receive FIFO watermark

  1510. #define I2S0_RCR2               *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register

  1511. #define I2S_RCR2_DIV(n)                 ((uint32_t)n & 0xff)          // Bit clock divide by (DIV+1)*2

  1512. #define I2S_RCR2_BCD                    ((uint32_t)1<<24)             // Bit clock direction

  1513. #define I2S_RCR2_BCP                    ((uint32_t)1<<25)             // Bit clock polarity

  1514. #define I2S_RCR2_MSEL(n)                ((uint32_t)(n & 3)<<26)       // MCLK select, 0=bus clock, 1=I2S0_MCLK

  1515. #define I2S_RCR2_BCI                    ((uint32_t)1<<28)             // Bit clock input

  1516. #define I2S_RCR2_BCS                    ((uint32_t)1<<29)             // Bit clock swap

  1517. #define I2S_RCR2_SYNC(n)                ((uint32_t)(n & 3)<<30)       // 0=async 1=sync with receiver

  1518. #define I2S0_RCR3               *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register

  1519. #define I2S_RCR3_WDFL(n)                ((uint32_t)n & 0x0f)          // word flag configuration

  1520. #define I2S_RCR3_RCE                    ((uint32_t)0x10000)           // receive channel enable

  1521. #define I2S0_RCR4               *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register

  1522. #define I2S_RCR4_FSD                    ((uint32_t)1)                 // Frame Sync Direction

  1523. #define I2S_RCR4_FSP                    ((uint32_t)2)                 // Frame Sync Polarity

  1524. #define I2S_RCR4_FSE                    ((uint32_t)8)                 // Frame Sync Early

  1525. #define I2S_RCR4_MF                     ((uint32_t)0x10)              // MSB First

  1526. #define I2S_RCR4_SYWD(n)                ((uint32_t)(n & 0x1f)<<8)     // Sync Width

  1527. #define I2S_RCR4_FRSZ(n)                ((uint32_t)(n & 0x0f)<<16)    // Frame Size

  1528. #define I2S0_RCR5               *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register

  1529. #define I2S_RCR5_FBT(n)                 ((uint32_t)(n & 0x1f)<<8)     // First Bit Shifted

  1530. #define I2S_RCR5_W0W(n)                 ((uint32_t)(n & 0x1f)<<16)    // Word 0 Width

  1531. #define I2S_RCR5_WNW(n)                 ((uint32_t)(n & 0x1f)<<24)    // Word N Width

  1532. #define I2S0_RDR0               *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register

  1533. #define I2S0_RFR0               *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register

  1534. #define I2S_RFR_RFP(n)                  ((uint32_t)n & 7)             // read FIFO pointer

  1535. #define I2S_RFR_WFP(n)                  ((uint32_t)(n & 7)<<16)       // write FIFO pointer

  1536. #define I2S0_RMR                *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register

  1537. #define I2S_RMR_RWM(n)                  ((uint32_t)n & 0xFFFFFFFF)

  1538. #define I2S0_MCR                *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register

  1539. #define I2S_MCR_DUF                     ((uint32_t)1<<31)             // Divider Update Flag

  1540. #define I2S_MCR_MOE                     ((uint32_t)1<<30)             // MCLK Output Enable

  1541. #define I2S_MCR_MICS(n)                 ((uint32_t)(n & 3)<<24)       // MCLK Input Clock Select

  1542. #define I2S0_MDR                *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register

  1543. #define I2S_MDR_FRACT(n)                ((uint32_t)(n & 0xff)<<12)    // MCLK Fraction

  1544. #define I2S_MDR_DIVIDE(n)               ((uint32_t)(n & 0xfff))       // MCLK Divide

  1545. 

  1546. // Chapter 47: General-Purpose Input/Output (GPIO)

  1547. #define GPIOA_PDOR              *(volatile uint32_t *)0x400FF000 // Port Data Output Register

  1548. #define GPIOA_PSOR              *(volatile uint32_t *)0x400FF004 // Port Set Output Register

  1549. #define GPIOA_PCOR              *(volatile uint32_t *)0x400FF008 // Port Clear Output Register

  1550. #define GPIOA_PTOR              *(volatile uint32_t *)0x400FF00C // Port Toggle Output Register

  1551. #define GPIOA_PDIR              *(volatile uint32_t *)0x400FF010 // Port Data Input Register

  1552. #define GPIOA_PDDR              *(volatile uint32_t *)0x400FF014 // Port Data Direction Register

  1553. #define GPIOB_PDOR              *(volatile uint32_t *)0x400FF040 // Port Data Output Register

  1554. #define GPIOB_PSOR              *(volatile uint32_t *)0x400FF044 // Port Set Output Register

  1555. #define GPIOB_PCOR              *(volatile uint32_t *)0x400FF048 // Port Clear Output Register

  1556. #define GPIOB_PTOR              *(volatile uint32_t *)0x400FF04C // Port Toggle Output Register

  1557. #define GPIOB_PDIR              *(volatile uint32_t *)0x400FF050 // Port Data Input Register

  1558. #define GPIOB_PDDR              *(volatile uint32_t *)0x400FF054 // Port Data Direction Register

  1559. #define GPIOC_PDOR              *(volatile uint32_t *)0x400FF080 // Port Data Output Register

  1560. #define GPIOC_PSOR              *(volatile uint32_t *)0x400FF084 // Port Set Output Register

  1561. #define GPIOC_PCOR              *(volatile uint32_t *)0x400FF088 // Port Clear Output Register

  1562. #define GPIOC_PTOR              *(volatile uint32_t *)0x400FF08C // Port Toggle Output Register

  1563. #define GPIOC_PDIR              *(volatile uint32_t *)0x400FF090 // Port Data Input Register

  1564. #define GPIOC_PDDR              *(volatile uint32_t *)0x400FF094 // Port Data Direction Register

  1565. #define GPIOD_PDOR              *(volatile uint32_t *)0x400FF0C0 // Port Data Output Register

  1566. #define GPIOD_PSOR              *(volatile uint32_t *)0x400FF0C4 // Port Set Output Register

  1567. #define GPIOD_PCOR              *(volatile uint32_t *)0x400FF0C8 // Port Clear Output Register

  1568. #define GPIOD_PTOR              *(volatile uint32_t *)0x400FF0CC // Port Toggle Output Register

  1569. #define GPIOD_PDIR              *(volatile uint32_t *)0x400FF0D0 // Port Data Input Register

  1570. #define GPIOD_PDDR              *(volatile uint32_t *)0x400FF0D4 // Port Data Direction Register

  1571. #define GPIOE_PDOR              *(volatile uint32_t *)0x400FF100 // Port Data Output Register

  1572. #define GPIOE_PSOR              *(volatile uint32_t *)0x400FF104 // Port Set Output Register

  1573. #define GPIOE_PCOR              *(volatile uint32_t *)0x400FF108 // Port Clear Output Register

  1574. #define GPIOE_PTOR              *(volatile uint32_t *)0x400FF10C // Port Toggle Output Register

  1575. #define GPIOE_PDIR              *(volatile uint32_t *)0x400FF110 // Port Data Input Register

  1576. #define GPIOE_PDDR              *(volatile uint32_t *)0x400FF114 // Port Data Direction Register

  1577. 

  1578. // Chapter 48: Touch sense input (TSI)

  1579. #define TSI0_GENCS              *(volatile uint32_t *)0x40045000 // General Control and Status Register

  1580. #define TSI_GENCS_LPCLKS		(uint32_t)0x10000000		// 

  1581. #define TSI_GENCS_LPSCNITV(n)		(((n) & 15) << 24)		// 

  1582. #define TSI_GENCS_NSCN(n)		(((n) & 31) << 19)		// 

  1583. #define TSI_GENCS_PS(n)			(((n) & 7) << 16)		// 

  1584. #define TSI_GENCS_EOSF			(uint32_t)0x00008000		// 

  1585. #define TSI_GENCS_OUTRGF		(uint32_t)0x00004000		// 

  1586. #define TSI_GENCS_EXTERF		(uint32_t)0x00002000		// 

  1587. #define TSI_GENCS_OVRF			(uint32_t)0x00001000		// 

  1588. #define TSI_GENCS_SCNIP			(uint32_t)0x00000200		// 

  1589. #define TSI_GENCS_SWTS			(uint32_t)0x00000100		// 

  1590. #define TSI_GENCS_TSIEN			(uint32_t)0x00000080		// 

  1591. #define TSI_GENCS_TSIIE			(uint32_t)0x00000040		// 

  1592. #define TSI_GENCS_ERIE			(uint32_t)0x00000020		// 

  1593. #define TSI_GENCS_ESOR			(uint32_t)0x00000010		// 

  1594. #define TSI_GENCS_STM			(uint32_t)0x00000002		// 

  1595. #define TSI_GENCS_STPE			(uint32_t)0x00000001		// 

  1596. #define TSI0_SCANC              *(volatile uint32_t *)0x40045004 // SCAN Control Register

  1597. #define TSI_SCANC_REFCHRG(n)		(((n) & 15) << 24)		// 

  1598. #define TSI_SCANC_EXTCHRG(n)		(((n) & 7) << 16)		// 

  1599. #define TSI_SCANC_SMOD(n)		(((n) & 255) << 8)		// 

  1600. #define TSI_SCANC_AMCLKS(n)		(((n) & 3) << 3)		// 

  1601. #define TSI_SCANC_AMPSC(n)		(((n) & 7) << 0)		// 

  1602. #define TSI0_PEN                *(volatile uint32_t *)0x40045008 // Pin Enable Register

  1603. #define TSI0_WUCNTR             *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register

  1604. #define TSI0_CNTR1              *(volatile uint32_t *)0x40045100 // Counter Register

  1605. #define TSI0_CNTR3              *(volatile uint32_t *)0x40045104 // Counter Register

  1606. #define TSI0_CNTR5              *(volatile uint32_t *)0x40045108 // Counter Register

  1607. #define TSI0_CNTR7              *(volatile uint32_t *)0x4004510C // Counter Register

  1608. #define TSI0_CNTR9              *(volatile uint32_t *)0x40045110 // Counter Register

  1609. #define TSI0_CNTR11             *(volatile uint32_t *)0x40045114 // Counter Register

  1610. #define TSI0_CNTR13             *(volatile uint32_t *)0x40045118 // Counter Register

  1611. #define TSI0_CNTR15             *(volatile uint32_t *)0x4004511C // Counter Register

  1612. #define TSI0_THRESHOLD          *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register

  1613. 

  1614. // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)

  1615. #define NVIC_ENABLE_IRQ(n)	(*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31)))

  1616. #define NVIC_DISABLE_IRQ(n)	(*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31)))

  1617. #define NVIC_SET_PENDING(n)	(*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31)))

  1618. #define NVIC_CLEAR_PENDING(n)	(*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31)))

  1619. 

  1620. #define NVIC_ISER0		*(volatile uint32_t *)0xE000E100

  1621. #define NVIC_ISER1		*(volatile uint32_t *)0xE000E104

  1622. #define NVIC_ICER0		*(volatile uint32_t *)0xE000E180

  1623. #define NVIC_ICER1		*(volatile uint32_t *)0xE000E184

  1624. 

  1625. // 0 = highest priority

  1626. // Cortex-M4: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240

  1627. #define NVIC_SET_PRIORITY(irqnum, priority)  (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority))

  1628. #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum)))

  1629. 

  1630. #define IRQ_DMA_CH0		0

  1631. #define IRQ_DMA_CH1		1

  1632. #define IRQ_DMA_CH2		2

  1633. #define IRQ_DMA_CH3		3

  1634. #define IRQ_DMA_ERROR		4

  1635. #define IRQ_FTFL_COMPLETE	6

  1636. #define IRQ_FTFL_COLLISION	7

  1637. #define IRQ_LOW_VOLTAGE		8

  1638. #define IRQ_LLWU		9

  1639. #define IRQ_WDOG		10

  1640. #define IRQ_I2C0		11

  1641. #define IRQ_SPI0		12

  1642. #define IRQ_I2S0_TX		13

  1643. #define IRQ_I2S0_RX		14

  1644. #define IRQ_UART0_LON		15

  1645. #define IRQ_UART0_STATUS	16

  1646. #define IRQ_UART0_ERROR		17

  1647. #define IRQ_UART1_STATUS	18

  1648. #define IRQ_UART1_ERROR		19

  1649. #define IRQ_UART2_STATUS	20

  1650. #define IRQ_UART2_ERROR		21

  1651. #define IRQ_ADC0		22

  1652. #define IRQ_CMP0		23

  1653. #define IRQ_CMP1		24

  1654. #define IRQ_FTM0		25

  1655. #define IRQ_FTM1		26

  1656. #define IRQ_CMT			27

  1657. #define IRQ_RTC_ALARM		28

  1658. #define IRQ_RTC_SECOND		29

  1659. #define IRQ_PIT_CH0		30

  1660. #define IRQ_PIT_CH1		31

  1661. #define IRQ_PIT_CH2		32

  1662. #define IRQ_PIT_CH3		33

  1663. #define IRQ_PDB			34

  1664. #define IRQ_USBOTG		35

  1665. #define IRQ_USBDCD		36

  1666. #define IRQ_TSI			37

  1667. #define IRQ_MCG			38

  1668. #define IRQ_LPTMR		39

  1669. #define IRQ_PORTA		40

  1670. #define IRQ_PORTB		41

  1671. #define IRQ_PORTC		42

  1672. #define IRQ_PORTD		43

  1673. #define IRQ_PORTE		44

  1674. #define IRQ_SOFTWARE		45

  1675. #define NVIC_NUM_INTERRUPTS	46

  1676. 

  1677. 

  1678. #define __disable_irq() asm volatile("CPSID i");

  1679. #define __enable_irq()  asm volatile("CPSIE i");

  1680. 

  1681. // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708

  1682. #define SCB_CPUID		*(const    uint32_t *)0xE000ED00 // CPUID Base Register

  1683. #define SCB_ICSR		*(volatile uint32_t *)0xE000ED04 // Interrupt Control and State

  1684. #define SCB_ICSR_PENDSTSET		(uint32_t)0x04000000

  1685. #define SCB_VTOR		*(volatile uint32_t *)0xE000ED08 // Vector Table Offset

  1686. #define SCB_AIRCR		*(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control

  1687. #define SCB_SCR			*(volatile uint32_t *)0xE000ED10 // System Control Register

  1688. #define SCB_CCR			*(volatile uint32_t *)0xE000ED14 // Configuration and Control

  1689. #define SCB_SHPR1		*(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1

  1690. #define SCB_SHPR2		*(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2

  1691. #define SCB_SHPR3		*(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3

  1692. #define SCB_SHCSR		*(volatile uint32_t *)0xE000ED24 // System Handler Control and State

  1693. #define SCB_CFSR		*(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register

  1694. #define SCB_HFSR		*(volatile uint32_t *)0xE000ED2C // HardFault Status

  1695. #define SCB_DFSR		*(volatile uint32_t *)0xE000ED30 // Debug Fault Status

  1696. #define SCB_MMFAR		*(volatile uint32_t *)0xE000ED34 // MemManage Fault Address

  1697. 

  1698. #define SYST_CSR		*(volatile uint32_t *)0xE000E010 // SysTick Control and Status

  1699. #define SYST_CSR_COUNTFLAG		(uint32_t)0x00010000

  1700. #define SYST_CSR_CLKSOURCE		(uint32_t)0x00000004

  1701. #define SYST_CSR_TICKINT		(uint32_t)0x00000002

  1702. #define SYST_CSR_ENABLE			(uint32_t)0x00000001

  1703. #define SYST_RVR		*(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register

  1704. #define SYST_CVR		*(volatile uint32_t *)0xE000E018 // SysTick Current Value Register

  1705. #define SYST_CALIB		*(const    uint32_t *)0xE000E01C // SysTick Calibration Value

  1706. 

  1707. 

  1708. #define ARM_DEMCR               *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control

  1709. #define ARM_DEMCR_TRCENA		(1 << 24)        // Enable debugging & monitoring blocks

  1710. #define ARM_DWT_CTRL            *(volatile uint32_t *)0xE0001000 // DWT control register

  1711. #define ARM_DWT_CTRL_CYCCNTENA          (1 << 0)                // Enable cycle count

  1712. #define ARM_DWT_CYCCNT          *(volatile uint32_t *)0xE0001004 // Cycle count register

  1713. 

  1714. extern int nvic_execution_priority(void);

  1715. 

  1716. extern void nmi_isr(void);

  1717. extern void hard_fault_isr(void);

  1718. extern void memmanage_fault_isr(void);

  1719. extern void bus_fault_isr(void);

  1720. extern void usage_fault_isr(void);

  1721. extern void svcall_isr(void);

  1722. extern void debugmonitor_isr(void);

  1723. extern void pendablesrvreq_isr(void);

  1724. extern void systick_isr(void);

  1725. extern void dma_ch0_isr(void);

  1726. extern void dma_ch1_isr(void);

  1727. extern void dma_ch2_isr(void);

  1728. extern void dma_ch3_isr(void);

  1729. extern void dma_error_isr(void);

  1730. extern void flash_cmd_isr(void);

  1731. extern void flash_error_isr(void);

  1732. extern void low_voltage_isr(void);

  1733. extern void wakeup_isr(void);

  1734. extern void watchdog_isr(void);

  1735. extern void i2c0_isr(void);

  1736. extern void spi0_isr(void);

  1737. extern void i2s0_tx_isr(void);

  1738. extern void i2s0_rx_isr(void);

  1739. extern void uart0_lon_isr(void);

  1740. extern void uart0_status_isr(void);

  1741. extern void uart0_error_isr(void);

  1742. extern void uart1_status_isr(void);

  1743. extern void uart1_error_isr(void);

  1744. extern void uart2_status_isr(void);

  1745. extern void uart2_error_isr(void);

  1746. extern void adc0_isr(void);

  1747. extern void cmp0_isr(void);

  1748. extern void cmp1_isr(void);

  1749. extern void ftm0_isr(void);

  1750. extern void ftm1_isr(void);

  1751. extern void cmt_isr(void);

  1752. extern void rtc_alarm_isr(void);

  1753. extern void rtc_seconds_isr(void);

  1754. extern void pit0_isr(void);

  1755. extern void pit1_isr(void);

  1756. extern void pit2_isr(void);

  1757. extern void pit3_isr(void);

  1758. extern void pdb_isr(void);

  1759. extern void usb_isr(void);

  1760. extern void usb_charge_isr(void);

  1761. extern void tsi0_isr(void);

  1762. extern void mcg_isr(void);

  1763. extern void lptmr_isr(void);

  1764. extern void porta_isr(void);

  1765. extern void portb_isr(void);

  1766. extern void portc_isr(void);

  1767. extern void portd_isr(void);

  1768. extern void porte_isr(void);

  1769. extern void software_isr(void);

  1770. 

  1771. 

  1772. 

  1773. 

  1774. #ifdef __cplusplus

  1775. }

  1776. #endif

  1777. #endif