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teensy-cores/teensy4/core_pins.h

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2018 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #pragma once

  32. #include "imxrt.h"

  33. #include "pins_arduino.h"

  34. 

  35. #define HIGH			1

  36. #define LOW			0

  37. #define INPUT			0

  38. #define OUTPUT			1

  39. #define INPUT_PULLUP		2

  40. #define INPUT_PULLDOWN		3

  41. #define OUTPUT_OPENDRAIN	4

  42. #define INPUT_DISABLE		5

  43. #define LSBFIRST		0

  44. #define MSBFIRST		1

  45. #define _BV(n)			(1<<(n))

  46. #define CHANGE			4

  47. #define FALLING			2

  48. #define RISING			3

  49. 

  50. #define CORE_NUM_TOTAL_PINS	34

  51. #define CORE_NUM_DIGITAL	34

  52. #define CORE_NUM_INTERRUPT	34

  53. #define CORE_NUM_ANALOG		14

  54. #define CORE_NUM_PWM		27

  55. 

  56. #define CORE_PIN0_BIT		3

  57. #define CORE_PIN1_BIT		2

  58. #define CORE_PIN2_BIT		4

  59. #define CORE_PIN3_BIT		5

  60. #define CORE_PIN4_BIT		6

  61. #define CORE_PIN5_BIT		7

  62. #define CORE_PIN6_BIT		17

  63. #define CORE_PIN7_BIT		16

  64. #define CORE_PIN8_BIT		10

  65. #define CORE_PIN9_BIT		11

  66. #define CORE_PIN10_BIT		0

  67. #define CORE_PIN11_BIT		2

  68. #define CORE_PIN12_BIT		1

  69. #define CORE_PIN13_BIT		3

  70. #define CORE_PIN14_BIT		18

  71. #define CORE_PIN15_BIT		19

  72. #define CORE_PIN16_BIT		23

  73. #define CORE_PIN17_BIT		22

  74. #define CORE_PIN18_BIT		17

  75. #define CORE_PIN19_BIT		16

  76. #define CORE_PIN20_BIT		26

  77. #define CORE_PIN21_BIT		27

  78. #define CORE_PIN22_BIT		24

  79. #define CORE_PIN23_BIT		25

  80. #define CORE_PIN24_BIT		12

  81. #define CORE_PIN25_BIT		13

  82. #define CORE_PIN26_BIT		30

  83. #define CORE_PIN27_BIT		31

  84. #define CORE_PIN28_BIT		18

  85. #define CORE_PIN29_BIT		31

  86. #define CORE_PIN30_BIT		24

  87. #define CORE_PIN31_BIT		23

  88. #define CORE_PIN32_BIT		12

  89. #define CORE_PIN33_BIT		8

  90. 

  91. #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))

  92. #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))

  93. #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))

  94. #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))

  95. #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))

  96. #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))

  97. #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))

  98. #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))

  99. #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))

  100. #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))

  101. #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))

  102. #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))

  103. #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))

  104. #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))

  105. #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))

  106. #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))

  107. #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))

  108. #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))

  109. #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))

  110. #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))

  111. #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))

  112. #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))

  113. #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))

  114. #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))

  115. #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))

  116. #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))

  117. #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))

  118. #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))

  119. #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))

  120. #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))

  121. #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))

  122. #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))

  123. #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))

  124. #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))

  125. 

  126. #define CORE_PIN0_PORTREG	GPIO1_DR

  127. #define CORE_PIN1_PORTREG	GPIO1_DR

  128. #define CORE_PIN2_PORTREG	GPIO4_DR

  129. #define CORE_PIN3_PORTREG	GPIO4_DR

  130. #define CORE_PIN4_PORTREG	GPIO4_DR

  131. #define CORE_PIN5_PORTREG	GPIO4_DR

  132. #define CORE_PIN6_PORTREG	GPIO2_DR

  133. #define CORE_PIN7_PORTREG	GPIO2_DR

  134. #define CORE_PIN8_PORTREG	GPIO2_DR

  135. #define CORE_PIN9_PORTREG	GPIO2_DR

  136. #define CORE_PIN10_PORTREG	GPIO2_DR

  137. #define CORE_PIN11_PORTREG	GPIO2_DR

  138. #define CORE_PIN12_PORTREG	GPIO2_DR

  139. #define CORE_PIN13_PORTREG	GPIO2_DR

  140. #define CORE_PIN14_PORTREG	GPIO1_DR

  141. #define CORE_PIN15_PORTREG	GPIO1_DR

  142. #define CORE_PIN16_PORTREG	GPIO1_DR

  143. #define CORE_PIN17_PORTREG	GPIO1_DR

  144. #define CORE_PIN18_PORTREG	GPIO1_DR

  145. #define CORE_PIN19_PORTREG	GPIO1_DR

  146. #define CORE_PIN20_PORTREG	GPIO1_DR

  147. #define CORE_PIN21_PORTREG	GPIO1_DR

  148. #define CORE_PIN22_PORTREG	GPIO1_DR

  149. #define CORE_PIN23_PORTREG	GPIO1_DR

  150. #define CORE_PIN24_PORTREG	GPIO1_DR

  151. #define CORE_PIN25_PORTREG	GPIO1_DR

  152. #define CORE_PIN26_PORTREG	GPIO1_DR

  153. #define CORE_PIN27_PORTREG	GPIO1_DR

  154. #define CORE_PIN28_PORTREG	GPIO3_DR

  155. #define CORE_PIN29_PORTREG	GPIO4_DR

  156. #define CORE_PIN30_PORTREG	GPIO4_DR

  157. #define CORE_PIN31_PORTREG	GPIO4_DR

  158. #define CORE_PIN32_PORTREG	GPIO2_DR

  159. #define CORE_PIN33_PORTREG	GPIO4_DR

  160. 

  161. #define CORE_PIN0_PORTSET	GPIO1_DR_SET

  162. #define CORE_PIN1_PORTSET	GPIO1_DR_SET

  163. #define CORE_PIN2_PORTSET	GPIO4_DR_SET

  164. #define CORE_PIN3_PORTSET	GPIO4_DR_SET

  165. #define CORE_PIN4_PORTSET	GPIO4_DR_SET

  166. #define CORE_PIN5_PORTSET	GPIO4_DR_SET

  167. #define CORE_PIN6_PORTSET	GPIO2_DR_SET

  168. #define CORE_PIN7_PORTSET	GPIO2_DR_SET

  169. #define CORE_PIN8_PORTSET	GPIO2_DR_SET

  170. #define CORE_PIN9_PORTSET	GPIO2_DR_SET

  171. #define CORE_PIN10_PORTSET	GPIO2_DR_SET

  172. #define CORE_PIN11_PORTSET	GPIO2_DR_SET

  173. #define CORE_PIN12_PORTSET	GPIO2_DR_SET

  174. #define CORE_PIN13_PORTSET	GPIO2_DR_SET

  175. #define CORE_PIN14_PORTSET	GPIO1_DR_SET

  176. #define CORE_PIN15_PORTSET	GPIO1_DR_SET

  177. #define CORE_PIN16_PORTSET	GPIO1_DR_SET

  178. #define CORE_PIN17_PORTSET	GPIO1_DR_SET

  179. #define CORE_PIN18_PORTSET	GPIO1_DR_SET

  180. #define CORE_PIN19_PORTSET	GPIO1_DR_SET

  181. #define CORE_PIN20_PORTSET	GPIO1_DR_SET

  182. #define CORE_PIN21_PORTSET	GPIO1_DR_SET

  183. #define CORE_PIN22_PORTSET	GPIO1_DR_SET

  184. #define CORE_PIN23_PORTSET	GPIO1_DR_SET

  185. #define CORE_PIN24_PORTSET	GPIO1_DR_SET

  186. #define CORE_PIN25_PORTSET	GPIO1_DR_SET

  187. #define CORE_PIN26_PORTSET	GPIO1_DR_SET

  188. #define CORE_PIN27_PORTSET	GPIO1_DR_SET

  189. #define CORE_PIN28_PORTSET	GPIO3_DR_SET

  190. #define CORE_PIN29_PORTSET	GPIO4_DR_SET

  191. #define CORE_PIN30_PORTSET	GPIO4_DR_SET

  192. #define CORE_PIN31_PORTSET	GPIO4_DR_SET

  193. #define CORE_PIN32_PORTSET	GPIO2_DR_SET

  194. #define CORE_PIN33_PORTSET	GPIO4_DR_SET

  195. 

  196. #define CORE_PIN0_PORTCLEAR	GPIO1_DR_CLEAR

  197. #define CORE_PIN1_PORTCLEAR	GPIO1_DR_CLEAR

  198. #define CORE_PIN2_PORTCLEAR	GPIO4_DR_CLEAR

  199. #define CORE_PIN3_PORTCLEAR	GPIO4_DR_CLEAR

  200. #define CORE_PIN4_PORTCLEAR	GPIO4_DR_CLEAR

  201. #define CORE_PIN5_PORTCLEAR	GPIO4_DR_CLEAR

  202. #define CORE_PIN6_PORTCLEAR	GPIO2_DR_CLEAR

  203. #define CORE_PIN7_PORTCLEAR	GPIO2_DR_CLEAR

  204. #define CORE_PIN8_PORTCLEAR	GPIO2_DR_CLEAR

  205. #define CORE_PIN9_PORTCLEAR	GPIO2_DR_CLEAR

  206. #define CORE_PIN10_PORTCLEAR	GPIO2_DR_CLEAR

  207. #define CORE_PIN11_PORTCLEAR	GPIO2_DR_CLEAR

  208. #define CORE_PIN12_PORTCLEAR	GPIO2_DR_CLEAR

  209. #define CORE_PIN13_PORTCLEAR	GPIO2_DR_CLEAR

  210. #define CORE_PIN14_PORTCLEAR	GPIO1_DR_CLEAR

  211. #define CORE_PIN15_PORTCLEAR	GPIO1_DR_CLEAR

  212. #define CORE_PIN16_PORTCLEAR	GPIO1_DR_CLEAR

  213. #define CORE_PIN17_PORTCLEAR	GPIO1_DR_CLEAR

  214. #define CORE_PIN18_PORTCLEAR	GPIO1_DR_CLEAR

  215. #define CORE_PIN19_PORTCLEAR	GPIO1_DR_CLEAR

  216. #define CORE_PIN20_PORTCLEAR	GPIO1_DR_CLEAR

  217. #define CORE_PIN21_PORTCLEAR	GPIO1_DR_CLEAR

  218. #define CORE_PIN22_PORTCLEAR	GPIO1_DR_CLEAR

  219. #define CORE_PIN23_PORTCLEAR	GPIO1_DR_CLEAR

  220. #define CORE_PIN24_PORTCLEAR	GPIO1_DR_CLEAR

  221. #define CORE_PIN25_PORTCLEAR	GPIO1_DR_CLEAR

  222. #define CORE_PIN26_PORTCLEAR	GPIO1_DR_CLEAR

  223. #define CORE_PIN27_PORTCLEAR	GPIO1_DR_CLEAR

  224. #define CORE_PIN28_PORTCLEAR	GPIO3_DR_CLEAR

  225. #define CORE_PIN29_PORTCLEAR	GPIO4_DR_CLEAR

  226. #define CORE_PIN30_PORTCLEAR	GPIO4_DR_CLEAR

  227. #define CORE_PIN31_PORTCLEAR	GPIO4_DR_CLEAR

  228. #define CORE_PIN32_PORTCLEAR	GPIO2_DR_CLEAR

  229. #define CORE_PIN33_PORTCLEAR	GPIO4_DR_CLEAR

  230. 

  231. #define CORE_PIN0_DDRREG	GPIO1_GDIR

  232. #define CORE_PIN1_DDRREG	GPIO1_GDIR

  233. #define CORE_PIN2_DDRREG	GPIO4_GDIR

  234. #define CORE_PIN3_DDRREG	GPIO4_GDIR

  235. #define CORE_PIN4_DDRREG	GPIO4_GDIR

  236. #define CORE_PIN5_DDRREG	GPIO4_GDIR

  237. #define CORE_PIN6_DDRREG	GPIO2_GDIR

  238. #define CORE_PIN7_DDRREG	GPIO2_GDIR

  239. #define CORE_PIN8_DDRREG	GPIO2_GDIR

  240. #define CORE_PIN9_DDRREG	GPIO2_GDIR

  241. #define CORE_PIN10_DDRREG	GPIO2_GDIR

  242. #define CORE_PIN11_DDRREG	GPIO2_GDIR

  243. #define CORE_PIN12_DDRREG	GPIO2_GDIR

  244. #define CORE_PIN13_DDRREG	GPIO2_GDIR

  245. #define CORE_PIN14_DDRREG	GPIO1_GDIR

  246. #define CORE_PIN15_DDRREG	GPIO1_GDIR

  247. #define CORE_PIN16_DDRREG	GPIO1_GDIR

  248. #define CORE_PIN17_DDRREG	GPIO1_GDIR

  249. #define CORE_PIN18_DDRREG	GPIO1_GDIR

  250. #define CORE_PIN19_DDRREG	GPIO1_GDIR

  251. #define CORE_PIN20_DDRREG	GPIO1_GDIR

  252. #define CORE_PIN21_DDRREG	GPIO1_GDIR

  253. #define CORE_PIN22_DDRREG	GPIO1_GDIR

  254. #define CORE_PIN23_DDRREG	GPIO1_GDIR

  255. #define CORE_PIN24_DDRREG	GPIO1_GDIR

  256. #define CORE_PIN25_DDRREG	GPIO1_GDIR

  257. #define CORE_PIN26_DDRREG	GPIO1_GDIR

  258. #define CORE_PIN27_DDRREG	GPIO1_GDIR

  259. #define CORE_PIN28_DDRREG	GPIO3_GDIR

  260. #define CORE_PIN29_DDRREG	GPIO4_GDIR

  261. #define CORE_PIN30_DDRREG	GPIO4_GDIR

  262. #define CORE_PIN31_DDRREG	GPIO4_GDIR

  263. #define CORE_PIN32_DDRREG	GPIO2_GDIR

  264. #define CORE_PIN33_DDRREG	GPIO4_GDIR

  265. 

  266. #define CORE_PIN0_PINREG	GPIO1_PSR

  267. #define CORE_PIN1_PINREG	GPIO1_PSR

  268. #define CORE_PIN2_PINREG	GPIO4_PSR

  269. #define CORE_PIN3_PINREG	GPIO4_PSR

  270. #define CORE_PIN4_PINREG	GPIO4_PSR

  271. #define CORE_PIN5_PINREG	GPIO4_PSR

  272. #define CORE_PIN6_PINREG	GPIO2_PSR

  273. #define CORE_PIN7_PINREG	GPIO2_PSR

  274. #define CORE_PIN8_PINREG	GPIO2_PSR

  275. #define CORE_PIN9_PINREG	GPIO2_PSR

  276. #define CORE_PIN10_PINREG	GPIO2_PSR

  277. #define CORE_PIN11_PINREG	GPIO2_PSR

  278. #define CORE_PIN12_PINREG	GPIO2_PSR

  279. #define CORE_PIN13_PINREG	GPIO2_PSR

  280. #define CORE_PIN14_PINREG	GPIO1_PSR

  281. #define CORE_PIN15_PINREG	GPIO1_PSR

  282. #define CORE_PIN16_PINREG	GPIO1_PSR

  283. #define CORE_PIN17_PINREG	GPIO1_PSR

  284. #define CORE_PIN18_PINREG	GPIO1_PSR

  285. #define CORE_PIN19_PINREG	GPIO1_PSR

  286. #define CORE_PIN20_PINREG	GPIO1_PSR

  287. #define CORE_PIN21_PINREG	GPIO1_PSR

  288. #define CORE_PIN22_PINREG	GPIO1_PSR

  289. #define CORE_PIN23_PINREG	GPIO1_PSR

  290. #define CORE_PIN24_PINREG	GPIO1_PSR

  291. #define CORE_PIN25_PINREG	GPIO1_PSR

  292. #define CORE_PIN26_PINREG	GPIO1_PSR

  293. #define CORE_PIN27_PINREG	GPIO1_PSR

  294. #define CORE_PIN28_PINREG	GPIO3_PSR

  295. #define CORE_PIN29_PINREG	GPIO4_PSR

  296. #define CORE_PIN30_PINREG	GPIO4_PSR

  297. #define CORE_PIN31_PINREG	GPIO4_PSR

  298. #define CORE_PIN32_PINREG	GPIO2_PSR

  299. #define CORE_PIN33_PINREG	GPIO4_PSR

  300. 

  301. // mux config registers control which peripheral uses the pin

  302. #define CORE_PIN0_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03

  303. #define CORE_PIN1_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02

  304. #define CORE_PIN2_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04

  305. #define CORE_PIN3_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05

  306. #define CORE_PIN4_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06

  307. #define CORE_PIN5_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07

  308. #define CORE_PIN6_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01

  309. #define CORE_PIN7_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00

  310. #define CORE_PIN8_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10

  311. #define CORE_PIN9_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11

  312. #define CORE_PIN10_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00

  313. #define CORE_PIN11_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02

  314. #define CORE_PIN12_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01

  315. #define CORE_PIN13_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03

  316. #define CORE_PIN14_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02

  317. #define CORE_PIN15_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03

  318. #define CORE_PIN16_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07

  319. #define CORE_PIN17_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06

  320. #define CORE_PIN18_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01

  321. #define CORE_PIN19_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00

  322. #define CORE_PIN20_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10

  323. #define CORE_PIN21_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11

  324. #define CORE_PIN22_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08

  325. #define CORE_PIN23_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09

  326. #define CORE_PIN24_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12

  327. #define CORE_PIN25_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13

  328. #define CORE_PIN26_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14

  329. #define CORE_PIN27_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15

  330. #define CORE_PIN28_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32

  331. #define CORE_PIN29_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31

  332. #define CORE_PIN30_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24

  333. #define CORE_PIN31_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23

  334. #define CORE_PIN32_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12

  335. #define CORE_PIN33_CONFIG	IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08

  336. 

  337. // pad config registers control pullup/pulldown/keeper, drive strength, etc

  338. #define CORE_PIN0_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03

  339. #define CORE_PIN1_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03

  340. #define CORE_PIN2_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04

  341. #define CORE_PIN3_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05

  342. #define CORE_PIN4_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06

  343. #define CORE_PIN5_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07

  344. #define CORE_PIN6_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01

  345. #define CORE_PIN7_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00

  346. #define CORE_PIN8_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10

  347. #define CORE_PIN9_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11

  348. #define CORE_PIN10_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00

  349. #define CORE_PIN11_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02

  350. #define CORE_PIN12_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01

  351. #define CORE_PIN13_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03

  352. #define CORE_PIN14_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02

  353. #define CORE_PIN15_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03

  354. #define CORE_PIN16_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07

  355. #define CORE_PIN17_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06

  356. #define CORE_PIN18_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01

  357. #define CORE_PIN19_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00

  358. #define CORE_PIN20_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10

  359. #define CORE_PIN21_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11

  360. #define CORE_PIN22_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08

  361. #define CORE_PIN23_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09

  362. #define CORE_PIN24_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12

  363. #define CORE_PIN25_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13

  364. #define CORE_PIN26_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14

  365. #define CORE_PIN27_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15

  366. #define CORE_PIN28_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32

  367. #define CORE_PIN29_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31

  368. #define CORE_PIN30_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24

  369. #define CORE_PIN31_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23

  370. #define CORE_PIN32_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12

  371. #define CORE_PIN33_PADCONFIG	IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08

  372. 

  373. #define CORE_LED0_PIN		13

  374. 

  375. #define CORE_ADC0_PIN		14

  376. #define CORE_ADC1_PIN		15

  377. #define CORE_ADC2_PIN		16

  378. #define CORE_ADC3_PIN		17

  379. #define CORE_ADC4_PIN		18

  380. #define CORE_ADC5_PIN		19

  381. #define CORE_ADC6_PIN		20

  382. #define CORE_ADC7_PIN		21

  383. #define CORE_ADC8_PIN		22

  384. #define CORE_ADC9_PIN		23

  385. 

  386. #define CORE_RXD0_PIN		0

  387. #define CORE_TXD0_PIN		1

  388. #define CORE_RXD1_PIN		6

  389. #define CORE_TXD1_PIN		7

  390. #define CORE_RXD2_PIN		15

  391. #define CORE_TXD2_PIN		14

  392. #define CORE_RXD3_PIN		16

  393. #define CORE_TXD3_PIN		17

  394. #define CORE_RXD4_PIN		21

  395. #define CORE_TXD4_PIN		20

  396. #define CORE_RXD5_PIN		25

  397. #define CORE_TXD5_PIN		24

  398. #define CORE_RXD6_PIN		28

  399. #define CORE_TXD6_PIN		29

  400. #define CORE_RXD7_PIN		30

  401. #define CORE_TXD7_PIN		31

  402. 

  403. #define CORE_INT0_PIN		0

  404. #define CORE_INT1_PIN		1

  405. #define CORE_INT2_PIN		2

  406. #define CORE_INT3_PIN		3

  407. #define CORE_INT4_PIN		4

  408. #define CORE_INT5_PIN		5

  409. #define CORE_INT6_PIN		6

  410. #define CORE_INT7_PIN		7

  411. #define CORE_INT8_PIN		8

  412. #define CORE_INT9_PIN		9

  413. #define CORE_INT10_PIN		10

  414. #define CORE_INT11_PIN		11

  415. #define CORE_INT12_PIN		12

  416. #define CORE_INT13_PIN		13

  417. #define CORE_INT14_PIN		14

  418. #define CORE_INT15_PIN		15

  419. #define CORE_INT16_PIN		16

  420. #define CORE_INT17_PIN		17

  421. #define CORE_INT18_PIN		18

  422. #define CORE_INT19_PIN		19

  423. #define CORE_INT20_PIN		20

  424. #define CORE_INT21_PIN		21

  425. #define CORE_INT22_PIN		22

  426. #define CORE_INT23_PIN		23

  427. #define CORE_INT24_PIN		24

  428. #define CORE_INT25_PIN		25

  429. #define CORE_INT26_PIN		26

  430. #define CORE_INT27_PIN		27

  431. #define CORE_INT28_PIN		28

  432. #define CORE_INT29_PIN		29

  433. #define CORE_INT30_PIN		30

  434. #define CORE_INT31_PIN		31

  435. #define CORE_INT32_PIN		32

  436. #define CORE_INT33_PIN		33

  437. #define CORE_INT_EVERY_PIN	1

  438. 

  439. 

  440. #ifdef __cplusplus

  441. extern "C" {

  442. #endif

  443. 

  444. 

  445. void digitalWrite(uint8_t pin, uint8_t val);

  446. static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));

  447. static inline void digitalWriteFast(uint8_t pin, uint8_t val)

  448. {

  449. 	if (__builtin_constant_p(pin)) {

  450. 		if (val) {

  451. 			if (pin == 0) {

  452. 				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;

  453. 			} else if (pin == 1) {

  454. 				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;

  455. 			} else if (pin == 2) {

  456. 				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;

  457. 			} else if (pin == 3) {

  458. 				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;

  459. 			} else if (pin == 4) {

  460. 				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;

  461. 			} else if (pin == 5) {

  462. 				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;

  463. 			} else if (pin == 6) {

  464. 				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;

  465. 			} else if (pin == 7) {

  466. 				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;

  467. 			} else if (pin == 8) {

  468. 				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;

  469. 			} else if (pin == 9) {

  470. 				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;

  471. 			} else if (pin == 10) {

  472. 				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;

  473. 			} else if (pin == 11) {

  474. 				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;

  475. 			} else if (pin == 12) {

  476. 				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;

  477. 			} else if (pin == 13) {

  478. 				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;

  479. 			} else if (pin == 14) {

  480. 				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;

  481. 			} else if (pin == 15) {

  482. 				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;

  483. 			} else if (pin == 16) {

  484. 				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;

  485. 			} else if (pin == 17) {

  486. 				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;

  487. 			} else if (pin == 18) {

  488. 				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;

  489. 			} else if (pin == 19) {

  490. 				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;

  491. 			} else if (pin == 20) {

  492. 				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;

  493. 			} else if (pin == 21) {

  494. 				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;

  495. 			} else if (pin == 22) {

  496. 				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;

  497. 			} else if (pin == 23) {

  498. 				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;

  499. 			} else if (pin == 24) {

  500. 				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;

  501. 			} else if (pin == 25) {

  502. 				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;

  503. 			} else if (pin == 26) {

  504. 				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;

  505. 			} else if (pin == 27) {

  506. 				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;

  507. 			} else if (pin == 28) {

  508. 				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;

  509. 			} else if (pin == 29) {

  510. 				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;

  511. 			} else if (pin == 30) {

  512. 				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;

  513. 			} else if (pin == 31) {

  514. 				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;

  515. 			} else if (pin == 32) {

  516. 				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;

  517. 			} else if (pin == 33) {

  518. 				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;

  519. 			}

  520. 		} else {

  521. 			if (pin == 0) {

  522. 				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;

  523. 			} else if (pin == 1) {

  524. 				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;

  525. 			} else if (pin == 2) {

  526. 				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;

  527. 			} else if (pin == 3) {

  528. 				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;

  529. 			} else if (pin == 4) {

  530. 				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;

  531. 			} else if (pin == 5) {

  532. 				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;

  533. 			} else if (pin == 6) {

  534. 				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;

  535. 			} else if (pin == 7) {

  536. 				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;

  537. 			} else if (pin == 8) {

  538. 				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;

  539. 			} else if (pin == 9) {

  540. 				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;

  541. 			} else if (pin == 10) {

  542. 				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;

  543. 			} else if (pin == 11) {

  544. 				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;

  545. 			} else if (pin == 12) {

  546. 				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;

  547. 			} else if (pin == 13) {

  548. 				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;

  549. 			} else if (pin == 14) {

  550. 				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;

  551. 			} else if (pin == 15) {

  552. 				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;

  553. 			} else if (pin == 16) {

  554. 				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;

  555. 			} else if (pin == 17) {

  556. 				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;

  557. 			} else if (pin == 18) {

  558. 				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;

  559. 			} else if (pin == 19) {

  560. 				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;

  561. 			} else if (pin == 20) {

  562. 				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;

  563. 			} else if (pin == 21) {

  564. 				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;

  565. 			} else if (pin == 22) {

  566. 				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;

  567. 			} else if (pin == 23) {

  568. 				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;

  569. 			} else if (pin == 24) {

  570. 				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;

  571. 			} else if (pin == 25) {

  572. 				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;

  573. 			} else if (pin == 26) {

  574. 				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;

  575. 			} else if (pin == 27) {

  576. 				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;

  577. 			} else if (pin == 28) {

  578. 				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;

  579. 			} else if (pin == 29) {

  580. 				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;

  581. 			} else if (pin == 30) {

  582. 				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;

  583. 			} else if (pin == 31) {

  584. 				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;

  585. 			} else if (pin == 32) {

  586. 				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;

  587. 			} else if (pin == 33) {

  588. 				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;

  589. 			}

  590. 		}

  591. 	} else {

  592. 		if(val) *portSetRegister(pin) = digitalPinToBitMask(pin);

  593. 		else *portClearRegister(pin) = digitalPinToBitMask(pin);

  594. 	}

  595. }

  596. 

  597. uint8_t digitalRead(uint8_t pin);

  598. static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));

  599. static inline uint8_t digitalReadFast(uint8_t pin)

  600. {

  601. 	if (__builtin_constant_p(pin)) {

  602. 		if (pin == 0) {

  603. 			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;

  604. 		} else if (pin == 1) {

  605. 			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;

  606. 		} else if (pin == 2) {

  607. 			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;

  608. 		} else if (pin == 3) {

  609. 			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;

  610. 		} else if (pin == 4) {

  611. 			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;

  612. 		} else if (pin == 5) {

  613. 			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;

  614. 		} else if (pin == 6) {

  615. 			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;

  616. 		} else if (pin == 7) {

  617. 			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;

  618. 		} else if (pin == 8) {

  619. 			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;

  620. 		} else if (pin == 9) {

  621. 			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;

  622. 		} else if (pin == 10) {

  623. 			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;

  624. 		} else if (pin == 11) {

  625. 			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;

  626. 		} else if (pin == 12) {

  627. 			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;

  628. 		} else if (pin == 13) {

  629. 			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;

  630. 		} else if (pin == 14) {

  631. 			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;

  632. 		} else if (pin == 15) {

  633. 			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;

  634. 		} else if (pin == 16) {

  635. 			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;

  636. 		} else if (pin == 17) {

  637. 			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;

  638. 		} else if (pin == 18) {

  639. 			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;

  640. 		} else if (pin == 19) {

  641. 			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;

  642. 		} else if (pin == 20) {

  643. 			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;

  644. 		} else if (pin == 21) {

  645. 			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;

  646. 		} else if (pin == 22) {

  647. 			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;

  648. 		} else if (pin == 23) {

  649. 			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;

  650. 		} else if (pin == 24) {

  651. 			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;

  652. 		} else if (pin == 25) {

  653. 			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;

  654. 		} else if (pin == 26) {

  655. 			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;

  656. 		} else if (pin == 27) {

  657. 			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;

  658. 		} else if (pin == 28) {

  659. 			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;

  660. 		} else if (pin == 29) {

  661. 			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;

  662. 		} else if (pin == 30) {

  663. 			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;

  664. 		} else if (pin == 31) {

  665. 			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;

  666. 		} else if (pin == 32) {

  667. 			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;

  668. 		} else if (pin == 33) {

  669. 			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;

  670. 		} else {

  671. 			return 0;

  672. 		}

  673. 	} else {

  674. 		return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;

  675. 	}

  676. }

  677. 

  678. 

  679. void pinMode(uint8_t pin, uint8_t mode);

  680. void init_pins(void);

  681. void analogWrite(uint8_t pin, int val);

  682. uint32_t analogWriteRes(uint32_t bits);

  683. static inline uint32_t analogWriteResolution(uint32_t bits) { return analogWriteRes(bits); }

  684. void analogWriteFrequency(uint8_t pin, float frequency);

  685. void attachInterrupt(uint8_t pin, void (*function)(void), int mode);

  686. void detachInterrupt(uint8_t pin);

  687. void _init_Teensyduino_internal_(void);

  688. int analogRead(uint8_t pin);

  689. void analogReference(uint8_t type);

  690. void analogReadRes(unsigned int bits);

  691. static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }

  692. void analogReadAveraging(unsigned int num);

  693. void analog_init(void);

  694. int touchRead(uint8_t pin);

  695. 

  696. static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  697. extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));

  698. extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  699. extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));

  700. 

  701. static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)

  702. {

  703.         if (__builtin_constant_p(bitOrder)) {

  704.                 if (bitOrder == LSBFIRST) {

  705.                         shiftOut_lsbFirst(dataPin, clockPin, value);

  706.                 } else {

  707.                         shiftOut_msbFirst(dataPin, clockPin, value);

  708.                 }

  709.         } else {

  710.                 _shiftOut(dataPin, clockPin, bitOrder, value);

  711.         }

  712. }

  713. 

  714. static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));

  715. extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));

  716. extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  717. extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));

  718. 

  719. static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)

  720. {

  721.         if (__builtin_constant_p(bitOrder)) {

  722.                 if (bitOrder == LSBFIRST) {

  723.                         return shiftIn_lsbFirst(dataPin, clockPin);

  724.                 } else {

  725.                         return shiftIn_msbFirst(dataPin, clockPin);

  726.                 }

  727.         } else {

  728.                 return _shiftIn(dataPin, clockPin, bitOrder);

  729.         }

  730. }

  731. 

  732. void _reboot_Teensyduino_(void) __attribute__((noreturn));

  733. void _restart_Teensyduino_(void) __attribute__((noreturn));

  734. 

  735. void yield(void);

  736. 

  737. void delay(uint32_t msec);

  738. 

  739. extern volatile uint32_t F_CPU_ACTUAL;

  740. extern volatile uint32_t F_BUS_ACTUAL;

  741. extern volatile uint32_t systick_millis_count;

  742. 

  743. static inline uint32_t millis(void) __attribute__((always_inline, unused));

  744. static inline uint32_t millis(void)

  745. {

  746. 	return systick_millis_count;

  747. }

  748. 

  749. uint32_t micros(void);

  750. 

  751. static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));

  752. static inline void delayMicroseconds(uint32_t usec)

  753. {

  754. 	uint32_t begin = ARM_DWT_CYCCNT;

  755. 	uint32_t cycles = F_CPU_ACTUAL / 1000000 * usec;

  756. 	// TODO: check if cycles is large, do a wait with yield calls until it's smaller

  757. 	while (ARM_DWT_CYCCNT - begin < cycles) ; // wait

  758. }

  759. 

  760. static inline void delayNanoseconds(uint32_t) __attribute__((always_inline, unused));

  761. static inline void delayNanoseconds(uint32_t nsec)

  762. {

  763. 	uint32_t begin = ARM_DWT_CYCCNT;

  764. 	uint32_t cycles =   ((F_CPU_ACTUAL>>16) * nsec) / (1000000000UL>>16);

  765. 	while (ARM_DWT_CYCCNT - begin < cycles) ; // wait

  766. }

  767. 

  768. 

  769. unsigned long rtc_get(void);

  770. void rtc_set(unsigned long t);

  771. void rtc_compensate(int adjust);

  772. 

  773. void tempmon_init(void);

  774. float tempmonGetTemp(void);

  775. void tempmon_Start();

  776. void tempmon_Stop();

  777. void tempmon_PwrDwn();

  778. 

  779. #ifdef __cplusplus

  780. }

  781. 

  782. class teensy3_clock_class

  783. {

  784. public:

  785.         static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }

  786.         static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }

  787.         static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }

  788. };

  789. extern teensy3_clock_class Teensy3Clock;

  790. 

  791. #endif // __cplusplus

  792. 

  793. 

  794.