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teensy-cores/teensy4/avr_emulation.h

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  1. /* Teensyduino Core Library

  2.  * http://www.pjrc.com/teensy/

  3.  * Copyright (c) 2019 PJRC.COM, LLC.

  4.  *

  5.  * Permission is hereby granted, free of charge, to any person obtaining

  6.  * a copy of this software and associated documentation files (the

  7.  * "Software"), to deal in the Software without restriction, including

  8.  * without limitation the rights to use, copy, modify, merge, publish,

  9.  * distribute, sublicense, and/or sell copies of the Software, and to

  10.  * permit persons to whom the Software is furnished to do so, subject to

  11.  * the following conditions:

  12.  *

  13.  * 1. The above copyright notice and this permission notice shall be

  14.  * included in all copies or substantial portions of the Software.

  15.  *

  16.  * 2. If the Software is incorporated into a build system that allows

  17.  * selection among a list of target devices, then similar target

  18.  * devices manufactured by PJRC.COM must be included in the list of

  19.  * target devices and selectable in the same manner.

  20.  *

  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

  22.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

  24.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS

  25.  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN

  26.  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

  27.  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

  28.  * SOFTWARE.

  29.  */

  30. 

  31. #ifndef _avr_emulation_h_

  32. #define _avr_emulation_h_

  33. 

  34. #include "imxrt.h"

  35. #include "core_pins.h"

  36. #include "pins_arduino.h"

  37. 

  38. #ifdef __cplusplus

  39. 

  40. 

  41. 

  42. // SPI Control Register ­ SPCR

  43. #define SPIE	7	// SPI Interrupt Enable - not supported

  44. #define SPE	6	// SPI Enable

  45. #define DORD	5	// DORD: Data Order

  46. #define MSTR	4	// MSTR: Master/Slave Select

  47. #define CPOL	3	// CPOL: Clock Polarity

  48. #define CPHA	2	// CPHA: Clock Phase

  49. #define SPR1	1	// Clock: 3 = 125 kHz, 2 = 250 kHz, 1 = 1 MHz, 0->4 MHz

  50. #define SPR0	0

  51. // SPI Status Register ­ SPSR

  52. #define SPIF	7	// SPIF: SPI Interrupt Flag

  53. #define WCOL	6	// WCOL: Write COLlision Flag - not implemented

  54. #define SPI2X	0	// SPI2X: Double SPI Speed Bit

  55. // SPI Data Register ­ SPDR

  56. 

  57. 

  58. class SPCRemulation;

  59. class SPSRemulation;

  60. class SPDRemulation;

  61. 

  62. class SPCRemulation

  63. {

  64. public:

  65. 	inline SPCRemulation & operator = (int val) __attribute__((always_inline)) {

  66. /*

  67. 		uint32_t ctar, mcr, sim6;

  68. 		//serial_print("SPCR=");

  69. 		//serial_phex(val);

  70. 		//serial_print("\n");

  71. 		sim6 = SIM_SCGC6;

  72. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  73. 			//serial_print("init1\n");

  74. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  75. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  76. 		}

  77. 		if (!(val & (1<<SPE))) {

  78. 			SPI0_MCR |= SPI_MCR_MDIS; // TODO: use bitband for atomic access

  79. 		}

  80. 		ctar = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1);

  81. 		if (val & (1<<DORD))  ctar |= SPI_CTAR_LSBFE;

  82. 		if (val & (1<<CPOL))  ctar |= SPI_CTAR_CPOL;

  83. 		if (val & (1<<CPHA)) {

  84. 			ctar |= SPI_CTAR_CPHA;

  85. 			if ((val & 3) == 0) {

  86. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_ASC(1);

  87. 			} else if ((val & 3) == 1) {

  88. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_ASC(4);

  89. 			} else if ((val & 3) == 2) {

  90. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_ASC(6);

  91. 			} else {

  92. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_ASC(7);

  93. 			}

  94. 		} else {

  95. 			if ((val & 3) == 0) {

  96. 				ctar |= SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);

  97. 			} else if ((val & 3) == 1) {

  98. 				ctar |= SPI_CTAR_BR(4) | SPI_CTAR_CSSCK(4);

  99. 			} else if ((val & 3) == 2) {

  100. 				ctar |= SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(6);

  101. 			} else {

  102. 				ctar |= SPI_CTAR_BR(7) | SPI_CTAR_CSSCK(7);

  103. 			}

  104. 		}

  105. 		ctar |= (SPI0_CTAR0 & SPI_CTAR_DBR);

  106. 		update_ctar(ctar);

  107. 		mcr = SPI_MCR_DCONF(0) | SPI_MCR_PCSIS(0x1F);

  108. 		if (val & (1<<MSTR)) mcr |= SPI_MCR_MSTR;

  109. 		if (val & (1<<SPE)) {

  110. 			mcr &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  111. 			SPI0_MCR = mcr;

  112. 			enable_pins();

  113. 		} else {

  114. 			mcr |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  115. 			SPI0_MCR = mcr;

  116. 			disable_pins();

  117. 		}

  118. 		//serial_print("MCR:");

  119. 		//serial_phex32(SPI0_MCR);

  120. 		//serial_print(", CTAR0:");

  121. 		//serial_phex32(SPI0_CTAR0);

  122. 		//serial_print("\n");

  123. */

  124. 		return *this;

  125. 	}

  126. 	inline SPCRemulation & operator |= (int val) __attribute__((always_inline)) {

  127. /*

  128. 		uint32_t sim6;

  129. 		//serial_print("SPCR |= ");

  130. 		//serial_phex(val);

  131. 		//serial_print("\n");

  132. 		sim6 = SIM_SCGC6;

  133. 		if (!(sim6 & SIM_SCGC6_SPI0)) {

  134. 			//serial_print("init2\n");

  135. 			SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;

  136. 			SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);

  137. 		}

  138. 		if (val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  139. 			uint32_t ctar = SPI0_CTAR0;

  140. 			if (val & (1<<DORD)) ctar |= SPI_CTAR_LSBFE; // TODO: use bitband

  141. 			if (val & (1<<CPOL)) ctar |= SPI_CTAR_CPOL;

  142. 			if (val & (1<<CPHA) && !(ctar & SPI_CTAR_CPHA)) {

  143. 				ctar |= SPI_CTAR_CPHA;

  144. 				ctar &= 0xFFFF00FF;

  145. 				ctar |= SPI_CTAR_ASC(ctar & 15);

  146. 			}

  147. 			if ((val & 3) != 0) {

  148. 				uint32_t br = ctar & 15;

  149. 				uint32_t priorval;

  150. 				if (br <= 1) priorval = 0;

  151. 				else if (br <= 4) priorval = 1;

  152. 				else if (br <= 6) priorval = 2;

  153. 				else priorval = 3;

  154. 				uint32_t newval = priorval | (val & 3);

  155. 				if (newval != priorval) {

  156. 					if (newval == 0) br = 1;

  157. 					else if (newval == 0) br = 4;

  158. 					else if (newval == 0) br = 6;

  159. 					else br = 7;

  160. 					ctar &= 0xFFFF00F0; // clear BR, ASC, CSSCK

  161. 					if ((ctar & SPI_CTAR_CPHA)) {

  162. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_ASC(br);

  163. 					} else {

  164. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_CSSCK(br);

  165. 					}

  166. 				}

  167. 			}

  168. 			update_ctar(ctar);

  169. 		}

  170. 		if (val & (1<<MSTR)) SPI0_MCR |= SPI_MCR_MSTR;

  171. 		if (val & (1<<SPE)) {

  172. 			SPI0_MCR &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);

  173. 			enable_pins();

  174. 		}

  175. 		//serial_print("MCR:");

  176. 		//serial_phex32(SPI0_MCR);

  177. 		//serial_print(", CTAR0:");

  178. 		//serial_phex32(SPI0_CTAR0);

  179. 		//serial_print("\n");

  180. */

  181. 		return *this;

  182. 	}

  183. 	inline SPCRemulation & operator &= (int val) __attribute__((always_inline)) {

  184. /*

  185. 		//serial_print("SPCR &= ");

  186. 		//serial_phex(val);

  187. 		//serial_print("\n");

  188. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  189. 		if (!(val & (1<<SPE))) {

  190. 			SPI0_MCR |= (SPI_MCR_MDIS | SPI_MCR_HALT);

  191. 			disable_pins();

  192. 		}

  193. 		if ((val & ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) != ((1<<DORD)|(1<<CPOL)|(1<<CPHA)|3)) {

  194. 			uint32_t ctar = SPI0_CTAR0;

  195. 			if (!(val & (1<<DORD))) ctar &= ~SPI_CTAR_LSBFE; // TODO: use bitband

  196. 			if (!(val & (1<<CPOL))) ctar &= ~SPI_CTAR_CPOL;

  197. 			if (!(val & (1<<CPHA)) && (ctar & SPI_CTAR_CPHA)) {

  198. 				ctar &= ~SPI_CTAR_CPHA;

  199. 				ctar &= 0xFFFF00FF;

  200. 				ctar |= SPI_CTAR_CSSCK(ctar & 15);

  201. 			}

  202. 			if ((val & 3) != 3) {

  203. 				uint32_t br = ctar & 15;

  204. 				uint32_t priorval;

  205. 				if (br <= 1) priorval = 0;

  206. 				else if (br <= 4) priorval = 1;

  207. 				else if (br <= 6) priorval = 2;

  208. 				else priorval = 3;

  209. 				uint32_t newval = priorval & (val & 3);

  210. 				if (newval != priorval) {

  211. 					if (newval == 0) br = 1;

  212. 					else if (newval == 0) br = 4;

  213. 					else if (newval == 0) br = 6;

  214. 					else br = 7;

  215. 					ctar &= 0xFFFF00F0; // clear BR, ASC, CSSCK

  216. 					if ((ctar & SPI_CTAR_CPHA)) {

  217. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_ASC(br);

  218. 					} else {

  219. 						ctar |= SPI_CTAR_BR(br) | SPI_CTAR_CSSCK(br);

  220. 					}

  221. 				}

  222. 			}

  223. 			update_ctar(ctar);

  224. 		}

  225. 		if (!(val & (1<<MSTR))) SPI0_MCR &= ~SPI_MCR_MSTR;

  226. */

  227. 		return *this;

  228. 	}

  229. 	inline int operator & (int val) const __attribute__((always_inline)) {

  230. 		int ret = 0;

  231. /*		

  232. 		//serial_print("SPCR & ");

  233. 		//serial_phex(val);

  234. 		//serial_print("\n");

  235. 		SIM_SCGC6 |= SIM_SCGC6_SPI0;

  236. 		if ((val & (1<<DORD)) && (SPI0_CTAR0 & SPI_CTAR_LSBFE)) ret |= (1<<DORD);

  237. 		if ((val & (1<<CPOL)) && (SPI0_CTAR0 & SPI_CTAR_CPOL)) ret |= (1<<CPOL);

  238. 		if ((val & (1<<CPHA)) && (SPI0_CTAR0 & SPI_CTAR_CPHA)) ret |= (1<<CPHA);

  239. 		if ((val & 3) != 0) {

  240. 			uint32_t dbr = SPI0_CTAR0 & 15;

  241. 			uint32_t spr10;

  242. 			if (dbr <= 1) {

  243. 				spr10 = 0;

  244. 			} else if (dbr <= 4) {

  245. 				spr10 |= (1<<SPR0);

  246. 			} else if (dbr <= 6) {

  247. 				spr10 |= (1<<SPR1);

  248. 			} else {

  249. 				spr10 |= (1<<SPR1)|(1<<SPR0);

  250. 			}

  251. 			ret |= spr10 & (val & 3);

  252. 		}

  253. 		if (val & (1<<SPE) && (!(SPI0_MCR & SPI_MCR_MDIS))) ret |= (1<<SPE);

  254. 		if (val & (1<<MSTR) && (SPI0_MCR & SPI_MCR_MSTR)) ret |= (1<<MSTR);

  255. 		//serial_print("ret = ");

  256. 		//serial_phex(ret);

  257. 		//serial_print("\n");

  258. */

  259. 		return ret;

  260. 	}

  261. 	operator int () const __attribute__((always_inline)) {

  262. 		int ret = 0;

  263. /*		

  264. 		if ((SIM_SCGC6 & SIM_SCGC6_SPI0)) {

  265. 			int ctar = SPI0_CTAR0;

  266. 			if (ctar & SPI_CTAR_LSBFE) ret |= (1<<DORD);

  267. 			if (ctar & SPI_CTAR_CPOL) ret |= (1<<CPOL);

  268. 			if (ctar & SPI_CTAR_CPHA) ret |= (1<<CPHA);

  269. 			ctar &= 15;

  270. 			if (ctar <= 1) {

  271. 			} else if (ctar <= 4) {

  272. 				ret |= (1<<SPR0);

  273. 			} else if (ctar <= 6) {

  274. 				ret |= (1<<SPR1);

  275. 			} else {

  276. 				ret |= (1<<SPR1)|(1<<SPR0);

  277. 			}

  278. 			int mcr = SPI0_MCR;

  279. 			if (!(mcr & SPI_MCR_MDIS)) ret |= (1<<SPE);

  280. 			if (mcr & SPI_MCR_MSTR) ret |= (1<<MSTR);

  281. 		}

  282. */

  283. 		return ret;

  284. 	}

  285. 	inline void setMOSI(uint8_t pin) __attribute__((always_inline)) {

  286. 	}

  287. 	inline void setMOSI_soft(uint8_t pin) __attribute__((always_inline)) {

  288. 	}

  289. 	inline void setMISO(uint8_t pin) __attribute__((always_inline)) {

  290. 	}

  291. 	inline void setSCK(uint8_t pin) __attribute__((always_inline)) {

  292. 	}

  293. 	friend class SPSRemulation;

  294. 	friend class SPIFIFOclass;

  295. private:

  296. 	static uint8_t pinout;

  297. public:

  298. 	inline void enable_pins(void) __attribute__((always_inline)) {

  299. 		//serial_print("enable_pins\n");

  300. 	}

  301. 	inline void disable_pins(void) __attribute__((always_inline)) {

  302. 	}

  303. };

  304. extern SPCRemulation SPCR;

  305. 

  306. 

  307. class SPSRemulation

  308. {

  309. public:

  310. 	inline SPSRemulation & operator = (int val) __attribute__((always_inline)) {

  311. 		//serial_print("SPSR=");

  312. 		//serial_phex(val);

  313. 		//serial_print("\n");

  314. /*

  315. 		uint32_t ctar = SPI0_CTAR0;

  316. 		if (val & (1<<SPI2X)) {

  317. 			ctar |= SPI_CTAR_DBR;

  318. 		} else {

  319. 			ctar &= ~SPI_CTAR_DBR;

  320. 		}

  321. 		SPCRemulation::update_ctar(ctar);

  322. 		//serial_print("MCR:");

  323. 		//serial_phex32(SPI0_MCR);

  324. 		//serial_print(", CTAR0:");

  325. 		//serial_phex32(SPI0_CTAR0);

  326. 		//serial_print("\n");

  327. */		

  328. 		return *this;

  329. 	}

  330. 	inline SPSRemulation & operator |= (int val) __attribute__((always_inline)) {

  331. /*

  332. 		//serial_print("SPSR |= ");

  333. 		//serial_phex(val);

  334. 		//serial_print("\n");

  335. 		if (val & (1<<SPI2X)) SPCRemulation::update_ctar(SPI0_CTAR0 |= SPI_CTAR_DBR);

  336. */

  337. 		return *this;

  338. 	}

  339. 	inline SPSRemulation & operator &= (int val) __attribute__((always_inline)) {

  340. /*

  341. 		//serial_print("SPSR &= ");

  342. 		//serial_phex(val);

  343. 		//serial_print("\n");

  344. 		if (!(val & (1<<SPI2X))) SPCRemulation::update_ctar(SPI0_CTAR0 &= ~SPI_CTAR_DBR);

  345. */

  346. 		return *this;

  347. 	}

  348. 	inline int operator & (int val) const __attribute__((always_inline)) {

  349. 		int ret = 0;

  350. 		//serial_print("SPSR & ");

  351. 		//serial_phex(val);

  352. 		//serial_print("\n");

  353. 		// TODO: using SPI_SR_TCF isn't quite right.  Control returns to the

  354. 		// caller after the final edge that captures data, which is 1/2 cycle

  355. 		// sooner than AVR returns.  At 500 kHz and slower SPI, this can make

  356. 		// a difference when digitalWrite is used to manually control the CS

  357. 		// pin, and perhaps it could matter at high clocks if faster register

  358. 		// access is used?  But does it really matter?  Do any SPI chips in

  359. 		// practice really perform differently if CS negates early, after the

  360. 		// final bit is clocked, but before the end of the whole clock cycle?

  361. 		if ((val & (1<<SPIF)) && ((LPSPI4_RSR & LPSPI_RSR_RXEMPTY) == 0)) ret = (1<<SPIF);

  362. 		//if ((val & (1<<SPI2X)) && (SPI0_CTAR0 & SPI_CTAR_DBR)) ret |= (1<<SPI2X);

  363. 		//delayMicroseconds(50000);

  364. 		return ret;

  365. 	}

  366. 	operator int () const __attribute__((always_inline)) {

  367. 		int ret = 0;

  368. 		//serial_print("SPSR (int)\n");

  369. 		if ((LPSPI4_RSR & LPSPI_RSR_RXEMPTY) == 0) ret = (1<<SPIF);

  370. 		//if (SPI0_CTAR0 & SPI_CTAR_DBR) ret |= (1<<SPI2X);

  371. 		return ret;

  372. 	}

  373. };

  374. extern SPSRemulation SPSR;

  375. 

  376. class SPDRemulation

  377. {

  378. public:

  379. 	inline SPDRemulation & operator = (int val) __attribute__((always_inline)) {

  380. 		//serial_print("SPDR = ");

  381. 		//serial_phex(val);

  382. 		//serial_print("\n");

  383. 		LPSPI4_CR = LPSPI_CR_RRF | LPSPI_CR_MEN;	// Module enabled anc clear the receive. 

  384. 		LPSPI4_TDR = (val & 255);

  385. 		return *this;

  386. 	}

  387. 	operator int () const __attribute__((always_inline)) {

  388. 		uint32_t val;

  389. 		val = LPSPI4_RDR & 255;

  390. 		return val;

  391. 	}

  392. };

  393. extern SPDRemulation SPDR;

  394. 

  395. 

  396. #endif // __cplusplus

  397. 

  398. #endif