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teensy-cores/teensy4/imxrt.h

9379 line
464KB
原始文件 Blame 歷史記錄 

  1. #pragma once

  2. #include <stdint.h>

  3. 

  4. // Definitions based these documents:

  5. //   i.MX RT1060 Reference Manual, Rev. 2, 12/2019 - https://www.pjrc.com/teensy/datasheets.html

  6. //   ARM v7-M Architecture Reference Manual (DDI 0403E.b)

  7. 

  8. enum IRQ_NUMBER_t {

  9.         IRQ_DMA_CH0 =           0,

  10.         IRQ_DMA_CH1 =           1,

  11.         IRQ_DMA_CH2 =           2,

  12.         IRQ_DMA_CH3 =           3,

  13.         IRQ_DMA_CH4 =           4,

  14.         IRQ_DMA_CH5 =           5,

  15.         IRQ_DMA_CH6 =           6,

  16.         IRQ_DMA_CH7 =           7,

  17.         IRQ_DMA_CH8 =           8,

  18.         IRQ_DMA_CH9 =           9,

  19.         IRQ_DMA_CH10 =          10,

  20.         IRQ_DMA_CH11 =          11,

  21.         IRQ_DMA_CH12 =          12,

  22.         IRQ_DMA_CH13 =          13,

  23.         IRQ_DMA_CH14 =          14,

  24.         IRQ_DMA_CH15 =          15,

  25.         IRQ_DMA_ERROR =         16,

  26.         IRQ_CTI0 =              17,

  27.         IRQ_CTI1 =              18,

  28.         IRQ_CORE_ERROR =        19, // TODO - name?

  29.         IRQ_LPUART1 =           20,

  30.         IRQ_LPUART2 =           21,

  31.         IRQ_LPUART3 =           22,

  32.         IRQ_LPUART4 =           23,

  33.         IRQ_LPUART5 =           24,

  34.         IRQ_LPUART6 =           25,

  35.         IRQ_LPUART7 =           26,

  36.         IRQ_LPUART8 =           27,

  37.         IRQ_LPI2C1 =            28,

  38.         IRQ_LPI2C2 =            29,

  39.         IRQ_LPI2C3 =            30,

  40.         IRQ_LPI2C4 =            31,

  41.         IRQ_LPSPI1 =            32,

  42.         IRQ_LPSPI2 =            33,

  43.         IRQ_LPSPI3 =            34,

  44.         IRQ_LPSPI4 =            35,

  45.         IRQ_CAN1 =              36,

  46.         IRQ_CAN2 =              37,

  47.         IRQ_ADDR_ERR =          38, // TODO: name?

  48.         IRQ_KPP =               39,

  49.         IRQ_TSC_DIG =           40,

  50.         IRQ_GPR_IRQ =           41,

  51.         IRQ_LCDIF =             42,

  52.         IRQ_CSI =               43,

  53.         IRQ_PXP =               44,

  54.         IRQ_WDOG2 =             45,

  55.         IRQ_SNVS_IRQ =          46,

  56.         IRQ_SNVS_SECURITY =     47,

  57.         IRQ_SNVS_ONOFF =        48,

  58.         IRQ_CSU =               49,

  59.         IRQ_DCP0 =              50, // TODO: ???

  60.         IRQ_DCP1 =              51, // TODO: ???

  61.         IRQ_DCP2 =              52, // TODO: ???

  62.         IRQ_TRNG =              53,

  63.         IRQ_SJC_IRQ =           54,

  64.         IRQ_BEE =               55,

  65.         IRQ_SAI1 =              56,

  66.         IRQ_SAI2 =              57,

  67.         IRQ_SAI3_RX =           58,

  68.         IRQ_SAI3_TX =           59,

  69.         IRQ_SPDIF =             60,

  70.         IRQ_BROWNOUT0 =         61,

  71.         IRQ_Reserved1 =         62,

  72.         IRQ_TEMPERATURE =       63,

  73.         IRQ_TEMPERATURE_PANIC = 64,

  74.         IRQ_USBPHY0 =           65,

  75.         IRQ_USBPHY1 =           66,

  76.         IRQ_ADC1 =              67,

  77.         IRQ_ADC2 =              68,

  78.         IRQ_DCDC =              69,

  79.         IRQ_SOFTWARE =          70,

  80.         IRQ_Reserved2 =         71,

  81.         IRQ_GPIO1_INT0 =        72,

  82.         IRQ_GPIO1_INT1 =        73,

  83.         IRQ_GPIO1_INT2 =        74,

  84.         IRQ_GPIO1_INT3 =        75,

  85.         IRQ_GPIO1_INT4 =        76,

  86.         IRQ_GPIO1_INT5 =        77,

  87.         IRQ_GPIO1_INT6 =        78,

  88.         IRQ_GPIO1_INT7 =        79,

  89.         IRQ_GPIO1_0_15 =        80,

  90.         IRQ_GPIO1_16_31 =       81,

  91.         IRQ_GPIO2_0_15 =        82,

  92.         IRQ_GPIO2_16_31 =       83,

  93.         IRQ_GPIO3_0_15 =        84,

  94.         IRQ_GPIO3_16_31 =       85,

  95.         IRQ_GPIO4_0_15 =        86,

  96.         IRQ_GPIO4_16_31 =       87,

  97.         IRQ_GPIO5_0_15 =        88,

  98.         IRQ_GPIO5_16_31 =       89,

  99.         IRQ_FLEXIO1 =           90,

  100.         IRQ_FLEXIO2 =           91,

  101.         IRQ_WDOG1 =             92,

  102.         IRQ_RTWDOG =            93,

  103.         IRQ_EWM =               94,

  104.         IRQ_CCM1 =              95,

  105.         IRQ_CCM2 =              96,

  106.         IRQ_GPC =               97,

  107.         IRQ_SRC =               98,

  108.         IRQ_Reserved3 =         99,

  109.         IRQ_GPT1 =              100,

  110.         IRQ_GPT2 =              101,

  111.         IRQ_FLEXPWM1_0 =        102,

  112.         IRQ_FLEXPWM1_1 =        103,

  113.         IRQ_FLEXPWM1_2 =        104,

  114.         IRQ_FLEXPWM1_3 =        105,

  115.         IRQ_FLEXPWM1_FAULT =    106,

  116.         IRQ_FLEXSPI2 =          107, // RT1060 only

  117.         IRQ_FLEXSPI =           108,

  118.         IRQ_SEMC =              109,

  119.         IRQ_SDHC1 =             110,

  120.         IRQ_SDHC2 =             111,

  121.         IRQ_USB2 =              112,

  122.         IRQ_USB1 =              113,

  123.         IRQ_ENET =              114,

  124.         IRQ_ENET_TIMER =        115,

  125.         IRQ_XBAR1_01 =          116,

  126.         IRQ_XBAR1_23 =          117,

  127.         IRQ_ADC_ETC0 =          118,

  128.         IRQ_ADC_ETC1 =          119,

  129.         IRQ_ADC_ETC2 =          120,

  130.         IRQ_ADC_ETC_ERR =       121,

  131.         IRQ_PIT =               122,

  132.         IRQ_ACMP1 =             123,

  133.         IRQ_ACMP2 =             124,

  134.         IRQ_ACMP3 =             125,

  135.         IRQ_ACMP4 =             126,

  136.         IRQ_Reserved4 =         127,

  137.         IRQ_Reserved5 =         128,

  138.         IRQ_ENC1 =              129,

  139.         IRQ_ENC2 =              130,

  140.         IRQ_ENC3 =              131,

  141.         IRQ_ENC4 =              132,

  142.         IRQ_QTIMER1 =           133,

  143.         IRQ_QTIMER2 =           134,

  144.         IRQ_QTIMER3 =           135,

  145.         IRQ_QTIMER4 =           136,

  146.         IRQ_FLEXPWM2_0 =        137,

  147.         IRQ_FLEXPWM2_1 =        138,

  148.         IRQ_FLEXPWM2_2 =        139,

  149.         IRQ_FLEXPWM2_3 =        140,

  150.         IRQ_FLEXPWM2_FAULT =    141,

  151.         IRQ_FLEXPWM3_0 =        142,

  152.         IRQ_FLEXPWM3_1 =        143,

  153.         IRQ_FLEXPWM3_2 =        144,

  154.         IRQ_FLEXPWM3_3 =        145,

  155.         IRQ_FLEXPWM3_FAULT =    146,

  156.         IRQ_FLEXPWM4_0 =        147,

  157.         IRQ_FLEXPWM4_1 =        148,

  158.         IRQ_FLEXPWM4_2 =        149,

  159.         IRQ_FLEXPWM4_3 =        150,

  160.         IRQ_FLEXPWM4_FAULT =    151,

  161.         IRQ_ENET2 =             152, // RT1060 only

  162.         IRQ_ENET2_TIMER =       153, // RT1060 only

  163.         IRQ_CAN3 =              154, // RT1060 only

  164.         IRQ_Reserved6 =         155,

  165.         IRQ_FLEXIO3 =           156, // RT1060 only

  166.         IRQ_GPIO6789 =          157, // RT1060 only

  167.         IRQ_SJC_DEBUG =         158,

  168.         IRQ_NMI_WAKEUP =        159

  169. };

  170. #define NVIC_NUM_INTERRUPTS     160

  171. #define DMA_NUM_CHANNELS        32

  172. 

  173. #ifdef __cplusplus

  174. extern "C" void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);

  175. static inline void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void)) __attribute__((always_inline, unused));

  176. static inline void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void)) { _VectorsRam[irq + 16] = function; asm volatile("": : :"memory"); }

  177. #else

  178. extern void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void);

  179. static inline void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void)) __attribute__((always_inline, unused));

  180. static inline void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void)) { _VectorsRam[irq + 16] = function; asm volatile("": : :"memory"); }

  181. #endif

  182. 

  183. 

  184. #define DMAMUX_SOURCE_FLEXIO1_REQUEST0		0

  185. #define DMAMUX_SOURCE_FLEXIO1_REQUEST1		0

  186. #define DMAMUX_SOURCE_FLEXIO2_REQUEST0		1

  187. #define DMAMUX_SOURCE_FLEXIO2_REQUEST1		1

  188. #define DMAMUX_SOURCE_LPUART1_TX		2

  189. #define DMAMUX_SOURCE_LPUART1_RX		3

  190. #define DMAMUX_SOURCE_LPUART3_TX		4

  191. #define DMAMUX_SOURCE_LPUART3_RX		5

  192. #define DMAMUX_SOURCE_LPUART5_TX		6

  193. #define DMAMUX_SOURCE_LPUART5_RX		7

  194. #define DMAMUX_SOURCE_LPUART7_TX		8

  195. #define DMAMUX_SOURCE_LPUART7_RX		9

  196. #define DMAMUX_SOURCE_FLEXCAN3			11

  197. #define DMAMUX_SOURCE_CSI			12

  198. #define DMAMUX_SOURCE_LPSPI1_RX			13

  199. #define DMAMUX_SOURCE_LPSPI1_TX			14

  200. #define DMAMUX_SOURCE_LPSPI3_RX			15

  201. #define DMAMUX_SOURCE_LPSPI3_TX			16

  202. #define DMAMUX_SOURCE_LPI2C1			17

  203. #define DMAMUX_SOURCE_LPI2C3			18

  204. #define DMAMUX_SOURCE_SAI1_RX			19

  205. #define DMAMUX_SOURCE_SAI1_TX			20

  206. #define DMAMUX_SOURCE_SAI2_RX			21

  207. #define DMAMUX_SOURCE_SAI2_TX			22

  208. #define DMAMUX_SOURCE_ADC_ETC			23

  209. #define DMAMUX_SOURCE_ADC1			24

  210. #define DMAMUX_SOURCE_ACMP1			25

  211. #define DMAMUX_SOURCE_ACMP3			26

  212. #define DMAMUX_SOURCE_FLEXSPI_RX		28

  213. #define DMAMUX_SOURCE_FLEXSPI_TX		29

  214. #define DMAMUX_SOURCE_XBAR1_0			30

  215. #define DMAMUX_SOURCE_XBAR1_1			31

  216. #define DMAMUX_SOURCE_FLEXPWM1_READ0		32

  217. #define DMAMUX_SOURCE_FLEXPWM1_READ1		33

  218. #define DMAMUX_SOURCE_FLEXPWM1_READ2		34

  219. #define DMAMUX_SOURCE_FLEXPWM1_READ3		35

  220. #define DMAMUX_SOURCE_FLEXPWM1_WRITE0		36

  221. #define DMAMUX_SOURCE_FLEXPWM1_WRITE1		37

  222. #define DMAMUX_SOURCE_FLEXPWM1_WRITE2		38

  223. #define DMAMUX_SOURCE_FLEXPWM1_WRITE3		39

  224. #define DMAMUX_SOURCE_FLEXPWM3_READ0		40

  225. #define DMAMUX_SOURCE_FLEXPWM3_READ1		41

  226. #define DMAMUX_SOURCE_FLEXPWM3_READ2		42

  227. #define DMAMUX_SOURCE_FLEXPWM3_READ3		43

  228. #define DMAMUX_SOURCE_FLEXPWM3_WRITE0		44

  229. #define DMAMUX_SOURCE_FLEXPWM3_WRITE1		45

  230. #define DMAMUX_SOURCE_FLEXPWM3_WRITE2		46

  231. #define DMAMUX_SOURCE_FLEXPWM3_WRITE3		47

  232. #define DMAMUX_SOURCE_QTIMER1_READ0		48

  233. #define DMAMUX_SOURCE_QTIMER1_READ1		49

  234. #define DMAMUX_SOURCE_QTIMER1_READ2		50

  235. #define DMAMUX_SOURCE_QTIMER1_READ3		51

  236. #define DMAMUX_SOURCE_QTIMER1_WRITE0_CMPLD1	52

  237. #define DMAMUX_SOURCE_QTIMER1_WRITE1_CMPLD1	53

  238. #define DMAMUX_SOURCE_QTIMER1_WRITE2_CMPLD1	54

  239. #define DMAMUX_SOURCE_QTIMER1_WRITE3_CMPLD1	55

  240. #define DMAMUX_SOURCE_QTIMER1_WRITE1_CMPLD2	52

  241. #define DMAMUX_SOURCE_QTIMER1_WRITE0_CMPLD2	53

  242. #define DMAMUX_SOURCE_QTIMER1_WRITE3_CMPLD2	54

  243. #define DMAMUX_SOURCE_QTIMER1_WRITE2_CMPLD2	55

  244. #define DMAMUX_SOURCE_QTIMER3_READ0		56

  245. #define DMAMUX_SOURCE_QTIMER3_READ1		57

  246. #define DMAMUX_SOURCE_QTIMER3_READ2		58

  247. #define DMAMUX_SOURCE_QTIMER3_READ3		59

  248. #define DMAMUX_SOURCE_QTIMER3_WRITE0_CMPLD1	56

  249. #define DMAMUX_SOURCE_QTIMER3_WRITE1_CMPLD1	57

  250. #define DMAMUX_SOURCE_QTIMER3_WRITE2_CMPLD1	58

  251. #define DMAMUX_SOURCE_QTIMER3_WRITE3_CMPLD1	59

  252. #define DMAMUX_SOURCE_QTIMER3_WRITE1_CMPLD2	56

  253. #define DMAMUX_SOURCE_QTIMER3_WRITE0_CMPLD2	57

  254. #define DMAMUX_SOURCE_QTIMER3_WRITE3_CMPLD2	58

  255. #define DMAMUX_SOURCE_QTIMER3_WRITE2_CMPLD2	59

  256. #define DMAMUX_SOURCE_FLEXSPI2_RX		60

  257. #define DMAMUX_SOURCE_FLEXSPI2_TX		61

  258. #define DMAMUX_SOURCE_FLEXIO1_REQUEST2		64

  259. #define DMAMUX_SOURCE_FLEXIO1_REQUEST3		64

  260. #define DMAMUX_SOURCE_FLEXIO2_REQUEST2		65

  261. #define DMAMUX_SOURCE_FLEXIO2_REQUEST3		65

  262. #define DMAMUX_SOURCE_LPUART2_TX		66

  263. #define DMAMUX_SOURCE_LPUART2_RX		67

  264. #define DMAMUX_SOURCE_LPUART4_TX		68

  265. #define DMAMUX_SOURCE_LPUART4_RX		69

  266. #define DMAMUX_SOURCE_LPUART6_TX                70

  267. #define DMAMUX_SOURCE_LPUART6_RX		71

  268. #define DMAMUX_SOURCE_LPUART8_TX		72

  269. #define DMAMUX_SOURCE_LPUART8_RX		73

  270. #define DMAMUX_SOURCE_PXP			75

  271. #define DMAMUX_SOURCE_LCDIF			76

  272. #define DMAMUX_SOURCE_LPSPI2_RX			77

  273. #define DMAMUX_SOURCE_LPSPI2_TX			78

  274. #define DMAMUX_SOURCE_LPSPI4_RX			79

  275. #define DMAMUX_SOURCE_LPSPI4_TX			80

  276. #define DMAMUX_SOURCE_LPI2C2			81

  277. #define DMAMUX_SOURCE_LPI2C4			82

  278. #define DMAMUX_SOURCE_SAI3_RX			83

  279. #define DMAMUX_SOURCE_SAI3_TX			84

  280. #define DMAMUX_SOURCE_SPDIF_RX			85

  281. #define DMAMUX_SOURCE_SPDIF_TX			86

  282. #define DMAMUX_SOURCE_ADC2			88

  283. #define DMAMUX_SOURCE_ACMP2			89

  284. #define DMAMUX_SOURCE_ACMP4			90

  285. #define DMAMUX_SOURCE_ENET1_TIMER0		92

  286. #define DMAMUX_SOURCE_ENET1_TIMER1		93

  287. #define DMAMUX_SOURCE_XBAR1_2			94

  288. #define DMAMUX_SOURCE_XBAR1_3			95

  289. #define DMAMUX_SOURCE_FLEXPWM2_READ0		96

  290. #define DMAMUX_SOURCE_FLEXPWM2_READ1		97

  291. #define DMAMUX_SOURCE_FLEXPWM2_READ2		98

  292. #define DMAMUX_SOURCE_FLEXPWM2_READ3		99

  293. #define DMAMUX_SOURCE_FLEXPWM2_WRITE0		100

  294. #define DMAMUX_SOURCE_FLEXPWM2_WRITE1		101

  295. #define DMAMUX_SOURCE_FLEXPWM2_WRITE2		102

  296. #define DMAMUX_SOURCE_FLEXPWM2_WRITE3		103

  297. #define DMAMUX_SOURCE_FLEXPWM4_READ0		104

  298. #define DMAMUX_SOURCE_FLEXPWM4_READ1		105

  299. #define DMAMUX_SOURCE_FLEXPWM4_READ2		106

  300. #define DMAMUX_SOURCE_FLEXPWM4_READ3		107

  301. #define DMAMUX_SOURCE_FLEXPWM4_WRITE0		108

  302. #define DMAMUX_SOURCE_FLEXPWM4_WRITE1		109

  303. #define DMAMUX_SOURCE_FLEXPWM4_WRITE2		110

  304. #define DMAMUX_SOURCE_FLEXPWM4_WRITE3		111

  305. #define DMAMUX_SOURCE_QTIMER2_READ0		112

  306. #define DMAMUX_SOURCE_QTIMER2_READ1		113

  307. #define DMAMUX_SOURCE_QTIMER2_READ2		114

  308. #define DMAMUX_SOURCE_QTIMER2_READ3		115

  309. #define DMAMUX_SOURCE_QTIMER2_WRITE0_CMPLD1	116

  310. #define DMAMUX_SOURCE_QTIMER2_WRITE1_CMPLD1	117

  311. #define DMAMUX_SOURCE_QTIMER2_WRITE2_CMPLD1	118

  312. #define DMAMUX_SOURCE_QTIMER2_WRITE3_CMPLD1	119

  313. #define DMAMUX_SOURCE_QTIMER2_WRITE1_CMPLD2	116

  314. #define DMAMUX_SOURCE_QTIMER2_WRITE0_CMPLD2	117

  315. #define DMAMUX_SOURCE_QTIMER2_WRITE3_CMPLD2	118

  316. #define DMAMUX_SOURCE_QTIMER2_WRITE2_CMPLD2	119

  317. #define DMAMUX_SOURCE_QTIMER4_READ0		120

  318. #define DMAMUX_SOURCE_QTIMER4_READ1		121

  319. #define DMAMUX_SOURCE_QTIMER4_READ2		122

  320. #define DMAMUX_SOURCE_QTIMER4_READ3		123

  321. #define DMAMUX_SOURCE_QTIMER4_WRITE0_CMPLD1	120

  322. #define DMAMUX_SOURCE_QTIMER4_WRITE1_CMPLD1	121

  323. #define DMAMUX_SOURCE_QTIMER4_WRITE2_CMPLD1	122

  324. #define DMAMUX_SOURCE_QTIMER4_WRITE3_CMPLD1	123

  325. #define DMAMUX_SOURCE_QTIMER4_WRITE1_CMPLD2	120

  326. #define DMAMUX_SOURCE_QTIMER4_WRITE0_CMPLD2	121

  327. #define DMAMUX_SOURCE_QTIMER4_WRITE3_CMPLD2	122

  328. #define DMAMUX_SOURCE_QTIMER4_WRITE2_CMPLD2	123

  329. #define DMAMUX_SOURCE_ENET2_TIMER0		124

  330. #define DMAMUX_SOURCE_ENET2_TIMER1		125

  331. 

  332. 

  333. typedef struct {

  334. 	volatile uint32_t offset000;

  335. 	volatile uint32_t offset004;

  336. 	volatile uint32_t offset008;

  337. 	volatile uint32_t offset00C;

  338. 	volatile uint32_t offset010;

  339. 	volatile uint32_t offset014;

  340. 	volatile uint32_t offset018;

  341. 	volatile uint32_t offset01C;

  342. 	volatile uint32_t offset020;

  343. 	volatile uint32_t offset024;

  344. 	volatile uint32_t offset028;

  345. 	volatile uint32_t offset02C;

  346. 	volatile uint32_t offset030;

  347. 	volatile uint32_t offset034;

  348. 	volatile uint32_t offset038;

  349. 	volatile uint32_t offset03C;

  350. 	volatile uint32_t offset040;

  351. 	volatile uint32_t offset044;

  352. 	volatile uint32_t offset048;

  353. 	volatile uint32_t offset04C;

  354. 	volatile uint32_t offset050;

  355. 	volatile uint32_t offset054;

  356. 	volatile uint32_t offset058;

  357. 	volatile uint32_t offset05C;

  358. 	volatile uint32_t offset060;

  359. 	volatile uint32_t offset064;

  360. 	volatile uint32_t offset068;

  361. 	volatile uint32_t offset06C;

  362. 	volatile uint32_t offset070;

  363. 	volatile uint32_t offset074;

  364. 	volatile uint32_t offset078;

  365. 	volatile uint32_t offset07C;

  366. 	volatile uint32_t offset080;

  367. 	volatile uint32_t offset084;

  368. 	volatile uint32_t offset088;

  369. 	volatile uint32_t offset08C;

  370. 	volatile uint32_t offset090;

  371. 	volatile uint32_t offset094;

  372. 	volatile uint32_t offset098;

  373. 	volatile uint32_t offset09C;

  374. 	volatile uint32_t offset0A0;

  375. 	volatile uint32_t offset0A4;

  376. 	volatile uint32_t offset0A8;

  377. 	volatile uint32_t offset0AC;

  378. 	volatile uint32_t offset0B0;

  379. 	volatile uint32_t offset0B4;

  380. 	volatile uint32_t offset0B8;

  381. 	volatile uint32_t offset0BC;

  382. 	volatile uint32_t offset0C0;

  383. 	volatile uint32_t offset0C4;

  384. 	volatile uint32_t offset0C8;

  385. 	volatile uint32_t offset0CC;

  386. 	volatile uint32_t offset0D0;

  387. 	volatile uint32_t offset0D4;

  388. 	volatile uint32_t offset0D8;

  389. 	volatile uint32_t offset0DC;

  390. 	volatile uint32_t offset0E0;

  391. 	volatile uint32_t offset0E4;

  392. 	volatile uint32_t offset0E8;

  393. 	volatile uint32_t offset0EC;

  394. 	volatile uint32_t offset0F0;

  395. 	volatile uint32_t offset0F4;

  396. 	volatile uint32_t offset0F8;

  397. 	volatile uint32_t offset0FC;

  398. 	volatile uint32_t offset100;

  399. 	volatile uint32_t offset104;

  400. 	volatile uint32_t offset108;

  401. 	volatile uint32_t offset10C;

  402. 	volatile uint32_t offset110;

  403. 	volatile uint32_t offset114;

  404. 	volatile uint32_t offset118;

  405. 	volatile uint32_t offset11C;

  406. 	volatile uint32_t offset120;

  407. 	volatile uint32_t offset124;

  408. 	volatile uint32_t offset128;

  409. 	volatile uint32_t offset12C;

  410. 	volatile uint32_t offset130;

  411. 	volatile uint32_t offset134;

  412. 	volatile uint32_t offset138;

  413. 	volatile uint32_t offset13C;

  414. 	volatile uint32_t offset140;

  415. 	volatile uint32_t offset144;

  416. 	volatile uint32_t offset148;

  417. 	volatile uint32_t offset14C;

  418. 	volatile uint32_t offset150;

  419. 	volatile uint32_t offset154;

  420. 	volatile uint32_t offset158;

  421. 	volatile uint32_t offset15C;

  422. 	volatile uint32_t offset160;

  423. 	volatile uint32_t offset164;

  424. 	volatile uint32_t offset168;

  425. 	volatile uint32_t offset16C;

  426. 	volatile uint32_t offset170;

  427. 	volatile uint32_t offset174;

  428. 	volatile uint32_t offset178;

  429. 	volatile uint32_t offset17C;

  430. 	volatile uint32_t offset180;

  431. 	volatile uint32_t offset184;

  432. 	volatile uint32_t offset188;

  433. 	volatile uint32_t offset18C;

  434. 	volatile uint32_t offset190;

  435. 	volatile uint32_t offset194;

  436. 	volatile uint32_t offset198;

  437. 	volatile uint32_t offset19C;

  438. 	volatile uint32_t offset1A0;

  439. 	volatile uint32_t offset1A4;

  440. 	volatile uint32_t offset1A8;

  441. 	volatile uint32_t offset1AC;

  442. 	volatile uint32_t offset1B0;

  443. 	volatile uint32_t offset1B4;

  444. 	volatile uint32_t offset1B8;

  445. 	volatile uint32_t offset1BC;

  446. 	volatile uint32_t offset1C0;

  447. 	volatile uint32_t offset1C4;

  448. 	volatile uint32_t offset1C8;

  449. 	volatile uint32_t offset1CC;

  450. 	volatile uint32_t offset1D0;

  451. 	volatile uint32_t offset1D4;

  452. 	volatile uint32_t offset1D8;

  453. 	volatile uint32_t offset1DC;

  454. 	volatile uint32_t offset1E0;

  455. 	volatile uint32_t offset1E4;

  456. 	volatile uint32_t offset1E8;

  457. 	volatile uint32_t offset1EC;

  458. 	volatile uint32_t offset1F0;

  459. 	volatile uint32_t offset1F4;

  460. 	volatile uint32_t offset1F8;

  461. 	volatile uint32_t offset1FC;

  462. 	volatile uint32_t offset200;

  463. 	volatile uint32_t offset204;

  464. 	volatile uint32_t offset208;

  465. 	volatile uint32_t offset20C;

  466. 	volatile uint32_t offset210;

  467. 	volatile uint32_t offset214;

  468. 	volatile uint32_t offset218;

  469. 	volatile uint32_t offset21C;

  470. 	volatile uint32_t offset220;

  471. 	volatile uint32_t offset224;

  472. 	volatile uint32_t offset228;

  473. 	volatile uint32_t offset22C;

  474. 	volatile uint32_t offset230;

  475. 	volatile uint32_t offset234;

  476. 	volatile uint32_t offset238;

  477. 	volatile uint32_t offset23C;

  478. 	volatile uint32_t offset240;

  479. 	volatile uint32_t offset244;

  480. 	volatile uint32_t offset248;

  481. 	volatile uint32_t offset24C;

  482. 	volatile uint32_t offset250;

  483. 	volatile uint32_t offset254;

  484. 	volatile uint32_t offset258;

  485. 	volatile uint32_t offset25C;

  486. 	volatile uint32_t offset260;

  487. 	volatile uint32_t offset264;

  488. 	volatile uint32_t offset268;

  489. 	volatile uint32_t offset26C;

  490. 	volatile uint32_t offset270;

  491. 	volatile uint32_t offset274;

  492. 	volatile uint32_t offset278;

  493. 	volatile uint32_t offset27C;

  494. 	volatile uint32_t offset280;

  495. 	volatile uint32_t offset284;

  496. 	volatile uint32_t offset288;

  497. 	volatile uint32_t offset28C;

  498. 	volatile uint32_t offset290;

  499. 	volatile uint32_t offset294;

  500. 	volatile uint32_t offset298;

  501. 	volatile uint32_t offset29C;

  502. 	volatile uint32_t offset2A0;

  503. 	volatile uint32_t offset2A4;

  504. 	volatile uint32_t offset2A8;

  505. 	volatile uint32_t offset2AC;

  506. 	volatile uint32_t offset2B0;

  507. 	volatile uint32_t offset2B4;

  508. 	volatile uint32_t offset2B8;

  509. 	volatile uint32_t offset2BC;

  510. 	volatile uint32_t offset2C0;

  511. 	volatile uint32_t offset2C4;

  512. 	volatile uint32_t offset2C8;

  513. 	volatile uint32_t offset2CC;

  514. 	volatile uint32_t offset2D0;

  515. 	volatile uint32_t offset2D4;

  516. 	volatile uint32_t offset2D8;

  517. 	volatile uint32_t offset2DC;

  518. 	volatile uint32_t offset2E0;

  519. 	volatile uint32_t offset2E4;

  520. 	volatile uint32_t offset2E8;

  521. 	volatile uint32_t offset2EC;

  522. 	volatile uint32_t offset2F0;

  523. 	volatile uint32_t offset2F4;

  524. 	volatile uint32_t offset2F8;

  525. 	volatile uint32_t offset2FC;

  526. 	volatile uint32_t offset300;

  527. 	volatile uint32_t offset304;

  528. 	volatile uint32_t offset308;

  529. 	volatile uint32_t offset30C;

  530. 	volatile uint32_t offset310;

  531. 	volatile uint32_t offset314;

  532. 	volatile uint32_t offset318;

  533. 	volatile uint32_t offset31C;

  534. 	volatile uint32_t offset320;

  535. 	volatile uint32_t offset324;

  536. 	volatile uint32_t offset328;

  537. 	volatile uint32_t offset32C;

  538. 	volatile uint32_t offset330;

  539. 	volatile uint32_t offset334;

  540. 	volatile uint32_t offset338;

  541. 	volatile uint32_t offset33C;

  542. 	volatile uint32_t offset340;

  543. 	volatile uint32_t offset344;

  544. 	volatile uint32_t offset348;

  545. 	volatile uint32_t offset34C;

  546. 	volatile uint32_t offset350;

  547. 	volatile uint32_t offset354;

  548. 	volatile uint32_t offset358;

  549. 	volatile uint32_t offset35C;

  550. 	volatile uint32_t offset360;

  551. 	volatile uint32_t offset364;

  552. 	volatile uint32_t offset368;

  553. 	volatile uint32_t offset36C;

  554. 	volatile uint32_t offset370;

  555. 	volatile uint32_t offset374;

  556. 	volatile uint32_t offset378;

  557. 	volatile uint32_t offset37C;

  558. 	volatile uint32_t offset380;

  559. 	volatile uint32_t offset384;

  560. 	volatile uint32_t offset388;

  561. 	volatile uint32_t offset38C;

  562. 	volatile uint32_t offset390;

  563. 	volatile uint32_t offset394;

  564. 	volatile uint32_t offset398;

  565. 	volatile uint32_t offset39C;

  566. 	volatile uint32_t offset3A0;

  567. 	volatile uint32_t offset3A4;

  568. 	volatile uint32_t offset3A8;

  569. 	volatile uint32_t offset3AC;

  570. 	volatile uint32_t offset3B0;

  571. 	volatile uint32_t offset3B4;

  572. 	volatile uint32_t offset3B8;

  573. 	volatile uint32_t offset3BC;

  574. 	volatile uint32_t offset3C0;

  575. 	volatile uint32_t offset3C4;

  576. 	volatile uint32_t offset3C8;

  577. 	volatile uint32_t offset3CC;

  578. 	volatile uint32_t offset3D0;

  579. 	volatile uint32_t offset3D4;

  580. 	volatile uint32_t offset3D8;

  581. 	volatile uint32_t offset3DC;

  582. 	volatile uint32_t offset3E0;

  583. 	volatile uint32_t offset3E4;

  584. 	volatile uint32_t offset3E8;

  585. 	volatile uint32_t offset3EC;

  586. 	volatile uint32_t offset3F0;

  587. 	volatile uint32_t offset3F4;

  588. 	volatile uint32_t offset3F8;

  589. 	volatile uint32_t offset3FC;

  590. } IMXRT_REGISTER32_t;

  591. 

  592. typedef struct {

  593. 	volatile uint16_t offset000;

  594. 	volatile uint16_t offset002;

  595. 	volatile uint16_t offset004;

  596. 	volatile uint16_t offset006;

  597. 	volatile uint16_t offset008;

  598. 	volatile uint16_t offset00A;

  599. 	volatile uint16_t offset00C;

  600. 	volatile uint16_t offset00E;

  601. 	volatile uint16_t offset010;

  602. 	volatile uint16_t offset012;

  603. 	volatile uint16_t offset014;

  604. 	volatile uint16_t offset016;

  605. 	volatile uint16_t offset018;

  606. 	volatile uint16_t offset01A;

  607. 	volatile uint16_t offset01C;

  608. 	volatile uint16_t offset01E;

  609. 	volatile uint16_t offset020;

  610. 	volatile uint16_t offset022;

  611. 	volatile uint16_t offset024;

  612. 	volatile uint16_t offset026;

  613. 	volatile uint16_t offset028;

  614. 	volatile uint16_t offset02A;

  615. 	volatile uint16_t offset02C;

  616. 	volatile uint16_t offset02E;

  617. 	volatile uint16_t offset030;

  618. 	volatile uint16_t offset032;

  619. 	volatile uint16_t offset034;

  620. 	volatile uint16_t offset036;

  621. 	volatile uint16_t offset038;

  622. 	volatile uint16_t offset03A;

  623. 	volatile uint16_t offset03C;

  624. 	volatile uint16_t offset03E;

  625. 	volatile uint16_t offset040;

  626. 	volatile uint16_t offset042;

  627. 	volatile uint16_t offset044;

  628. 	volatile uint16_t offset046;

  629. 	volatile uint16_t offset048;

  630. 	volatile uint16_t offset04A;

  631. 	volatile uint16_t offset04C;

  632. 	volatile uint16_t offset04E;

  633. 	volatile uint16_t offset050;

  634. 	volatile uint16_t offset052;

  635. 	volatile uint16_t offset054;

  636. 	volatile uint16_t offset056;

  637. 	volatile uint16_t offset058;

  638. 	volatile uint16_t offset05A;

  639. 	volatile uint16_t offset05C;

  640. 	volatile uint16_t offset05E;

  641. 	volatile uint16_t offset060;

  642. 	volatile uint16_t offset062;

  643. 	volatile uint16_t offset064;

  644. 	volatile uint16_t offset066;

  645. 	volatile uint16_t offset068;

  646. 	volatile uint16_t offset06A;

  647. 	volatile uint16_t offset06C;

  648. 	volatile uint16_t offset06E;

  649. 	volatile uint16_t offset070;

  650. 	volatile uint16_t offset072;

  651. 	volatile uint16_t offset074;

  652. 	volatile uint16_t offset076;

  653. 	volatile uint16_t offset078;

  654. 	volatile uint16_t offset07A;

  655. 	volatile uint16_t offset07C;

  656. 	volatile uint16_t offset07E;

  657. 	volatile uint16_t offset080;

  658. 	volatile uint16_t offset082;

  659. 	volatile uint16_t offset084;

  660. 	volatile uint16_t offset086;

  661. 	volatile uint16_t offset088;

  662. 	volatile uint16_t offset08A;

  663. 	volatile uint16_t offset08C;

  664. 	volatile uint16_t offset08E;

  665. 	volatile uint16_t offset090;

  666. 	volatile uint16_t offset092;

  667. 	volatile uint16_t offset094;

  668. 	volatile uint16_t offset096;

  669. 	volatile uint16_t offset098;

  670. 	volatile uint16_t offset09A;

  671. 	volatile uint16_t offset09C;

  672. 	volatile uint16_t offset09E;

  673. 	volatile uint16_t offset0A0;

  674. 	volatile uint16_t offset0A2;

  675. 	volatile uint16_t offset0A4;

  676. 	volatile uint16_t offset0A6;

  677. 	volatile uint16_t offset0A8;

  678. 	volatile uint16_t offset0AA;

  679. 	volatile uint16_t offset0AC;

  680. 	volatile uint16_t offset0AE;

  681. 	volatile uint16_t offset0B0;

  682. 	volatile uint16_t offset0B2;

  683. 	volatile uint16_t offset0B4;

  684. 	volatile uint16_t offset0B6;

  685. 	volatile uint16_t offset0B8;

  686. 	volatile uint16_t offset0BA;

  687. 	volatile uint16_t offset0BC;

  688. 	volatile uint16_t offset0BE;

  689. 	volatile uint16_t offset0C0;

  690. 	volatile uint16_t offset0C2;

  691. 	volatile uint16_t offset0C4;

  692. 	volatile uint16_t offset0C6;

  693. 	volatile uint16_t offset0C8;

  694. 	volatile uint16_t offset0CA;

  695. 	volatile uint16_t offset0CC;

  696. 	volatile uint16_t offset0CE;

  697. 	volatile uint16_t offset0D0;

  698. 	volatile uint16_t offset0D2;

  699. 	volatile uint16_t offset0D4;

  700. 	volatile uint16_t offset0D6;

  701. 	volatile uint16_t offset0D8;

  702. 	volatile uint16_t offset0DA;

  703. 	volatile uint16_t offset0DC;

  704. 	volatile uint16_t offset0DE;

  705. 	volatile uint16_t offset0E0;

  706. 	volatile uint16_t offset0E2;

  707. 	volatile uint16_t offset0E4;

  708. 	volatile uint16_t offset0E6;

  709. 	volatile uint16_t offset0E8;

  710. 	volatile uint16_t offset0EA;

  711. 	volatile uint16_t offset0EC;

  712. 	volatile uint16_t offset0EE;

  713. 	volatile uint16_t offset0F0;

  714. 	volatile uint16_t offset0F2;

  715. 	volatile uint16_t offset0F4;

  716. 	volatile uint16_t offset0F6;

  717. 	volatile uint16_t offset0F8;

  718. 	volatile uint16_t offset0FA;

  719. 	volatile uint16_t offset0FC;

  720. 	volatile uint16_t offset0FE;

  721. 	volatile uint16_t offset100;

  722. 	volatile uint16_t offset102;

  723. 	volatile uint16_t offset104;

  724. 	volatile uint16_t offset106;

  725. 	volatile uint16_t offset108;

  726. 	volatile uint16_t offset10A;

  727. 	volatile uint16_t offset10C;

  728. 	volatile uint16_t offset10E;

  729. 	volatile uint16_t offset110;

  730. 	volatile uint16_t offset112;

  731. 	volatile uint16_t offset114;

  732. 	volatile uint16_t offset116;

  733. 	volatile uint16_t offset118;

  734. 	volatile uint16_t offset11A;

  735. 	volatile uint16_t offset11C;

  736. 	volatile uint16_t offset11E;

  737. 	volatile uint16_t offset120;

  738. 	volatile uint16_t offset122;

  739. 	volatile uint16_t offset124;

  740. 	volatile uint16_t offset126;

  741. 	volatile uint16_t offset128;

  742. 	volatile uint16_t offset12A;

  743. 	volatile uint16_t offset12C;

  744. 	volatile uint16_t offset12E;

  745. 	volatile uint16_t offset130;

  746. 	volatile uint16_t offset132;

  747. 	volatile uint16_t offset134;

  748. 	volatile uint16_t offset136;

  749. 	volatile uint16_t offset138;

  750. 	volatile uint16_t offset13A;

  751. 	volatile uint16_t offset13C;

  752. 	volatile uint16_t offset13E;

  753. 	volatile uint16_t offset140;

  754. 	volatile uint16_t offset142;

  755. 	volatile uint16_t offset144;

  756. 	volatile uint16_t offset146;

  757. 	volatile uint16_t offset148;

  758. 	volatile uint16_t offset14A;

  759. 	volatile uint16_t offset14C;

  760. 	volatile uint16_t offset14E;

  761. 	volatile uint16_t offset150;

  762. 	volatile uint16_t offset152;

  763. 	volatile uint16_t offset154;

  764. 	volatile uint16_t offset156;

  765. 	volatile uint16_t offset158;

  766. 	volatile uint16_t offset15A;

  767. 	volatile uint16_t offset15C;

  768. 	volatile uint16_t offset15E;

  769. 	volatile uint16_t offset160;

  770. 	volatile uint16_t offset162;

  771. 	volatile uint16_t offset164;

  772. 	volatile uint16_t offset166;

  773. 	volatile uint16_t offset168;

  774. 	volatile uint16_t offset16A;

  775. 	volatile uint16_t offset16C;

  776. 	volatile uint16_t offset16E;

  777. 	volatile uint16_t offset170;

  778. 	volatile uint16_t offset172;

  779. 	volatile uint16_t offset174;

  780. 	volatile uint16_t offset176;

  781. 	volatile uint16_t offset178;

  782. 	volatile uint16_t offset17A;

  783. 	volatile uint16_t offset17C;

  784. 	volatile uint16_t offset17E;

  785. 	volatile uint16_t offset180;

  786. 	volatile uint16_t offset182;

  787. 	volatile uint16_t offset184;

  788. 	volatile uint16_t offset186;

  789. 	volatile uint16_t offset188;

  790. 	volatile uint16_t offset18A;

  791. 	volatile uint16_t offset18C;

  792. 	volatile uint16_t offset18E;

  793. 	volatile uint16_t offset190;

  794. 	volatile uint16_t offset192;

  795. 	volatile uint16_t offset194;

  796. 	volatile uint16_t offset196;

  797. 	volatile uint16_t offset198;

  798. 	volatile uint16_t offset19A;

  799. 	volatile uint16_t offset19C;

  800. 	volatile uint16_t offset19E;

  801. 	volatile uint16_t offset1A0;

  802. 	volatile uint16_t offset1A2;

  803. 	volatile uint16_t offset1A4;

  804. 	volatile uint16_t offset1A6;

  805. 	volatile uint16_t offset1A8;

  806. 	volatile uint16_t offset1AA;

  807. 	volatile uint16_t offset1AC;

  808. 	volatile uint16_t offset1AE;

  809. 	volatile uint16_t offset1B0;

  810. 	volatile uint16_t offset1B2;

  811. 	volatile uint16_t offset1B4;

  812. 	volatile uint16_t offset1B6;

  813. 	volatile uint16_t offset1B8;

  814. 	volatile uint16_t offset1BA;

  815. 	volatile uint16_t offset1BC;

  816. 	volatile uint16_t offset1BE;

  817. 	volatile uint16_t offset1C0;

  818. 	volatile uint16_t offset1C2;

  819. 	volatile uint16_t offset1C4;

  820. 	volatile uint16_t offset1C6;

  821. 	volatile uint16_t offset1C8;

  822. 	volatile uint16_t offset1CA;

  823. 	volatile uint16_t offset1CC;

  824. 	volatile uint16_t offset1CE;

  825. 	volatile uint16_t offset1D0;

  826. 	volatile uint16_t offset1D2;

  827. 	volatile uint16_t offset1D4;

  828. 	volatile uint16_t offset1D6;

  829. 	volatile uint16_t offset1D8;

  830. 	volatile uint16_t offset1DA;

  831. 	volatile uint16_t offset1DC;

  832. 	volatile uint16_t offset1DE;

  833. 	volatile uint16_t offset1E0;

  834. 	volatile uint16_t offset1E2;

  835. 	volatile uint16_t offset1E4;

  836. 	volatile uint16_t offset1E6;

  837. 	volatile uint16_t offset1E8;

  838. 	volatile uint16_t offset1EA;

  839. 	volatile uint16_t offset1EC;

  840. 	volatile uint16_t offset1EE;

  841. 	volatile uint16_t offset1F0;

  842. 	volatile uint16_t offset1F2;

  843. 	volatile uint16_t offset1F4;

  844. 	volatile uint16_t offset1F6;

  845. 	volatile uint16_t offset1F8;

  846. 	volatile uint16_t offset1FA;

  847. 	volatile uint16_t offset1FC;

  848. 	volatile uint16_t offset1FE;

  849. } IMXRT_REGISTER16_t;

  850. 

  851. typedef struct {

  852. 	volatile uint8_t offset00;

  853. 	volatile uint8_t offset01;

  854. 	volatile uint8_t offset02;

  855. 	volatile uint8_t offset03;

  856. 	volatile uint8_t offset04;

  857. 	volatile uint8_t offset05;

  858. 	volatile uint8_t offset06;

  859. 	volatile uint8_t offset07;

  860. 	volatile uint8_t offset08;

  861. 	volatile uint8_t offset09;

  862. 	volatile uint8_t offset0A;

  863. 	volatile uint8_t offset0B;

  864. 	volatile uint8_t offset0C;

  865. 	volatile uint8_t offset0D;

  866. 	volatile uint8_t offset0E;

  867. 	volatile uint8_t offset0F;

  868. } IMXRT_REGISTER8_t;

  869. 

  870. // 65.3: page 3302

  871. #define IMXRT_CMP1		(*(IMXRT_REGISTER8_t *)0x40094000)

  872. #define CMP1_CR0			(IMXRT_CMP1.offset00)

  873. #define CMP1_CR1			(IMXRT_CMP1.offset01)

  874. #define CMP1_FPR			(IMXRT_CMP1.offset02)

  875. #define CMP1_SCR			(IMXRT_CMP1.offset03)

  876. #define CMP1_DACCR			(IMXRT_CMP1.offset04)

  877. #define CMP1_MUXCR			(IMXRT_CMP1.offset05)

  878. #define IMXRT_CMP2		(*(IMXRT_REGISTER8_t *)0x40094008)

  879. #define CMP2_CR0			(IMXRT_CMP2.offset00)

  880. #define CMP2_CR1			(IMXRT_CMP2.offset01)

  881. #define CMP2_FPR			(IMXRT_CMP2.offset02)

  882. #define CMP2_SCR			(IMXRT_CMP2.offset03)

  883. #define CMP2_DACCR			(IMXRT_CMP2.offset04)

  884. #define CMP2_MUXCR			(IMXRT_CMP2.offset05)

  885. #define IMXRT_CMP3		(*(IMXRT_REGISTER8_t *)0x40094010)

  886. #define CMP3_CR0			(IMXRT_CMP3.offset00)

  887. #define CMP3_CR1			(IMXRT_CMP3.offset01)

  888. #define CMP3_FPR			(IMXRT_CMP3.offset02)

  889. #define CMP3_SCR			(IMXRT_CMP3.offset03)

  890. #define CMP3_DACCR			(IMXRT_CMP3.offset04)

  891. #define CMP3_MUXCR			(IMXRT_CMP3.offset05)

  892. #define IMXRT_CMP4		(*(IMXRT_REGISTER8_t *)0x40094018)

  893. #define CMP4_CR0			(IMXRT_CMP4.offset00)

  894. #define CMP4_CR1			(IMXRT_CMP4.offset01)

  895. #define CMP4_FPR			(IMXRT_CMP4.offset02)

  896. #define CMP4_SCR			(IMXRT_CMP4.offset03)

  897. #define CMP4_DACCR			(IMXRT_CMP4.offset04)

  898. #define CMP4_MUXCR			(IMXRT_CMP4.offset05)

  899. 

  900. // 65.3 page 3302

  901. typedef struct {

  902.         volatile uint32_t HC0;

  903.         volatile uint32_t HC1;

  904.         volatile uint32_t HC2;

  905.         volatile uint32_t HC3;

  906.         volatile uint32_t HC4;

  907.         volatile uint32_t HC5;

  908.         volatile uint32_t HC6;

  909.         volatile uint32_t HC7;

  910.         volatile uint32_t HS; 

  911.         volatile uint32_t R0; 

  912.         volatile uint32_t R1; 

  913.         volatile uint32_t R2; 

  914.         volatile uint32_t R3; 

  915.         volatile uint32_t R4; 

  916.         volatile uint32_t R5; 

  917.         volatile uint32_t R6; 

  918.         volatile uint32_t R7; 

  919.         volatile uint32_t CFG;

  920.         volatile uint32_t GC; 

  921.         volatile uint32_t GS; 

  922.         volatile uint32_t CV; 

  923.         volatile uint32_t OFS;

  924.         volatile uint32_t CAL;

  925. } IMXRT_ADCS_t;

  926. 

  927. 

  928. 

  929. #define IMXRT_ADC1                  (*(IMXRT_ADCS_t *)0x400C4000)

  930. #define IMXRT_ADC1S                 (*(IMXRT_ADCS_t *)0x400C4000)

  931. #define ADC1_HC0			(IMXRT_ADC1.HC0)

  932. #define ADC1_HC1			(IMXRT_ADC1.HC1)

  933. #define ADC1_HC2			(IMXRT_ADC1.HC2)

  934. #define ADC1_HC3			(IMXRT_ADC1.HC3)

  935. #define ADC1_HC4			(IMXRT_ADC1.HC4)

  936. #define ADC1_HC5			(IMXRT_ADC1.HC5)

  937. #define ADC1_HC6			(IMXRT_ADC1.HC6)

  938. #define ADC1_HC7			(IMXRT_ADC1.HC7)

  939. #define ADC1_HS				(IMXRT_ADC1.HS)

  940. #define ADC1_R0				(IMXRT_ADC1.R0)

  941. #define ADC1_R1				(IMXRT_ADC1.R1)

  942. #define ADC1_R2				(IMXRT_ADC1.R2)

  943. #define ADC1_R3				(IMXRT_ADC1.R3)

  944. #define ADC1_R4				(IMXRT_ADC1.R4)

  945. #define ADC1_R5				(IMXRT_ADC1.R5)

  946. #define ADC1_R6				(IMXRT_ADC1.R6)

  947. #define ADC1_R7				(IMXRT_ADC1.R7)

  948. #define ADC1_CFG			(IMXRT_ADC1.CFG)

  949. #define ADC1_GC				(IMXRT_ADC1.GC)

  950. #define ADC1_GS				(IMXRT_ADC1.GS)

  951. #define ADC1_CV				(IMXRT_ADC1.CV)

  952. #define ADC1_OFS			(IMXRT_ADC1.OFS)

  953. #define ADC1_CAL			(IMXRT_ADC1.CAL)

  954. #define IMXRT_ADC2                 (*(IMXRT_ADCS_t *)0x400C8000)

  955. #define IMXRT_ADC2S                (*(IMXRT_ADCS_t *)0x400C8000)

  956. #define ADC2_HC0			(IMXRT_ADC2.HC0)

  957. #define ADC2_HC1			(IMXRT_ADC2.HC1)

  958. #define ADC2_HC2			(IMXRT_ADC2.HC2)

  959. #define ADC2_HC3			(IMXRT_ADC2.HC3)

  960. #define ADC2_HC4			(IMXRT_ADC2.HC4)

  961. #define ADC2_HC5			(IMXRT_ADC2.HC5)

  962. #define ADC2_HC6			(IMXRT_ADC2.HC6)

  963. #define ADC2_HC7			(IMXRT_ADC2.HC7)

  964. #define ADC2_HS				(IMXRT_ADC2.HS)

  965. #define ADC2_R0				(IMXRT_ADC2.R0)

  966. #define ADC2_R1				(IMXRT_ADC2.R1)

  967. #define ADC2_R2				(IMXRT_ADC2.R2)

  968. #define ADC2_R3				(IMXRT_ADC2.R3)

  969. #define ADC2_R4				(IMXRT_ADC2.R4)

  970. #define ADC2_R5				(IMXRT_ADC2.R5)

  971. #define ADC2_R6				(IMXRT_ADC2.R6)

  972. #define ADC2_R7				(IMXRT_ADC2.R7)

  973. #define ADC2_CFG			(IMXRT_ADC2.CFG)

  974. #define ADC2_GC				(IMXRT_ADC2.GC)

  975. #define ADC2_GS				(IMXRT_ADC2.GS)

  976. #define ADC2_CV				(IMXRT_ADC2.CV)

  977. #define ADC2_OFS			(IMXRT_ADC2.OFS)

  978. #define ADC2_CAL			(IMXRT_ADC2.CAL)

  979. #define ADC_HC_AIEN				((uint32_t)(1<<7))

  980. #define ADC_HC_ADCH(n)				((uint32_t)(((n) & 0x1F) << 0))

  981. #define ADC_HS_COCO0				((uint32_t)(1<<0))

  982. #define ADC_CFG_OVWREN				((uint32_t)(1<<16))

  983. #define ADC_CFG_AVGS(n)				((uint32_t)(((n) & 0x03) << 14))

  984. #define ADC_CFG_ADTRG				((uint32_t)(1<<13))

  985. #define ADC_CFG_REFSEL(n)			((uint32_t)(((n) & 0x03) << 11))

  986. #define ADC_CFG_ADHSC				((uint32_t)(1<<10))

  987. #define ADC_CFG_ADSTS(n)			((uint32_t)(((n) & 0x03) << 8))

  988. #define ADC_CFG_ADLPC				((uint32_t)(1<<7))

  989. #define ADC_CFG_ADIV(n)				((uint32_t)(((n) & 0x03) << 5))

  990. #define ADC_CFG_ADLSMP				((uint32_t)(1<<4))

  991. #define ADC_CFG_MODE(n)				((uint32_t)(((n) & 0x03) << 2))

  992. #define ADC_CFG_ADICLK(n)			((uint32_t)(((n) & 0x03) << 0))

  993. #define ADC_GC_CAL				((uint32_t)(1<<7))

  994. #define ADC_GC_ADCO				((uint32_t)(1<<6))

  995. #define ADC_GC_AVGE				((uint32_t)(1<<5))

  996. #define ADC_GC_ACFE				((uint32_t)(1<<4))

  997. #define ADC_GC_ACFGT				((uint32_t)(1<<3))

  998. #define ADC_GC_ACREN				((uint32_t)(1<<2))

  999. #define ADC_GC_DMAEN				((uint32_t)(1<<1))

  1000. #define ADC_GC_ADACKEN				((uint32_t)(1<<0))

  1001. #define ADC_GS_AWKST				((uint32_t)(1<<2))

  1002. #define ADC_GS_CALF				((uint32_t)(1<<1))

  1003. #define ADC_GS_ADACT				((uint32_t)(1<<0))

  1004. #define ADC_CV_CV2(n)				((uint32_t)(((n) & 0xFFF) << 16))

  1005. #define ADC_CV_CV1(n)				((uint32_t)(((n) & 0xFFF) << 0))

  1006. #define ADC_OFS_SIGN				((uint32_t)(1<<12))

  1007. #define ADC_OFS_OFS(n)				((uint32_t)(((n) & 0xFFF) << 0))

  1008. #define ADC_CAL_CAL_CODE(n)			((uint32_t)(((n) & 0x0F) << 0))

  1009. 

  1010. // 66.5.1 Page 3504

  1011. typedef struct {

  1012.   volatile uint32_t CTRL;              // offset 0

  1013.   volatile uint32_t DONE0_1_IRQ;       // offset004

  1014.   volatile uint32_t DONE2_ERR_IRQ;     // offset008

  1015.   volatile uint32_t DMA_CTRL;          // offset00C

  1016.   struct {

  1017.     volatile uint32_t CTRL;            //offset010

  1018.     volatile uint32_t COUNTER;         //offset014

  1019.     volatile uint32_t CHAIN_1_0;

  1020.     volatile uint32_t CHAIN_3_2;

  1021.     volatile uint32_t CHAIN_5_4;

  1022.     volatile uint32_t CHAIN_7_6;

  1023.     volatile uint32_t RESULT_1_0;

  1024.     volatile uint32_t RESULT_3_2;

  1025.     volatile uint32_t RESULT_5_4;

  1026.     volatile uint32_t RESULT_7_6;

  1027.   } TRIG[7];

  1028. } IMXRT_ADC_ETC_t;

  1029. 

  1030. #define IMXRT_ADC_ETC		(*(IMXRT_ADC_ETC_t *)0x403B0000)

  1031. #define ADC_ETC_CTRL			(IMXRT_ADC_ETC.CTRL)

  1032. #define ADC_ETC_DONE0_1_IRQ		(IMXRT_ADC_ETC.DONE0_1_IRQ)

  1033. #define ADC_ETC_DONE2_ERR_IRQ		(IMXRT_ADC_ETC.DONE2_ERR_IRQ)

  1034. #define ADC_ETC_DMA_CTRL		(IMXRT_ADC_ETC.DMA_CTRL)

  1035. #define ADC_ETC_TRIG0_CTRL		(IMXRT_ADC_ETC.TRIG[0].CTRL)

  1036. #define ADC_ETC_TRIG0_COUNTER		(IMXRT_ADC_ETC.TRIG[0].COUNTER)

  1037. #define ADC_ETC_TRIG0_CHAIN_1_0		(IMXRT_ADC_ETC.TRIG[0].CHAIN_1_0)

  1038. #define ADC_ETC_TRIG0_CHAIN_3_2		(IMXRT_ADC_ETC.TRIG[0].CHAIN_3_2)

  1039. #define ADC_ETC_TRIG0_CHAIN_5_4		(IMXRT_ADC_ETC.TRIG[0].CHAIN_5_4)

  1040. #define ADC_ETC_TRIG0_CHAIN_7_6		(IMXRT_ADC_ETC.TRIG[0].CHAIN_7_6)

  1041. #define ADC_ETC_TRIG0_RESULT_1_0	(IMXRT_ADC_ETC.TRIG[0].RESULT_1_0)

  1042. #define ADC_ETC_TRIG0_RESULT_3_2	(IMXRT_ADC_ETC.TRIG[0].RESULT_3_2)

  1043. #define ADC_ETC_TRIG0_RESULT_5_4	(IMXRT_ADC_ETC.TRIG[0].RESULT_5_4)

  1044. #define ADC_ETC_TRIG0_RESULT_7_6	(IMXRT_ADC_ETC.TRIG[0].RESULT_7_6)

  1045. 

  1046. #define ADC_ETC_TRIG1_CTRL              (IMXRT_ADC_ETC.TRIG[1].CTRL)

  1047. #define ADC_ETC_TRIG1_COUNTER           (IMXRT_ADC_ETC.TRIG[1].COUNTER)

  1048. #define ADC_ETC_TRIG1_CHAIN_1_0         (IMXRT_ADC_ETC.TRIG[1].CHAIN_1_0)

  1049. #define ADC_ETC_TRIG1_CHAIN_3_2         (IMXRT_ADC_ETC.TRIG[1].CHAIN_3_2)

  1050. #define ADC_ETC_TRIG1_CHAIN_5_4         (IMXRT_ADC_ETC.TRIG[1].CHAIN_5_4)

  1051. #define ADC_ETC_TRIG1_CHAIN_7_6         (IMXRT_ADC_ETC.TRIG[1].CHAIN_7_6)

  1052. #define ADC_ETC_TRIG1_RESULT_1_0        (IMXRT_ADC_ETC.TRIG[1].RESULT_1_0)

  1053. #define ADC_ETC_TRIG1_RESULT_3_2        (IMXRT_ADC_ETC.TRIG[1].RESULT_3_2)

  1054. #define ADC_ETC_TRIG1_RESULT_5_4        (IMXRT_ADC_ETC.TRIG[1].RESULT_5_4)

  1055. #define ADC_ETC_TRIG1_RESULT_7_6        (IMXRT_ADC_ETC.TRIG[1].RESULT_7_6)

  1056. #define ADC_ETC_TRIG2_CTRL              (IMXRT_ADC_ETC.TRIG[2].CTRL)

  1057. #define ADC_ETC_TRIG2_COUNTER           (IMXRT_ADC_ETC.TRIG[2].COUNTER)

  1058. #define ADC_ETC_TRIG2_CHAIN_1_0         (IMXRT_ADC_ETC.TRIG[2].CHAIN_1_0)

  1059. #define ADC_ETC_TRIG2_CHAIN_3_2         (IMXRT_ADC_ETC.TRIG[2].CHAIN_3_2)

  1060. #define ADC_ETC_TRIG2_CHAIN_5_4         (IMXRT_ADC_ETC.TRIG[2].CHAIN_5_4)

  1061. #define ADC_ETC_TRIG2_CHAIN_7_6         (IMXRT_ADC_ETC.TRIG[2].CHAIN_7_6)

  1062. #define ADC_ETC_TRIG2_RESULT_1_0        (IMXRT_ADC_ETC.TRIG[2].RESULT_1_0)

  1063. #define ADC_ETC_TRIG2_RESULT_3_2        (IMXRT_ADC_ETC.TRIG[2].RESULT_3_2)

  1064. #define ADC_ETC_TRIG2_RESULT_5_4        (IMXRT_ADC_ETC.TRIG[2].RESULT_5_4)

  1065. #define ADC_ETC_TRIG2_RESULT_7_6        (IMXRT_ADC_ETC.TRIG[2].RESULT_7_6)

  1066. #define ADC_ETC_TRIG3_CTRL              (IMXRT_ADC_ETC.TRIG[3].CTRL)

  1067. #define ADC_ETC_TRIG3_COUNTER           (IMXRT_ADC_ETC.TRIG[3].COUNTER)

  1068. #define ADC_ETC_TRIG3_CHAIN_1_0         (IMXRT_ADC_ETC.TRIG[3].CHAIN_1_0)

  1069. #define ADC_ETC_TRIG3_CHAIN_3_2         (IMXRT_ADC_ETC.TRIG[3].CHAIN_3_2)

  1070. #define ADC_ETC_TRIG3_CHAIN_5_4         (IMXRT_ADC_ETC.TRIG[3].CHAIN_5_4)

  1071. #define ADC_ETC_TRIG3_CHAIN_7_6         (IMXRT_ADC_ETC.TRIG[3].CHAIN_7_6)

  1072. #define ADC_ETC_TRIG3_RESULT_1_0        (IMXRT_ADC_ETC.TRIG[3].RESULT_1_0)

  1073. #define ADC_ETC_TRIG3_RESULT_3_2        (IMXRT_ADC_ETC.TRIG[3].RESULT_3_2)

  1074. #define ADC_ETC_TRIG3_RESULT_5_4        (IMXRT_ADC_ETC.TRIG[3].RESULT_5_4)

  1075. #define ADC_ETC_TRIG3_RESULT_7_6        (IMXRT_ADC_ETC.TRIG[3].RESULT_7_6)

  1076. #define ADC_ETC_TRIG4_CTRL              (IMXRT_ADC_ETC.TRIG[4].CTRL)

  1077. #define ADC_ETC_TRIG4_COUNTER           (IMXRT_ADC_ETC.TRIG[4].COUNTER)

  1078. #define ADC_ETC_TRIG4_CHAIN_1_0         (IMXRT_ADC_ETC.TRIG[4].CHAIN_1_0)

  1079. #define ADC_ETC_TRIG4_CHAIN_3_2         (IMXRT_ADC_ETC.TRIG[4].CHAIN_3_2)

  1080. #define ADC_ETC_TRIG4_CHAIN_5_4         (IMXRT_ADC_ETC.TRIG[4].CHAIN_5_4)

  1081. #define ADC_ETC_TRIG4_CHAIN_7_6         (IMXRT_ADC_ETC.TRIG[4].CHAIN_7_6)

  1082. #define ADC_ETC_TRIG4_RESULT_1_0        (IMXRT_ADC_ETC.TRIG[4].RESULT_1_0)

  1083. #define ADC_ETC_TRIG4_RESULT_3_2        (IMXRT_ADC_ETC.TRIG[4].RESULT_3_2)

  1084. #define ADC_ETC_TRIG4_RESULT_5_4        (IMXRT_ADC_ETC.TRIG[4].RESULT_5_4)

  1085. #define ADC_ETC_TRIG4_RESULT_7_6        (IMXRT_ADC_ETC.TRIG[4].RESULT_7_6)

  1086. #define ADC_ETC_TRIG5_CTRL              (IMXRT_ADC_ETC.TRIG[5].CTRL)

  1087. #define ADC_ETC_TRIG5_COUNTER           (IMXRT_ADC_ETC.TRIG[5].COUNTER)

  1088. #define ADC_ETC_TRIG5_CHAIN_1_0         (IMXRT_ADC_ETC.TRIG[5].CHAIN_1_0)

  1089. #define ADC_ETC_TRIG5_CHAIN_3_2         (IMXRT_ADC_ETC.TRIG[5].CHAIN_3_2)

  1090. #define ADC_ETC_TRIG5_CHAIN_5_4         (IMXRT_ADC_ETC.TRIG[5].CHAIN_5_4)

  1091. #define ADC_ETC_TRIG5_CHAIN_7_6         (IMXRT_ADC_ETC.TRIG[5].CHAIN_7_6)

  1092. #define ADC_ETC_TRIG5_RESULT_1_0        (IMXRT_ADC_ETC.TRIG[5].RESULT_1_0)

  1093. #define ADC_ETC_TRIG5_RESULT_3_2        (IMXRT_ADC_ETC.TRIG[5].RESULT_3_2)

  1094. #define ADC_ETC_TRIG5_RESULT_5_4        (IMXRT_ADC_ETC.TRIG[5].RESULT_5_4)

  1095. #define ADC_ETC_TRIG5_RESULT_7_6        (IMXRT_ADC_ETC.TRIG[5].RESULT_7_6)

  1096. #define ADC_ETC_TRIG6_CTRL              (IMXRT_ADC_ETC.TRIG[6].CTRL)

  1097. #define ADC_ETC_TRIG6_COUNTER           (IMXRT_ADC_ETC.TRIG[6].COUNTER)

  1098. #define ADC_ETC_TRIG6_CHAIN_1_0         (IMXRT_ADC_ETC.TRIG[6].CHAIN_1_0)

  1099. #define ADC_ETC_TRIG6_CHAIN_3_2         (IMXRT_ADC_ETC.TRIG[6].CHAIN_3_2)

  1100. #define ADC_ETC_TRIG6_CHAIN_5_4         (IMXRT_ADC_ETC.TRIG[6].CHAIN_5_4)

  1101. #define ADC_ETC_TRIG6_CHAIN_7_6         (IMXRT_ADC_ETC.TRIG[6].CHAIN_7_6)

  1102. #define ADC_ETC_TRIG6_RESULT_1_0        (IMXRT_ADC_ETC.TRIG[6].RESULT_1_0)

  1103. #define ADC_ETC_TRIG6_RESULT_3_2        (IMXRT_ADC_ETC.TRIG[6].RESULT_3_2)

  1104. #define ADC_ETC_TRIG6_RESULT_5_4        (IMXRT_ADC_ETC.TRIG[6].RESULT_5_4)

  1105. #define ADC_ETC_TRIG6_RESULT_7_6        (IMXRT_ADC_ETC.TRIG[6].RESULT_7_6)

  1106. #define ADC_ETC_TRIG7_CTRL              (IMXRT_ADC_ETC.TRIG[7].CTRL)

  1107. #define ADC_ETC_TRIG7_COUNTER           (IMXRT_ADC_ETC.TRIG[7].COUNTER)

  1108. #define ADC_ETC_TRIG7_CHAIN_1_0         (IMXRT_ADC_ETC.TRIG[7].CHAIN_1_0)

  1109. #define ADC_ETC_TRIG7_CHAIN_3_2         (IMXRT_ADC_ETC.TRIG[7].CHAIN_3_2)

  1110. #define ADC_ETC_TRIG7_CHAIN_5_4         (IMXRT_ADC_ETC.TRIG[7].CHAIN_5_4)

  1111. #define ADC_ETC_TRIG7_CHAIN_7_6         (IMXRT_ADC_ETC.TRIG[7].CHAIN_7_6)

  1112. #define ADC_ETC_TRIG7_RESULT_1_0        (IMXRT_ADC_ETC.TRIG[7].RESULT_1_0)

  1113. #define ADC_ETC_TRIG7_RESULT_3_2        (IMXRT_ADC_ETC.TRIG[7].RESULT_3_2)

  1114. #define ADC_ETC_TRIG7_RESULT_5_4        (IMXRT_ADC_ETC.TRIG[7].RESULT_5_4)

  1115. #define ADC_ETC_TRIG7_RESULT_7_6        (IMXRT_ADC_ETC.TRIG[7].RESULT_7_6)

  1116. 

  1117. #define ADC_ETC_CTRL_SOFTRST            ((uint32_t)(1<<31))

  1118. #define ADC_ETC_CTRL_TSC_BYPASS         ((uint32_t)(1<<30))

  1119. #define ADC_ETC_CTRL_DMA_MODE_SEL       ((uint32_t)(1<<29))

  1120. #define ADC_ETC_CTRL_PRE_DIVIDER(n)     ((uint32_t)(((n) & 0xff) << 16))

  1121. #define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(n)  ((uint32_t)(((n) & 0x07) << 13))

  1122. #define ADC_ETC_CTRL_EXT1_TRIG_ENABLE       ((uint32_t)(1<<12))

  1123. #define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(n)  ((uint32_t)(((n) & 0x07) << 9))

  1124. #define ADC_ETC_CTRL_EXT0_TRIG_ENABLE       ((uint32_t)(1<<8))

  1125. #define ADC_ETC_CTRL_TRIG_ENABLE(n)     ((uint32_t)(((n) & 0xff) << 0))

  1126. 

  1127. #define ADC_ETC_DONE0_1_IRQ_TRIG_DONE1(n)  ((uint32_t)(1<<(16 + ((n) &0x7))))

  1128. #define ADC_ETC_DONE0_1_IRQ_TRIG_DONE0(n)  ((uint32_t)(1<<((n) &0x7)))

  1129. 

  1130. #define ADC_ETC_DONE2_ERR_IRQ_TRIG_ERR(n)  ((uint32_t)(1<<(16 + ((n) &0x7))))

  1131. #define ADC_ETC_DONE2_ERR_IRQ_TRIG_DONE2(n)  ((uint32_t)(1<<((n) &0x7)))

  1132. 

  1133. #define ADC_ETC_DMA_CTRL_TRIQ_REQ(n)    ((uint32_t)(1<<(16 + ((n) &0x7))))

  1134. #define ADC_ETC_DMA_CTRL_TRIQ_ENABLE(n) ((uint32_t)(1<<((n) &0x7)))

  1135. 

  1136. // For each TRIG elements in array

  1137. #define ADC_ETC_TRIG_CTRL_SYNC_MODE     ((uint32_t)(1<<16))

  1138. #define ADC_ETC_TRIG_CTRL_TRIG_PRIORITY(n)  ((uint32_t)(((n) & 0x07) << 12))

  1139. #define ADC_ETC_TRIG_CTRL_TRIG_CHAIN(n) ((uint32_t)(((n) & 0x07) << 8))

  1140. #define ADC_ETC_TRIG_CTRL_TRIG_MODE     ((uint32_t)(1<<4))

  1141. #define ADC_ETC_TRIG_CTRL_SW_TRIG       ((uint32_t)(1<<0))

  1142. 

  1143. #define ADC_ETC_TRIG_COUNTER_SAMPLE_INTERVAL(n) ((uint32_t)(((n) & 0xff) << 16))

  1144. #define ADC_ETC_TRIG_COUNTER_INIT_DELAY(n)    ((uint32_t)(((n) & 0xff) << 0))

  1145. 

  1146. #define ADC_ETC_TRIG_CHAIN_IE1(n)       ((uint32_t)(((n) & 0x03) << 29))

  1147. #define ADC_ETC_TRIG_CHAIN_B2B1         ((uint32_t)(1<<28))

  1148. #define ADC_ETC_TRIG_CHAIN_HWTS1(n)     ((uint32_t)(((n) & 0xff) << 20))

  1149. #define ADC_ETC_TRIG_CHAIN_CSEL1(n)     ((uint32_t)(((n) & 0x0f) << 16))

  1150. #define ADC_ETC_TRIG_CHAIN_IE0(n)       ((uint32_t)(((n) & 0x03) << 13))

  1151. #define ADC_ETC_TRIG_CHAIN_B2B0         ((uint32_t)(1<<12))

  1152. #define ADC_ETC_TRIG_CHAIN_HWTS0(n)     ((uint32_t)(((n) & 0xff) << 4))

  1153. #define ADC_ETC_TRIG_CHAIN_CSEL0(n)     ((uint32_t)(((n) & 0x0f) << 0))

  1154. 

  1155. #define ADC_ETC_TRIG_RESULT_DATA1(n)    ((uint32_t)(((n) & 0xfff) << 16))

  1156. #define ADC_ETC_TRIG_RESULT_DATA0(n)    ((uint32_t)(((n) & 0xfff) << 0))

  1157. 

  1158. // 32.8: page 1778

  1159. #define IMXRT_AIPSTZ1		(*(IMXRT_REGISTER32_t *)0x4007C000)

  1160. #define AIPSTZ1_MPR			(IMXRT_AIPSTZ1.offset000)

  1161. #define AIPSTZ1_OPACR			(IMXRT_AIPSTZ1.offset040)

  1162. #define AIPSTZ1_OPACR1			(IMXRT_AIPSTZ1.offset044)

  1163. #define AIPSTZ1_OPACR2			(IMXRT_AIPSTZ1.offset048)

  1164. #define AIPSTZ1_OPACR3			(IMXRT_AIPSTZ1.offset04C)

  1165. #define AIPSTZ1_OPACR4			(IMXRT_AIPSTZ1.offset050)

  1166. #define IMXRT_AIPSTZ2		(*(IMXRT_REGISTER32_t *)0x4017C000)

  1167. #define AIPSTZ2_MPR			(IMXRT_AIPSTZ2.offset000)

  1168. #define AIPSTZ2_OPACR			(IMXRT_AIPSTZ2.offset040)

  1169. #define AIPSTZ2_OPACR1			(IMXRT_AIPSTZ2.offset044)

  1170. #define AIPSTZ2_OPACR2			(IMXRT_AIPSTZ2.offset048)

  1171. #define AIPSTZ2_OPACR3			(IMXRT_AIPSTZ2.offset04C)

  1172. #define AIPSTZ2_OPACR4			(IMXRT_AIPSTZ2.offset050)

  1173. #define IMXRT_AIPSTZ3		(*(IMXRT_REGISTER32_t *)0x4027C000)

  1174. #define AIPSTZ3_MPR			(IMXRT_AIPSTZ3.offset000)

  1175. #define AIPSTZ3_OPACR			(IMXRT_AIPSTZ3.offset040)

  1176. #define AIPSTZ3_OPACR1			(IMXRT_AIPSTZ3.offset044)

  1177. #define AIPSTZ3_OPACR2			(IMXRT_AIPSTZ3.offset048)

  1178. #define AIPSTZ3_OPACR3			(IMXRT_AIPSTZ3.offset04C)

  1179. #define AIPSTZ3_OPACR4			(IMXRT_AIPSTZ3.offset050)

  1180. #define IMXRT_AIPSTZ4		(*(IMXRT_REGISTER32_t *)0x4037C000)

  1181. #define AIPSTZ4_MPR			(IMXRT_AIPSTZ4.offset000)

  1182. #define AIPSTZ4_OPACR			(IMXRT_AIPSTZ4.offset040)

  1183. #define AIPSTZ4_OPACR1			(IMXRT_AIPSTZ4.offset044)

  1184. #define AIPSTZ4_OPACR2			(IMXRT_AIPSTZ4.offset048)

  1185. #define AIPSTZ4_OPACR3			(IMXRT_AIPSTZ4.offset04C)

  1186. #define AIPSTZ4_OPACR4			(IMXRT_AIPSTZ4.offset050)

  1187. 

  1188. // 63.4: page 3287

  1189. #define IMXRT_AOI1		(*(IMXRT_REGISTER16_t *)0x403B4000)

  1190. #define AOI1_BFCRT010			(IMXRT_AOI1.offset000)

  1191. #define AOI1_BFCRT230			(IMXRT_AOI1.offset002)

  1192. #define AOI1_BFCRT011			(IMXRT_AOI1.offset004)

  1193. #define AOI1_BFCRT231			(IMXRT_AOI1.offset006)

  1194. #define AOI1_BFCRT012			(IMXRT_AOI1.offset008)

  1195. #define AOI1_BFCRT232			(IMXRT_AOI1.offset00A)

  1196. #define AOI1_BFCRT013			(IMXRT_AOI1.offset00C)

  1197. #define AOI1_BFCRT233			(IMXRT_AOI1.offset00E)

  1198. #define IMXRT_AOI2		(*(IMXRT_REGISTER16_t *)0x403B8000)

  1199. #define AOI2_BFCRT010			(IMXRT_AOI2.offset000)

  1200. #define AOI2_BFCRT230			(IMXRT_AOI2.offset002)

  1201. #define AOI2_BFCRT011			(IMXRT_AOI2.offset004)

  1202. #define AOI2_BFCRT231			(IMXRT_AOI2.offset006)

  1203. #define AOI2_BFCRT012			(IMXRT_AOI2.offset008)

  1204. #define AOI2_BFCRT232			(IMXRT_AOI2.offset00A)

  1205. #define AOI2_BFCRT013			(IMXRT_AOI2.offset00C)

  1206. #define AOI2_BFCRT233			(IMXRT_AOI2.offset00E)

  1207. 

  1208. // 14.7: page 1045

  1209. #define IMXRT_CCM		(*(IMXRT_REGISTER32_t *)0x400FC000)

  1210. #define CCM_CCR				(IMXRT_CCM.offset000)

  1211. #define CCM_CSR				(IMXRT_CCM.offset008)

  1212. #define CCM_CCSR			(IMXRT_CCM.offset00C)

  1213. #define CCM_CACRR			(IMXRT_CCM.offset010)

  1214. #define CCM_CBCDR			(IMXRT_CCM.offset014)

  1215. #define CCM_CBCMR			(IMXRT_CCM.offset018)

  1216. #define CCM_CSCMR1			(IMXRT_CCM.offset01C)

  1217. #define CCM_CSCMR2			(IMXRT_CCM.offset020)

  1218. #define CCM_CSCDR1			(IMXRT_CCM.offset024)

  1219. #define CCM_CS1CDR			(IMXRT_CCM.offset028)

  1220. #define CCM_CS2CDR			(IMXRT_CCM.offset02C)

  1221. #define CCM_CDCDR			(IMXRT_CCM.offset030)

  1222. #define CCM_CSCDR2			(IMXRT_CCM.offset038)

  1223. #define CCM_CSCDR3			(IMXRT_CCM.offset03C)

  1224. #define CCM_CDHIPR			(IMXRT_CCM.offset048)

  1225. #define CCM_CLPCR			(IMXRT_CCM.offset054)

  1226. #define CCM_CISR			(IMXRT_CCM.offset058)

  1227. #define CCM_CIMR			(IMXRT_CCM.offset05C)

  1228. #define CCM_CCOSR			(IMXRT_CCM.offset060)

  1229. #define CCM_CGPR			(IMXRT_CCM.offset064)

  1230. #define CCM_CCGR0			(IMXRT_CCM.offset068)

  1231. #define CCM_CCGR1			(IMXRT_CCM.offset06C)

  1232. #define CCM_CCGR2			(IMXRT_CCM.offset070)

  1233. #define CCM_CCGR3			(IMXRT_CCM.offset074)

  1234. #define CCM_CCGR4			(IMXRT_CCM.offset078)

  1235. #define CCM_CCGR5			(IMXRT_CCM.offset07C)

  1236. #define CCM_CCGR6			(IMXRT_CCM.offset080)

  1237. #define CCM_CCGR7			(IMXRT_CCM.offset084)

  1238. #define CCM_CMEOR			(IMXRT_CCM.offset088)

  1239. #define CCM_CCR_RBC_EN				((uint32_t)(1<<27))

  1240. #define CCM_CCR_REG_BYPASS_COUNT(n)		((uint32_t)(((n) & 0x3F) << 21))

  1241. #define CCM_CCR_COSC_EN				((uint32_t)(1<<12))

  1242. #define CCM_CCR_OSCNT(n)			((uint32_t)(((n) & 0xFF) << 0))

  1243. #define CCM_CSR_COSC_READY			((uint32_t)(1<<5))

  1244. #define CCM_CSR_CAMP2_READY			((uint32_t)(1<<3))

  1245. #define CCM_CSR_REF_EN_B			((uint32_t)(1<<0))

  1246. #define CCM_CCSR_PLL3_SW_CLK_SEL		((uint32_t)(1<<0))

  1247. #define CCM_CACRR_ARM_PODF(n)			((uint32_t)(((n) & 0x07) << 0))

  1248. #define CCM_CACRR_ARM_PODF_MASK			((uint32_t)(0x07 << 0))

  1249. #define CCM_CBCDR_PERIPH_CLK2_PODF(n)		((uint32_t)(((n) & 0x07) << 27))

  1250. #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK		((uint32_t)(0x07 << 27))

  1251. #define CCM_CBCDR_PERIPH_CLK_SEL		((uint32_t)(1<<25))

  1252. #define CCM_CBCDR_SEMC_PODF(n)			((uint32_t)(((n) & 0x07) << 16))

  1253. #define CCM_CBCDR_AHB_PODF(n)			((uint32_t)(((n) & 0x07) << 10))

  1254. #define CCM_CBCDR_AHB_PODF_MASK			((uint32_t)(0x07 << 10))

  1255. #define CCM_CBCDR_IPG_PODF(n)			((uint32_t)(((n) & 0x03) << 8))

  1256. #define CCM_CBCDR_IPG_PODF_MASK			((uint32_t)(0x03 << 8))

  1257. #define CCM_CBCDR_SEMC_ALT_CLK_SEL		((uint32_t)(1<<7))

  1258. #define CCM_CBCDR_SEMC_CLK_SEL			((uint32_t)(1<<6))

  1259. #define CCM_CBCMR_FLEXSPI2_PODF(n)		((uint32_t)(((n) & 0x07) << 29))

  1260. #define CCM_CBCMR_LPSPI_PODF(n)			((uint32_t)(((n) & 0x07) << 26))

  1261. #define CCM_CBCMR_LCDIF_PODF(n)			((uint32_t)(((n) & 0x07) << 23))

  1262. #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 18))

  1263. #define CCM_CBCMR_TRACE_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 14))

  1264. #define CCM_CBCMR_PERIPH_CLK2_SEL(n)		((uint32_t)(((n) & 0x03) << 12))

  1265. #define CCM_CBCMR_FLEXSPI2_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 8))

  1266. #define CCM_CBCMR_LPSPI_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 4))

  1267. #define CCM_CBCMR_FLEXSPI2_PODF_MASK		((uint32_t)(0x07 << 29))

  1268. #define CCM_CBCMR_LPSPI_PODF_MASK		((uint32_t)(0x07 << 26))

  1269. #define CCM_CBCMR_LCDIF_PODF_MASK		((uint32_t)(0x07 << 23))

  1270. #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK	((uint32_t)(0x03 << 18))

  1271. #define CCM_CBCMR_TRACE_CLK_SEL_MASK		((uint32_t)(0x03 << 14))

  1272. #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK		((uint32_t)(0x03 << 12))

  1273. #define CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK		((uint32_t)(0x03 << 8))

  1274. #define CCM_CBCMR_LPSPI_CLK_SEL_MASK		((uint32_t)(0x03 << 4))

  1275. #define CCM_CSCMR1_FLEXSPI_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 29))

  1276. #define CCM_CSCMR1_FLEXSPI_PODF(n)		((uint32_t)(((n) & 0x07) << 23))

  1277. #define CCM_CSCMR1_USDHC2_CLK_SEL		((uint32_t)(1<<17))

  1278. #define CCM_CSCMR1_USDHC1_CLK_SEL		((uint32_t)(1<<16))

  1279. #define CCM_CSCMR1_SAI3_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 14))

  1280. #define CCM_CSCMR1_SAI2_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 12))

  1281. #define CCM_CSCMR1_SAI1_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 10))

  1282. #define CCM_CSCMR1_PERCLK_CLK_SEL		((uint32_t)(1<<6))

  1283. #define CCM_CSCMR1_PERCLK_PODF(n)		((uint32_t)(((n) & 0x3F) << 0))

  1284. #define CCM_CSCMR2_FLEXIO2_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 19))

  1285. #define CCM_CSCMR2_CAN_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 8))

  1286. #define CCM_CSCMR2_CAN_CLK_PODF(n)		((uint32_t)(((n) & 0x3F) << 2))

  1287. #define CCM_CSCDR1_TRACE_PODF(n)		((uint32_t)(((n) & 0x07) << 25))

  1288. #define CCM_CSCDR1_USDHC2_PODF(n)		((uint32_t)(((n) & 0x07) << 16))

  1289. #define CCM_CSCDR1_USDHC1_PODF(n)		((uint32_t)(((n) & 0x07) << 11))

  1290. #define CCM_CSCDR1_UART_CLK_SEL			((uint32_t)(1<<6))

  1291. #define CCM_CSCDR1_UART_CLK_PODF(n)		((uint32_t)(((n) & 0x3F) << 0))

  1292. #define CCM_CS1CDR_FLEXIO2_CLK_PODF(n)		((uint32_t)(((n) & 0x07) << 25))

  1293. #define CCM_CS1CDR_SAI3_CLK_PRED(n)		((uint32_t)(((n) & 0x07) << 22))

  1294. #define CCM_CS1CDR_SAI3_CLK_PODF(n)		((uint32_t)(((n) & 0x3F) << 16))

  1295. #define CCM_CS1CDR_FLEXIO2_CLK_PRED(n)		((uint32_t)(((n) & 0x07) << 9))

  1296. #define CCM_CS1CDR_SAI1_CLK_PRED(n)		((uint32_t)(((n) & 0x07) << 6))

  1297. #define CCM_CS1CDR_SAI1_CLK_PODF(n)		((uint32_t)(((n) & 0x3F) << 0))

  1298. #define CCM_CS2CDR_SAI2_CLK_PRED(n)		((uint32_t)(((n) & 0x07) << 6))

  1299. #define CCM_CS2CDR_SAI2_CLK_PODF(n)		((uint32_t)(((n) & 0x3F) << 0))

  1300. #define CCM_CDCDR_SPDIF0_CLK_PRED(n)		((uint32_t)(((n) & 0x07) << 25))

  1301. #define CCM_CDCDR_SPDIF0_CLK_PODF(n)		((uint32_t)(((n) & 0x07) << 22))

  1302. #define CCM_CDCDR_SPDIF0_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 20))

  1303. #define CCM_CDCDR_FLEXIO1_CLK_PRED(n)		((uint32_t)(((n) & 0x07) << 12))

  1304. #define CCM_CDCDR_FLEXIO1_CLK_PODF(n)		((uint32_t)(((n) & 0x07) << 9))

  1305. #define CCM_CDCDR_FLEXIO1_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 7))

  1306. #define CCM_CSCDR2_LPI2C_CLK_PODF(n)		((uint32_t)(((n) & 0x1F) << 19))

  1307. #define CCM_CSCDR2_LPI2C_CLK_SEL		((uint32_t)(1<<18))

  1308. #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(n)		((uint32_t)(((n) & 0x07) << 15))

  1309. #define CCM_CSCDR2_LCDIF_PRED(n)		((uint32_t)(((n) & 0x07) << 12))

  1310. #define CCM_CSCDR2_LCDIF_CLK_SEL(n)		((uint32_t)(((n) & 0x07) << 9))

  1311. #define CCM_CSCDR3_CSI_PODF(n)			((uint32_t)(((n) & 0x07) << 11))

  1312. #define CCM_CSCDR3_CSI_CLK_SEL(n)		((uint32_t)(((n) & 0x03) << 9))

  1313. #define CCM_CDHIPR_ARM_PODF_BUSY		((uint32_t)(1<<16))

  1314. #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		((uint32_t)(1<<5))

  1315. #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY		((uint32_t)(1<<3))

  1316. #define CCM_CDHIPR_AHB_PODF_BUSY		((uint32_t)(1<<1))

  1317. #define CCM_CDHIPR_SEMC_PODF_BUSY		((uint32_t)(1<<0))

  1318. #define CCM_CLPCR_MASK_L2CC_IDLE		((uint32_t)(1<<27))

  1319. #define CCM_CLPCR_MASK_SCU_IDLE			((uint32_t)(1<<26))

  1320. #define CCM_CLPCR_MASK_CORE0_WFI		((uint32_t)(1<<22))

  1321. #define CCM_CLPCR_BYPASS_LPM_HS0		((uint32_t)(1<<21))

  1322. #define CCM_CLPCR_BYPASS_LPM_HS1		((uint32_t)(1<<19))

  1323. #define CCM_CLPCR_COSC_PWRDOWN			((uint32_t)(1<<11))

  1324. #define CCM_CLPCR_STBY_COUNT(n)			((uint32_t)(((n) & 0x03) << 9))

  1325. #define CCM_CLPCR_VSTBY				((uint32_t)(1<<8))

  1326. #define CCM_CLPCR_DIS_REF_OSC			((uint32_t)(1<<7))

  1327. #define CCM_CLPCR_SBYOS				((uint32_t)(1<<6))

  1328. #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM		((uint32_t)(1<<5))

  1329. #define CCM_CLPCR_LPM(n)			((uint32_t)(((n) & 0x03) << 0))

  1330. #define CCM_CISR_ARM_PODF_LOADED		((uint32_t)(1<<26))

  1331. #define CCM_CISR_PERIPH_CLK_SEL_LOADED		((uint32_t)(1<<22))

  1332. #define CCM_CISR_AHB_PODF_LOADED		((uint32_t)(1<<20))

  1333. #define CCM_CISR_PERIPH2_CLK_SEL_LOADED		((uint32_t)(1<<19))

  1334. #define CCM_CISR_SEMC_PODF_LOADED		((uint32_t)(1<<17))

  1335. #define CCM_CISR_COSC_READY			((uint32_t)(1<<6))

  1336. #define CCM_CISR_LRF_PLL			((uint32_t)(1<<0))

  1337. #define CCM_CIMR_ARM_PODF_LOADED		((uint32_t)(1<<26))

  1338. #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED	((uint32_t)(1<<22))

  1339. #define CCM_CIMR_MASK_AHB_PODF_LOADED		((uint32_t)(1<<20))

  1340. #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED	((uint32_t)(1<<19))

  1341. #define CCM_CIMR_MASK_SEMC_PODF_LOADED		((uint32_t)(1<<17))

  1342. #define CCM_CIMR_MASK_COSC_READY		((uint32_t)(1<<6))

  1343. #define CCM_CIMR_MASK_LRF_PLL			((uint32_t)(1<<0))

  1344. #define CCM_CCOSR_CLKO2_EN			((uint32_t)(1<<24))

  1345. #define CCM_CCOSR_CLKO2_DIV(n)			((uint32_t)(((n) & 0x07) << 21))

  1346. #define CCM_CCOSR_CLKO2_SEL(n)			((uint32_t)(((n) & 0x1F) << 16))

  1347. #define CCM_CCOSR_CLK_OUT_SEL			((uint32_t)(1<<8))

  1348. #define CCM_CCOSR_CLKO1_EN			((uint32_t)(1<<7))

  1349. #define CCM_CCOSR_CLKO1_DIV(n)			((uint32_t)(((n) & 0x07) << 4))

  1350. #define CCM_CCOSR_CLKO1_SEL(n)			((uint32_t)(((n) & 0x0F) << 0))

  1351. #define CCM_CGPR_INT_MEM_CLK_LPM		((uint32_t)(1<<17))

  1352. #define CCM_CGPR_FPL				((uint32_t)(1<<16))

  1353. #define CCM_CGPR_SYS_MEM_DS_CTRL(n)		((uint32_t)(((n) & 0x03) << 14))

  1354. #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		((uint32_t)(1<<4))

  1355. #define CCM_CGPR_PMIC_DELAY_SCALER		((uint32_t)(1<<0))

  1356. #define CCM_CCGR_OFF				0

  1357. #define CCM_CCGR_ON_RUNONLY			1

  1358. #define CCM_CCGR_ON				3

  1359. #define CCM_CCGR0_GPIO2(n)			((uint32_t)(((n) & 0x03) << 30))

  1360. #define CCM_CCGR0_LPUART2(n)			((uint32_t)(((n) & 0x03) << 28))

  1361. #define CCM_CCGR0_GPT2_SERIAL(n)		((uint32_t)(((n) & 0x03) << 26))

  1362. #define CCM_CCGR0_GPT2_BUS(n)			((uint32_t)(((n) & 0x03) << 24))

  1363. #define CCM_CCGR0_TRACE(n)			((uint32_t)(((n) & 0x03) << 22))

  1364. #define CCM_CCGR0_CAN2_SERIAL(n)		((uint32_t)(((n) & 0x03) << 20))

  1365. #define CCM_CCGR0_CAN2(n)			((uint32_t)(((n) & 0x03) << 18))

  1366. #define CCM_CCGR0_CAN1_SERIAL(n)		((uint32_t)(((n) & 0x03) << 16))

  1367. #define CCM_CCGR0_CAN1(n)			((uint32_t)(((n) & 0x03) << 14))

  1368. #define CCM_CCGR0_LPUART3(n)			((uint32_t)(((n) & 0x03) << 12))

  1369. #define CCM_CCGR0_DCP(n)			((uint32_t)(((n) & 0x03) << 10))

  1370. #define CCM_CCGR0_MQS_HMCLK(n)			((uint32_t)(((n) & 0x03) << 4))

  1371. #define CCM_CCGR0_AIPS_TZ2(n)			((uint32_t)(((n) & 0x03) << 2))

  1372. #define CCM_CCGR0_AIPS_TZ1(n)			((uint32_t)(((n) & 0x03) << 0))

  1373. #define CCM_CCGR1_CSU(n)			((uint32_t)(((n) & 0x03) << 28))

  1374. #define CCM_CCGR1_GPIO1(n)			((uint32_t)(((n) & 0x03) << 26))

  1375. #define CCM_CCGR1_LPUART4(n)			((uint32_t)(((n) & 0x03) << 24))

  1376. #define CCM_CCGR1_GPT1_SERIAL(n)		((uint32_t)(((n) & 0x03) << 22))

  1377. #define CCM_CCGR1_GPT1_BUS(n)			((uint32_t)(((n) & 0x03) << 20))

  1378. #define CCM_CCGR1_GPT(n)			((uint32_t)(((n) & 0x03) << 20))

  1379. #define CCM_CCGR1_ADC1(n)			((uint32_t)(((n) & 0x03) << 16))

  1380. #define CCM_CCGR1_AOI2(n)			((uint32_t)(((n) & 0x03) << 14))

  1381. #define CCM_CCGR1_PIT(n)			((uint32_t)(((n) & 0x03) << 12))

  1382. #define CCM_CCGR1_ENET(n)			((uint32_t)(((n) & 0x03) << 10))

  1383. #define CCM_CCGR1_ADC2(n)			((uint32_t)(((n) & 0x03) << 8))

  1384. #define CCM_CCGR1_LPSPI4(n)			((uint32_t)(((n) & 0x03) << 6))

  1385. #define CCM_CCGR1_LPSPI3(n)			((uint32_t)(((n) & 0x03) << 4))

  1386. #define CCM_CCGR1_LPSPI2(n)			((uint32_t)(((n) & 0x03) << 2))

  1387. #define CCM_CCGR1_LPSPI1(n)			((uint32_t)(((n) & 0x03) << 0))

  1388. #define CCM_CCGR2_PXP(n)			((uint32_t)(((n) & 0x03) << 30))

  1389. #define CCM_CCGR2_LCD(n)			((uint32_t)(((n) & 0x03) << 28))

  1390. #define CCM_CCGR2_GPIO3(n)			((uint32_t)(((n) & 0x03) << 26))

  1391. #define CCM_CCGR2_XBAR2(n)			((uint32_t)(((n) & 0x03) << 24))

  1392. #define CCM_CCGR2_XBAR1(n)			((uint32_t)(((n) & 0x03) << 22))

  1393. #define CCM_CCGR2_IPMUX3(n)			((uint32_t)(((n) & 0x03) << 20))

  1394. #define CCM_CCGR2_IPMUX2(n)			((uint32_t)(((n) & 0x03) << 18))

  1395. #define CCM_CCGR2_IPMUX1(n)			((uint32_t)(((n) & 0x03) << 16))

  1396. #define CCM_CCGR2_XBAR3(n)			((uint32_t)(((n) & 0x03) << 14))

  1397. #define CCM_CCGR2_IIM(n)			((uint32_t)(((n) & 0x03) << 12))

  1398. #define CCM_CCGR2_LPI2C3(n)			((uint32_t)(((n) & 0x03) << 10))

  1399. #define CCM_CCGR2_LPI2C2(n)			((uint32_t)(((n) & 0x03) << 8))

  1400. #define CCM_CCGR2_LPI2C1(n)			((uint32_t)(((n) & 0x03) << 6))

  1401. #define CCM_CCGR2_IOMUXC_SNVS(n)		((uint32_t)(((n) & 0x03) << 4))

  1402. #define CCM_CCGR2_CSI(n)			((uint32_t)(((n) & 0x03) << 2))

  1403. #define CCM_CCGR3_IOMUXC_SNVS_GPR(n)		((uint32_t)(((n) & 0x03) << 30))

  1404. #define CCM_CCGR3_OCRAM(n)			((uint32_t)(((n) & 0x03) << 28))

  1405. #define CCM_CCGR3_ACMP4(n)			((uint32_t)(((n) & 0x03) << 26))

  1406. #define CCM_CCGR3_ACMP3(n)			((uint32_t)(((n) & 0x03) << 24))

  1407. #define CCM_CCGR3_ACMP2(n)			((uint32_t)(((n) & 0x03) << 22))

  1408. #define CCM_CCGR3_ACMP1(n)			((uint32_t)(((n) & 0x03) << 20))

  1409. #define CCM_CCGR3_FLEXRAM(n)			((uint32_t)(((n) & 0x03) << 18))

  1410. #define CCM_CCGR3_WDOG1(n)			((uint32_t)(((n) & 0x03) << 16))

  1411. #define CCM_CCGR3_EWM(n)			((uint32_t)(((n) & 0x03) << 14))

  1412. #define CCM_CCGR3_GPIO4(n)			((uint32_t)(((n) & 0x03) << 12))

  1413. #define CCM_CCGR3_LCDIF_PIX(n)			((uint32_t)(((n) & 0x03) << 10))

  1414. #define CCM_CCGR3_AOI1(n)			((uint32_t)(((n) & 0x03) << 8))

  1415. #define CCM_CCGR3_LPUART6(n)			((uint32_t)(((n) & 0x03) << 6))

  1416. #define CCM_CCGR3_SEMC(n)			((uint32_t)(((n) & 0x03) << 4))

  1417. #define CCM_CCGR3_LPUART5(n)			((uint32_t)(((n) & 0x03) << 2))

  1418. #define CCM_CCGR3_FLEXIO2(n)			((uint32_t)(((n) & 0x03) << 0))

  1419. #define CCM_CCGR4_ENC4(n)			((uint32_t)(((n) & 0x03) << 30))

  1420. #define CCM_CCGR4_ENC3(n)			((uint32_t)(((n) & 0x03) << 28))

  1421. #define CCM_CCGR4_ENC2(n)			((uint32_t)(((n) & 0x03) << 26))

  1422. #define CCM_CCGR4_ENC1(n)			((uint32_t)(((n) & 0x03) << 24))

  1423. #define CCM_CCGR4_PWM4(n)			((uint32_t)(((n) & 0x03) << 22))

  1424. #define CCM_CCGR4_PWM3(n)			((uint32_t)(((n) & 0x03) << 20))

  1425. #define CCM_CCGR4_PWM2(n)			((uint32_t)(((n) & 0x03) << 18))

  1426. #define CCM_CCGR4_PWM1(n)			((uint32_t)(((n) & 0x03) << 16))

  1427. #define CCM_CCGR4_SIM_EMS(n)			((uint32_t)(((n) & 0x03) << 14))

  1428. #define CCM_CCGR4_SIM_M(n)			((uint32_t)(((n) & 0x03) << 12))

  1429. #define CCM_CCGR4_TSC(n)			((uint32_t)(((n) & 0x03) << 10))

  1430. #define CCM_CCGR4_SIM_M7(n)			((uint32_t)(((n) & 0x03) << 8))

  1431. #define CCM_CCGR4_BEE(n)			((uint32_t)(((n) & 0x03) << 6))

  1432. #define CCM_CCGR4_IOMUXC_GPR(n)			((uint32_t)(((n) & 0x03) << 4))

  1433. #define CCM_CCGR4_IOMUXC(n)			((uint32_t)(((n) & 0x03) << 2))

  1434. #define CCM_CCGR5_SNVS_LP(n)			((uint32_t)(((n) & 0x03) << 30))

  1435. #define CCM_CCGR5_SNVS_HP(n)			((uint32_t)(((n) & 0x03) << 28))

  1436. #define CCM_CCGR5_LPUART7(n)			((uint32_t)(((n) & 0x03) << 26))

  1437. #define CCM_CCGR5_LPUART1(n)			((uint32_t)(((n) & 0x03) << 24))

  1438. #define CCM_CCGR5_SAI3(n)			((uint32_t)(((n) & 0x03) << 22))

  1439. #define CCM_CCGR5_SAI2(n)			((uint32_t)(((n) & 0x03) << 20))

  1440. #define CCM_CCGR5_SAI1(n)			((uint32_t)(((n) & 0x03) << 18))

  1441. #define CCM_CCGR5_SIM_MAIN(n)			((uint32_t)(((n) & 0x03) << 16))

  1442. #define CCM_CCGR5_SPDIF(n)			((uint32_t)(((n) & 0x03) << 14))

  1443. #define CCM_CCGR5_AIPS_TZ4(n)			((uint32_t)(((n) & 0x03) << 12))

  1444. #define CCM_CCGR5_WDOG2(n)			((uint32_t)(((n) & 0x03) << 10))

  1445. #define CCM_CCGR5_KPP(n)			((uint32_t)(((n) & 0x03) << 8))

  1446. #define CCM_CCGR5_DMA(n)			((uint32_t)(((n) & 0x03) << 6))

  1447. #define CCM_CCGR5_WDOG3(n)			((uint32_t)(((n) & 0x03) << 4))

  1448. #define CCM_CCGR5_FLEXIO1(n)			((uint32_t)(((n) & 0x03) << 2))

  1449. #define CCM_CCGR5_ROM(n)			((uint32_t)(((n) & 0x03) << 0))

  1450. #define CCM_CCGR6_QTIMER3(n)			((uint32_t)(((n) & 0x03) << 30))

  1451. #define CCM_CCGR6_QTIMER2(n)			((uint32_t)(((n) & 0x03) << 28))

  1452. #define CCM_CCGR6_QTIMER1(n)			((uint32_t)(((n) & 0x03) << 26))

  1453. #define CCM_CCGR6_LPI2C4_SERIAL(n)		((uint32_t)(((n) & 0x03) << 24))

  1454. #define CCM_CCGR6_ANADIG(n)			((uint32_t)(((n) & 0x03) << 22))

  1455. #define CCM_CCGR6_SIM_PER(n)			((uint32_t)(((n) & 0x03) << 20)) /* IMXRT1052 */

  1456. #define CCM_CCGR6_AXBS_P(n)			((uint32_t)(((n) & 0x03) << 20)) /* IMXRT1062 */

  1457. #define CCM_CCGR6_AIPS_TZ3(n)			((uint32_t)(((n) & 0x03) << 18))

  1458. #define CCM_CCGR6_QTIMER4(n)			((uint32_t)(((n) & 0x03) << 16))

  1459. #define CCM_CCGR6_LPUART8(n)			((uint32_t)(((n) & 0x03) << 14))

  1460. #define CCM_CCGR6_TRNG(n)			((uint32_t)(((n) & 0x03) << 12))

  1461. #define CCM_CCGR6_FLEXSPI(n)			((uint32_t)(((n) & 0x03) << 10))

  1462. #define CCM_CCGR6_IPMUX4(n)			((uint32_t)(((n) & 0x03) << 8))

  1463. #define CCM_CCGR6_DCDC(n)			((uint32_t)(((n) & 0x03) << 6))

  1464. #define CCM_CCGR6_USDHC2(n)			((uint32_t)(((n) & 0x03) << 4))

  1465. #define CCM_CCGR6_USDHC1(n)			((uint32_t)(((n) & 0x03) << 2))

  1466. #define CCM_CCGR6_USBOH3(n)			((uint32_t)(((n) & 0x03) << 0))

  1467. #define CCM_CCGR7_FLEXIO3(n)			((uint32_t)(((n) & 0x03) << 12))

  1468. #define CCM_CCGR7_APIS_LITE(n)			((uint32_t)(((n) & 0x03) << 10))

  1469. #define CCM_CCGR7_CAN3_SERIAL(n)		((uint32_t)(((n) & 0x03) << 8))

  1470. #define CCM_CCGR7_CAN3(n)			((uint32_t)(((n) & 0x03) << 6))

  1471. #define CCM_CCGR7_AXBS_L(n)			((uint32_t)(((n) & 0x03) << 4))

  1472. #define CCM_CCGR7_FLEXSPI2(n)			((uint32_t)(((n) & 0x03) << 2))

  1473. #define CCM_CCGR7_ENET2(n)			((uint32_t)(((n) & 0x03) << 0))

  1474. #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI		((uint32_t)(1<<30))

  1475. #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI		((uint32_t)(1<<28))

  1476. #define CCM_CMEOR_MOD_EN_OV_TRNG		((uint32_t)(1<<9))

  1477. #define CCM_CMEOR_MOD_EN_USDHC			((uint32_t)(1<<7))

  1478. #define CCM_CMEOR_MOD_EN_OV_PIT			((uint32_t)(1<<6))

  1479. #define CCM_CMEOR_MOD_EN_OV_GPT			((uint32_t)(1<<5))

  1480. 

  1481. #define CCM_CSCMR1_SAI1_CLK_SEL_MASK		(CCM_CSCMR1_SAI1_CLK_SEL(0x03))

  1482. #define CCM_CS1CDR_SAI1_CLK_PRED_MASK		(CCM_CS1CDR_SAI1_CLK_PRED(0x07))

  1483. #define CCM_CS1CDR_SAI1_CLK_PODF_MASK		(CCM_CS1CDR_SAI1_CLK_PODF(0x3f))

  1484. #define CCM_CSCMR1_SAI2_CLK_SEL_MASK		(CCM_CSCMR1_SAI2_CLK_SEL(0x03))

  1485. #define CCM_CS2CDR_SAI2_CLK_PRED_MASK		(CCM_CS2CDR_SAI2_CLK_PRED(0x07))

  1486. #define CCM_CS2CDR_SAI2_CLK_PODF_MASK		(CCM_CS2CDR_SAI2_CLK_PODF(0x3f))

  1487. #define CCM_CSCMR1_SAI3_CLK_SEL_MASK		(CCM_CSCMR1_SAI3_CLK_SEL(0x03))

  1488. #define CCM_CS1CDR_SAI3_CLK_PRED_MASK		(CCM_CS1CDR_SAI3_CLK_PRED(0x07))

  1489. #define CCM_CS1CDR_SAI3_CLK_PODF_MASK		(CCM_CS1CDR_SAI3_CLK_PODF(0x3f))

  1490. #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK		(CCM_CDCDR_SPDIF0_CLK_SEL(0x03))

  1491. #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(CCM_CDCDR_SPDIF0_CLK_PRED(0x07))

  1492. #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(CCM_CDCDR_SPDIF0_CLK_PODF(0x07))

  1493. 

  1494. // 14.8: page 1096

  1495. #define IMXRT_CCM_ANALOG	(*(IMXRT_REGISTER32_t *)0x400D8000)

  1496. #define CCM_ANALOG_PLL_ARM		(IMXRT_CCM_ANALOG.offset000)

  1497. #define CCM_ANALOG_PLL_ARM_SET		(IMXRT_CCM_ANALOG.offset004)

  1498. #define CCM_ANALOG_PLL_ARM_CLR		(IMXRT_CCM_ANALOG.offset008)

  1499. #define CCM_ANALOG_PLL_ARM_TOG		(IMXRT_CCM_ANALOG.offset00C)

  1500. #define CCM_ANALOG_PLL_USB1		(IMXRT_CCM_ANALOG.offset010)

  1501. #define CCM_ANALOG_PLL_USB1_SET		(IMXRT_CCM_ANALOG.offset014)

  1502. #define CCM_ANALOG_PLL_USB1_CLR		(IMXRT_CCM_ANALOG.offset018)

  1503. #define CCM_ANALOG_PLL_USB1_TOG		(IMXRT_CCM_ANALOG.offset01C)

  1504. #define CCM_ANALOG_PLL_USB2		(IMXRT_CCM_ANALOG.offset020)

  1505. #define CCM_ANALOG_PLL_USB2_SET		(IMXRT_CCM_ANALOG.offset024)

  1506. #define CCM_ANALOG_PLL_USB2_CLR		(IMXRT_CCM_ANALOG.offset028)

  1507. #define CCM_ANALOG_PLL_USB2_TOG		(IMXRT_CCM_ANALOG.offset02C)

  1508. #define CCM_ANALOG_PLL_SYS		(IMXRT_CCM_ANALOG.offset030)

  1509. #define CCM_ANALOG_PLL_SYS_SET		(IMXRT_CCM_ANALOG.offset034)

  1510. #define CCM_ANALOG_PLL_SYS_CLR		(IMXRT_CCM_ANALOG.offset038)

  1511. #define CCM_ANALOG_PLL_SYS_TOG		(IMXRT_CCM_ANALOG.offset03C)

  1512. #define CCM_ANALOG_PLL_SYS_SS		(IMXRT_CCM_ANALOG.offset040)

  1513. #define CCM_ANALOG_PLL_SYS_NUM		(IMXRT_CCM_ANALOG.offset050)

  1514. #define CCM_ANALOG_PLL_SYS_DENOM	(IMXRT_CCM_ANALOG.offset060)

  1515. #define CCM_ANALOG_PLL_AUDIO		(IMXRT_CCM_ANALOG.offset070)

  1516. #define CCM_ANALOG_PLL_AUDIO_SET	(IMXRT_CCM_ANALOG.offset074)

  1517. #define CCM_ANALOG_PLL_AUDIO_CLR	(IMXRT_CCM_ANALOG.offset078)

  1518. #define CCM_ANALOG_PLL_AUDIO_TOG	(IMXRT_CCM_ANALOG.offset07C)

  1519. #define CCM_ANALOG_PLL_AUDIO_NUM	(IMXRT_CCM_ANALOG.offset080)

  1520. #define CCM_ANALOG_PLL_AUDIO_DENOM	(IMXRT_CCM_ANALOG.offset090)

  1521. #define CCM_ANALOG_PLL_VIDEO		(IMXRT_CCM_ANALOG.offset0A0)

  1522. #define CCM_ANALOG_PLL_VIDEO_SET	(IMXRT_CCM_ANALOG.offset0A4)

  1523. #define CCM_ANALOG_PLL_VIDEO_CLR	(IMXRT_CCM_ANALOG.offset0A8)

  1524. #define CCM_ANALOG_PLL_VIDEO_TOG	(IMXRT_CCM_ANALOG.offset0AC)

  1525. #define CCM_ANALOG_PLL_VIDEO_NUM	(IMXRT_CCM_ANALOG.offset0B0)

  1526. #define CCM_ANALOG_PLL_VIDEO_DENOM	(IMXRT_CCM_ANALOG.offset0C0)

  1527. #define CCM_ANALOG_PLL_ENET		(IMXRT_CCM_ANALOG.offset0EC)

  1528. #define CCM_ANALOG_PLL_ENET_SET		(IMXRT_CCM_ANALOG.offset0E4)

  1529. #define CCM_ANALOG_PLL_ENET_CLR		(IMXRT_CCM_ANALOG.offset0E8)

  1530. #define CCM_ANALOG_PLL_ENET_TOG		(IMXRT_CCM_ANALOG.offset0EC)

  1531. #define CCM_ANALOG_PFD_480		(IMXRT_CCM_ANALOG.offset0F0)

  1532. #define CCM_ANALOG_PFD_480_SET		(IMXRT_CCM_ANALOG.offset0F4)

  1533. #define CCM_ANALOG_PFD_480_CLR		(IMXRT_CCM_ANALOG.offset0F8)

  1534. #define CCM_ANALOG_PFD_480_TOG		(IMXRT_CCM_ANALOG.offset0FC)

  1535. #define CCM_ANALOG_PFD_528		(IMXRT_CCM_ANALOG.offset100)

  1536. #define CCM_ANALOG_PFD_528_SET		(IMXRT_CCM_ANALOG.offset104)

  1537. #define CCM_ANALOG_PFD_528_CLR		(IMXRT_CCM_ANALOG.offset108)

  1538. #define CCM_ANALOG_PFD_528_TOG		(IMXRT_CCM_ANALOG.offset10C)

  1539. #define CCM_ANALOG_MISC0		(IMXRT_CCM_ANALOG.offset150)

  1540. #define CCM_ANALOG_MISC0_SET		(IMXRT_CCM_ANALOG.offset154)

  1541. #define CCM_ANALOG_MISC0_CLR		(IMXRT_CCM_ANALOG.offset158)

  1542. #define CCM_ANALOG_MISC0_TOG		(IMXRT_CCM_ANALOG.offset15C)

  1543. #define CCM_ANALOG_MISC1		(IMXRT_CCM_ANALOG.offset160)

  1544. #define CCM_ANALOG_MISC1_SET		(IMXRT_CCM_ANALOG.offset164)

  1545. #define CCM_ANALOG_MISC1_CLR		(IMXRT_CCM_ANALOG.offset168)

  1546. #define CCM_ANALOG_MISC1_TOG		(IMXRT_CCM_ANALOG.offset16C)

  1547. #define CCM_ANALOG_MISC2		(IMXRT_CCM_ANALOG.offset170)

  1548. #define CCM_ANALOG_MISC2_SET		(IMXRT_CCM_ANALOG.offset174)

  1549. #define CCM_ANALOG_MISC2_CLR		(IMXRT_CCM_ANALOG.offset178)

  1550. #define CCM_ANALOG_MISC2_TOG		(IMXRT_CCM_ANALOG.offset17C)

  1551. #define CCM_ANALOG_PLL_ARM_LOCK			((uint32_t)(1<<31))

  1552. #define CCM_ANALOG_PLL_ARM_BYPASS		((uint32_t)(1<<16))

  1553. #define CCM_ANALOG_PLL_ARM_ENABLE		((uint32_t)(1<<13))

  1554. #define CCM_ANALOG_PLL_ARM_POWERDOWN		((uint32_t)(1<<12))

  1555. #define CCM_ANALOG_PLL_ARM_DIV_SELECT(n)	((uint32_t)(((n) & 0x7F) << 0))

  1556. #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK	((uint32_t)(0x7F << 0))

  1557. #define CCM_ANALOG_PLL_USB1_LOCK		((uint32_t)(1<<31))

  1558. #define CCM_ANALOG_PLL_USB1_BYPASS		((uint32_t)(1<<16))

  1559. #define CCM_ANALOG_PLL_USB1_ENABLE		((uint32_t)(1<<13))

  1560. #define CCM_ANALOG_PLL_USB1_POWER		((uint32_t)(1<<12))

  1561. #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS		((uint32_t)(1<<6))

  1562. #define CCM_ANALOG_PLL_USB1_DIV_SELECT		((uint32_t)(1<<1))

  1563. #define CCM_ANALOG_PLL_USB2_LOCK		((uint32_t)(1<<31))

  1564. #define CCM_ANALOG_PLL_USB2_BYPASS		((uint32_t)(1<<16))

  1565. #define CCM_ANALOG_PLL_USB2_ENABLE		((uint32_t)(1<<13))

  1566. #define CCM_ANALOG_PLL_USB2_POWER		((uint32_t)(1<<12))

  1567. #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS		((uint32_t)(1<<6))

  1568. #define CCM_ANALOG_PLL_USB2_DIV_SELECT		((uint32_t)(1<<1))

  1569. #define CCM_ANALOG_PLL_SYS_LOCK			((uint32_t)(1<<31))

  1570. #define CCM_ANALOG_PLL_SYS_BYPASS		((uint32_t)(1<<16))

  1571. #define CCM_ANALOG_PLL_SYS_ENABLE		((uint32_t)(1<<13))

  1572. #define CCM_ANALOG_PLL_SYS_POWERDOWN		((uint32_t)(1<<12))

  1573. #define CCM_ANALOG_PLL_SYS_DIV_SELECT		((uint32_t)(1<<1))

  1574. #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(n)	((uint32_t)(((n) & 0x03) <<19)) 

  1575. #define CCM_ANALOG_PLL_AUDIO_BYPASS		((uint32_t)(1<<16)) 

  1576. #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(n)	((uint32_t)(((n) & 0x03) <<14)) 

  1577. #define CCM_ANALOG_PLL_AUDIO_ENABLE		((uint32_t)(1<<13)) 

  1578. #define CCM_ANALOG_PLL_AUDIO_POWERDOWN		((uint32_t)(1<<12)) 

  1579. #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n)	((uint32_t)((n) & ((1<<6)-1)))

  1580. #define CCM_ANALOG_PLL_VIDEO_LOCK		((uint32_t)(1<<31))

  1581. #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(n)	((uint32_t)(((n) & 0x03) << 19))

  1582. #define CCM_ANALOG_PLL_VIDEO_BYPASS		((uint32_t)(1<<16))

  1583. #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(n)	((uint32_t)(((n) & 0x03) << 14))

  1584. #define CCM_ANALOG_PLL_VIDEO_ENABLE		((uint32_t)(1<<13))

  1585. #define CCM_ANALOG_PLL_VIDEO_POWERDOWN		((uint32_t)(1<<12))

  1586. #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n)	((uint32_t)(((n) & 0x7F) << 0))

  1587. #define CCM_ANALOG_PLL_ENET_LOCK		((uint32_t)(1<<31))

  1588. #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN	((uint32_t)(1<<21))

  1589. #define CCM_ANALOG_PLL_ENET_ENET2_REF_EN	((uint32_t)(1<<20))

  1590. #define CCM_ANALOG_PLL_ENET_BYPASS		((uint32_t)(1<<16))

  1591. #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(n)	((uint32_t)(((n) & 0x03) << 14))

  1592. #define CCM_ANALOG_PLL_ENET_ENABLE		((uint32_t)(1<<13))

  1593. #define CCM_ANALOG_PLL_ENET_POWERDOWN		((uint32_t)(1<<12))

  1594. #define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(n)	((uint32_t)(((n) & 0x03) << 2))

  1595. #define CCM_ANALOG_PLL_ENET_DIV_SELECT(n)	((uint32_t)(((n) & 0x03) << 0))

  1596. #define CCM_ANALOG_MISC0_XTAL_24M_PWD		((uint32_t)(1<<30))

  1597. #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE	((uint32_t)(1<<29))

  1598. #define CCM_ANALOG_MISC0_CLKGATE_DELAY(n)	((uint32_t)(((n) & 0x07) << 26))

  1599. #define CCM_ANALOG_MISC0_CLKGATE_CTRL		((uint32_t)(1<<25))

  1600. #define CCM_ANALOG_MISC0_OSC_XTALOK_EN		((uint32_t)(1<<16))

  1601. #define CCM_ANALOG_MISC0_OSC_XTALOK		((uint32_t)(1<<15))

  1602. #define CCM_ANALOG_MISC0_OSC_I(n)		((uint32_t)(((n) & 0x03) << 13))

  1603. #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS	((uint32_t)(1<<12))

  1604. #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n)	((uint32_t)(((n) & 0x03) << 10))

  1605. #define CCM_ANALOG_MISC0_REFTOP_VBGUP		((uint32_t)(1<<7))

  1606. #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n)	((uint32_t)(((n) & 0x07) << 4))

  1607. #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF	((uint32_t)(1<<3))

  1608. #define CCM_ANALOG_MISC0_REFTOP_PWD		((uint32_t)(1<<0))

  1609. #define CCM_ANALOG_MISC1_IRQ_DIG_BO		((uint32_t)(1<<31))

  1610. #define CCM_ANALOG_MISC1_IRQ_ANA_BO		((uint32_t)(1<<30))

  1611. #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH		((uint32_t)(1<<29))

  1612. #define CCM_ANALOG_MISC1_IRQ_TEMPLOW		((uint32_t)(1<<28))

  1613. #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC		((uint32_t)(1<<27))

  1614. #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN	((uint32_t)(1<<17))

  1615. #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN	((uint32_t)(1<<16))

  1616. #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN		((uint32_t)(1<<12))

  1617. #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN		((uint32_t)(1<<10))

  1618. #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(n)	((uint32_t)(((n) & 0x1F) << 0))

  1619. #define CCM_ANALOG_MISC2_VIDEO_DIV(n)		((uint32_t)(((n) & 0x03) << 30))

  1620. #define CCM_ANALOG_MISC2_REG2_STEP_TIME(n)	((uint32_t)(((n) & 0x03) << 28))

  1621. #define CCM_ANALOG_MISC2_REG1_STEP_TIME(n)	((uint32_t)(((n) & 0x03) << 26))

  1622. #define CCM_ANALOG_MISC2_REG0_STEP_TIME(n)	((uint32_t)(((n) & 0x03) << 24))

  1623. #define CCM_ANALOG_MISC2_DIV_MSB		((uint32_t)(1<<23))

  1624. #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB		((uint32_t)(1<<23))

  1625. #define CCM_ANALOG_MISC2_REG2_OK		((uint32_t)(1<<22))

  1626. #define CCM_ANALOG_MISC2_REG2_ENABLE_BO		((uint32_t)(1<<21))

  1627. #define CCM_ANALOG_MISC2_REG2_BO_STATUS		((uint32_t)(1<<19))

  1628. #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(n)	((uint32_t)(((n) & 0x07) << 16))

  1629. #define CCM_ANALOG_MISC2_DIV_LSB		((uint32_t)(1<<15))

  1630. #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB		((uint32_t)(1<<15))

  1631. #define CCM_ANALOG_MISC2_REG1_OK		((uint32_t)(1<<14))

  1632. #define CCM_ANALOG_MISC2_REG1_ENABLE_BO		((uint32_t)(1<<13))

  1633. #define CCM_ANALOG_MISC2_REG1_BO_STATUS		((uint32_t)(1<<11))

  1634. #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(n)	((uint32_t)(((n) & 0x07) << 8))

  1635. #define CCM_ANALOG_MISC2_PLL3_DISABLE		((uint32_t)(1<<7))

  1636. #define CCM_ANALOG_MISC2_REG0_OK		((uint32_t)(1<<6))

  1637. #define CCM_ANALOG_MISC2_REG0_ENABLE_BO		((uint32_t)(1<<5))

  1638. #define CCM_ANALOG_MISC2_REG0_BO_STATUS		((uint32_t)(1<<3))

  1639. #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(n)	((uint32_t)(((n) & 0x07) << 0))

  1640. #define CCM_ANALOG_PLL_AUDIO_NUM_MASK		(((1<<29)-1))

  1641. #define CCM_ANALOG_PLL_AUDIO_DENOM_MASK		(((1<<29)-1))

  1642. #define CCM_ANALOG_PLL_AUDIO_LOCK		((uint32_t)(1<<31))

  1643. 

  1644. 

  1645. // 34.8: page 1818

  1646. #define IMXRT_CSI		(*(IMXRT_REGISTER32_t *)0x402BC000)

  1647. #define CSI_CSICR1			(IMXRT_CSI.offset000)

  1648. #define CSI_CSICR2			(IMXRT_CSI.offset004)

  1649. #define CSI_CSICR3			(IMXRT_CSI.offset008)

  1650. #define CSI_CSISTATFIFO			(IMXRT_CSI.offset00C)

  1651. #define CSI_CSIRFIFO			(IMXRT_CSI.offset010)

  1652. #define CSI_CSIRXCNT			(IMXRT_CSI.offset014)

  1653. #define CSI_CSISR			(IMXRT_CSI.offset018)

  1654. #define CSI_CSIDMASA_STATFIFO		(IMXRT_CSI.offset020)

  1655. #define CSI_CSIDMATS_STATFIFO		(IMXRT_CSI.offset024)

  1656. #define CSI_CSIDMASA_FB1		(IMXRT_CSI.offset028)

  1657. #define CSI_CSIDMASA_FB2		(IMXRT_CSI.offset02C)

  1658. #define CSI_CSIFBUF_PARA		(IMXRT_CSI.offset030)

  1659. #define CSI_CSIIMAG_PARA		(IMXRT_CSI.offset034)

  1660. #define CSI_CSICR18			(IMXRT_CSI.offset048)

  1661. #define CSI_CSICR19			(IMXRT_CSI.offset04C)

  1662. 

  1663. #define CSI_CSICR1_SWAP16_EN                    ((uint32_t)(1<<31))

  1664. #define CSI_CSICR1_EXT_VSYNC                    ((uint32_t)(1<<30))

  1665. #define CSI_CSICR1_EOF_INT_EN                   ((uint32_t)(1<<29))

  1666. #define CSI_CSICR1_PrP_IF_EN                    ((uint32_t)(1<<28))

  1667. #define CSI_CSICR1_CCIR_MODE                    ((uint32_t)(1<<27))

  1668. #define CSI_CSICR1_COF_INT_EN                   ((uint32_t)(1<<26))

  1669. #define CSI_CSICR1_SF_OR_INTEN                  ((uint32_t)(1<<25))

  1670. #define CSI_CSICR1_RF_OR_INTEN                  ((uint32_t)(1<<24))

  1671. #define CSI_CSICR1_SFF_DMA_DONE_INTEN           ((uint32_t)(1<<22))

  1672. #define CSI_CSICR1_STATFF_INTEN                 ((uint32_t)(1<<21))

  1673. #define CSI_CSICR1_FB2_DMA_DONE_INTEN           ((uint32_t)(1<<20))

  1674. #define CSI_CSICR1_FB1_DMA_DONE_INTEN           ((uint32_t)(1<<19))

  1675. #define CSI_CSICR1_RXFF_INTEN                   ((uint32_t)(1<<18))

  1676. #define CSI_CSICR1_SOF_POL                      ((uint32_t)(1<<17))

  1677. #define CSI_CSICR1_SOF_INTEN                    ((uint32_t)(1<<16))

  1678. #define CSI_CSICR1_HSYNC_POL                    ((uint32_t)(1<<11))

  1679. #define CSI_CSICR1_CCIR_EN                      ((uint32_t)(1<<10))

  1680. #define CSI_CSICR1_FCC                          ((uint32_t)(1<<8))

  1681. #define CSI_CSICR1_PACK_DIR                     ((uint32_t)(1<<7))

  1682. #define CSI_CSICR1_CLR_STATFIFO                 ((uint32_t)(1<<6))

  1683. #define CSI_CSICR1_CLR_RXFIFO                   ((uint32_t)(1<<5))

  1684. #define CSI_CSICR1_GCLK_MODE                    ((uint32_t)(1<<4))

  1685. #define CSI_CSICR1_INV_DATA                     ((uint32_t)(1<<3))

  1686. #define CSI_CSICR1_INV_PCLK                     ((uint32_t)(1<<2))

  1687. #define CSI_CSICR1_REDGE                        ((uint32_t)(1<<1))

  1688. #define CSI_CSICR1_PIXEL_BIT                    ((uint32_t)(1<<0))

  1689. 

  1690. #define CSI_CSICR2_DMA_BURST_TYPE_RFF(n)        ((uint32_t)(((n) & 0x3)<<30))

  1691. #define CSI_CSICR2_DMA_BURST_TYPE_SFF(n)        ((uint32_t)(((n) & 0x3)<<28))

  1692. #define CSI_CSICR2_DRM                          ((uint32_t)(1<<26))

  1693. #define CSI_CSICR2_AFS(n)                       ((uint32_t)(((n) & 0x3)<<24))

  1694. #define CSI_CSICR2_SCE                          ((uint32_t)(1<<23))

  1695. #define CSI_CSICR2_BTS(n)                       ((uint32_t)(((n) & 0x3)<<19))

  1696. #define CSI_CSICR2_LVRM(n)                      ((uint32_t)(((n) & 0x7)<<16))

  1697. #define CSI_CSICR2_VSC(n)                       ((uint32_t)(((n) & 0xff)<<8))

  1698. #define CSI_CSICR2_HSC(n)                       ((uint32_t)(((n) & 0xff)<<0))

  1699.     

  1700. #define CSI_CSICR3_FRMCNT(n)                    ((uint32_t)(((n) & 0xffff)<<16))

  1701. #define CSI_CSICR3_FRMCNT_RST                   ((uint32_t)(1<<15))

  1702. #define CSI_CSICR3_DMA_REFLASH_RFF              ((uint32_t)(1<<14))

  1703. #define CSI_CSICR3_DMA_REFLASH_SFF              ((uint32_t)(1<<13))

  1704. #define CSI_CSICR3_DMA_REQ_EN_RFF               ((uint32_t)(1<<12))

  1705. #define CSI_CSICR3_DMA_REQ_EN_SFF               ((uint32_t)(1<<11))

  1706. #define CSI_CSICR3_STATFF_LEVEL(n)              ((uint32_t)(((n) & 0x7)<<8))

  1707. #define CSI_CSICR3_HRESP_ERR_EN                 ((uint32_t)(1<<7))

  1708. #define CSI_CSICR3_RxFF_LEVEL(n)                ((uint32_t)(((n) & 0x7)<<4))

  1709. #define CSI_CSICR3_TWO_8BIT_SENSOR              ((uint32_t)(1<<3))

  1710. #define CSI_CSICR3_ZERO_PACK_EN                 ((uint32_t)(1<<2))

  1711. #define CSI_CSICR3_ECC_INT_EN                   ((uint32_t)(1<<1))

  1712. #define CSI_CSICR3_ECC_AUTO_EN                  ((uint32_t)(1<<0))

  1713. 

  1714. #define CSI_CSISR_BASEADDR_CHHANGE_ERROR        ((uint32_t)(1<<28))

  1715. #define CSI_CSISR_DMA_FIELD0_DONE               ((uint32_t)(1<<27))

  1716. #define CSI_CSISR_DMA_FIELD1_DONE               ((uint32_t)(1<<26))

  1717. #define CSI_CSISR_SF_OR_INT                     ((uint32_t)(1<<25))

  1718. #define CSI_CSISR_RF_OR_INT                     ((uint32_t)(1<<24))

  1719. #define CSI_CSISR_DMA_TSF_DONE_SFF              ((uint32_t)(1<<22))

  1720. #define CSI_CSISR_STATFF_INT                    ((uint32_t)(1<<21))

  1721. #define CSI_CSISR_DMA_TSF_DONE_FB2              ((uint32_t)(1<<20))

  1722. #define CSI_CSISR_DMA_TSF_DONE_FB1              ((uint32_t)(1<<19))

  1723. #define CSI_CSISR_RxFF_INT                      ((uint32_t)(1<<18))

  1724. #define CSI_CSISR_EOF_INT                       ((uint32_t)(1<<17))

  1725. #define CSI_CSISR_SOF_INT                       ((uint32_t)(1<<16))

  1726. #define CSI_CSISR_F2_INT                        ((uint32_t)(1<<15))

  1727. #define CSI_CSISR_F1_INT                        ((uint32_t)(1<<14))

  1728. #define CSI_CSISR_COF_INT                       ((uint32_t)(1<<13))

  1729. #define CSI_CSISR_HRESP_ERR_INT                 ((uint32_t)(1<<7))

  1730. #define CSI_CSISR_ECC_INT                       ((uint32_t)(1<<1))

  1731. #define CSI_CSISR_DRDY                          ((uint32_t)(1<<0))

  1732. 

  1733. #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(n)  ((uint32_t)(((n) & 0xffff)<<16))

  1734. #define CSI_CSIFBUF_PARA_FBUF_STRIDE(n)         ((uint32_t)(((n) & 0xffff)<<0))

  1735. 

  1736. #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(n)         ((uint32_t)(((n) & 0xffff)<<16))

  1737. #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(n)        ((uint32_t)(((n) & 0xffff)<<0))

  1738. 

  1739. #define CSI_CSICR18_CSI_ENABLE                  ((uint32_t)(1<<31))

  1740. #define CSI_CSICR18_MASK_OPTION(n)              ((uint32_t)(((n) & 0x3)<<18))

  1741. #define CSI_CSICR18_AHB_HPROT(n)                ((uint32_t)(((n) & 0xf)<<12))

  1742. 

  1743. #define CSI_CSICR18_RGB888A_FORMAT_SEL          ((uint32_t)(1<<10))

  1744. #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE    ((uint32_t)(1<<9))

  1745. #define CSI_CSICR18_LAST_DMA_REQ_SEL            ((uint32_t)(1<<8))

  1746. #define CSI_CSICR18_DMA_FIELD1_DONE_IE          ((uint32_t)(1<<7))

  1747. #define CSI_CSICR18_FIELD0_DONE_IE              ((uint32_t)(1<<6))

  1748. #define CSI_CSICR18_BASEADDR_SWITCH_SEL         ((uint32_t)(1<<5))

  1749. #define CSI_CSICR18_BASEADDR_SWITCH_EN          ((uint32_t)(1<<4))

  1750. #define CSI_CSICR18_PARALLEL24_EN               ((uint32_t)(1<<3))

  1751. #define CSI_CSICR18_DEINTERLACE_EN              ((uint32_t)(1<<2))

  1752. 

  1753. #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(n) ((uint32_t)(((n) & 0xf)<<12))

  1754. 

  1755. 

  1756. // 18.7.1.1: page 1209

  1757. #define IMXRT_DCDC		(*(IMXRT_REGISTER32_t *)0x40080000)

  1758. #define DCDC_REG0			(IMXRT_DCDC.offset000)

  1759. #define DCDC_REG1			(IMXRT_DCDC.offset004)

  1760. #define DCDC_REG2			(IMXRT_DCDC.offset008)

  1761. #define DCDC_REG3			(IMXRT_DCDC.offset00C)

  1762. #define DCDC_REG0_STS_DC_OK			((uint32_t)(1<<31))

  1763. #define DCDC_REG0_XTAL_24M_OK			((uint32_t)(1<<29))

  1764. #define DCDC_REG0_CURRENT_ALERT_RESET		((uint32_t)(1<<28))

  1765. #define DCDC_REG0_XTALOK_DISABLE		((uint32_t)(1<<27))

  1766. #define DCDC_REG0_PWD_CMP_OFFSET		((uint32_t)(1<<26))

  1767. #define DCDC_REG0_LP_HIGH_HYS			((uint32_t)(1<<21))

  1768. #define DCDC_REG0_LP_OVERLOAD_FREQ_SEL		((uint32_t)(1<<20))

  1769. #define DCDC_REG0_LP_OVERLOAD_THRSH(n)		((uint32_t)(((n) & 0x03) << 18))

  1770. #define DCDC_REG0_PWD_HIGH_VOLT_DET		((uint32_t)(1<<17))

  1771. #define DCDC_REG0_EN_LP_OVERLOAD_SNS		((uint32_t)(1<<16))

  1772. #define DCDC_REG0_ADJ_POSLIMIT_BUCK(n)		((uint32_t)(((n) & 0x0F) << 12))

  1773. #define DCDC_REG0_PWD_CMP_BATT_DET		((uint32_t)(1<<11))

  1774. #define DCDC_REG0_OVERCUR_TRIG_ADJ(n)		((uint32_t)(((n) & 0x03) << 9))

  1775. #define DCDC_REG0_PWD_OVERCUR_DET		((uint32_t)(1<<8))

  1776. #define DCDC_REG0_CUR_SNS_THRSH(n)		((uint32_t)(((n) & 0x07) << 5))

  1777. #define DCDC_REG0_PWD_CUR_SNS_CMP		((uint32_t)(1<<4))

  1778. #define DCDC_REG0_PWD_OSC_INT			((uint32_t)(1<<3))

  1779. #define DCDC_REG0_SEL_CLK			((uint32_t)(1<<2))

  1780. #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH	((uint32_t)(1<<1))

  1781. #define DCDC_REG0_PWD_ZCD			((uint32_t)(1<<0))

  1782. #define DCDC_REG1_VBG_TRIM(n)			((uint32_t)(((n) & 0x1F) << 24))

  1783. #define DCDC_REG1_LOOPCTRL_EN_HYST		((uint32_t)(1<<23))

  1784. #define DCDC_REG1_LOOPCTRL_HST_THRESH		((uint32_t)(1<<21))

  1785. #define DCDC_REG1_LP_CMP_ISRC_SEL(n)		((uint32_t)(((n) & 0x03) << 12))

  1786. #define DCDC_REG1_REG_RLOAD_SW			((uint32_t)(1<<9))

  1787. #define DCDC_REG1_REG_FBK_SEL(n)		((uint32_t)(((n) & 0x03) << 7))

  1788. #define DCDC_REG2_DCM_SET_CTRL			((uint32_t)(1<<28))

  1789. #define DCDC_REG2_DISABLE_PULSE_SKIP		((uint32_t)(1<<27))

  1790. #define DCDC_REG2_LOOPCTRL_HYST_SIGN		((uint32_t)(1<<13))

  1791. #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH	((uint32_t)(1<<12))

  1792. #define DCDC_REG2_LOOPCTRL_EN_RCSCALE		((uint32_t)(((n) & 0x07) << 9))

  1793. #define DCDC_REG2_LOOPCTRL_DC_FF		((uint32_t)(((n) & 0x07) << 6))

  1794. #define DCDC_REG2_LOOPCTRL_DC_R			((uint32_t)(((n) & 0x0F) << 2))

  1795. #define DCDC_REG2_LOOPCTRL_DC_C			((uint32_t)(((n) & 0x03) << 0))

  1796. #define DCDC_REG3_DISABLE_STEP			((uint32_t)(1<<30))

  1797. #define DCDC_REG3_MISC_DISABLEFET_LOGIC		((uint32_t)(1<<28))

  1798. #define DCDC_REG3_MISC_DELAY_TIMING		((uint32_t)(1<<27))

  1799. #define DCDC_REG3_MINPWR_DC_HALFCLK		((uint32_t)(1<<24))

  1800. #define DCDC_REG3_TARGET_LP(n)			((uint32_t)(((n) & 0x07) << 8))

  1801. #define DCDC_REG3_TRG(n)			((uint32_t)(((n) & 0x1F) << 0))

  1802. #define DCDC_REG3_TRG_MASK			((uint32_t)(0x1F << 0))

  1803. 

  1804. // 5.6.1.1: page 85

  1805. #define IMXRT_DMAMUX		(*(IMXRT_REGISTER32_t *)0x400EC000)

  1806. #define DMAMUX_CHCFG0			(IMXRT_DMAMUX.offset000)

  1807. #define DMAMUX_CHCFG1			(IMXRT_DMAMUX.offset004)

  1808. #define DMAMUX_CHCFG2			(IMXRT_DMAMUX.offset008)

  1809. #define DMAMUX_CHCFG3			(IMXRT_DMAMUX.offset00C)

  1810. #define DMAMUX_CHCFG4			(IMXRT_DMAMUX.offset010)

  1811. #define DMAMUX_CHCFG5			(IMXRT_DMAMUX.offset014)

  1812. #define DMAMUX_CHCFG6			(IMXRT_DMAMUX.offset018)

  1813. #define DMAMUX_CHCFG7			(IMXRT_DMAMUX.offset01C)

  1814. #define DMAMUX_CHCFG8			(IMXRT_DMAMUX.offset020)

  1815. #define DMAMUX_CHCFG9			(IMXRT_DMAMUX.offset024)

  1816. #define DMAMUX_CHCFG10			(IMXRT_DMAMUX.offset028)

  1817. #define DMAMUX_CHCFG11			(IMXRT_DMAMUX.offset02C)

  1818. #define DMAMUX_CHCFG12			(IMXRT_DMAMUX.offset030)

  1819. #define DMAMUX_CHCFG13			(IMXRT_DMAMUX.offset034)

  1820. #define DMAMUX_CHCFG14			(IMXRT_DMAMUX.offset038)

  1821. #define DMAMUX_CHCFG15			(IMXRT_DMAMUX.offset03C)

  1822. #define DMAMUX_CHCFG16			(IMXRT_DMAMUX.offset040)

  1823. #define DMAMUX_CHCFG17			(IMXRT_DMAMUX.offset044)

  1824. #define DMAMUX_CHCFG18			(IMXRT_DMAMUX.offset048)

  1825. #define DMAMUX_CHCFG19			(IMXRT_DMAMUX.offset04C)

  1826. #define DMAMUX_CHCFG20			(IMXRT_DMAMUX.offset050)

  1827. #define DMAMUX_CHCFG21			(IMXRT_DMAMUX.offset054)

  1828. #define DMAMUX_CHCFG22			(IMXRT_DMAMUX.offset058)

  1829. #define DMAMUX_CHCFG23			(IMXRT_DMAMUX.offset05C)

  1830. #define DMAMUX_CHCFG24			(IMXRT_DMAMUX.offset060)

  1831. #define DMAMUX_CHCFG25			(IMXRT_DMAMUX.offset064)

  1832. #define DMAMUX_CHCFG26			(IMXRT_DMAMUX.offset068)

  1833. #define DMAMUX_CHCFG27			(IMXRT_DMAMUX.offset06C)

  1834. #define DMAMUX_CHCFG28			(IMXRT_DMAMUX.offset070)

  1835. #define DMAMUX_CHCFG29			(IMXRT_DMAMUX.offset074)

  1836. #define DMAMUX_CHCFG30			(IMXRT_DMAMUX.offset078)

  1837. #define DMAMUX_CHCFG31			(IMXRT_DMAMUX.offset07C)

  1838. #define DMAMUX_CHCFG_ENBL			((uint32_t)(1<<31))

  1839. #define DMAMUX_CHCFG_TRIG			((uint32_t)(1<<30))

  1840. #define DMAMUX_CHCFG_A_ON			((uint32_t)(1<<29))

  1841. 

  1842. // 6.6.5.1: page 116

  1843. typedef struct {

  1844. 	volatile uint32_t CR;	// 0

  1845. 	volatile uint32_t ES;	// 4

  1846. 	uint32_t unused1;	// 8

  1847. 	volatile uint32_t ERQ;	// C

  1848. 	uint32_t unused2;	// 10

  1849. 	volatile uint32_t EEI;	// 14

  1850. 	volatile uint8_t CEEI;	// 18

  1851. 	volatile uint8_t SEEI;	// 19

  1852. 	volatile uint8_t CERQ;	// 1A

  1853. 	volatile uint8_t SERQ;	// 1B

  1854. 	volatile uint8_t CDNE;	// 1C

  1855. 	volatile uint8_t SSRT;	// 1D

  1856. 	volatile uint8_t CERR;	// 1E

  1857. 	volatile uint8_t CINT;	// 1F

  1858. 	uint32_t unused3;	// 20

  1859. 	volatile uint32_t INT;	// 24

  1860. 	uint32_t unused4;	// 28

  1861. 	volatile uint32_t ERR;	// 2C

  1862. 	uint32_t unused5;	// 30

  1863. 	volatile uint32_t HRS;	// 34

  1864. 	uint32_t unused6;	// 38

  1865. 	uint32_t unused7;	// 3C

  1866. 	uint32_t unused8;	// 40

  1867. 	volatile uint32_t EARS;	// 44

  1868. 	uint32_t unused[46];

  1869. 	volatile uint8_t DCHPRI3;

  1870. 	volatile uint8_t DCHPRI2;

  1871. 	volatile uint8_t DCHPRI1;

  1872. 	volatile uint8_t DCHPRI0;

  1873. 	volatile uint8_t DCHPRI7;

  1874. 	volatile uint8_t DCHPRI6;

  1875. 	volatile uint8_t DCHPRI5;

  1876. 	volatile uint8_t DCHPRI4;

  1877. 	volatile uint8_t DCHPRI11;

  1878. 	volatile uint8_t DCHPRI10;

  1879. 	volatile uint8_t DCHPRI9;

  1880. 	volatile uint8_t DCHPRI8;

  1881. 	volatile uint8_t DCHPRI15;

  1882. 	volatile uint8_t DCHPRI14;

  1883. 	volatile uint8_t DCHPRI13;

  1884. 	volatile uint8_t DCHPRI12;

  1885. 	volatile uint8_t DCHPRI19;

  1886. 	volatile uint8_t DCHPRI18;

  1887. 	volatile uint8_t DCHPRI17;

  1888. 	volatile uint8_t DCHPRI16;

  1889. 	volatile uint8_t DCHPRI23;

  1890. 	volatile uint8_t DCHPRI22;

  1891. 	volatile uint8_t DCHPRI21;

  1892. 	volatile uint8_t DCHPRI20;

  1893. 	volatile uint8_t DCHPRI27;

  1894. 	volatile uint8_t DCHPRI26;

  1895. 	volatile uint8_t DCHPRI25;

  1896. 	volatile uint8_t DCHPRI24;

  1897. 	volatile uint8_t DCHPRI31;

  1898. 	volatile uint8_t DCHPRI30;

  1899. 	volatile uint8_t DCHPRI29;

  1900. 	volatile uint8_t DCHPRI28;

  1901. } IMXRT_DMA_t;

  1902. 

  1903. typedef struct {

  1904. 	volatile const void * volatile SADDR;

  1905. 	int16_t SOFF;

  1906. 	union {

  1907. 		uint16_t ATTR;

  1908. 		struct {

  1909. 			uint8_t ATTR_DST;

  1910. 			uint8_t ATTR_SRC;

  1911. 		};

  1912. 	};

  1913. 	union {

  1914. 		uint32_t NBYTES;

  1915. 		uint32_t NBYTES_MLNO;

  1916. 		uint32_t NBYTES_MLOFFNO;

  1917. 		uint32_t NBYTES_MLOFFYES;

  1918. 	};

  1919. 	int32_t SLAST;

  1920. 	volatile void * volatile DADDR;

  1921. 	int16_t DOFF;

  1922. 	union {

  1923. 		volatile uint16_t CITER;

  1924. 		volatile uint16_t CITER_ELINKYES;

  1925. 		volatile uint16_t CITER_ELINKNO;

  1926. 	};

  1927. 	int32_t DLASTSGA;

  1928. 	volatile uint16_t CSR;

  1929. 	union {

  1930. 		volatile uint16_t BITER;

  1931. 		volatile uint16_t BITER_ELINKYES;

  1932. 		volatile uint16_t BITER_ELINKNO;

  1933. 	};

  1934. } IMXRT_DMA_TCD_t;

  1935. #define IMXRT_DMA		(*(IMXRT_DMA_t *)0x400E8000)

  1936. #define DMA_CR				(IMXRT_DMA.CR)

  1937. #define DMA_ES				(IMXRT_DMA.ES)

  1938. #define DMA_ERQ				(IMXRT_DMA.ERQ)

  1939. #define DMA_EEI				(IMXRT_DMA.EEI)

  1940. #define DMA_CEEI			(IMXRT_DMA.CEEI)

  1941. #define DMA_SEEI			(IMXRT_DMA.SEEI)

  1942. #define DMA_CERQ			(IMXRT_DMA.CERQ)

  1943. #define DMA_SERQ			(IMXRT_DMA.SERQ)

  1944. #define DMA_CDNE			(IMXRT_DMA.CDNE)

  1945. #define DMA_SSRT			(IMXRT_DMA.SSRT)

  1946. #define DMA_CERR			(IMXRT_DMA.CERR)

  1947. #define DMA_CINT			(IMXRT_DMA.CINT)

  1948. #define DMA_INT				(IMXRT_DMA.INT)

  1949. #define DMA_ERR				(IMXRT_DMA.ERR)

  1950. #define DMA_HRS				(IMXRT_DMA.HRS)

  1951. #define DMA_EARS			(IMXRT_DMA.EARS)

  1952. #define DMA_DCHPRI3			(IMXRT_DMA.DCHPRI3)

  1953. #define DMA_DCHPRI2			(IMXRT_DMA.DCHPRI2)

  1954. #define DMA_DCHPRI1			(IMXRT_DMA.DCHPRI1)

  1955. #define DMA_DCHPRI0			(IMXRT_DMA.DCHPRI0)

  1956. #define DMA_DCHPRI7			(IMXRT_DMA.DCHPRI7)

  1957. #define DMA_DCHPRI6			(IMXRT_DMA.DCHPRI6)

  1958. #define DMA_DCHPRI5			(IMXRT_DMA.DCHPRI5)

  1959. #define DMA_DCHPRI4			(IMXRT_DMA.DCHPRI4)

  1960. #define DMA_DCHPRI11			(IMXRT_DMA.DCHPRI11)

  1961. #define DMA_DCHPRI10			(IMXRT_DMA.DCHPRI10)

  1962. #define DMA_DCHPRI9			(IMXRT_DMA.DCHPRI9)

  1963. #define DMA_DCHPRI8			(IMXRT_DMA.DCHPRI8)

  1964. #define DMA_DCHPRI15			(IMXRT_DMA.DCHPRI15)

  1965. #define DMA_DCHPRI14			(IMXRT_DMA.DCHPRI14)

  1966. #define DMA_DCHPRI13			(IMXRT_DMA.DCHPRI13)

  1967. #define DMA_DCHPRI12			(IMXRT_DMA.DCHPRI12)

  1968. #define DMA_DCHPRI19			(IMXRT_DMA.DCHPRI19)

  1969. #define DMA_DCHPRI18			(IMXRT_DMA.DCHPRI18)

  1970. #define DMA_DCHPRI17			(IMXRT_DMA.DCHPRI17)

  1971. #define DMA_DCHPRI16			(IMXRT_DMA.DCHPRI16)

  1972. #define DMA_DCHPRI23			(IMXRT_DMA.DCHPRI23)

  1973. #define DMA_DCHPRI22			(IMXRT_DMA.DCHPRI22)

  1974. #define DMA_DCHPRI21			(IMXRT_DMA.DCHPRI21)

  1975. #define DMA_DCHPRI20			(IMXRT_DMA.DCHPRI20)

  1976. #define DMA_DCHPRI27			(IMXRT_DMA.DCHPRI27)

  1977. #define DMA_DCHPRI26			(IMXRT_DMA.DCHPRI26)

  1978. #define DMA_DCHPRI25			(IMXRT_DMA.DCHPRI25)

  1979. #define DMA_DCHPRI24			(IMXRT_DMA.DCHPRI24)

  1980. #define DMA_DCHPRI31			(IMXRT_DMA.DCHPRI31)

  1981. #define DMA_DCHPRI30			(IMXRT_DMA.DCHPRI30)

  1982. #define DMA_DCHPRI29			(IMXRT_DMA.DCHPRI29)

  1983. #define DMA_DCHPRI28			(IMXRT_DMA.DCHPRI28)

  1984. 

  1985. #define DMA_CR_ACTIVE                   ((uint32_t)(1<<31))     // 1=DMA is executing

  1986. #define DMA_CR_CX                       ((uint32_t)(1<<17))     // Cancel Transfer

  1987. #define DMA_CR_ECX                      ((uint32_t)(1<<16))     // Error Cancel Transfer

  1988. #define DMA_CR_GRP1PRI                  ((uint32_t)(1<<10))

  1989. #define DMA_CR_GRP0PRI                  ((uint32_t)(1<<8))

  1990. #define DMA_CR_EMLM                     ((uint32_t)(1<<7))      // Enable Minor Loop Mapping

  1991. #define DMA_CR_CLM                      ((uint32_t)(1<<6))      // Continuous Link Mode

  1992. #define DMA_CR_HALT                     ((uint32_t)(1<<5))      // Halt DMA Operations

  1993. #define DMA_CR_HOE                      ((uint32_t)(1<<4))      // Halt On Error

  1994. #define DMA_CR_ERGA                     ((uint32_t)(1<<3))      // Enable Round Robin Group Arb

  1995. #define DMA_CR_ERCA                     ((uint32_t)(1<<2))      // Enable Round Robin Channel Arb

  1996. #define DMA_CR_EDBG                     ((uint32_t)(1<<1))      // Enable Debug

  1997. #define DMA_CEEI_CEEI(n)                ((uint8_t)(n & 0x1F))   // Clear Enable Error Interrupt

  1998. #define DMA_CEEI_CAEE                   ((uint8_t)1<<6)         // Clear All Enable Error Interrupts

  1999. #define DMA_CEEI_NOP                    ((uint8_t)1<<7)         // NOP

  2000. #define DMA_SEEI_SEEI(n)                ((uint8_t)(n & 0x1F))   // Set Enable Error Interrupt

  2001. #define DMA_SEEI_SAEE                   ((uint8_t)1<<6)         // Set All Enable Error Interrupts

  2002. #define DMA_SEEI_NOP                    ((uint8_t)1<<7)         // NOP

  2003. #define DMA_CERQ_CERQ(n)                ((uint8_t)(n & 0x1F))   // Clear Enable Request

  2004. #define DMA_CERQ_CAER                   ((uint8_t)1<<6)         // Clear All Enable Requests

  2005. #define DMA_CERQ_NOP                    ((uint8_t)1<<7)         // NOP

  2006. #define DMA_SERQ_SERQ(n)                ((uint8_t)(n & 0x1F))   // Set Enable Request

  2007. #define DMA_SERQ_SAER                   ((uint8_t)1<<6)         // Set All Enable Requests

  2008. #define DMA_SERQ_NOP                    ((uint8_t)1<<7)         // NOP

  2009. #define DMA_CDNE_CDNE(n)                ((uint8_t)(n & 0x1F))   // Clear Done Bit

  2010. #define DMA_CDNE_CADN                   ((uint8_t)1<<6)         // Clear All Done Bits

  2011. #define DMA_CDNE_NOP                    ((uint8_t)1<<7)         // NOP

  2012. #define DMA_SSRT_SSRT(n)                ((uint8_t)(n & 0x1F))   // Set Start Bit

  2013. #define DMA_SSRT_SAST                   ((uint8_t)1<<6)         // Set All Start Bits

  2014. #define DMA_SSRT_NOP                    ((uint8_t)1<<7)         // NOP

  2015. #define DMA_CERR_CERR(n)                ((uint8_t)(n & 0x1F))   // Clear Error Indicator

  2016. #define DMA_CERR_CAEI                   ((uint8_t)1<<6)         // Clear All Error Indicators

  2017. #define DMA_CERR_NOP                    ((uint8_t)1<<7)         // NOP

  2018. #define DMA_CINT_CINT(n)                ((uint8_t)(n & 0x1F))   // Clear Interrupt Request

  2019. #define DMA_CINT_CAIR                   ((uint8_t)1<<6)         // Clear All Interrupt Requests

  2020. #define DMA_CINT_NOP                    ((uint8_t)1<<7)         // NOP

  2021. 

  2022. #define IMXRT_DMA_TCD		((IMXRT_DMA_TCD_t *)0x400E9000)

  2023. #define DMA_TCD0_SADDR			(IMXRT_DMA_TCD[0].SADDR)

  2024. #define DMA_TCD0_SOFF			(IMXRT_DMA_TCD[0].SOFF)

  2025. #define DMA_TCD0_ATTR			(IMXRT_DMA_TCD[0].ATTR)

  2026. #define DMA_TCD0_NBYTES			(IMXRT_DMA_TCD[0].NBYTES)

  2027. #define DMA_TCD0_NBYTES_MLNO		(IMXRT_DMA_TCD[0].NBYTES_MLNO)

  2028. #define DMA_TCD0_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[0].NBYTES_MLOFFNO)

  2029. #define DMA_TCD0_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[0].NBYTES_MLOFFYES)

  2030. #define DMA_TCD0_SLAST			(IMXRT_DMA_TCD[0].SLAST)

  2031. #define DMA_TCD0_DADDR			(IMXRT_DMA_TCD[0].DADDR)

  2032. #define DMA_TCD0_DOFF			(IMXRT_DMA_TCD[0].DOFF)

  2033. #define DMA_TCD0_CITER			(IMXRT_DMA_TCD[0].CITER)

  2034. #define DMA_TCD0_CITER_ELINKYES		(IMXRT_DMA_TCD[0].CITER_ELINKYES)

  2035. #define DMA_TCD0_CITER_ELINKNO		(IMXRT_DMA_TCD[0].CITER_ELINKNO)

  2036. #define DMA_TCD0_DLASTSGA		(IMXRT_DMA_TCD[0].DLASTSGA)

  2037. #define DMA_TCD0_CSR			(IMXRT_DMA_TCD[0].CSR)

  2038. #define DMA_TCD0_BITER			(IMXRT_DMA_TCD[0].BITER)

  2039. #define DMA_TCD0_BITER_ELINKYES		(IMXRT_DMA_TCD[0].BITER_ELINKYES)

  2040. #define DMA_TCD0_BITER_ELINKNO		(IMXRT_DMA_TCD[0].BITER_ELINKNO)

  2041. 

  2042. #define DMA_TCD1_SADDR			(IMXRT_DMA_TCD[1].SADDR)

  2043. #define DMA_TCD1_SOFF			(IMXRT_DMA_TCD[1].SOFF)

  2044. #define DMA_TCD1_ATTR			(IMXRT_DMA_TCD[1].ATTR)

  2045. #define DMA_TCD1_NBYTES			(IMXRT_DMA_TCD[1].NBYTES)

  2046. #define DMA_TCD1_NBYTES_MLNO		(IMXRT_DMA_TCD[1].NBYTES_MLNO)

  2047. #define DMA_TCD1_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[1].NBYTES_MLOFFNO)

  2048. #define DMA_TCD1_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[1].NBYTES_MLOFFYES)

  2049. #define DMA_TCD1_SLAST			(IMXRT_DMA_TCD[1].SLAST)

  2050. #define DMA_TCD1_DADDR			(IMXRT_DMA_TCD[1].DADDR)

  2051. #define DMA_TCD1_DOFF			(IMXRT_DMA_TCD[1].DOFF)

  2052. #define DMA_TCD1_CITER			(IMXRT_DMA_TCD[1].CITER)

  2053. #define DMA_TCD1_CITER_ELINKYES		(IMXRT_DMA_TCD[1].CITER_ELINKYES)

  2054. #define DMA_TCD1_CITER_ELINKNO		(IMXRT_DMA_TCD[1].CITER_ELINKNO)

  2055. #define DMA_TCD1_DLASTSGA		(IMXRT_DMA_TCD[1].DLASTSGA)

  2056. #define DMA_TCD1_CSR			(IMXRT_DMA_TCD[1].CSR)

  2057. #define DMA_TCD1_BITER			(IMXRT_DMA_TCD[1].BITER)

  2058. #define DMA_TCD1_BITER_ELINKYES		(IMXRT_DMA_TCD[1].BITER_ELINKYES)

  2059. #define DMA_TCD1_BITER_ELINKNO		(IMXRT_DMA_TCD[1].BITER_ELINKNO)

  2060. 

  2061. #define DMA_TCD2_SADDR			(IMXRT_DMA_TCD[2].SADDR)

  2062. #define DMA_TCD2_SOFF			(IMXRT_DMA_TCD[2].SOFF)

  2063. #define DMA_TCD2_ATTR			(IMXRT_DMA_TCD[2].ATTR)

  2064. #define DMA_TCD2_NBYTES			(IMXRT_DMA_TCD[2].NBYTES)

  2065. #define DMA_TCD2_NBYTES_MLNO		(IMXRT_DMA_TCD[2].NBYTES_MLNO)

  2066. #define DMA_TCD2_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[2].NBYTES_MLOFFNO)

  2067. #define DMA_TCD2_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[2].NBYTES_MLOFFYES)

  2068. #define DMA_TCD2_SLAST			(IMXRT_DMA_TCD[2].SLAST)

  2069. #define DMA_TCD2_DADDR			(IMXRT_DMA_TCD[2].DADDR)

  2070. #define DMA_TCD2_DOFF			(IMXRT_DMA_TCD[2].DOFF)

  2071. #define DMA_TCD2_CITER			(IMXRT_DMA_TCD[2].CITER)

  2072. #define DMA_TCD2_CITER_ELINKYES		(IMXRT_DMA_TCD[2].CITER_ELINKYES)

  2073. #define DMA_TCD2_CITER_ELINKNO		(IMXRT_DMA_TCD[2].CITER_ELINKNO)

  2074. #define DMA_TCD2_DLASTSGA		(IMXRT_DMA_TCD[2].DLASTSGA)

  2075. #define DMA_TCD2_CSR			(IMXRT_DMA_TCD[2].CSR)

  2076. #define DMA_TCD2_BITER			(IMXRT_DMA_TCD[2].BITER)

  2077. #define DMA_TCD2_BITER_ELINKYES		(IMXRT_DMA_TCD[2].BITER_ELINKYES)

  2078. #define DMA_TCD2_BITER_ELINKNO		(IMXRT_DMA_TCD[2].BITER_ELINKNO)

  2079. 

  2080. #define DMA_TCD3_SADDR			(IMXRT_DMA_TCD[3].SADDR)

  2081. #define DMA_TCD3_SOFF			(IMXRT_DMA_TCD[3].SOFF)

  2082. #define DMA_TCD3_ATTR			(IMXRT_DMA_TCD[3].ATTR)

  2083. #define DMA_TCD3_NBYTES			(IMXRT_DMA_TCD[3].NBYTES)

  2084. #define DMA_TCD3_NBYTES_MLNO		(IMXRT_DMA_TCD[3].NBYTES_MLNO)

  2085. #define DMA_TCD3_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[3].NBYTES_MLOFFNO)

  2086. #define DMA_TCD3_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[3].NBYTES_MLOFFYES)

  2087. #define DMA_TCD3_SLAST			(IMXRT_DMA_TCD[3].SLAST)

  2088. #define DMA_TCD3_DADDR			(IMXRT_DMA_TCD[3].DADDR)

  2089. #define DMA_TCD3_DOFF			(IMXRT_DMA_TCD[3].DOFF)

  2090. #define DMA_TCD3_CITER			(IMXRT_DMA_TCD[3].CITER)

  2091. #define DMA_TCD3_CITER_ELINKYES		(IMXRT_DMA_TCD[3].CITER_ELINKYES)

  2092. #define DMA_TCD3_CITER_ELINKNO		(IMXRT_DMA_TCD[3].CITER_ELINKNO)

  2093. #define DMA_TCD3_DLASTSGA		(IMXRT_DMA_TCD[3].DLASTSGA)

  2094. #define DMA_TCD3_CSR			(IMXRT_DMA_TCD[3].CSR)

  2095. #define DMA_TCD3_BITER			(IMXRT_DMA_TCD[3].BITER)

  2096. #define DMA_TCD3_BITER_ELINKYES		(IMXRT_DMA_TCD[3].BITER_ELINKYES)

  2097. #define DMA_TCD3_BITER_ELINKNO		(IMXRT_DMA_TCD[3].BITER_ELINKNO)

  2098. 

  2099. #define DMA_TCD4_SADDR			(IMXRT_DMA_TCD[4].SADDR)

  2100. #define DMA_TCD4_SOFF			(IMXRT_DMA_TCD[4].SOFF)

  2101. #define DMA_TCD4_ATTR			(IMXRT_DMA_TCD[4].ATTR)

  2102. #define DMA_TCD4_NBYTES			(IMXRT_DMA_TCD[4].NBYTES)

  2103. #define DMA_TCD4_NBYTES_MLNO		(IMXRT_DMA_TCD[4].NBYTES_MLNO)

  2104. #define DMA_TCD4_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[4].NBYTES_MLOFFNO)

  2105. #define DMA_TCD4_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[4].NBYTES_MLOFFYES)

  2106. #define DMA_TCD4_SLAST			(IMXRT_DMA_TCD[4].SLAST)

  2107. #define DMA_TCD4_DADDR			(IMXRT_DMA_TCD[4].DADDR)

  2108. #define DMA_TCD4_DOFF			(IMXRT_DMA_TCD[4].DOFF)

  2109. #define DMA_TCD4_CITER			(IMXRT_DMA_TCD[4].CITER)

  2110. #define DMA_TCD4_CITER_ELINKYES		(IMXRT_DMA_TCD[4].CITER_ELINKYES)

  2111. #define DMA_TCD4_CITER_ELINKNO		(IMXRT_DMA_TCD[4].CITER_ELINKNO)

  2112. #define DMA_TCD4_DLASTSGA		(IMXRT_DMA_TCD[4].DLASTSGA)

  2113. #define DMA_TCD4_CSR			(IMXRT_DMA_TCD[4].CSR)

  2114. #define DMA_TCD4_BITER			(IMXRT_DMA_TCD[4].BITER)

  2115. #define DMA_TCD4_BITER_ELINKYES		(IMXRT_DMA_TCD[4].BITER_ELINKYES)

  2116. #define DMA_TCD4_BITER_ELINKNO		(IMXRT_DMA_TCD[4].BITER_ELINKNO)

  2117. 

  2118. #define DMA_TCD5_SADDR			(IMXRT_DMA_TCD[5].SADDR)

  2119. #define DMA_TCD5_SOFF			(IMXRT_DMA_TCD[5].SOFF)

  2120. #define DMA_TCD5_ATTR			(IMXRT_DMA_TCD[5].ATTR)

  2121. #define DMA_TCD5_NBYTES			(IMXRT_DMA_TCD[5].NBYTES)

  2122. #define DMA_TCD5_NBYTES_MLNO		(IMXRT_DMA_TCD[5].NBYTES_MLNO)

  2123. #define DMA_TCD5_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[5].NBYTES_MLOFFNO)

  2124. #define DMA_TCD5_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[5].NBYTES_MLOFFYES)

  2125. #define DMA_TCD5_SLAST			(IMXRT_DMA_TCD[5].SLAST)

  2126. #define DMA_TCD5_DADDR			(IMXRT_DMA_TCD[5].DADDR)

  2127. #define DMA_TCD5_DOFF			(IMXRT_DMA_TCD[5].DOFF)

  2128. #define DMA_TCD5_CITER			(IMXRT_DMA_TCD[5].CITER)

  2129. #define DMA_TCD5_CITER_ELINKYES		(IMXRT_DMA_TCD[5].CITER_ELINKYES)

  2130. #define DMA_TCD5_CITER_ELINKNO		(IMXRT_DMA_TCD[5].CITER_ELINKNO)

  2131. #define DMA_TCD5_DLASTSGA		(IMXRT_DMA_TCD[5].DLASTSGA)

  2132. #define DMA_TCD5_CSR			(IMXRT_DMA_TCD[5].CSR)

  2133. #define DMA_TCD5_BITER			(IMXRT_DMA_TCD[5].BITER)

  2134. #define DMA_TCD5_BITER_ELINKYES		(IMXRT_DMA_TCD[5].BITER_ELINKYES)

  2135. #define DMA_TCD5_BITER_ELINKNO		(IMXRT_DMA_TCD[5].BITER_ELINKNO)

  2136. 

  2137. #define DMA_TCD6_SADDR			(IMXRT_DMA_TCD[6].SADDR)

  2138. #define DMA_TCD6_SOFF			(IMXRT_DMA_TCD[6].SOFF)

  2139. #define DMA_TCD6_ATTR			(IMXRT_DMA_TCD[6].ATTR)

  2140. #define DMA_TCD6_NBYTES			(IMXRT_DMA_TCD[6].NBYTES)

  2141. #define DMA_TCD6_NBYTES_MLNO		(IMXRT_DMA_TCD[6].NBYTES_MLNO)

  2142. #define DMA_TCD6_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[6].NBYTES_MLOFFNO)

  2143. #define DMA_TCD6_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[6].NBYTES_MLOFFYES)

  2144. #define DMA_TCD6_SLAST			(IMXRT_DMA_TCD[6].SLAST)

  2145. #define DMA_TCD6_DADDR			(IMXRT_DMA_TCD[6].DADDR)

  2146. #define DMA_TCD6_DOFF			(IMXRT_DMA_TCD[6].DOFF)

  2147. #define DMA_TCD6_CITER			(IMXRT_DMA_TCD[6].CITER)

  2148. #define DMA_TCD6_CITER_ELINKYES		(IMXRT_DMA_TCD[6].CITER_ELINKYES)

  2149. #define DMA_TCD6_CITER_ELINKNO		(IMXRT_DMA_TCD[6].CITER_ELINKNO)

  2150. #define DMA_TCD6_DLASTSGA		(IMXRT_DMA_TCD[6].DLASTSGA)

  2151. #define DMA_TCD6_CSR			(IMXRT_DMA_TCD[6].CSR)

  2152. #define DMA_TCD6_BITER			(IMXRT_DMA_TCD[6].BITER)

  2153. #define DMA_TCD6_BITER_ELINKYES		(IMXRT_DMA_TCD[6].BITER_ELINKYES)

  2154. #define DMA_TCD6_BITER_ELINKNO		(IMXRT_DMA_TCD[6].BITER_ELINKNO)

  2155. 

  2156. #define DMA_TCD7_SADDR			(IMXRT_DMA_TCD[7].SADDR)

  2157. #define DMA_TCD7_SOFF			(IMXRT_DMA_TCD[7].SOFF)

  2158. #define DMA_TCD7_ATTR			(IMXRT_DMA_TCD[7].ATTR)

  2159. #define DMA_TCD7_NBYTES			(IMXRT_DMA_TCD[7].NBYTES)

  2160. #define DMA_TCD7_NBYTES_MLNO		(IMXRT_DMA_TCD[7].NBYTES_MLNO)

  2161. #define DMA_TCD7_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[7].NBYTES_MLOFFNO)

  2162. #define DMA_TCD7_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[7].NBYTES_MLOFFYES)

  2163. #define DMA_TCD7_SLAST			(IMXRT_DMA_TCD[7].SLAST)

  2164. #define DMA_TCD7_DADDR			(IMXRT_DMA_TCD[7].DADDR)

  2165. #define DMA_TCD7_DOFF			(IMXRT_DMA_TCD[7].DOFF)

  2166. #define DMA_TCD7_CITER			(IMXRT_DMA_TCD[7].CITER)

  2167. #define DMA_TCD7_CITER_ELINKYES		(IMXRT_DMA_TCD[7].CITER_ELINKYES)

  2168. #define DMA_TCD7_CITER_ELINKNO		(IMXRT_DMA_TCD[7].CITER_ELINKNO)

  2169. #define DMA_TCD7_DLASTSGA		(IMXRT_DMA_TCD[7].DLASTSGA)

  2170. #define DMA_TCD7_CSR			(IMXRT_DMA_TCD[7].CSR)

  2171. #define DMA_TCD7_BITER			(IMXRT_DMA_TCD[7].BITER)

  2172. #define DMA_TCD7_BITER_ELINKYES		(IMXRT_DMA_TCD[7].BITER_ELINKYES)

  2173. #define DMA_TCD7_BITER_ELINKNO		(IMXRT_DMA_TCD[7].BITER_ELINKNO)

  2174. 

  2175. #define DMA_TCD8_SADDR			(IMXRT_DMA_TCD[8].SADDR)

  2176. #define DMA_TCD8_SOFF			(IMXRT_DMA_TCD[8].SOFF)

  2177. #define DMA_TCD8_ATTR			(IMXRT_DMA_TCD[8].ATTR)

  2178. #define DMA_TCD8_NBYTES			(IMXRT_DMA_TCD[8].NBYTES)

  2179. #define DMA_TCD8_NBYTES_MLNO		(IMXRT_DMA_TCD[8].NBYTES_MLNO)

  2180. #define DMA_TCD8_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[8].NBYTES_MLOFFNO)

  2181. #define DMA_TCD8_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[8].NBYTES_MLOFFYES)

  2182. #define DMA_TCD8_SLAST			(IMXRT_DMA_TCD[8].SLAST)

  2183. #define DMA_TCD8_DADDR			(IMXRT_DMA_TCD[8].DADDR)

  2184. #define DMA_TCD8_DOFF			(IMXRT_DMA_TCD[8].DOFF)

  2185. #define DMA_TCD8_CITER			(IMXRT_DMA_TCD[8].CITER)

  2186. #define DMA_TCD8_CITER_ELINKYES		(IMXRT_DMA_TCD[8].CITER_ELINKYES)

  2187. #define DMA_TCD8_CITER_ELINKNO		(IMXRT_DMA_TCD[8].CITER_ELINKNO)

  2188. #define DMA_TCD8_DLASTSGA		(IMXRT_DMA_TCD[8].DLASTSGA)

  2189. #define DMA_TCD8_CSR			(IMXRT_DMA_TCD[8].CSR)

  2190. #define DMA_TCD8_BITER			(IMXRT_DMA_TCD[8].BITER)

  2191. #define DMA_TCD8_BITER_ELINKYES		(IMXRT_DMA_TCD[8].BITER_ELINKYES)

  2192. #define DMA_TCD8_BITER_ELINKNO		(IMXRT_DMA_TCD[8].BITER_ELINKNO)

  2193. 

  2194. #define DMA_TCD9_SADDR			(IMXRT_DMA_TCD[9].SADDR)

  2195. #define DMA_TCD9_SOFF			(IMXRT_DMA_TCD[9].SOFF)

  2196. #define DMA_TCD9_ATTR			(IMXRT_DMA_TCD[9].ATTR)

  2197. #define DMA_TCD9_NBYTES			(IMXRT_DMA_TCD[9].NBYTES)

  2198. #define DMA_TCD9_NBYTES_MLNO		(IMXRT_DMA_TCD[9].NBYTES_MLNO)

  2199. #define DMA_TCD9_NBYTES_MLOFFNO		(IMXRT_DMA_TCD[9].NBYTES_MLOFFNO)

  2200. #define DMA_TCD9_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[9].NBYTES_MLOFFYES)

  2201. #define DMA_TCD9_SLAST			(IMXRT_DMA_TCD[9].SLAST)

  2202. #define DMA_TCD9_DADDR			(IMXRT_DMA_TCD[9].DADDR)

  2203. #define DMA_TCD9_DOFF			(IMXRT_DMA_TCD[9].DOFF)

  2204. #define DMA_TCD9_CITER			(IMXRT_DMA_TCD[9].CITER)

  2205. #define DMA_TCD9_CITER_ELINKYES		(IMXRT_DMA_TCD[9].CITER_ELINKYES)

  2206. #define DMA_TCD9_CITER_ELINKNO		(IMXRT_DMA_TCD[9].CITER_ELINKNO)

  2207. #define DMA_TCD9_DLASTSGA		(IMXRT_DMA_TCD[9].DLASTSGA)

  2208. #define DMA_TCD9_CSR			(IMXRT_DMA_TCD[9].CSR)

  2209. #define DMA_TCD9_BITER			(IMXRT_DMA_TCD[9].BITER)

  2210. #define DMA_TCD9_BITER_ELINKYES		(IMXRT_DMA_TCD[9].BITER_ELINKYES)

  2211. #define DMA_TCD9_BITER_ELINKNO		(IMXRT_DMA_TCD[9].BITER_ELINKNO)

  2212. 

  2213. #define DMA_TCD10_SADDR			(IMXRT_DMA_TCD[10].SADDR)

  2214. #define DMA_TCD10_SOFF			(IMXRT_DMA_TCD[10].SOFF)

  2215. #define DMA_TCD10_ATTR			(IMXRT_DMA_TCD[10].ATTR)

  2216. #define DMA_TCD10_NBYTES		(IMXRT_DMA_TCD[10].NBYTES)

  2217. #define DMA_TCD10_NBYTES_MLNO		(IMXRT_DMA_TCD[10].NBYTES_MLNO)

  2218. #define DMA_TCD10_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[10].NBYTES_MLOFFNO)

  2219. #define DMA_TCD10_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[10].NBYTES_MLOFFYES)

  2220. #define DMA_TCD10_SLAST			(IMXRT_DMA_TCD[10].SLAST)

  2221. #define DMA_TCD10_DADDR			(IMXRT_DMA_TCD[10].DADDR)

  2222. #define DMA_TCD10_DOFF			(IMXRT_DMA_TCD[10].DOFF)

  2223. #define DMA_TCD10_CITER			(IMXRT_DMA_TCD[10].CITER)

  2224. #define DMA_TCD10_CITER_ELINKYES	(IMXRT_DMA_TCD[10].CITER_ELINKYES)

  2225. #define DMA_TCD10_CITER_ELINKNO		(IMXRT_DMA_TCD[10].CITER_ELINKNO)

  2226. #define DMA_TCD10_DLASTSGA		(IMXRT_DMA_TCD[10].DLASTSGA)

  2227. #define DMA_TCD10_CSR			(IMXRT_DMA_TCD[10].CSR)

  2228. #define DMA_TCD10_BITER			(IMXRT_DMA_TCD[10].BITER)

  2229. #define DMA_TCD10_BITER_ELINKYES	(IMXRT_DMA_TCD[10].BITER_ELINKYES)

  2230. #define DMA_TCD10_BITER_ELINKNO		(IMXRT_DMA_TCD[10].BITER_ELINKNO)

  2231. 

  2232. #define DMA_TCD11_SADDR			(IMXRT_DMA_TCD[11].SADDR)

  2233. #define DMA_TCD11_SOFF			(IMXRT_DMA_TCD[11].SOFF)

  2234. #define DMA_TCD11_ATTR			(IMXRT_DMA_TCD[11].ATTR)

  2235. #define DMA_TCD11_NBYTES		(IMXRT_DMA_TCD[11].NBYTES)

  2236. #define DMA_TCD11_NBYTES_MLNO		(IMXRT_DMA_TCD[11].NBYTES_MLNO)

  2237. #define DMA_TCD11_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[11].NBYTES_MLOFFNO)

  2238. #define DMA_TCD11_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[11].NBYTES_MLOFFYES)

  2239. #define DMA_TCD11_SLAST			(IMXRT_DMA_TCD[11].SLAST)

  2240. #define DMA_TCD11_DADDR			(IMXRT_DMA_TCD[11].DADDR)

  2241. #define DMA_TCD11_DOFF			(IMXRT_DMA_TCD[11].DOFF)

  2242. #define DMA_TCD11_CITER			(IMXRT_DMA_TCD[11].CITER)

  2243. #define DMA_TCD11_CITER_ELINKYES	(IMXRT_DMA_TCD[11].CITER_ELINKYES)

  2244. #define DMA_TCD11_CITER_ELINKNO		(IMXRT_DMA_TCD[11].CITER_ELINKNO)

  2245. #define DMA_TCD11_DLASTSGA		(IMXRT_DMA_TCD[11].DLASTSGA)

  2246. #define DMA_TCD11_CSR			(IMXRT_DMA_TCD[11].CSR)

  2247. #define DMA_TCD11_BITER			(IMXRT_DMA_TCD[11].BITER)

  2248. #define DMA_TCD11_BITER_ELINKYES	(IMXRT_DMA_TCD[11].BITER_ELINKYES)

  2249. #define DMA_TCD11_BITER_ELINKNO		(IMXRT_DMA_TCD[11].BITER_ELINKNO)

  2250. 

  2251. #define DMA_TCD12_SADDR			(IMXRT_DMA_TCD[12].SADDR)

  2252. #define DMA_TCD12_SOFF			(IMXRT_DMA_TCD[12].SOFF)

  2253. #define DMA_TCD12_ATTR			(IMXRT_DMA_TCD[12].ATTR)

  2254. #define DMA_TCD12_NBYTES		(IMXRT_DMA_TCD[12].NBYTES)

  2255. #define DMA_TCD12_NBYTES_MLNO		(IMXRT_DMA_TCD[12].NBYTES_MLNO)

  2256. #define DMA_TCD12_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[12].NBYTES_MLOFFNO)

  2257. #define DMA_TCD12_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[12].NBYTES_MLOFFYES)

  2258. #define DMA_TCD12_SLAST			(IMXRT_DMA_TCD[12].SLAST)

  2259. #define DMA_TCD12_DADDR			(IMXRT_DMA_TCD[12].DADDR)

  2260. #define DMA_TCD12_DOFF			(IMXRT_DMA_TCD[12].DOFF)

  2261. #define DMA_TCD12_CITER			(IMXRT_DMA_TCD[12].CITER)

  2262. #define DMA_TCD12_CITER_ELINKYES	(IMXRT_DMA_TCD[12].CITER_ELINKYES)

  2263. #define DMA_TCD12_CITER_ELINKNO		(IMXRT_DMA_TCD[12].CITER_ELINKNO)

  2264. #define DMA_TCD12_DLASTSGA		(IMXRT_DMA_TCD[12].DLASTSGA)

  2265. #define DMA_TCD12_CSR			(IMXRT_DMA_TCD[12].CSR)

  2266. #define DMA_TCD12_BITER			(IMXRT_DMA_TCD[12].BITER)

  2267. #define DMA_TCD12_BITER_ELINKYES	(IMXRT_DMA_TCD[12].BITER_ELINKYES)

  2268. #define DMA_TCD12_BITER_ELINKNO		(IMXRT_DMA_TCD[12].BITER_ELINKNO)

  2269. 

  2270. #define DMA_TCD13_SADDR			(IMXRT_DMA_TCD[13].SADDR)

  2271. #define DMA_TCD13_SOFF			(IMXRT_DMA_TCD[13].SOFF)

  2272. #define DMA_TCD13_ATTR			(IMXRT_DMA_TCD[13].ATTR)

  2273. #define DMA_TCD13_NBYTES		(IMXRT_DMA_TCD[13].NBYTES)

  2274. #define DMA_TCD13_NBYTES_MLNO		(IMXRT_DMA_TCD[13].NBYTES_MLNO)

  2275. #define DMA_TCD13_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[13].NBYTES_MLOFFNO)

  2276. #define DMA_TCD13_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[13].NBYTES_MLOFFYES)

  2277. #define DMA_TCD13_SLAST			(IMXRT_DMA_TCD[13].SLAST)

  2278. #define DMA_TCD13_DADDR			(IMXRT_DMA_TCD[13].DADDR)

  2279. #define DMA_TCD13_DOFF			(IMXRT_DMA_TCD[13].DOFF)

  2280. #define DMA_TCD13_CITER			(IMXRT_DMA_TCD[13].CITER)

  2281. #define DMA_TCD13_CITER_ELINKYES	(IMXRT_DMA_TCD[13].CITER_ELINKYES)

  2282. #define DMA_TCD13_CITER_ELINKNO		(IMXRT_DMA_TCD[13].CITER_ELINKNO)

  2283. #define DMA_TCD13_DLASTSGA		(IMXRT_DMA_TCD[13].DLASTSGA)

  2284. #define DMA_TCD13_CSR			(IMXRT_DMA_TCD[13].CSR)

  2285. #define DMA_TCD13_BITER			(IMXRT_DMA_TCD[13].BITER)

  2286. #define DMA_TCD13_BITER_ELINKYES	(IMXRT_DMA_TCD[13].BITER_ELINKYES)

  2287. #define DMA_TCD13_BITER_ELINKNO		(IMXRT_DMA_TCD[13].BITER_ELINKNO)

  2288. 

  2289. #define DMA_TCD14_SADDR			(IMXRT_DMA_TCD[14].SADDR)

  2290. #define DMA_TCD14_SOFF			(IMXRT_DMA_TCD[14].SOFF)

  2291. #define DMA_TCD14_ATTR			(IMXRT_DMA_TCD[14].ATTR)

  2292. #define DMA_TCD14_NBYTES		(IMXRT_DMA_TCD[14].NBYTES)

  2293. #define DMA_TCD14_NBYTES_MLNO		(IMXRT_DMA_TCD[14].NBYTES_MLNO)

  2294. #define DMA_TCD14_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[14].NBYTES_MLOFFNO)

  2295. #define DMA_TCD14_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[14].NBYTES_MLOFFYES)

  2296. #define DMA_TCD14_SLAST			(IMXRT_DMA_TCD[14].SLAST)

  2297. #define DMA_TCD14_DADDR			(IMXRT_DMA_TCD[14].DADDR)

  2298. #define DMA_TCD14_DOFF			(IMXRT_DMA_TCD[14].DOFF)

  2299. #define DMA_TCD14_CITER			(IMXRT_DMA_TCD[14].CITER)

  2300. #define DMA_TCD14_CITER_ELINKYES	(IMXRT_DMA_TCD[14].CITER_ELINKYES)

  2301. #define DMA_TCD14_CITER_ELINKNO		(IMXRT_DMA_TCD[14].CITER_ELINKNO)

  2302. #define DMA_TCD14_DLASTSGA		(IMXRT_DMA_TCD[14].DLASTSGA)

  2303. #define DMA_TCD14_CSR			(IMXRT_DMA_TCD[14].CSR)

  2304. #define DMA_TCD14_BITER			(IMXRT_DMA_TCD[14].BITER)

  2305. #define DMA_TCD14_BITER_ELINKYES	(IMXRT_DMA_TCD[14].BITER_ELINKYES)

  2306. #define DMA_TCD14_BITER_ELINKNO		(IMXRT_DMA_TCD[14].BITER_ELINKNO)

  2307. 

  2308. #define DMA_TCD15_SADDR			(IMXRT_DMA_TCD[15].SADDR)

  2309. #define DMA_TCD15_SOFF			(IMXRT_DMA_TCD[15].SOFF)

  2310. #define DMA_TCD15_ATTR			(IMXRT_DMA_TCD[15].ATTR)

  2311. #define DMA_TCD15_NBYTES		(IMXRT_DMA_TCD[15].NBYTES)

  2312. #define DMA_TCD15_NBYTES_MLNO		(IMXRT_DMA_TCD[15].NBYTES_MLNO)

  2313. #define DMA_TCD15_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[15].NBYTES_MLOFFNO)

  2314. #define DMA_TCD15_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[15].NBYTES_MLOFFYES)

  2315. #define DMA_TCD15_SLAST			(IMXRT_DMA_TCD[15].SLAST)

  2316. #define DMA_TCD15_DADDR			(IMXRT_DMA_TCD[15].DADDR)

  2317. #define DMA_TCD15_DOFF			(IMXRT_DMA_TCD[15].DOFF)

  2318. #define DMA_TCD15_CITER			(IMXRT_DMA_TCD[15].CITER)

  2319. #define DMA_TCD15_CITER_ELINKYES	(IMXRT_DMA_TCD[15].CITER_ELINKYES)

  2320. #define DMA_TCD15_CITER_ELINKNO		(IMXRT_DMA_TCD[15].CITER_ELINKNO)

  2321. #define DMA_TCD15_DLASTSGA		(IMXRT_DMA_TCD[15].DLASTSGA)

  2322. #define DMA_TCD15_CSR			(IMXRT_DMA_TCD[15].CSR)

  2323. #define DMA_TCD15_BITER			(IMXRT_DMA_TCD[15].BITER)

  2324. #define DMA_TCD15_BITER_ELINKYES	(IMXRT_DMA_TCD[15].BITER_ELINKYES)

  2325. #define DMA_TCD15_BITER_ELINKNO		(IMXRT_DMA_TCD[15].BITER_ELINKNO)

  2326. 

  2327. #define DMA_TCD16_SADDR			(IMXRT_DMA_TCD[16].SADDR)

  2328. #define DMA_TCD16_SOFF			(IMXRT_DMA_TCD[16].SOFF)

  2329. #define DMA_TCD16_ATTR			(IMXRT_DMA_TCD[16].ATTR)

  2330. #define DMA_TCD16_NBYTES		(IMXRT_DMA_TCD[16].NBYTES)

  2331. #define DMA_TCD16_NBYTES_MLNO		(IMXRT_DMA_TCD[16].NBYTES_MLNO)

  2332. #define DMA_TCD16_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[16].NBYTES_MLOFFNO)

  2333. #define DMA_TCD16_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[16].NBYTES_MLOFFYES)

  2334. #define DMA_TCD16_SLAST			(IMXRT_DMA_TCD[16].SLAST)

  2335. #define DMA_TCD16_DADDR			(IMXRT_DMA_TCD[16].DADDR)

  2336. #define DMA_TCD16_DOFF			(IMXRT_DMA_TCD[16].DOFF)

  2337. #define DMA_TCD16_CITER			(IMXRT_DMA_TCD[16].CITER)

  2338. #define DMA_TCD16_CITER_ELINKYES	(IMXRT_DMA_TCD[16].CITER_ELINKYES)

  2339. #define DMA_TCD16_CITER_ELINKNO		(IMXRT_DMA_TCD[16].CITER_ELINKNO)

  2340. #define DMA_TCD16_DLASTSGA		(IMXRT_DMA_TCD[16].DLASTSGA)

  2341. #define DMA_TCD16_CSR			(IMXRT_DMA_TCD[16].CSR)

  2342. #define DMA_TCD16_BITER			(IMXRT_DMA_TCD[16].BITER)

  2343. #define DMA_TCD16_BITER_ELINKYES	(IMXRT_DMA_TCD[16].BITER_ELINKYES)

  2344. #define DMA_TCD16_BITER_ELINKNO		(IMXRT_DMA_TCD[16].BITER_ELINKNO)

  2345. 

  2346. #define DMA_TCD17_SADDR			(IMXRT_DMA_TCD[17].SADDR)

  2347. #define DMA_TCD17_SOFF			(IMXRT_DMA_TCD[17].SOFF)

  2348. #define DMA_TCD17_ATTR			(IMXRT_DMA_TCD[17].ATTR)

  2349. #define DMA_TCD17_NBYTES		(IMXRT_DMA_TCD[17].NBYTES)

  2350. #define DMA_TCD17_NBYTES_MLNO		(IMXRT_DMA_TCD[17].NBYTES_MLNO)

  2351. #define DMA_TCD17_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[17].NBYTES_MLOFFNO)

  2352. #define DMA_TCD17_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[17].NBYTES_MLOFFYES)

  2353. #define DMA_TCD17_SLAST			(IMXRT_DMA_TCD[17].SLAST)

  2354. #define DMA_TCD17_DADDR			(IMXRT_DMA_TCD[17].DADDR)

  2355. #define DMA_TCD17_DOFF			(IMXRT_DMA_TCD[17].DOFF)

  2356. #define DMA_TCD17_CITER			(IMXRT_DMA_TCD[17].CITER)

  2357. #define DMA_TCD17_CITER_ELINKYES	(IMXRT_DMA_TCD[17].CITER_ELINKYES)

  2358. #define DMA_TCD17_CITER_ELINKNO		(IMXRT_DMA_TCD[17].CITER_ELINKNO)

  2359. #define DMA_TCD17_DLASTSGA		(IMXRT_DMA_TCD[17].DLASTSGA)

  2360. #define DMA_TCD17_CSR			(IMXRT_DMA_TCD[17].CSR)

  2361. #define DMA_TCD17_BITER			(IMXRT_DMA_TCD[17].BITER)

  2362. #define DMA_TCD17_BITER_ELINKYES	(IMXRT_DMA_TCD[17].BITER_ELINKYES)

  2363. #define DMA_TCD17_BITER_ELINKNO		(IMXRT_DMA_TCD[17].BITER_ELINKNO)

  2364. 

  2365. #define DMA_TCD18_SADDR			(IMXRT_DMA_TCD[18].SADDR)

  2366. #define DMA_TCD18_SOFF			(IMXRT_DMA_TCD[18].SOFF)

  2367. #define DMA_TCD18_ATTR			(IMXRT_DMA_TCD[18].ATTR)

  2368. #define DMA_TCD18_NBYTES		(IMXRT_DMA_TCD[18].NBYTES)

  2369. #define DMA_TCD18_NBYTES_MLNO		(IMXRT_DMA_TCD[18].NBYTES_MLNO)

  2370. #define DMA_TCD18_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[18].NBYTES_MLOFFNO)

  2371. #define DMA_TCD18_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[18].NBYTES_MLOFFYES)

  2372. #define DMA_TCD18_SLAST			(IMXRT_DMA_TCD[18].SLAST)

  2373. #define DMA_TCD18_DADDR			(IMXRT_DMA_TCD[18].DADDR)

  2374. #define DMA_TCD18_DOFF			(IMXRT_DMA_TCD[18].DOFF)

  2375. #define DMA_TCD18_CITER			(IMXRT_DMA_TCD[18].CITER)

  2376. #define DMA_TCD18_CITER_ELINKYES	(IMXRT_DMA_TCD[18].CITER_ELINKYES)

  2377. #define DMA_TCD18_CITER_ELINKNO		(IMXRT_DMA_TCD[18].CITER_ELINKNO)

  2378. #define DMA_TCD18_DLASTSGA		(IMXRT_DMA_TCD[18].DLASTSGA)

  2379. #define DMA_TCD18_CSR			(IMXRT_DMA_TCD[18].CSR)

  2380. #define DMA_TCD18_BITER			(IMXRT_DMA_TCD[18].BITER)

  2381. #define DMA_TCD18_BITER_ELINKYES	(IMXRT_DMA_TCD[18].BITER_ELINKYES)

  2382. #define DMA_TCD18_BITER_ELINKNO		(IMXRT_DMA_TCD[18].BITER_ELINKNO)

  2383. 

  2384. #define DMA_TCD19_SADDR			(IMXRT_DMA_TCD[19].SADDR)

  2385. #define DMA_TCD19_SOFF			(IMXRT_DMA_TCD[19].SOFF)

  2386. #define DMA_TCD19_ATTR			(IMXRT_DMA_TCD[19].ATTR)

  2387. #define DMA_TCD19_NBYTES		(IMXRT_DMA_TCD[19].NBYTES)

  2388. #define DMA_TCD19_NBYTES_MLNO		(IMXRT_DMA_TCD[19].NBYTES_MLNO)

  2389. #define DMA_TCD19_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[19].NBYTES_MLOFFNO)

  2390. #define DMA_TCD19_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[19].NBYTES_MLOFFYES)

  2391. #define DMA_TCD19_SLAST			(IMXRT_DMA_TCD[19].SLAST)

  2392. #define DMA_TCD19_DADDR			(IMXRT_DMA_TCD[19].DADDR)

  2393. #define DMA_TCD19_DOFF			(IMXRT_DMA_TCD[19].DOFF)

  2394. #define DMA_TCD19_CITER			(IMXRT_DMA_TCD[19].CITER)

  2395. #define DMA_TCD19_CITER_ELINKYES	(IMXRT_DMA_TCD[19].CITER_ELINKYES)

  2396. #define DMA_TCD19_CITER_ELINKNO		(IMXRT_DMA_TCD[19].CITER_ELINKNO)

  2397. #define DMA_TCD19_DLASTSGA		(IMXRT_DMA_TCD[19].DLASTSGA)

  2398. #define DMA_TCD19_CSR			(IMXRT_DMA_TCD[19].CSR)

  2399. #define DMA_TCD19_BITER			(IMXRT_DMA_TCD[19].BITER)

  2400. #define DMA_TCD19_BITER_ELINKYES	(IMXRT_DMA_TCD[19].BITER_ELINKYES)

  2401. #define DMA_TCD19_BITER_ELINKNO		(IMXRT_DMA_TCD[19].BITER_ELINKNO)

  2402. 

  2403. #define DMA_TCD20_SADDR			(IMXRT_DMA_TCD[20].SADDR)

  2404. #define DMA_TCD20_SOFF			(IMXRT_DMA_TCD[20].SOFF)

  2405. #define DMA_TCD20_ATTR			(IMXRT_DMA_TCD[20].ATTR)

  2406. #define DMA_TCD20_NBYTES		(IMXRT_DMA_TCD[20].NBYTES)

  2407. #define DMA_TCD20_NBYTES_MLNO		(IMXRT_DMA_TCD[20].NBYTES_MLNO)

  2408. #define DMA_TCD20_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[20].NBYTES_MLOFFNO)

  2409. #define DMA_TCD20_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[20].NBYTES_MLOFFYES)

  2410. #define DMA_TCD20_SLAST			(IMXRT_DMA_TCD[20].SLAST)

  2411. #define DMA_TCD20_DADDR			(IMXRT_DMA_TCD[20].DADDR)

  2412. #define DMA_TCD20_DOFF			(IMXRT_DMA_TCD[20].DOFF)

  2413. #define DMA_TCD20_CITER			(IMXRT_DMA_TCD[20].CITER)

  2414. #define DMA_TCD20_CITER_ELINKYES	(IMXRT_DMA_TCD[20].CITER_ELINKYES)

  2415. #define DMA_TCD20_CITER_ELINKNO		(IMXRT_DMA_TCD[20].CITER_ELINKNO)

  2416. #define DMA_TCD20_DLASTSGA		(IMXRT_DMA_TCD[20].DLASTSGA)

  2417. #define DMA_TCD20_CSR			(IMXRT_DMA_TCD[20].CSR)

  2418. #define DMA_TCD20_BITER			(IMXRT_DMA_TCD[20].BITER)

  2419. #define DMA_TCD20_BITER_ELINKYES	(IMXRT_DMA_TCD[20].BITER_ELINKYES)

  2420. #define DMA_TCD20_BITER_ELINKNO		(IMXRT_DMA_TCD[20].BITER_ELINKNO)

  2421. 

  2422. #define DMA_TCD21_SADDR			(IMXRT_DMA_TCD[21].SADDR)

  2423. #define DMA_TCD21_SOFF			(IMXRT_DMA_TCD[21].SOFF)

  2424. #define DMA_TCD21_ATTR			(IMXRT_DMA_TCD[21].ATTR)

  2425. #define DMA_TCD21_NBYTES		(IMXRT_DMA_TCD[21].NBYTES)

  2426. #define DMA_TCD21_NBYTES_MLNO		(IMXRT_DMA_TCD[21].NBYTES_MLNO)

  2427. #define DMA_TCD21_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[21].NBYTES_MLOFFNO)

  2428. #define DMA_TCD21_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[21].NBYTES_MLOFFYES)

  2429. #define DMA_TCD21_SLAST			(IMXRT_DMA_TCD[21].SLAST)

  2430. #define DMA_TCD21_DADDR			(IMXRT_DMA_TCD[21].DADDR)

  2431. #define DMA_TCD21_DOFF			(IMXRT_DMA_TCD[21].DOFF)

  2432. #define DMA_TCD21_CITER			(IMXRT_DMA_TCD[21].CITER)

  2433. #define DMA_TCD21_CITER_ELINKYES	(IMXRT_DMA_TCD[21].CITER_ELINKYES)

  2434. #define DMA_TCD21_CITER_ELINKNO		(IMXRT_DMA_TCD[21].CITER_ELINKNO)

  2435. #define DMA_TCD21_DLASTSGA		(IMXRT_DMA_TCD[21].DLASTSGA)

  2436. #define DMA_TCD21_CSR			(IMXRT_DMA_TCD[21].CSR)

  2437. #define DMA_TCD21_BITER			(IMXRT_DMA_TCD[21].BITER)

  2438. #define DMA_TCD21_BITER_ELINKYES	(IMXRT_DMA_TCD[21].BITER_ELINKYES)

  2439. #define DMA_TCD21_BITER_ELINKNO		(IMXRT_DMA_TCD[21].BITER_ELINKNO)

  2440. 

  2441. #define DMA_TCD22_SADDR			(IMXRT_DMA_TCD[22].SADDR)

  2442. #define DMA_TCD22_SOFF			(IMXRT_DMA_TCD[22].SOFF)

  2443. #define DMA_TCD22_ATTR			(IMXRT_DMA_TCD[22].ATTR)

  2444. #define DMA_TCD22_NBYTES		(IMXRT_DMA_TCD[22].NBYTES)

  2445. #define DMA_TCD22_NBYTES_MLNO		(IMXRT_DMA_TCD[22].NBYTES_MLNO)

  2446. #define DMA_TCD22_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[22].NBYTES_MLOFFNO)

  2447. #define DMA_TCD22_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[22].NBYTES_MLOFFYES)

  2448. #define DMA_TCD22_SLAST			(IMXRT_DMA_TCD[22].SLAST)

  2449. #define DMA_TCD22_DADDR			(IMXRT_DMA_TCD[22].DADDR)

  2450. #define DMA_TCD22_DOFF			(IMXRT_DMA_TCD[22].DOFF)

  2451. #define DMA_TCD22_CITER			(IMXRT_DMA_TCD[22].CITER)

  2452. #define DMA_TCD22_CITER_ELINKYES	(IMXRT_DMA_TCD[22].CITER_ELINKYES)

  2453. #define DMA_TCD22_CITER_ELINKNO		(IMXRT_DMA_TCD[22].CITER_ELINKNO)

  2454. #define DMA_TCD22_DLASTSGA		(IMXRT_DMA_TCD[22].DLASTSGA)

  2455. #define DMA_TCD22_CSR			(IMXRT_DMA_TCD[22].CSR)

  2456. #define DMA_TCD22_BITER			(IMXRT_DMA_TCD[22].BITER)

  2457. #define DMA_TCD22_BITER_ELINKYES	(IMXRT_DMA_TCD[22].BITER_ELINKYES)

  2458. #define DMA_TCD22_BITER_ELINKNO		(IMXRT_DMA_TCD[22].BITER_ELINKNO)

  2459. 

  2460. #define DMA_TCD23_SADDR			(IMXRT_DMA_TCD[23].SADDR)

  2461. #define DMA_TCD23_SOFF			(IMXRT_DMA_TCD[23].SOFF)

  2462. #define DMA_TCD23_ATTR			(IMXRT_DMA_TCD[23].ATTR)

  2463. #define DMA_TCD23_NBYTES		(IMXRT_DMA_TCD[23].NBYTES)

  2464. #define DMA_TCD23_NBYTES_MLNO		(IMXRT_DMA_TCD[23].NBYTES_MLNO)

  2465. #define DMA_TCD23_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[23].NBYTES_MLOFFNO)

  2466. #define DMA_TCD23_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[23].NBYTES_MLOFFYES)

  2467. #define DMA_TCD23_SLAST			(IMXRT_DMA_TCD[23].SLAST)

  2468. #define DMA_TCD23_DADDR			(IMXRT_DMA_TCD[23].DADDR)

  2469. #define DMA_TCD23_DOFF			(IMXRT_DMA_TCD[23].DOFF)

  2470. #define DMA_TCD23_CITER			(IMXRT_DMA_TCD[23].CITER)

  2471. #define DMA_TCD23_CITER_ELINKYES	(IMXRT_DMA_TCD[23].CITER_ELINKYES)

  2472. #define DMA_TCD23_CITER_ELINKNO		(IMXRT_DMA_TCD[23].CITER_ELINKNO)

  2473. #define DMA_TCD23_DLASTSGA		(IMXRT_DMA_TCD[23].DLASTSGA)

  2474. #define DMA_TCD23_CSR			(IMXRT_DMA_TCD[23].CSR)

  2475. #define DMA_TCD23_BITER			(IMXRT_DMA_TCD[23].BITER)

  2476. #define DMA_TCD23_BITER_ELINKYES	(IMXRT_DMA_TCD[23].BITER_ELINKYES)

  2477. #define DMA_TCD23_BITER_ELINKNO		(IMXRT_DMA_TCD[23].BITER_ELINKNO)

  2478. 

  2479. #define DMA_TCD24_SADDR			(IMXRT_DMA_TCD[24].SADDR)

  2480. #define DMA_TCD24_SOFF			(IMXRT_DMA_TCD[24].SOFF)

  2481. #define DMA_TCD24_ATTR			(IMXRT_DMA_TCD[24].ATTR)

  2482. #define DMA_TCD24_NBYTES		(IMXRT_DMA_TCD[24].NBYTES)

  2483. #define DMA_TCD24_NBYTES_MLNO		(IMXRT_DMA_TCD[24].NBYTES_MLNO)

  2484. #define DMA_TCD24_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[24].NBYTES_MLOFFNO)

  2485. #define DMA_TCD24_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[24].NBYTES_MLOFFYES)

  2486. #define DMA_TCD24_SLAST			(IMXRT_DMA_TCD[24].SLAST)

  2487. #define DMA_TCD24_DADDR			(IMXRT_DMA_TCD[24].DADDR)

  2488. #define DMA_TCD24_DOFF			(IMXRT_DMA_TCD[24].DOFF)

  2489. #define DMA_TCD24_CITER			(IMXRT_DMA_TCD[24].CITER)

  2490. #define DMA_TCD24_CITER_ELINKYES	(IMXRT_DMA_TCD[24].CITER_ELINKYES)

  2491. #define DMA_TCD24_CITER_ELINKNO		(IMXRT_DMA_TCD[24].CITER_ELINKNO)

  2492. #define DMA_TCD24_DLASTSGA		(IMXRT_DMA_TCD[24].DLASTSGA)

  2493. #define DMA_TCD24_CSR			(IMXRT_DMA_TCD[24].CSR)

  2494. #define DMA_TCD24_BITER			(IMXRT_DMA_TCD[24].BITER)

  2495. #define DMA_TCD24_BITER_ELINKYES	(IMXRT_DMA_TCD[24].BITER_ELINKYES)

  2496. #define DMA_TCD24_BITER_ELINKNO		(IMXRT_DMA_TCD[24].BITER_ELINKNO)

  2497. 

  2498. #define DMA_TCD25_SADDR			(IMXRT_DMA_TCD[25].SADDR)

  2499. #define DMA_TCD25_SOFF			(IMXRT_DMA_TCD[25].SOFF)

  2500. #define DMA_TCD25_ATTR			(IMXRT_DMA_TCD[25].ATTR)

  2501. #define DMA_TCD25_NBYTES		(IMXRT_DMA_TCD[25].NBYTES)

  2502. #define DMA_TCD25_NBYTES_MLNO		(IMXRT_DMA_TCD[25].NBYTES_MLNO)

  2503. #define DMA_TCD25_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[25].NBYTES_MLOFFNO)

  2504. #define DMA_TCD25_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[25].NBYTES_MLOFFYES)

  2505. #define DMA_TCD25_SLAST			(IMXRT_DMA_TCD[25].SLAST)

  2506. #define DMA_TCD25_DADDR			(IMXRT_DMA_TCD[25].DADDR)

  2507. #define DMA_TCD25_DOFF			(IMXRT_DMA_TCD[25].DOFF)

  2508. #define DMA_TCD25_CITER			(IMXRT_DMA_TCD[25].CITER)

  2509. #define DMA_TCD25_CITER_ELINKYES	(IMXRT_DMA_TCD[25].CITER_ELINKYES)

  2510. #define DMA_TCD25_CITER_ELINKNO		(IMXRT_DMA_TCD[25].CITER_ELINKNO)

  2511. #define DMA_TCD25_DLASTSGA		(IMXRT_DMA_TCD[25].DLASTSGA)

  2512. #define DMA_TCD25_CSR			(IMXRT_DMA_TCD[25].CSR)

  2513. #define DMA_TCD25_BITER			(IMXRT_DMA_TCD[25].BITER)

  2514. #define DMA_TCD25_BITER_ELINKYES	(IMXRT_DMA_TCD[25].BITER_ELINKYES)

  2515. #define DMA_TCD25_BITER_ELINKNO		(IMXRT_DMA_TCD[25].BITER_ELINKNO)

  2516. 

  2517. #define DMA_TCD26_SADDR			(IMXRT_DMA_TCD[26].SADDR)

  2518. #define DMA_TCD26_SOFF			(IMXRT_DMA_TCD[26].SOFF)

  2519. #define DMA_TCD26_ATTR			(IMXRT_DMA_TCD[26].ATTR)

  2520. #define DMA_TCD26_NBYTES		(IMXRT_DMA_TCD[26].NBYTES)

  2521. #define DMA_TCD26_NBYTES_MLNO		(IMXRT_DMA_TCD[26].NBYTES_MLNO)

  2522. #define DMA_TCD26_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[26].NBYTES_MLOFFNO)

  2523. #define DMA_TCD26_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[26].NBYTES_MLOFFYES)

  2524. #define DMA_TCD26_SLAST			(IMXRT_DMA_TCD[26].SLAST)

  2525. #define DMA_TCD26_DADDR			(IMXRT_DMA_TCD[26].DADDR)

  2526. #define DMA_TCD26_DOFF			(IMXRT_DMA_TCD[26].DOFF)

  2527. #define DMA_TCD26_CITER			(IMXRT_DMA_TCD[26].CITER)

  2528. #define DMA_TCD26_CITER_ELINKYES	(IMXRT_DMA_TCD[26].CITER_ELINKYES)

  2529. #define DMA_TCD26_CITER_ELINKNO		(IMXRT_DMA_TCD[26].CITER_ELINKNO)

  2530. #define DMA_TCD26_DLASTSGA		(IMXRT_DMA_TCD[26].DLASTSGA)

  2531. #define DMA_TCD26_CSR			(IMXRT_DMA_TCD[26].CSR)

  2532. #define DMA_TCD26_BITER			(IMXRT_DMA_TCD[26].BITER)

  2533. #define DMA_TCD26_BITER_ELINKYES	(IMXRT_DMA_TCD[26].BITER_ELINKYES)

  2534. #define DMA_TCD26_BITER_ELINKNO		(IMXRT_DMA_TCD[26].BITER_ELINKNO)

  2535. 

  2536. #define DMA_TCD27_SADDR			(IMXRT_DMA_TCD[27].SADDR)

  2537. #define DMA_TCD27_SOFF			(IMXRT_DMA_TCD[27].SOFF)

  2538. #define DMA_TCD27_ATTR			(IMXRT_DMA_TCD[27].ATTR)

  2539. #define DMA_TCD27_NBYTES		(IMXRT_DMA_TCD[27].NBYTES)

  2540. #define DMA_TCD27_NBYTES_MLNO		(IMXRT_DMA_TCD[27].NBYTES_MLNO)

  2541. #define DMA_TCD27_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[27].NBYTES_MLOFFNO)

  2542. #define DMA_TCD27_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[27].NBYTES_MLOFFYES)

  2543. #define DMA_TCD27_SLAST			(IMXRT_DMA_TCD[27].SLAST)

  2544. #define DMA_TCD27_DADDR			(IMXRT_DMA_TCD[27].DADDR)

  2545. #define DMA_TCD27_DOFF			(IMXRT_DMA_TCD[27].DOFF)

  2546. #define DMA_TCD27_CITER			(IMXRT_DMA_TCD[27].CITER)

  2547. #define DMA_TCD27_CITER_ELINKYES	(IMXRT_DMA_TCD[27].CITER_ELINKYES)

  2548. #define DMA_TCD27_CITER_ELINKNO		(IMXRT_DMA_TCD[27].CITER_ELINKNO)

  2549. #define DMA_TCD27_DLASTSGA		(IMXRT_DMA_TCD[27].DLASTSGA)

  2550. #define DMA_TCD27_CSR			(IMXRT_DMA_TCD[27].CSR)

  2551. #define DMA_TCD27_BITER			(IMXRT_DMA_TCD[27].BITER)

  2552. #define DMA_TCD27_BITER_ELINKYES	(IMXRT_DMA_TCD[27].BITER_ELINKYES)

  2553. #define DMA_TCD27_BITER_ELINKNO		(IMXRT_DMA_TCD[27].BITER_ELINKNO)

  2554. 

  2555. #define DMA_TCD28_SADDR			(IMXRT_DMA_TCD[28].SADDR)

  2556. #define DMA_TCD28_SOFF			(IMXRT_DMA_TCD[28].SOFF)

  2557. #define DMA_TCD28_ATTR			(IMXRT_DMA_TCD[28].ATTR)

  2558. #define DMA_TCD28_NBYTES		(IMXRT_DMA_TCD[28].NBYTES)

  2559. #define DMA_TCD28_NBYTES_MLNO		(IMXRT_DMA_TCD[28].NBYTES_MLNO)

  2560. #define DMA_TCD28_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[28].NBYTES_MLOFFNO)

  2561. #define DMA_TCD28_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[28].NBYTES_MLOFFYES)

  2562. #define DMA_TCD28_SLAST			(IMXRT_DMA_TCD[28].SLAST)

  2563. #define DMA_TCD28_DADDR			(IMXRT_DMA_TCD[28].DADDR)

  2564. #define DMA_TCD28_DOFF			(IMXRT_DMA_TCD[28].DOFF)

  2565. #define DMA_TCD28_CITER			(IMXRT_DMA_TCD[28].CITER)

  2566. #define DMA_TCD28_CITER_ELINKYES	(IMXRT_DMA_TCD[28].CITER_ELINKYES)

  2567. #define DMA_TCD28_CITER_ELINKNO		(IMXRT_DMA_TCD[28].CITER_ELINKNO)

  2568. #define DMA_TCD28_DLASTSGA		(IMXRT_DMA_TCD[28].DLASTSGA)

  2569. #define DMA_TCD28_CSR			(IMXRT_DMA_TCD[28].CSR)

  2570. #define DMA_TCD28_BITER			(IMXRT_DMA_TCD[28].BITER)

  2571. #define DMA_TCD28_BITER_ELINKYES	(IMXRT_DMA_TCD[28].BITER_ELINKYES)

  2572. #define DMA_TCD28_BITER_ELINKNO		(IMXRT_DMA_TCD[28].BITER_ELINKNO)

  2573. 

  2574. #define DMA_TCD29_SADDR			(IMXRT_DMA_TCD[29].SADDR)

  2575. #define DMA_TCD29_SOFF			(IMXRT_DMA_TCD[29].SOFF)

  2576. #define DMA_TCD29_ATTR			(IMXRT_DMA_TCD[29].ATTR)

  2577. #define DMA_TCD29_NBYTES		(IMXRT_DMA_TCD[29].NBYTES)

  2578. #define DMA_TCD29_NBYTES_MLNO		(IMXRT_DMA_TCD[29].NBYTES_MLNO)

  2579. #define DMA_TCD29_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[29].NBYTES_MLOFFNO)

  2580. #define DMA_TCD29_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[29].NBYTES_MLOFFYES)

  2581. #define DMA_TCD29_SLAST			(IMXRT_DMA_TCD[29].SLAST)

  2582. #define DMA_TCD29_DADDR			(IMXRT_DMA_TCD[29].DADDR)

  2583. #define DMA_TCD29_DOFF			(IMXRT_DMA_TCD[29].DOFF)

  2584. #define DMA_TCD29_CITER			(IMXRT_DMA_TCD[29].CITER)

  2585. #define DMA_TCD29_CITER_ELINKYES	(IMXRT_DMA_TCD[29].CITER_ELINKYES)

  2586. #define DMA_TCD29_CITER_ELINKNO		(IMXRT_DMA_TCD[29].CITER_ELINKNO)

  2587. #define DMA_TCD29_DLASTSGA		(IMXRT_DMA_TCD[29].DLASTSGA)

  2588. #define DMA_TCD29_CSR			(IMXRT_DMA_TCD[29].CSR)

  2589. #define DMA_TCD29_BITER			(IMXRT_DMA_TCD[29].BITER)

  2590. #define DMA_TCD29_BITER_ELINKYES	(IMXRT_DMA_TCD[29].BITER_ELINKYES)

  2591. #define DMA_TCD29_BITER_ELINKNO		(IMXRT_DMA_TCD[29].BITER_ELINKNO)

  2592. 

  2593. #define DMA_TCD30_SADDR			(IMXRT_DMA_TCD[30].SADDR)

  2594. #define DMA_TCD30_SOFF			(IMXRT_DMA_TCD[30].SOFF)

  2595. #define DMA_TCD30_ATTR			(IMXRT_DMA_TCD[30].ATTR)

  2596. #define DMA_TCD30_NBYTES		(IMXRT_DMA_TCD[30].NBYTES)

  2597. #define DMA_TCD30_NBYTES_MLNO		(IMXRT_DMA_TCD[30].NBYTES_MLNO)

  2598. #define DMA_TCD30_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[30].NBYTES_MLOFFNO)

  2599. #define DMA_TCD30_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[30].NBYTES_MLOFFYES)

  2600. #define DMA_TCD30_SLAST			(IMXRT_DMA_TCD[30].SLAST)

  2601. #define DMA_TCD30_DADDR			(IMXRT_DMA_TCD[30].DADDR)

  2602. #define DMA_TCD30_DOFF			(IMXRT_DMA_TCD[30].DOFF)

  2603. #define DMA_TCD30_CITER			(IMXRT_DMA_TCD[30].CITER)

  2604. #define DMA_TCD30_CITER_ELINKYES	(IMXRT_DMA_TCD[30].CITER_ELINKYES)

  2605. #define DMA_TCD30_CITER_ELINKNO		(IMXRT_DMA_TCD[30].CITER_ELINKNO)

  2606. #define DMA_TCD30_DLASTSGA		(IMXRT_DMA_TCD[30].DLASTSGA)

  2607. #define DMA_TCD30_CSR			(IMXRT_DMA_TCD[30].CSR)

  2608. #define DMA_TCD30_BITER			(IMXRT_DMA_TCD[30].BITER)

  2609. #define DMA_TCD30_BITER_ELINKYES	(IMXRT_DMA_TCD[30].BITER_ELINKYES)

  2610. #define DMA_TCD30_BITER_ELINKNO		(IMXRT_DMA_TCD[30].BITER_ELINKNO)

  2611. 

  2612. #define DMA_TCD31_SADDR			(IMXRT_DMA_TCD[31].SADDR)

  2613. #define DMA_TCD31_SOFF			(IMXRT_DMA_TCD[31].SOFF)

  2614. #define DMA_TCD31_ATTR			(IMXRT_DMA_TCD[31].ATTR)

  2615. #define DMA_TCD31_NBYTES		(IMXRT_DMA_TCD[31].NBYTES)

  2616. #define DMA_TCD31_NBYTES_MLNO		(IMXRT_DMA_TCD[31].NBYTES_MLNO)

  2617. #define DMA_TCD31_NBYTES_MLOFFNO	(IMXRT_DMA_TCD[31].NBYTES_MLOFFNO)

  2618. #define DMA_TCD31_NBYTES_MLOFFYES	(IMXRT_DMA_TCD[31].NBYTES_MLOFFYES)

  2619. #define DMA_TCD31_SLAST			(IMXRT_DMA_TCD[31].SLAST)

  2620. #define DMA_TCD31_DADDR			(IMXRT_DMA_TCD[31].DADDR)

  2621. #define DMA_TCD31_DOFF			(IMXRT_DMA_TCD[31].DOFF)

  2622. #define DMA_TCD31_CITER			(IMXRT_DMA_TCD[31].CITER)

  2623. #define DMA_TCD31_CITER_ELINKYES	(IMXRT_DMA_TCD[31].CITER_ELINKYES)

  2624. #define DMA_TCD31_CITER_ELINKNO		(IMXRT_DMA_TCD[31].CITER_ELINKNO)

  2625. #define DMA_TCD31_DLASTSGA		(IMXRT_DMA_TCD[31].DLASTSGA)

  2626. #define DMA_TCD31_CSR			(IMXRT_DMA_TCD[31].CSR)

  2627. #define DMA_TCD31_BITER			(IMXRT_DMA_TCD[31].BITER)

  2628. #define DMA_TCD31_BITER_ELINKYES	(IMXRT_DMA_TCD[31].BITER_ELINKYES)

  2629. #define DMA_TCD31_BITER_ELINKNO		(IMXRT_DMA_TCD[31].BITER_ELINKNO)

  2630. 

  2631. // TODO: double check these defines from Teensy 3.x are still correct for IMXRT

  2632. #define DMA_TCD_ATTR_SMOD(n)            (((n) & 0x1F) << 11)

  2633. #define DMA_TCD_ATTR_SSIZE(n)           (((n) & 0x7) << 8)

  2634. #define DMA_TCD_ATTR_DMOD(n)            (((n) & 0x1F) << 3)

  2635. #define DMA_TCD_ATTR_DSIZE(n)           (((n) & 0x7) << 0)

  2636. #define DMA_TCD_ATTR_SIZE_8BIT          0

  2637. #define DMA_TCD_ATTR_SIZE_16BIT         1

  2638. #define DMA_TCD_ATTR_SIZE_32BIT         2

  2639. #define DMA_TCD_ATTR_SIZE_64BIT         3

  2640. #define DMA_TCD_ATTR_SIZE_32BYTE        5

  2641. #define DMA_TCD_CSR_BWC(n)              (((n) & 0x3) << 14)

  2642. #define DMA_TCD_CSR_BWC_MASK            0xC000

  2643. #define DMA_TCD_CSR_MAJORLINKCH(n)      (((n) & 0x1F) << 8)

  2644. #define DMA_TCD_CSR_MAJORLINKCH_MASK    0x1F00

  2645. #define DMA_TCD_CSR_DONE                0x0080

  2646. #define DMA_TCD_CSR_ACTIVE              0x0040

  2647. #define DMA_TCD_CSR_MAJORELINK          0x0020

  2648. #define DMA_TCD_CSR_ESG                 0x0010

  2649. #define DMA_TCD_CSR_DREQ                0x0008

  2650. #define DMA_TCD_CSR_INTHALF             0x0004

  2651. #define DMA_TCD_CSR_INTMAJOR            0x0002

  2652. #define DMA_TCD_CSR_START               0x0001

  2653. #define DMA_TCD_CITER_MASK              ((uint16_t)0x7FFF)         // Loop count mask

  2654. #define DMA_TCD_CITER_ELINK             ((uint16_t)1<<15)          // Enable channel linking on minor-loop complete

  2655. #define DMA_TCD_BITER_MASK              ((uint16_t)0x7FFF)         // Loop count mask

  2656. #define DMA_TCD_BITER_ELINK             ((uint16_t)1<<15)          // Enable channel linking on minor-loop complete

  2657. #define DMA_TCD_BITER_ELINKYES_ELINK            0x8000

  2658. #define DMA_TCD_BITER_ELINKYES_LINKCH(n)        (((n) & 0x1F) << 9)

  2659. #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK      0x3E00

  2660. #define DMA_TCD_BITER_ELINKYES_BITER(n)         (((n) & 0x1FF) << 0)

  2661. #define DMA_TCD_BITER_ELINKYES_BITER_MASK       0x01FF

  2662. #define DMA_TCD_CITER_ELINKYES_ELINK            0x8000

  2663. #define DMA_TCD_CITER_ELINKYES_LINKCH(n)        (((n) & 0x1F) << 9)

  2664. #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK      0x3E00

  2665. #define DMA_TCD_CITER_ELINKYES_CITER(n)         (((n) & 0x1FF) << 0)

  2666. #define DMA_TCD_CITER_ELINKYES_CITER_MASK       0x01FF

  2667. #define DMA_TCD_NBYTES_SMLOE                ((uint32_t)1<<31)               // Source Minor Loop Offset Enable

  2668. #define DMA_TCD_NBYTES_DMLOE                ((uint32_t)1<<30)               // Destination Minor Loop Offset Enable

  2669. #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n)    ((uint32_t)((n) & 0x3FFFFFFF))  // NBytes transfer count when minor loop disabled

  2670. #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n)   ((uint32_t)((n) & 0x3FF))       // NBytes transfer count when minor loop enabled

  2671. #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n)    ((uint32_t)((n) & 0xFFFFF)<<10) // Minor loop offset

  2672. 

  2673. 

  2674. // 56.8.1: page 3151

  2675. typedef struct {

  2676.   volatile uint16_t CTRL;		/**< Control Register, offset: 0x0 */

  2677.   volatile uint16_t FILT;		/**< Input Filter Register, offset: 0x2 */

  2678.   volatile uint16_t WTR;		/**< Watchdog Timeout Register, offset: 0x4 */

  2679.   volatile uint16_t POSD;		/**< Position Difference Counter Register, offset: 0x6 */

  2680.   volatile uint16_t POSDH;		/**< Position Difference Hold Register, offset: 0x8 */

  2681.   volatile uint16_t REV;		/**< Revolution Counter Register, offset: 0xA */

  2682.   volatile uint16_t REVH;		/**< Revolution Hold Register, offset: 0xC */

  2683.   volatile uint16_t UPOS;		/**< Upper Position Counter Register, offset: 0xE */

  2684.   volatile uint16_t LPOS;		/**< Lower Position Counter Register, offset: 0x10 */

  2685.   volatile uint16_t UPOSH;		/**< Upper Position Hold Register, offset: 0x12 */

  2686.   volatile uint16_t LPOSH;		/**< Lower Position Hold Register, offset: 0x14 */

  2687.   volatile uint16_t UINIT;		/**< Upper Initialization Register, offset: 0x16 */

  2688.   volatile uint16_t LINIT;		/**< Lower Initialization Register, offset: 0x18 */

  2689.   volatile uint16_t IMR;		/**< Input Monitor Register, offset: 0x1A */

  2690.   volatile uint16_t TST;		/**< Test Register, offset: 0x1C */

  2691.   volatile uint16_t CTRL2;		/**< Control 2 Register, offset: 0x1E */

  2692.   volatile uint16_t UMOD;		/**< Upper Modulus Register, offset: 0x20 */

  2693.   volatile uint16_t LMOD;		/**< Lower Modulus Register, offset: 0x22 */

  2694.   volatile uint16_t UCOMP;		/**< Upper Position Compare Register, offset: 0x24 */

  2695.   volatile uint16_t LCOMP;		/**< Lower Position Compare Register, offset: 0x26 */

  2696. } IMXRT_ENC_t;

  2697. 

  2698. 

  2699. #define IMXRT_ENC1		(*(IMXRT_ENC_t *)0x403C8000)

  2700. #define ENC1_CTRL			(IMXRT_ENC1.CTRL)

  2701. #define ENC1_FILT			(IMXRT_ENC1.FILT)

  2702. #define ENC1_WTR			(IMXRT_ENC1.WTR)

  2703. #define ENC1_POSD			(IMXRT_ENC1.POSD)

  2704. #define ENC1_POSDH			(IMXRT_ENC1.POSDH)

  2705. #define ENC1_REV			(IMXRT_ENC1.REV)

  2706. #define ENC1_REVH			(IMXRT_ENC1.REVH)

  2707. #define ENC1_UPOS			(IMXRT_ENC1.UPOS)

  2708. #define ENC1_LPOS			(IMXRT_ENC1.LPOS)

  2709. #define ENC1_UPOSH			(IMXRT_ENC1.UPOSH)

  2710. #define ENC1_LPOSH			(IMXRT_ENC1.LPOSH)

  2711. #define ENC1_UINIT			(IMXRT_ENC1.UINIT)

  2712. #define ENC1_LINIT			(IMXRT_ENC1.LINIT)

  2713. #define ENC1_IMR			(IMXRT_ENC1.IMR)

  2714. #define ENC1_TST			(IMXRT_ENC1.TST)

  2715. #define ENC1_CTRL2			(IMXRT_ENC1.CTRL2)

  2716. #define ENC1_UMOD			(IMXRT_ENC1.UMOD)

  2717. #define ENC1_LMOD			(IMXRT_ENC1.LMOD)

  2718. #define ENC1_UCOMP			(IMXRT_ENC1.UCOMP)

  2719. #define ENC1_LCOMP			(IMXRT_ENC1.LCOMP)

  2720. #define IMXRT_ENC2		(*(IMXRT_ENC_t *)0x403CC000)

  2721. #define ENC2_CTRL			(IMXRT_ENC2.CTRL)

  2722. #define ENC2_FILT			(IMXRT_ENC2.FILT)

  2723. #define ENC2_WTR			(IMXRT_ENC2.WTR)

  2724. #define ENC2_POSD			(IMXRT_ENC2.POSD)

  2725. #define ENC2_POSDH			(IMXRT_ENC2.POSDH)

  2726. #define ENC2_REV			(IMXRT_ENC2.REV)

  2727. #define ENC2_REVH			(IMXRT_ENC2.REVH)

  2728. #define ENC2_UPOS			(IMXRT_ENC2.UPOS)

  2729. #define ENC2_LPOS			(IMXRT_ENC2.LPOS)

  2730. #define ENC2_UPOSH			(IMXRT_ENC2.UPOSH)

  2731. #define ENC2_LPOSH			(IMXRT_ENC2.LPOSH)

  2732. #define ENC2_UINIT			(IMXRT_ENC2.UINIT)

  2733. #define ENC2_LINIT			(IMXRT_ENC2.LINIT)

  2734. #define ENC2_IMR			(IMXRT_ENC2.IMR)

  2735. #define ENC2_TST			(IMXRT_ENC2.TST)

  2736. #define ENC2_CTRL2			(IMXRT_ENC2.CTRL2)

  2737. #define ENC2_UMOD			(IMXRT_ENC2.UMOD)

  2738. #define ENC2_LMOD			(IMXRT_ENC2.LMOD)

  2739. #define ENC2_UCOMP			(IMXRT_ENC2.UCOMP)

  2740. #define ENC2_LCOMP			(IMXRT_ENC2.LCOMP)

  2741. #define IMXRT_ENC3		(*(IMXRT_ENC_t *)0x403D0000)

  2742. #define ENC3_CTRL			(IMXRT_ENC3.CTRL)

  2743. #define ENC3_FILT			(IMXRT_ENC3.FILT)

  2744. #define ENC3_WTR			(IMXRT_ENC3.WTR)

  2745. #define ENC3_POSD			(IMXRT_ENC3.POSD)

  2746. #define ENC3_POSDH			(IMXRT_ENC3.POSDH)

  2747. #define ENC3_REV			(IMXRT_ENC3.REV)

  2748. #define ENC3_REVH			(IMXRT_ENC3.REVH)

  2749. #define ENC3_UPOS			(IMXRT_ENC3.UPOS)

  2750. #define ENC3_LPOS			(IMXRT_ENC3.LPOS)

  2751. #define ENC3_UPOSH			(IMXRT_ENC3.UPOSH)

  2752. #define ENC3_LPOSH			(IMXRT_ENC3.LPOSH)

  2753. #define ENC3_UINIT			(IMXRT_ENC3.UINIT)

  2754. #define ENC3_LINIT			(IMXRT_ENC3.LINIT)

  2755. #define ENC3_IMR			(IMXRT_ENC3.IMR)

  2756. #define ENC3_TST			(IMXRT_ENC3.TST)

  2757. #define ENC3_CTRL2			(IMXRT_ENC3.CTRL2)

  2758. #define ENC3_UMOD			(IMXRT_ENC3.UMOD)

  2759. #define ENC3_LMOD			(IMXRT_ENC3.LMOD)

  2760. #define ENC3_UCOMP			(IMXRT_ENC3.UCOMP)

  2761. #define ENC3_LCOMP			(IMXRT_ENC3.LCOMP)

  2762. #define IMXRT_ENC4		(*(IMXRT_ENC_t *)0x403D4000)

  2763. #define ENC4_CTRL			(IMXRT_ENC4.CTRL)

  2764. #define ENC4_FILT			(IMXRT_ENC4.FILT)

  2765. #define ENC4_WTR			(IMXRT_ENC4.WTR)

  2766. #define ENC4_POSD			(IMXRT_ENC4.POSD)

  2767. #define ENC4_POSDH			(IMXRT_ENC4.POSDH)

  2768. #define ENC4_REV			(IMXRT_ENC4.REV)

  2769. #define ENC4_REVH			(IMXRT_ENC4.REVH)

  2770. #define ENC4_UPOS			(IMXRT_ENC4.UPOS)

  2771. #define ENC4_LPOS			(IMXRT_ENC4.LPOS)

  2772. #define ENC4_UPOSH			(IMXRT_ENC4.UPOSH)

  2773. #define ENC4_LPOSH			(IMXRT_ENC4.LPOSH)

  2774. #define ENC4_UINIT			(IMXRT_ENC4.UINIT)

  2775. #define ENC4_LINIT			(IMXRT_ENC4.LINIT)

  2776. #define ENC4_IMR			(IMXRT_ENC4.IMR)

  2777. #define ENC4_TST			(IMXRT_ENC4.TST)

  2778. #define ENC4_CTRL2			(IMXRT_ENC4.CTRL2)

  2779. #define ENC4_UMOD			(IMXRT_ENC4.UMOD)

  2780. #define ENC4_LMOD			(IMXRT_ENC4.LMOD)

  2781. #define ENC4_UCOMP			(IMXRT_ENC4.UCOMP)

  2782. #define ENC4_LCOMP			(IMXRT_ENC4.LCOMP)

  2783. 

  2784. // 41.6: page 2068

  2785. #define IMXRT_ENET		(*(IMXRT_REGISTER32_t *)0x402D8000)

  2786. #define IMXRT_ENET_TIMER	(*(IMXRT_REGISTER32_t *)0x402D8400)

  2787. #define ENET_EIR			(IMXRT_ENET.offset004)

  2788. #define ENET_EIMR			(IMXRT_ENET.offset008)

  2789. #define ENET_RDAR			(IMXRT_ENET.offset010)

  2790. #define ENET_TDAR			(IMXRT_ENET.offset014)

  2791. #define ENET_ECR			(IMXRT_ENET.offset024)

  2792. #define ENET_MMFR			(IMXRT_ENET.offset040)

  2793. #define ENET_MSCR			(IMXRT_ENET.offset044)

  2794. #define ENET_MIBC			(IMXRT_ENET.offset064)

  2795. #define ENET_RCR			(IMXRT_ENET.offset084)

  2796. #define ENET_TCR			(IMXRT_ENET.offset0C4)

  2797. #define ENET_PALR			(IMXRT_ENET.offset0E4)

  2798. #define ENET_PAUR			(IMXRT_ENET.offset0E8)

  2799. #define ENET_OPD			(IMXRT_ENET.offset0EC)

  2800. #define ENET_TXIC			(IMXRT_ENET.offset0F0)

  2801. #define ENET_RXIC			(IMXRT_ENET.offset100)

  2802. #define ENET_IAUR			(IMXRT_ENET.offset118)

  2803. #define ENET_IALR			(IMXRT_ENET.offset11C)

  2804. #define ENET_GAUR			(IMXRT_ENET.offset120)

  2805. #define ENET_GALR			(IMXRT_ENET.offset124)

  2806. #define ENET_TFWR			(IMXRT_ENET.offset144)

  2807. #define ENET_RDSR			(IMXRT_ENET.offset180)

  2808. #define ENET_TDSR			(IMXRT_ENET.offset184)

  2809. #define ENET_MRBR			(IMXRT_ENET.offset188)

  2810. #define ENET_RSFL			(IMXRT_ENET.offset190)

  2811. #define ENET_RSEM			(IMXRT_ENET.offset194)

  2812. #define ENET_RAEM			(IMXRT_ENET.offset198)

  2813. #define ENET_RAFL			(IMXRT_ENET.offset19C)

  2814. #define ENET_TSEM			(IMXRT_ENET.offset1A0)

  2815. #define ENET_TAEM			(IMXRT_ENET.offset1A4)

  2816. #define ENET_TAFL			(IMXRT_ENET.offset1A8)

  2817. #define ENET_TIPG			(IMXRT_ENET.offset1AC)

  2818. #define ENET_FTRL			(IMXRT_ENET.offset1B0)

  2819. #define ENET_TACC			(IMXRT_ENET.offset1C0)

  2820. #define ENET_RACC			(IMXRT_ENET.offset1C4)

  2821. #define ENET_RMON_T_DROP		(IMXRT_ENET.offset200)

  2822. #define ENET_RMON_T_PACKETS		(IMXRT_ENET.offset204)

  2823. #define ENET_RMON_T_BC_PKT		(IMXRT_ENET.offset208)

  2824. #define ENET_RMON_T_MC_PKT		(IMXRT_ENET.offset20C)

  2825. #define ENET_RMON_T_CRC_ALIGN		(IMXRT_ENET.offset210)

  2826. #define ENET_RMON_T_UNDERSIZE		(IMXRT_ENET.offset214)

  2827. #define ENET_RMON_T_OVERSIZE		(IMXRT_ENET.offset218)

  2828. #define ENET_RMON_T_FRAG		(IMXRT_ENET.offset21C)

  2829. #define ENET_RMON_T_JAB			(IMXRT_ENET.offset220)

  2830. #define ENET_RMON_T_COL			(IMXRT_ENET.offset224)

  2831. #define ENET_RMON_T_P64			(IMXRT_ENET.offset228)

  2832. #define ENET_RMON_T_P65TO127		(IMXRT_ENET.offset22C)

  2833. #define ENET_RMON_T_P128TO255		(IMXRT_ENET.offset230)

  2834. #define ENET_RMON_T_P256TO511		(IMXRT_ENET.offset234)

  2835. #define ENET_RMON_T_P512TO1023		(IMXRT_ENET.offset238)

  2836. #define ENET_RMON_T_P1024TO2047		(IMXRT_ENET.offset23C)

  2837. #define ENET_RMON_T_P_GTE2048		(IMXRT_ENET.offset240)

  2838. #define ENET_RMON_T_OCTETS		(IMXRT_ENET.offset244)

  2839. #define ENET_IEEE_T_DROP		(IMXRT_ENET.offset248)

  2840. #define ENET_IEEE_T_FRAME_OK		(IMXRT_ENET.offset24C)

  2841. #define ENET_IEEE_T_1COL		(IMXRT_ENET.offset250)

  2842. #define ENET_IEEE_T_MCOL		(IMXRT_ENET.offset254)

  2843. #define ENET_IEEE_T_DEF			(IMXRT_ENET.offset258)

  2844. #define ENET_IEEE_T_LCOL		(IMXRT_ENET.offset25C)

  2845. #define ENET_IEEE_T_EXCOL		(IMXRT_ENET.offset260)

  2846. #define ENET_IEEE_T_MACERR		(IMXRT_ENET.offset264)

  2847. #define ENET_IEEE_T_CSERR		(IMXRT_ENET.offset268)

  2848. #define ENET_IEEE_T_SQE			(IMXRT_ENET.offset26C)

  2849. #define ENET_IEEE_T_FDXFC		(IMXRT_ENET.offset270)

  2850. #define ENET_IEEE_T_OCTETS_OK		(IMXRT_ENET.offset274)

  2851. #define ENET_RMON_R_PACKETS		(IMXRT_ENET.offset284)

  2852. #define ENET_RMON_R_BC_PKT		(IMXRT_ENET.offset288)

  2853. #define ENET_RMON_R_MC_PKT		(IMXRT_ENET.offset28C)

  2854. #define ENET_RMON_R_CRC_ALIGN		(IMXRT_ENET.offset290)

  2855. #define ENET_RMON_R_UNDERSIZE		(IMXRT_ENET.offset294)

  2856. #define ENET_RMON_R_OVERSIZE		(IMXRT_ENET.offset298)

  2857. #define ENET_RMON_R_FRAG		(IMXRT_ENET.offset29C)

  2858. #define ENET_RMON_R_JAB			(IMXRT_ENET.offset2A0)

  2859. #define ENET_RMON_R_RESVD_0		(IMXRT_ENET.offset2A4)

  2860. #define ENET_RMON_R_P64			(IMXRT_ENET.offset2A8)

  2861. #define ENET_RMON_R_P65TO127		(IMXRT_ENET.offset2AC)

  2862. #define ENET_RMON_R_P128TO255		(IMXRT_ENET.offset2B0)

  2863. #define ENET_RMON_R_P256TO511		(IMXRT_ENET.offset2B4)

  2864. #define ENET_RMON_R_P512TO1023		(IMXRT_ENET.offset2B8)

  2865. #define ENET_RMON_R_P1024TO2047		(IMXRT_ENET.offset2BC)

  2866. #define ENET_RMON_R_P_GTE2048		(IMXRT_ENET.offset2C0)

  2867. #define ENET_RMON_R_OCTETS		(IMXRT_ENET.offset2C4)

  2868. #define ENET_IEEE_R_DROP		(IMXRT_ENET.offset2C8)

  2869. #define ENET_IEEE_R_FRAME_OK		(IMXRT_ENET.offset2CC)

  2870. #define ENET_IEEE_R_CRC			(IMXRT_ENET.offset2D0)

  2871. #define ENET_IEEE_R_ALIGN		(IMXRT_ENET.offset2D4)

  2872. #define ENET_IEEE_R_MACERR		(IMXRT_ENET.offset2D8)

  2873. #define ENET_IEEE_R_FDXFC		(IMXRT_ENET.offset2DC)

  2874. #define ENET_IEEE_R_OCTETS_OK		(IMXRT_ENET.offset2E0)

  2875. #define ENET_ATCR			(IMXRT_ENET_TIMER.offset000)

  2876. #define ENET_ATVR			(IMXRT_ENET_TIMER.offset004)

  2877. #define ENET_ATOFF			(IMXRT_ENET_TIMER.offset008)

  2878. #define ENET_ATPER			(IMXRT_ENET_TIMER.offset00C)

  2879. #define ENET_ATCOR			(IMXRT_ENET_TIMER.offset010)

  2880. #define ENET_ATINC			(IMXRT_ENET_TIMER.offset014)

  2881. #define ENET_ATSTMP			(IMXRT_ENET_TIMER.offset018)

  2882. #define ENET_TGSR			(IMXRT_ENET_TIMER.offset204)

  2883. #define ENET_TCSR0			(IMXRT_ENET_TIMER.offset208)

  2884. #define ENET_TCCR0			(IMXRT_ENET_TIMER.offset20C)

  2885. #define ENET_TCSR1			(IMXRT_ENET_TIMER.offset210)

  2886. #define ENET_TCCR1			(IMXRT_ENET_TIMER.offset214)

  2887. #define ENET_TCSR2			(IMXRT_ENET_TIMER.offset218)

  2888. #define ENET_TCCR2			(IMXRT_ENET_TIMER.offset21C)

  2889. #define ENET_TCSR3			(IMXRT_ENET_TIMER.offset220)

  2890. #define ENET_TCCR3			(IMXRT_ENET_TIMER.offset224)

  2891. #define ENET_EIR_BABR				((uint32_t)(1<<30))

  2892. #define ENET_EIR_BABT				((uint32_t)(1<<29))

  2893. #define ENET_EIR_GRA				((uint32_t)(1<<28))

  2894. #define ENET_EIR_TXF				((uint32_t)(1<<27))

  2895. #define ENET_EIR_TXB				((uint32_t)(1<<26))

  2896. #define ENET_EIR_RXF				((uint32_t)(1<<25))

  2897. #define ENET_EIR_RXB				((uint32_t)(1<<24))

  2898. #define ENET_EIR_MII				((uint32_t)(1<<23))

  2899. #define ENET_EIR_EBERR				((uint32_t)(1<<22))

  2900. #define ENET_EIR_LC				((uint32_t)(1<<21))

  2901. #define ENET_EIR_RL				((uint32_t)(1<<20))

  2902. #define ENET_EIR_UN				((uint32_t)(1<<19))

  2903. #define ENET_EIR_PLR				((uint32_t)(1<<18))

  2904. #define ENET_EIR_WAKEUP				((uint32_t)(1<<17))

  2905. #define ENET_EIR_TS_AVAIL			((uint32_t)(1<<16))

  2906. #define ENET_EIR_TS_TIMER			((uint32_t)(1<<15))

  2907. #define ENET_EIMR_BABR				((uint32_t)(1<<30))

  2908. #define ENET_EIMR_BABT				((uint32_t)(1<<29))

  2909. #define ENET_EIMR_GRA				((uint32_t)(1<<28))

  2910. #define ENET_EIMR_TXF				((uint32_t)(1<<27))

  2911. #define ENET_EIMR_TXB				((uint32_t)(1<<26))

  2912. #define ENET_EIMR_RXF				((uint32_t)(1<<25))

  2913. #define ENET_EIMR_RXB				((uint32_t)(1<<24))

  2914. #define ENET_EIMR_MII				((uint32_t)(1<<23))

  2915. #define ENET_EIMR_EBERR				((uint32_t)(1<<22))

  2916. #define ENET_EIMR_LC				((uint32_t)(1<<21))

  2917. #define ENET_EIMR_RL				((uint32_t)(1<<20))

  2918. #define ENET_EIMR_UN				((uint32_t)(1<<19))

  2919. #define ENET_EIMR_PLR				((uint32_t)(1<<18))

  2920. #define ENET_EIMR_WAKEUP			((uint32_t)(1<<17))

  2921. #define ENET_EIMR_TS_AVAIL			((uint32_t)(1<<16))

  2922. #define ENET_EIMR_TS_TIMER			((uint32_t)(1<<15))

  2923. #define ENET_RDAR_RDAR				((uint32_t)(1<<24))

  2924. #define ENET_TDAR_TDAR				((uint32_t)(1<<24))

  2925. #define ENET_ECR_DBSWP				((uint32_t)(1<<8))

  2926. #define ENET_ECR_DBGEN				((uint32_t)(1<<6))

  2927. #define ENET_ECR_EN1588				((uint32_t)(1<<4))

  2928. #define ENET_ECR_SLEEP				((uint32_t)(1<<3))

  2929. #define ENET_ECR_MAGICEN			((uint32_t)(1<<2))

  2930. #define ENET_ECR_ETHEREN			((uint32_t)(1<<1))

  2931. #define ENET_ECR_RESET				((uint32_t)(1<<0))

  2932. #define ENET_MMFR_ST(n)				((uint32_t)(((n) & 0x03) << 30))

  2933. #define ENET_MMFR_OP(n)				((uint32_t)(((n) & 0x03) << 28))

  2934. #define ENET_MMFR_PA(n)				((uint32_t)(((n) & 0x1F) << 23))

  2935. #define ENET_MMFR_RA(n)				((uint32_t)(((n) & 0x1F) << 18))

  2936. #define ENET_MMFR_TA(n)				((uint32_t)(((n) & 0x03) << 16))

  2937. #define ENET_MMFR_DATA(n)			((uint32_t)(((n) & 0xFFFF) << 0))

  2938. #define ENET_MSCR_HOLDTIME(n)			((uint32_t)(((n) & 0x07) << 8))

  2939. #define ENET_MSCR_DIS_PRE			((uint32_t)(1<<7))

  2940. #define ENET_MSCR_MII_SPEED(n)			((uint32_t)(((n) & 0x3F) << 1))

  2941. #define ENET_MIBC_MIB_DIS			((uint32_t)(1<<31))

  2942. #define ENET_MIBC_MIB_IDLE			((uint32_t)(1<<30))

  2943. #define ENET_MIBC_MIB_CLEAR			((uint32_t)(1<<29))

  2944. #define ENET_RCR_GRS				((uint32_t)(1<<31))

  2945. #define ENET_RCR_NLC				((uint32_t)(1<<30))

  2946. #define ENET_RCR_MAX_FL(n)			((uint32_t)(((n) & 0x3FFF) << 16))

  2947. #define ENET_RCR_CFEN				((uint32_t)(1<<15))

  2948. #define ENET_RCR_CRCFWD				((uint32_t)(1<<14))

  2949. #define ENET_RCR_PAUFWD				((uint32_t)(1<<13))

  2950. #define ENET_RCR_PADEN				((uint32_t)(1<<12))

  2951. #define ENET_RCR_RMII_10T			((uint32_t)(1<<9))

  2952. #define ENET_RCR_RMII_MODE			((uint32_t)(1<<8))

  2953. #define ENET_RCR_FCE				((uint32_t)(1<<5))

  2954. #define ENET_RCR_BC_REJ				((uint32_t)(1<<4))

  2955. #define ENET_RCR_PROM				((uint32_t)(1<<3))

  2956. #define ENET_RCR_MII_MODE			((uint32_t)(1<<2))

  2957. #define ENET_RCR_DRT				((uint32_t)(1<<1))

  2958. #define ENET_RCR_LOOP				((uint32_t)(1<<0))

  2959. #define ENET_TCR_CRCFWD				((uint32_t)(1<<9))

  2960. #define ENET_TCR_ADDINS				((uint32_t)(1<<8))

  2961. #define ENET_TCR_ADDSEL(n)			((uint32_t)(((n) & 0x07) << 5))

  2962. #define ENET_TCR_RFC_PAUSE			((uint32_t)(1<<4))

  2963. #define ENET_TCR_TFC_PAUSE			((uint32_t)(1<<3))

  2964. #define ENET_TCR_FDEN				((uint32_t)(1<<2))

  2965. #define ENET_TCR_GTS				((uint32_t)(1<<0))

  2966. #define ENET_PAUR_PADDR2(n)			((uint32_t)(((n) & 0xFFFF) << 16))

  2967. #define ENET_PAUR_TYPE(n)			((uint32_t)(((n) & 0xFFFF) << 0))

  2968. #define ENET_OPD_OPCODE(n)			((uint32_t)(((n) & 0xFFFF) << 16))

  2969. #define ENET_OPD_PAUSE_DUR(n)			((uint32_t)(((n) & 0xFFFF) << 0))

  2970. #define ENET_TXIC_ICEN				((uint32_t)(1<<31))

  2971. #define ENET_TXIC_ICCS				((uint32_t)(1<<30))

  2972. #define ENET_TXIC_ICFT(n)			((uint32_t)(((n) & 0xFF) << 20))

  2973. #define ENET_TXIC_ICTT(n)			((uint32_t)(((n) & 0xFFFF) << 0))

  2974. #define ENET_RXIC_ICEN				((uint32_t)(1<<31))

  2975. #define ENET_RXIC_ICCS				((uint32_t)(1<<30))

  2976. #define ENET_RXIC_ICFT(n)			((uint32_t)(((n) & 0xFF) << 20))

  2977. #define ENET_RXIC_ICTT(n)			((uint32_t)(((n) & 0xFFFF) << 0))

  2978. #define ENET_TFWR_STRFWD			((uint32_t)(1<<8))

  2979. #define ENET_TFWR_TFWR(n)			((uint32_t)(((n) & 0x3F) << 0))

  2980. #define ENET_TACC_PROCHK			((uint32_t)(1<<4))

  2981. #define ENET_TACC_IPCHK				((uint32_t)(1<<3))

  2982. #define ENET_TACC_SHIFT16			((uint32_t)(1<<0))

  2983. #define ENET_RACC_SHIFT16			((uint32_t)(1<<7))

  2984. #define ENET_RACC_LINEDIS			((uint32_t)(1<<6))

  2985. #define ENET_RACC_PRODIS			((uint32_t)(1<<2))

  2986. #define ENET_RACC_IPDIS				((uint32_t)(1<<1))

  2987. #define ENET_RACC_PADREM			((uint32_t)(1<<0))

  2988. 

  2989. #define IMXRT_ENET2		(*(IMXRT_REGISTER32_t *)0x402D4000)

  2990. #define IMXRT_ENET2_TIMER	(*(IMXRT_REGISTER32_t *)0x402D4400)

  2991. #define ENET2_EIR			(IMXRT_ENET2.offset004)

  2992. #define ENET2_EIMR			(IMXRT_ENET2.offset008)

  2993. #define ENET2_RDAR			(IMXRT_ENET2.offset010)

  2994. #define ENET2_TDAR			(IMXRT_ENET2.offset014)

  2995. #define ENET2_ECR			(IMXRT_ENET2.offset024)

  2996. #define ENET2_MMFR			(IMXRT_ENET2.offset040)

  2997. #define ENET2_MSCR			(IMXRT_ENET2.offset044)

  2998. #define ENET2_MIBC			(IMXRT_ENET2.offset064)

  2999. #define ENET2_RCR			(IMXRT_ENET2.offset084)

  3000. #define ENET2_TCR			(IMXRT_ENET2.offset0C4)

  3001. #define ENET2_PALR			(IMXRT_ENET2.offset0E4)

  3002. #define ENET2_PAUR			(IMXRT_ENET2.offset0E8)

  3003. #define ENET2_OPD			(IMXRT_ENET2.offset0EC)

  3004. #define ENET2_TXIC			(IMXRT_ENET2.offset0F0)

  3005. #define ENET2_RXIC			(IMXRT_ENET2.offset100)

  3006. #define ENET2_IAUR			(IMXRT_ENET2.offset118)

  3007. #define ENET2_IALR			(IMXRT_ENET2.offset11C)

  3008. #define ENET2_GAUR			(IMXRT_ENET2.offset120)

  3009. #define ENET2_GALR			(IMXRT_ENET2.offset124)

  3010. #define ENET2_TFWR			(IMXRT_ENET2.offset144)

  3011. #define ENET2_RDSR			(IMXRT_ENET2.offset180)

  3012. #define ENET2_TDSR			(IMXRT_ENET2.offset184)

  3013. #define ENET2_MRBR			(IMXRT_ENET2.offset188)

  3014. #define ENET2_RSFL			(IMXRT_ENET2.offset190)

  3015. #define ENET2_RSEM			(IMXRT_ENET2.offset194)

  3016. #define ENET2_RAEM			(IMXRT_ENET2.offset198)

  3017. #define ENET2_RAFL			(IMXRT_ENET2.offset19C)

  3018. #define ENET2_TSEM			(IMXRT_ENET2.offset1A0)

  3019. #define ENET2_TAEM			(IMXRT_ENET2.offset1A4)

  3020. #define ENET2_TAFL			(IMXRT_ENET2.offset1A8)

  3021. #define ENET2_TIPG			(IMXRT_ENET2.offset1AC)

  3022. #define ENET2_FTRL			(IMXRT_ENET2.offset1B0)

  3023. #define ENET2_TACC			(IMXRT_ENET2.offset1C0)

  3024. #define ENET2_RACC			(IMXRT_ENET2.offset1C4)

  3025. #define ENET2_RMON_T_DROP		(IMXRT_ENET2.offset200)

  3026. #define ENET2_RMON_T_PACKETS		(IMXRT_ENET2.offset204)

  3027. #define ENET2_RMON_T_BC_PKT		(IMXRT_ENET2.offset208)

  3028. #define ENET2_RMON_T_MC_PKT		(IMXRT_ENET2.offset20C)

  3029. #define ENET2_RMON_T_CRC_ALIGN		(IMXRT_ENET2.offset210)

  3030. #define ENET2_RMON_T_UNDERSIZE		(IMXRT_ENET2.offset214)

  3031. #define ENET2_RMON_T_OVERSIZE		(IMXRT_ENET2.offset218)

  3032. #define ENET2_RMON_T_FRAG		(IMXRT_ENET2.offset21C)

  3033. #define ENET2_RMON_T_JAB		(IMXRT_ENET2.offset220)

  3034. #define ENET2_RMON_T_COL		(IMXRT_ENET2.offset224)

  3035. #define ENET2_RMON_T_P64		(IMXRT_ENET2.offset228)

  3036. #define ENET2_RMON_T_P65TO127		(IMXRT_ENET2.offset22C)

  3037. #define ENET2_RMON_T_P128TO255		(IMXRT_ENET2.offset230)

  3038. #define ENET2_RMON_T_P256TO511		(IMXRT_ENET2.offset234)

  3039. #define ENET2_RMON_T_P512TO1023		(IMXRT_ENET2.offset238)

  3040. #define ENET2_RMON_T_P1024TO2047	(IMXRT_ENET2.offset23C)

  3041. #define ENET2_RMON_T_P_GTE2048		(IMXRT_ENET2.offset240)

  3042. #define ENET2_RMON_T_OCTETS		(IMXRT_ENET2.offset244)

  3043. #define ENET2_IEEE_T_DROP		(IMXRT_ENET2.offset248)

  3044. #define ENET2_IEEE_T_FRAME_OK		(IMXRT_ENET2.offset24C)

  3045. #define ENET2_IEEE_T_1COL		(IMXRT_ENET2.offset250)

  3046. #define ENET2_IEEE_T_MCOL		(IMXRT_ENET2.offset254)

  3047. #define ENET2_IEEE_T_DEF		(IMXRT_ENET2.offset258)

  3048. #define ENET2_IEEE_T_LCOL		(IMXRT_ENET2.offset25C)

  3049. #define ENET2_IEEE_T_EXCOL		(IMXRT_ENET2.offset260)

  3050. #define ENET2_IEEE_T_MACERR		(IMXRT_ENET2.offset264)

  3051. #define ENET2_IEEE_T_CSERR		(IMXRT_ENET2.offset268)

  3052. #define ENET2_IEEE_T_SQE		(IMXRT_ENET2.offset26C)

  3053. #define ENET2_IEEE_T_FDXFC		(IMXRT_ENET2.offset270)

  3054. #define ENET2_IEEE_T_OCTETS_OK		(IMXRT_ENET2.offset274)

  3055. #define ENET2_RMON_R_PACKETS		(IMXRT_ENET2.offset284)

  3056. #define ENET2_RMON_R_BC_PKT		(IMXRT_ENET2.offset288)

  3057. #define ENET2_RMON_R_MC_PKT		(IMXRT_ENET2.offset28C)

  3058. #define ENET2_RMON_R_CRC_ALIGN		(IMXRT_ENET2.offset290)

  3059. #define ENET2_RMON_R_UNDERSIZE		(IMXRT_ENET2.offset294)

  3060. #define ENET2_RMON_R_OVERSIZE		(IMXRT_ENET2.offset298)

  3061. #define ENET2_RMON_R_FRAG		(IMXRT_ENET2.offset29C)

  3062. #define ENET2_RMON_R_JAB		(IMXRT_ENET2.offset2A0)

  3063. #define ENET2_RMON_R_RESVD_0		(IMXRT_ENET2.offset2A4)

  3064. #define ENET2_RMON_R_P64		(IMXRT_ENET2.offset2A8)

  3065. #define ENET2_RMON_R_P65TO127		(IMXRT_ENET2.offset2AC)

  3066. #define ENET2_RMON_R_P128TO255		(IMXRT_ENET2.offset2B0)

  3067. #define ENET2_RMON_R_P256TO511		(IMXRT_ENET2.offset2B4)

  3068. #define ENET2_RMON_R_P512TO1023		(IMXRT_ENET2.offset2B8)

  3069. #define ENET2_RMON_R_P1024TO2047	(IMXRT_ENET2.offset2BC)

  3070. #define ENET2_RMON_R_P_GTE2048		(IMXRT_ENET2.offset2C0)

  3071. #define ENET2_RMON_R_OCTETS		(IMXRT_ENET2.offset2C4)

  3072. #define ENET2_IEEE_R_DROP		(IMXRT_ENET2.offset2C8)

  3073. #define ENET2_IEEE_R_FRAME_OK		(IMXRT_ENET2.offset2CC)

  3074. #define ENET2_IEEE_R_CRC		(IMXRT_ENET2.offset2D0)

  3075. #define ENET2_IEEE_R_ALIGN		(IMXRT_ENET2.offset2D4)

  3076. #define ENET2_IEEE_R_MACERR		(IMXRT_ENET2.offset2D8)

  3077. #define ENET2_IEEE_R_FDXFC		(IMXRT_ENET2.offset2DC)

  3078. #define ENET2_IEEE_R_OCTETS_OK		(IMXRT_ENET2.offset2E0)

  3079. #define ENET2_ATCR			(IMXRT_ENET2_TIMER.offset000)

  3080. #define ENET2_ATVR			(IMXRT_ENET2_TIMER.offset004)

  3081. #define ENET2_ATOFF			(IMXRT_ENET2_TIMER.offset008)

  3082. #define ENET2_ATPER			(IMXRT_ENET2_TIMER.offset00C)

  3083. #define ENET2_ATCOR			(IMXRT_ENET2_TIMER.offset010)

  3084. #define ENET2_ATINC			(IMXRT_ENET2_TIMER.offset014)

  3085. #define ENET2_ATSTMP			(IMXRT_ENET2_TIMER.offset018)

  3086. #define ENET2_TGSR			(IMXRT_ENET2_TIMER.offset204)

  3087. #define ENET2_TCSR0			(IMXRT_ENET2_TIMER.offset208)

  3088. #define ENET2_TCCR0			(IMXRT_ENET2_TIMER.offset20C)

  3089. #define ENET2_TCSR1			(IMXRT_ENET2_TIMER.offset210)

  3090. #define ENET2_TCCR1			(IMXRT_ENET2_TIMER.offset214)

  3091. #define ENET2_TCSR2			(IMXRT_ENET2_TIMER.offset218)

  3092. #define ENET2_TCCR2			(IMXRT_ENET2_TIMER.offset21C)

  3093. #define ENET2_TCSR3			(IMXRT_ENET2_TIMER.offset220)

  3094. #define ENET2_TCCR3			(IMXRT_ENET2_TIMER.offset224)

  3095. 

  3096. // 59.6.1.1: page 3221

  3097. #define IMXRT_EWM		(*(IMXRT_REGISTER8_t *)0x400B4000)

  3098. #define EWM_CTRL			(IMXRT_EWM.offset00)

  3099. #define EWM_SERV			(IMXRT_EWM.offset01)

  3100. #define EWM_CMPL			(IMXRT_EWM.offset02)

  3101. #define EWM_CMPH			(IMXRT_EWM.offset03)

  3102. #define EWM_CLKCTRL			(IMXRT_EWM.offset04)

  3103. #define EWM_CLKPRESCALER		(IMXRT_EWM.offset05)

  3104. 

  3105. // 44.9: page 2555

  3106. #define IMXRT_FLEXCAN1		(*(IMXRT_REGISTER32_t *)0x401D0000)

  3107. #define IMXRT_FLEXCAN1_MASK	(*(IMXRT_REGISTER32_t *)0x401D0800)

  3108. #define FLEXCAN1_MCR			(IMXRT_FLEXCAN1.offset000)

  3109. #define FLEXCAN1_CTRL1			(IMXRT_FLEXCAN1.offset004)

  3110. #define FLEXCAN1_TIMER			(IMXRT_FLEXCAN1.offset008)

  3111. #define FLEXCAN1_RXMGMASK		(IMXRT_FLEXCAN1.offset010)

  3112. #define FLEXCAN1_RX14MASK		(IMXRT_FLEXCAN1.offset014)

  3113. #define FLEXCAN1_RX15MASK		(IMXRT_FLEXCAN1.offset018)

  3114. #define FLEXCAN1_ECR			(IMXRT_FLEXCAN1.offset01C)

  3115. #define FLEXCAN1_ESR1			(IMXRT_FLEXCAN1.offset020)

  3116. #define FLEXCAN1_IMASK2			(IMXRT_FLEXCAN1.offset024)

  3117. #define FLEXCAN1_IMASK1			(IMXRT_FLEXCAN1.offset028)

  3118. #define FLEXCAN1_IFLAG2			(IMXRT_FLEXCAN1.offset02C)

  3119. #define FLEXCAN1_IFLAG1			(IMXRT_FLEXCAN1.offset030)

  3120. #define FLEXCAN1_CTRL2			(IMXRT_FLEXCAN1.offset034)

  3121. #define FLEXCAN1_ESR2			(IMXRT_FLEXCAN1.offset038)

  3122. #define FLEXCAN1_CRCR			(IMXRT_FLEXCAN1.offset044)

  3123. #define FLEXCAN1_RXFGMASK		(IMXRT_FLEXCAN1.offset048)

  3124. #define FLEXCAN1_RXFIR			(IMXRT_FLEXCAN1.offset04C)

  3125. #define FLEXCAN1_RXIMR0			(IMXRT_FLEXCAN1_MASK.offset080)

  3126. #define FLEXCAN1_RXIMR1			(IMXRT_FLEXCAN1_MASK.offset084)

  3127. #define FLEXCAN1_RXIMR2			(IMXRT_FLEXCAN1_MASK.offset088)

  3128. #define FLEXCAN1_RXIMR3			(IMXRT_FLEXCAN1_MASK.offset08C)

  3129. #define FLEXCAN1_RXIMR4			(IMXRT_FLEXCAN1_MASK.offset090)

  3130. #define FLEXCAN1_RXIMR5			(IMXRT_FLEXCAN1_MASK.offset094)

  3131. #define FLEXCAN1_RXIMR6			(IMXRT_FLEXCAN1_MASK.offset098)

  3132. #define FLEXCAN1_RXIMR7			(IMXRT_FLEXCAN1_MASK.offset09C)

  3133. #define FLEXCAN1_RXIMR8			(IMXRT_FLEXCAN1_MASK.offset0A0)

  3134. #define FLEXCAN1_RXIMR9			(IMXRT_FLEXCAN1_MASK.offset0A4)

  3135. #define FLEXCAN1_RXIMR10		(IMXRT_FLEXCAN1_MASK.offset0A8)

  3136. #define FLEXCAN1_RXIMR11		(IMXRT_FLEXCAN1_MASK.offset0AC)

  3137. #define FLEXCAN1_RXIMR12		(IMXRT_FLEXCAN1_MASK.offset0B0)

  3138. #define FLEXCAN1_RXIMR13		(IMXRT_FLEXCAN1_MASK.offset0B4)

  3139. #define FLEXCAN1_RXIMR14		(IMXRT_FLEXCAN1_MASK.offset0B8)

  3140. #define FLEXCAN1_RXIMR15		(IMXRT_FLEXCAN1_MASK.offset0BC)

  3141. #define FLEXCAN1_RXIMR16		(IMXRT_FLEXCAN1_MASK.offset0C0)

  3142. #define FLEXCAN1_RXIMR17		(IMXRT_FLEXCAN1_MASK.offset0C4)

  3143. #define FLEXCAN1_RXIMR18		(IMXRT_FLEXCAN1_MASK.offset0C8)

  3144. #define FLEXCAN1_RXIMR19		(IMXRT_FLEXCAN1_MASK.offset0CC)

  3145. #define FLEXCAN1_RXIMR20		(IMXRT_FLEXCAN1_MASK.offset0D0)

  3146. #define FLEXCAN1_RXIMR21		(IMXRT_FLEXCAN1_MASK.offset0D4)

  3147. #define FLEXCAN1_RXIMR22		(IMXRT_FLEXCAN1_MASK.offset0D8)

  3148. #define FLEXCAN1_RXIMR23		(IMXRT_FLEXCAN1_MASK.offset0DC)

  3149. #define FLEXCAN1_RXIMR24		(IMXRT_FLEXCAN1_MASK.offset0E0)

  3150. #define FLEXCAN1_RXIMR25		(IMXRT_FLEXCAN1_MASK.offset0E4)

  3151. #define FLEXCAN1_RXIMR26		(IMXRT_FLEXCAN1_MASK.offset0E8)

  3152. #define FLEXCAN1_RXIMR27		(IMXRT_FLEXCAN1_MASK.offset0EC)

  3153. #define FLEXCAN1_RXIMR28		(IMXRT_FLEXCAN1_MASK.offset0F0)

  3154. #define FLEXCAN1_RXIMR29		(IMXRT_FLEXCAN1_MASK.offset0F4)

  3155. #define FLEXCAN1_RXIMR30		(IMXRT_FLEXCAN1_MASK.offset0F8)

  3156. #define FLEXCAN1_RXIMR31		(IMXRT_FLEXCAN1_MASK.offset0FC)

  3157. #define FLEXCAN1_RXIMR32		(IMXRT_FLEXCAN1_MASK.offset100)

  3158. #define FLEXCAN1_RXIMR33		(IMXRT_FLEXCAN1_MASK.offset104)

  3159. #define FLEXCAN1_RXIMR34		(IMXRT_FLEXCAN1_MASK.offset108)

  3160. #define FLEXCAN1_RXIMR35		(IMXRT_FLEXCAN1_MASK.offset10C)

  3161. #define FLEXCAN1_RXIMR36		(IMXRT_FLEXCAN1_MASK.offset110)

  3162. #define FLEXCAN1_RXIMR37		(IMXRT_FLEXCAN1_MASK.offset114)

  3163. #define FLEXCAN1_RXIMR38		(IMXRT_FLEXCAN1_MASK.offset118)

  3164. #define FLEXCAN1_RXIMR39		(IMXRT_FLEXCAN1_MASK.offset11C)

  3165. #define FLEXCAN1_RXIMR40		(IMXRT_FLEXCAN1_MASK.offset120)

  3166. #define FLEXCAN1_RXIMR41		(IMXRT_FLEXCAN1_MASK.offset124)

  3167. #define FLEXCAN1_RXIMR42		(IMXRT_FLEXCAN1_MASK.offset128)

  3168. #define FLEXCAN1_RXIMR43		(IMXRT_FLEXCAN1_MASK.offset12C)

  3169. #define FLEXCAN1_RXIMR44		(IMXRT_FLEXCAN1_MASK.offset130)

  3170. #define FLEXCAN1_RXIMR45		(IMXRT_FLEXCAN1_MASK.offset134)

  3171. #define FLEXCAN1_RXIMR46		(IMXRT_FLEXCAN1_MASK.offset138)

  3172. #define FLEXCAN1_RXIMR47		(IMXRT_FLEXCAN1_MASK.offset13C)

  3173. #define FLEXCAN1_RXIMR48		(IMXRT_FLEXCAN1_MASK.offset140)

  3174. #define FLEXCAN1_RXIMR49		(IMXRT_FLEXCAN1_MASK.offset144)

  3175. #define FLEXCAN1_RXIMR50		(IMXRT_FLEXCAN1_MASK.offset148)

  3176. #define FLEXCAN1_RXIMR51		(IMXRT_FLEXCAN1_MASK.offset14C)

  3177. #define FLEXCAN1_RXIMR52		(IMXRT_FLEXCAN1_MASK.offset150)

  3178. #define FLEXCAN1_RXIMR53		(IMXRT_FLEXCAN1_MASK.offset154)

  3179. #define FLEXCAN1_RXIMR54		(IMXRT_FLEXCAN1_MASK.offset158)

  3180. #define FLEXCAN1_RXIMR55		(IMXRT_FLEXCAN1_MASK.offset15C)

  3181. #define FLEXCAN1_RXIMR56		(IMXRT_FLEXCAN1_MASK.offset160)

  3182. #define FLEXCAN1_RXIMR57		(IMXRT_FLEXCAN1_MASK.offset164)

  3183. #define FLEXCAN1_RXIMR58		(IMXRT_FLEXCAN1_MASK.offset168)

  3184. #define FLEXCAN1_RXIMR59		(IMXRT_FLEXCAN1_MASK.offset16C)

  3185. #define FLEXCAN1_RXIMR60		(IMXRT_FLEXCAN1_MASK.offset170)

  3186. #define FLEXCAN1_RXIMR61		(IMXRT_FLEXCAN1_MASK.offset174)

  3187. #define FLEXCAN1_RXIMR62		(IMXRT_FLEXCAN1_MASK.offset178)

  3188. #define FLEXCAN1_RXIMR63		(IMXRT_FLEXCAN1_MASK.offset17C)

  3189. #define FLEXCAN1_GFWR			(IMXRT_FLEXCAN1_MASK.offset1E0)

  3190. #define IMXRT_FLEXCAN2		(*(IMXRT_REGISTER32_t *)0x401D4000)

  3191. #define IMXRT_FLEXCAN2_MASK	(*(IMXRT_REGISTER32_t *)0x401D4800)

  3192. #define FLEXCAN2_MCR			(IMXRT_FLEXCAN2.offset000)

  3193. #define FLEXCAN2_CTRL1			(IMXRT_FLEXCAN2.offset004)

  3194. #define FLEXCAN2_TIMER			(IMXRT_FLEXCAN2.offset008)

  3195. #define FLEXCAN2_RXMGMASK		(IMXRT_FLEXCAN2.offset010)

  3196. #define FLEXCAN2_RX14MASK		(IMXRT_FLEXCAN2.offset014)

  3197. #define FLEXCAN2_RX15MASK		(IMXRT_FLEXCAN2.offset018)

  3198. #define FLEXCAN2_ECR			(IMXRT_FLEXCAN2.offset01C)

  3199. #define FLEXCAN2_ESR1			(IMXRT_FLEXCAN2.offset020)

  3200. #define FLEXCAN2_IMASK2			(IMXRT_FLEXCAN2.offset024)

  3201. #define FLEXCAN2_IMASK1			(IMXRT_FLEXCAN2.offset028)

  3202. #define FLEXCAN2_IFLAG2			(IMXRT_FLEXCAN2.offset02C)

  3203. #define FLEXCAN2_IFLAG1			(IMXRT_FLEXCAN2.offset030)

  3204. #define FLEXCAN2_CTRL2			(IMXRT_FLEXCAN2.offset034)

  3205. #define FLEXCAN2_ESR2			(IMXRT_FLEXCAN2.offset038)

  3206. #define FLEXCAN2_CRCR			(IMXRT_FLEXCAN2.offset044)

  3207. #define FLEXCAN2_RXFGMASK		(IMXRT_FLEXCAN2.offset048)

  3208. #define FLEXCAN2_RXFIR			(IMXRT_FLEXCAN2.offset04C)

  3209. #define FLEXCAN2_RXIMR0			(IMXRT_FLEXCAN2_MASK.offset080)

  3210. #define FLEXCAN2_RXIMR1			(IMXRT_FLEXCAN2_MASK.offset084)

  3211. #define FLEXCAN2_RXIMR2			(IMXRT_FLEXCAN2_MASK.offset088)

  3212. #define FLEXCAN2_RXIMR3			(IMXRT_FLEXCAN2_MASK.offset08C)

  3213. #define FLEXCAN2_RXIMR4			(IMXRT_FLEXCAN2_MASK.offset090)

  3214. #define FLEXCAN2_RXIMR5			(IMXRT_FLEXCAN2_MASK.offset094)

  3215. #define FLEXCAN2_RXIMR6			(IMXRT_FLEXCAN2_MASK.offset098)

  3216. #define FLEXCAN2_RXIMR7			(IMXRT_FLEXCAN2_MASK.offset09C)

  3217. #define FLEXCAN2_RXIMR8			(IMXRT_FLEXCAN2_MASK.offset0A0)

  3218. #define FLEXCAN2_RXIMR9			(IMXRT_FLEXCAN2_MASK.offset0A4)

  3219. #define FLEXCAN2_RXIMR10		(IMXRT_FLEXCAN2_MASK.offset0A8)

  3220. #define FLEXCAN2_RXIMR11		(IMXRT_FLEXCAN2_MASK.offset0AC)

  3221. #define FLEXCAN2_RXIMR12		(IMXRT_FLEXCAN2_MASK.offset0B0)

  3222. #define FLEXCAN2_RXIMR13		(IMXRT_FLEXCAN2_MASK.offset0B4)

  3223. #define FLEXCAN2_RXIMR14		(IMXRT_FLEXCAN2_MASK.offset0B8)

  3224. #define FLEXCAN2_RXIMR15		(IMXRT_FLEXCAN2_MASK.offset0BC)

  3225. #define FLEXCAN2_RXIMR16		(IMXRT_FLEXCAN2_MASK.offset0C0)

  3226. #define FLEXCAN2_RXIMR17		(IMXRT_FLEXCAN2_MASK.offset0C4)

  3227. #define FLEXCAN2_RXIMR18		(IMXRT_FLEXCAN2_MASK.offset0C8)

  3228. #define FLEXCAN2_RXIMR19		(IMXRT_FLEXCAN2_MASK.offset0CC)

  3229. #define FLEXCAN2_RXIMR20		(IMXRT_FLEXCAN2_MASK.offset0D0)

  3230. #define FLEXCAN2_RXIMR21		(IMXRT_FLEXCAN2_MASK.offset0D4)

  3231. #define FLEXCAN2_RXIMR22		(IMXRT_FLEXCAN2_MASK.offset0D8)

  3232. #define FLEXCAN2_RXIMR23		(IMXRT_FLEXCAN2_MASK.offset0DC)

  3233. #define FLEXCAN2_RXIMR24		(IMXRT_FLEXCAN2_MASK.offset0E0)

  3234. #define FLEXCAN2_RXIMR25		(IMXRT_FLEXCAN2_MASK.offset0E4)

  3235. #define FLEXCAN2_RXIMR26		(IMXRT_FLEXCAN2_MASK.offset0E8)

  3236. #define FLEXCAN2_RXIMR27		(IMXRT_FLEXCAN2_MASK.offset0EC)

  3237. #define FLEXCAN2_RXIMR28		(IMXRT_FLEXCAN2_MASK.offset0F0)

  3238. #define FLEXCAN2_RXIMR29		(IMXRT_FLEXCAN2_MASK.offset0F4)

  3239. #define FLEXCAN2_RXIMR30		(IMXRT_FLEXCAN2_MASK.offset0F8)

  3240. #define FLEXCAN2_RXIMR31		(IMXRT_FLEXCAN2_MASK.offset0FC)

  3241. #define FLEXCAN2_RXIMR32		(IMXRT_FLEXCAN2_MASK.offset100)

  3242. #define FLEXCAN2_RXIMR33		(IMXRT_FLEXCAN2_MASK.offset104)

  3243. #define FLEXCAN2_RXIMR34		(IMXRT_FLEXCAN2_MASK.offset108)

  3244. #define FLEXCAN2_RXIMR35		(IMXRT_FLEXCAN2_MASK.offset10C)

  3245. #define FLEXCAN2_RXIMR36		(IMXRT_FLEXCAN2_MASK.offset110)

  3246. #define FLEXCAN2_RXIMR37		(IMXRT_FLEXCAN2_MASK.offset114)

  3247. #define FLEXCAN2_RXIMR38		(IMXRT_FLEXCAN2_MASK.offset118)

  3248. #define FLEXCAN2_RXIMR39		(IMXRT_FLEXCAN2_MASK.offset11C)

  3249. #define FLEXCAN2_RXIMR40		(IMXRT_FLEXCAN2_MASK.offset120)

  3250. #define FLEXCAN2_RXIMR41		(IMXRT_FLEXCAN2_MASK.offset124)

  3251. #define FLEXCAN2_RXIMR42		(IMXRT_FLEXCAN2_MASK.offset128)

  3252. #define FLEXCAN2_RXIMR43		(IMXRT_FLEXCAN2_MASK.offset12C)

  3253. #define FLEXCAN2_RXIMR44		(IMXRT_FLEXCAN2_MASK.offset130)

  3254. #define FLEXCAN2_RXIMR45		(IMXRT_FLEXCAN2_MASK.offset134)

  3255. #define FLEXCAN2_RXIMR46		(IMXRT_FLEXCAN2_MASK.offset138)

  3256. #define FLEXCAN2_RXIMR47		(IMXRT_FLEXCAN2_MASK.offset13C)

  3257. #define FLEXCAN2_RXIMR48		(IMXRT_FLEXCAN2_MASK.offset140)

  3258. #define FLEXCAN2_RXIMR49		(IMXRT_FLEXCAN2_MASK.offset144)

  3259. #define FLEXCAN2_RXIMR50		(IMXRT_FLEXCAN2_MASK.offset148)

  3260. #define FLEXCAN2_RXIMR51		(IMXRT_FLEXCAN2_MASK.offset14C)

  3261. #define FLEXCAN2_RXIMR52		(IMXRT_FLEXCAN2_MASK.offset150)

  3262. #define FLEXCAN2_RXIMR53		(IMXRT_FLEXCAN2_MASK.offset154)

  3263. #define FLEXCAN2_RXIMR54		(IMXRT_FLEXCAN2_MASK.offset158)

  3264. #define FLEXCAN2_RXIMR55		(IMXRT_FLEXCAN2_MASK.offset15C)

  3265. #define FLEXCAN2_RXIMR56		(IMXRT_FLEXCAN2_MASK.offset160)

  3266. #define FLEXCAN2_RXIMR57		(IMXRT_FLEXCAN2_MASK.offset164)

  3267. #define FLEXCAN2_RXIMR58		(IMXRT_FLEXCAN2_MASK.offset168)

  3268. #define FLEXCAN2_RXIMR59		(IMXRT_FLEXCAN2_MASK.offset16C)

  3269. #define FLEXCAN2_RXIMR60		(IMXRT_FLEXCAN2_MASK.offset170)

  3270. #define FLEXCAN2_RXIMR61		(IMXRT_FLEXCAN2_MASK.offset174)

  3271. #define FLEXCAN2_RXIMR62		(IMXRT_FLEXCAN2_MASK.offset178)

  3272. #define FLEXCAN2_RXIMR63		(IMXRT_FLEXCAN2_MASK.offset17C)

  3273. #define FLEXCAN2_GFWR			(IMXRT_FLEXCAN2_MASK.offset1E0)

  3274. 

  3275. #define IMXRT_FLEXCAN3		(*(IMXRT_REGISTER32_t *)0x401D8000)

  3276. #define IMXRT_FLEXCAN3_MASK	(*(IMXRT_REGISTER32_t *)0x401D8800)

  3277. #define IMXRT_FLEXCAN3_EXT	(*(IMXRT_REGISTER32_t *)0x401D8B00)

  3278. #define IMXRT_FLEXCAN3_ERXFIFO	(*(IMXRT_REGISTER32_t *)0x401DB000)

  3279. #define FLEXCAN3_MCR			(IMXRT_FLEXCAN3.offset000)

  3280. #define FLEXCAN3_CTRL1			(IMXRT_FLEXCAN3.offset004)

  3281. #define FLEXCAN3_TIMER			(IMXRT_FLEXCAN3.offset008)

  3282. #define FLEXCAN3_RXMGMASK		(IMXRT_FLEXCAN3.offset010)

  3283. #define FLEXCAN3_RX14MASK		(IMXRT_FLEXCAN3.offset014)

  3284. #define FLEXCAN3_RX15MASK		(IMXRT_FLEXCAN3.offset018)

  3285. #define FLEXCAN3_ECR			(IMXRT_FLEXCAN3.offset01C)

  3286. #define FLEXCAN3_ESR1			(IMXRT_FLEXCAN3.offset020)

  3287. #define FLEXCAN3_IMASK2			(IMXRT_FLEXCAN3.offset024)

  3288. #define FLEXCAN3_IMASK1			(IMXRT_FLEXCAN3.offset028)

  3289. #define FLEXCAN3_IFLAG2			(IMXRT_FLEXCAN3.offset02C)

  3290. #define FLEXCAN3_IFLAG1			(IMXRT_FLEXCAN3.offset030)

  3291. #define FLEXCAN3_CTRL2			(IMXRT_FLEXCAN3.offset034)

  3292. #define FLEXCAN3_ESR2			(IMXRT_FLEXCAN3.offset038)

  3293. #define FLEXCAN3_CRCR			(IMXRT_FLEXCAN3.offset044)

  3294. #define FLEXCAN3_RXFGMASK		(IMXRT_FLEXCAN3.offset048)

  3295. #define FLEXCAN3_RXFIR			(IMXRT_FLEXCAN3.offset04C)

  3296. #define FLEXCAN3_CBT			(IMXRT_FLEXCAN3.offset050)

  3297. #define FLEXCAN3_RXIMR0			(IMXRT_FLEXCAN3_MASK.offset080)

  3298. #define FLEXCAN3_RXIMR1			(IMXRT_FLEXCAN3_MASK.offset084)

  3299. #define FLEXCAN3_RXIMR2			(IMXRT_FLEXCAN3_MASK.offset088)

  3300. #define FLEXCAN3_RXIMR3			(IMXRT_FLEXCAN3_MASK.offset08C)

  3301. #define FLEXCAN3_RXIMR4			(IMXRT_FLEXCAN3_MASK.offset090)

  3302. #define FLEXCAN3_RXIMR5			(IMXRT_FLEXCAN3_MASK.offset094)

  3303. #define FLEXCAN3_RXIMR6			(IMXRT_FLEXCAN3_MASK.offset098)

  3304. #define FLEXCAN3_RXIMR7			(IMXRT_FLEXCAN3_MASK.offset09C)

  3305. #define FLEXCAN3_RXIMR8			(IMXRT_FLEXCAN3_MASK.offset0A0)

  3306. #define FLEXCAN3_RXIMR9			(IMXRT_FLEXCAN3_MASK.offset0A4)

  3307. #define FLEXCAN3_RXIMR10		(IMXRT_FLEXCAN3_MASK.offset0A8)

  3308. #define FLEXCAN3_RXIMR11		(IMXRT_FLEXCAN3_MASK.offset0AC)

  3309. #define FLEXCAN3_RXIMR12		(IMXRT_FLEXCAN3_MASK.offset0B0)

  3310. #define FLEXCAN3_RXIMR13		(IMXRT_FLEXCAN3_MASK.offset0B4)

  3311. #define FLEXCAN3_RXIMR14		(IMXRT_FLEXCAN3_MASK.offset0B8)

  3312. #define FLEXCAN3_RXIMR15		(IMXRT_FLEXCAN3_MASK.offset0BC)

  3313. #define FLEXCAN3_RXIMR16		(IMXRT_FLEXCAN3_MASK.offset0C0)

  3314. #define FLEXCAN3_RXIMR17		(IMXRT_FLEXCAN3_MASK.offset0C4)

  3315. #define FLEXCAN3_RXIMR18		(IMXRT_FLEXCAN3_MASK.offset0C8)

  3316. #define FLEXCAN3_RXIMR19		(IMXRT_FLEXCAN3_MASK.offset0CC)

  3317. #define FLEXCAN3_RXIMR20		(IMXRT_FLEXCAN3_MASK.offset0D0)

  3318. #define FLEXCAN3_RXIMR21		(IMXRT_FLEXCAN3_MASK.offset0D4)

  3319. #define FLEXCAN3_RXIMR22		(IMXRT_FLEXCAN3_MASK.offset0D8)

  3320. #define FLEXCAN3_RXIMR23		(IMXRT_FLEXCAN3_MASK.offset0DC)

  3321. #define FLEXCAN3_RXIMR24		(IMXRT_FLEXCAN3_MASK.offset0E0)

  3322. #define FLEXCAN3_RXIMR25		(IMXRT_FLEXCAN3_MASK.offset0E4)

  3323. #define FLEXCAN3_RXIMR26		(IMXRT_FLEXCAN3_MASK.offset0E8)

  3324. #define FLEXCAN3_RXIMR27		(IMXRT_FLEXCAN3_MASK.offset0EC)

  3325. #define FLEXCAN3_RXIMR28		(IMXRT_FLEXCAN3_MASK.offset0F0)

  3326. #define FLEXCAN3_RXIMR29		(IMXRT_FLEXCAN3_MASK.offset0F4)

  3327. #define FLEXCAN3_RXIMR30		(IMXRT_FLEXCAN3_MASK.offset0F8)

  3328. #define FLEXCAN3_RXIMR31		(IMXRT_FLEXCAN3_MASK.offset0FC)

  3329. #define FLEXCAN3_RXIMR32		(IMXRT_FLEXCAN3_MASK.offset100)

  3330. #define FLEXCAN3_RXIMR33		(IMXRT_FLEXCAN3_MASK.offset104)

  3331. #define FLEXCAN3_RXIMR34		(IMXRT_FLEXCAN3_MASK.offset108)

  3332. #define FLEXCAN3_RXIMR35		(IMXRT_FLEXCAN3_MASK.offset10C)

  3333. #define FLEXCAN3_RXIMR36		(IMXRT_FLEXCAN3_MASK.offset110)

  3334. #define FLEXCAN3_RXIMR37		(IMXRT_FLEXCAN3_MASK.offset114)

  3335. #define FLEXCAN3_RXIMR38		(IMXRT_FLEXCAN3_MASK.offset118)

  3336. #define FLEXCAN3_RXIMR39		(IMXRT_FLEXCAN3_MASK.offset11C)

  3337. #define FLEXCAN3_RXIMR40		(IMXRT_FLEXCAN3_MASK.offset120)

  3338. #define FLEXCAN3_RXIMR41		(IMXRT_FLEXCAN3_MASK.offset124)

  3339. #define FLEXCAN3_RXIMR42		(IMXRT_FLEXCAN3_MASK.offset128)

  3340. #define FLEXCAN3_RXIMR43		(IMXRT_FLEXCAN3_MASK.offset12C)

  3341. #define FLEXCAN3_RXIMR44		(IMXRT_FLEXCAN3_MASK.offset130)

  3342. #define FLEXCAN3_RXIMR45		(IMXRT_FLEXCAN3_MASK.offset134)

  3343. #define FLEXCAN3_RXIMR46		(IMXRT_FLEXCAN3_MASK.offset138)

  3344. #define FLEXCAN3_RXIMR47		(IMXRT_FLEXCAN3_MASK.offset13C)

  3345. #define FLEXCAN3_RXIMR48		(IMXRT_FLEXCAN3_MASK.offset140)

  3346. #define FLEXCAN3_RXIMR49		(IMXRT_FLEXCAN3_MASK.offset144)

  3347. #define FLEXCAN3_RXIMR50		(IMXRT_FLEXCAN3_MASK.offset148)

  3348. #define FLEXCAN3_RXIMR51		(IMXRT_FLEXCAN3_MASK.offset14C)

  3349. #define FLEXCAN3_RXIMR52		(IMXRT_FLEXCAN3_MASK.offset150)

  3350. #define FLEXCAN3_RXIMR53		(IMXRT_FLEXCAN3_MASK.offset154)

  3351. #define FLEXCAN3_RXIMR54		(IMXRT_FLEXCAN3_MASK.offset158)

  3352. #define FLEXCAN3_RXIMR55		(IMXRT_FLEXCAN3_MASK.offset15C)

  3353. #define FLEXCAN3_RXIMR56		(IMXRT_FLEXCAN3_MASK.offset160)

  3354. #define FLEXCAN3_RXIMR57		(IMXRT_FLEXCAN3_MASK.offset164)

  3355. #define FLEXCAN3_RXIMR58		(IMXRT_FLEXCAN3_MASK.offset168)

  3356. #define FLEXCAN3_RXIMR59		(IMXRT_FLEXCAN3_MASK.offset16C)

  3357. #define FLEXCAN3_RXIMR60		(IMXRT_FLEXCAN3_MASK.offset170)

  3358. #define FLEXCAN3_RXIMR61		(IMXRT_FLEXCAN3_MASK.offset174)

  3359. #define FLEXCAN3_RXIMR62		(IMXRT_FLEXCAN3_MASK.offset178)

  3360. #define FLEXCAN3_RXIMR63		(IMXRT_FLEXCAN3_MASK.offset17C)

  3361. #define FLEXCAN3_EPRS			(IMXRT_FLEXCAN3_EXT.offset0F0)

  3362. #define FLEXCAN3_ENCBT			(IMXRT_FLEXCAN3_EXT.offset0F4)

  3363. #define FLEXCAN3_EDCBT			(IMXRT_FLEXCAN3_EXT.offset0F8)

  3364. #define FLEXCAN3_ETDC			(IMXRT_FLEXCAN3_EXT.offset0FC)

  3365. #define FLEXCAN3_FDCTRL			(IMXRT_FLEXCAN3_EXT.offset100)

  3366. #define FLEXCAN3_FDCBT			(IMXRT_FLEXCAN3_EXT.offset104)

  3367. #define FLEXCAN3_FDCRC			(IMXRT_FLEXCAN3_EXT.offset108)

  3368. #define FLEXCAN3_ERFCR			(IMXRT_FLEXCAN3_EXT.offset10C)

  3369. #define FLEXCAN3_ERFIER			(IMXRT_FLEXCAN3_EXT.offset110)

  3370. #define FLEXCAN3_ERFSR			(IMXRT_FLEXCAN3_EXT.offset114)

  3371. #define FLEXCAN3_HR_TIME_STAMP0		(IMXRT_FLEXCAN3_EXT.offset130)

  3372. #define FLEXCAN3_HR_TIME_STAMP1		(IMXRT_FLEXCAN3_EXT.offset134)

  3373. #define FLEXCAN3_HR_TIME_STAMP2		(IMXRT_FLEXCAN3_EXT.offset138)

  3374. #define FLEXCAN3_HR_TIME_STAMP3		(IMXRT_FLEXCAN3_EXT.offset13C)

  3375. #define FLEXCAN3_HR_TIME_STAMP4		(IMXRT_FLEXCAN3_EXT.offset140)

  3376. #define FLEXCAN3_HR_TIME_STAMP5		(IMXRT_FLEXCAN3_EXT.offset144)

  3377. #define FLEXCAN3_HR_TIME_STAMP6		(IMXRT_FLEXCAN3_EXT.offset148)

  3378. #define FLEXCAN3_HR_TIME_STAMP7		(IMXRT_FLEXCAN3_EXT.offset14C)

  3379. #define FLEXCAN3_HR_TIME_STAMP8		(IMXRT_FLEXCAN3_EXT.offset150)

  3380. #define FLEXCAN3_HR_TIME_STAMP9		(IMXRT_FLEXCAN3_EXT.offset154)

  3381. #define FLEXCAN3_HR_TIME_STAMP10	(IMXRT_FLEXCAN3_EXT.offset158)

  3382. #define FLEXCAN3_HR_TIME_STAMP11	(IMXRT_FLEXCAN3_EXT.offset15C)

  3383. #define FLEXCAN3_HR_TIME_STAMP12	(IMXRT_FLEXCAN3_EXT.offset160)

  3384. #define FLEXCAN3_HR_TIME_STAMP13	(IMXRT_FLEXCAN3_EXT.offset164)

  3385. #define FLEXCAN3_HR_TIME_STAMP14	(IMXRT_FLEXCAN3_EXT.offset168)

  3386. #define FLEXCAN3_HR_TIME_STAMP15	(IMXRT_FLEXCAN3_EXT.offset16C)

  3387. #define FLEXCAN3_HR_TIME_STAMP16	(IMXRT_FLEXCAN3_EXT.offset170)

  3388. #define FLEXCAN3_HR_TIME_STAMP17	(IMXRT_FLEXCAN3_EXT.offset174)

  3389. #define FLEXCAN3_HR_TIME_STAMP18	(IMXRT_FLEXCAN3_EXT.offset178)

  3390. #define FLEXCAN3_HR_TIME_STAMP19	(IMXRT_FLEXCAN3_EXT.offset17C)

  3391. #define FLEXCAN3_HR_TIME_STAMP20	(IMXRT_FLEXCAN3_EXT.offset180)

  3392. #define FLEXCAN3_HR_TIME_STAMP21	(IMXRT_FLEXCAN3_EXT.offset184)

  3393. #define FLEXCAN3_HR_TIME_STAMP22	(IMXRT_FLEXCAN3_EXT.offset188)

  3394. #define FLEXCAN3_HR_TIME_STAMP23	(IMXRT_FLEXCAN3_EXT.offset18C)

  3395. #define FLEXCAN3_HR_TIME_STAMP24	(IMXRT_FLEXCAN3_EXT.offset190)

  3396. #define FLEXCAN3_HR_TIME_STAMP25	(IMXRT_FLEXCAN3_EXT.offset194)

  3397. #define FLEXCAN3_HR_TIME_STAMP26	(IMXRT_FLEXCAN3_EXT.offset198)

  3398. #define FLEXCAN3_HR_TIME_STAMP27	(IMXRT_FLEXCAN3_EXT.offset19C)

  3399. #define FLEXCAN3_HR_TIME_STAMP28	(IMXRT_FLEXCAN3_EXT.offset1A0)

  3400. #define FLEXCAN3_HR_TIME_STAMP29	(IMXRT_FLEXCAN3_EXT.offset1A4)

  3401. #define FLEXCAN3_HR_TIME_STAMP30	(IMXRT_FLEXCAN3_EXT.offset1A8)

  3402. #define FLEXCAN3_HR_TIME_STAMP31	(IMXRT_FLEXCAN3_EXT.offset1AC)

  3403. #define FLEXCAN3_HR_TIME_STAMP32	(IMXRT_FLEXCAN3_EXT.offset1B0)

  3404. #define FLEXCAN3_HR_TIME_STAMP33	(IMXRT_FLEXCAN3_EXT.offset1B4)

  3405. #define FLEXCAN3_HR_TIME_STAMP34	(IMXRT_FLEXCAN3_EXT.offset1B8)

  3406. #define FLEXCAN3_HR_TIME_STAMP35	(IMXRT_FLEXCAN3_EXT.offset1BC)

  3407. #define FLEXCAN3_HR_TIME_STAMP36	(IMXRT_FLEXCAN3_EXT.offset1C0)

  3408. #define FLEXCAN3_HR_TIME_STAMP37	(IMXRT_FLEXCAN3_EXT.offset1C4)

  3409. #define FLEXCAN3_HR_TIME_STAMP38	(IMXRT_FLEXCAN3_EXT.offset1C8)

  3410. #define FLEXCAN3_HR_TIME_STAMP39	(IMXRT_FLEXCAN3_EXT.offset1CC)

  3411. #define FLEXCAN3_HR_TIME_STAMP40	(IMXRT_FLEXCAN3_EXT.offset1D0)

  3412. #define FLEXCAN3_HR_TIME_STAMP41	(IMXRT_FLEXCAN3_EXT.offset1D4)

  3413. #define FLEXCAN3_HR_TIME_STAMP42	(IMXRT_FLEXCAN3_EXT.offset1D8)

  3414. #define FLEXCAN3_HR_TIME_STAMP43	(IMXRT_FLEXCAN3_EXT.offset1DC)

  3415. #define FLEXCAN3_HR_TIME_STAMP44	(IMXRT_FLEXCAN3_EXT.offset1E0)

  3416. #define FLEXCAN3_HR_TIME_STAMP45	(IMXRT_FLEXCAN3_EXT.offset1E4)

  3417. #define FLEXCAN3_HR_TIME_STAMP46	(IMXRT_FLEXCAN3_EXT.offset1E8)

  3418. #define FLEXCAN3_HR_TIME_STAMP47	(IMXRT_FLEXCAN3_EXT.offset1EC)

  3419. #define FLEXCAN3_HR_TIME_STAMP48	(IMXRT_FLEXCAN3_EXT.offset1F0)

  3420. #define FLEXCAN3_HR_TIME_STAMP49	(IMXRT_FLEXCAN3_EXT.offset1F4)

  3421. #define FLEXCAN3_HR_TIME_STAMP50	(IMXRT_FLEXCAN3_EXT.offset1F8)

  3422. #define FLEXCAN3_HR_TIME_STAMP51	(IMXRT_FLEXCAN3_EXT.offset1FC)

  3423. #define FLEXCAN3_HR_TIME_STAMP52	(IMXRT_FLEXCAN3_EXT.offset200)

  3424. #define FLEXCAN3_HR_TIME_STAMP53	(IMXRT_FLEXCAN3_EXT.offset204)

  3425. #define FLEXCAN3_HR_TIME_STAMP54	(IMXRT_FLEXCAN3_EXT.offset208)

  3426. #define FLEXCAN3_HR_TIME_STAMP55	(IMXRT_FLEXCAN3_EXT.offset20C)

  3427. #define FLEXCAN3_HR_TIME_STAMP56	(IMXRT_FLEXCAN3_EXT.offset210)

  3428. #define FLEXCAN3_HR_TIME_STAMP57	(IMXRT_FLEXCAN3_EXT.offset234)

  3429. #define FLEXCAN3_HR_TIME_STAMP58	(IMXRT_FLEXCAN3_EXT.offset218)

  3430. #define FLEXCAN3_HR_TIME_STAMP59	(IMXRT_FLEXCAN3_EXT.offset21C)

  3431. #define FLEXCAN3_HR_TIME_STAMP60	(IMXRT_FLEXCAN3_EXT.offset220)

  3432. #define FLEXCAN3_HR_TIME_STAMP61	(IMXRT_FLEXCAN3_EXT.offset224)

  3433. #define FLEXCAN3_HR_TIME_STAMP62	(IMXRT_FLEXCAN3_EXT.offset228)

  3434. #define FLEXCAN3_HR_TIME_STAMP63	(IMXRT_FLEXCAN3_EXT.offset22C)

  3435. #define FLEXCAN3_ERFFEL0		(IMXRT_FLEXCAN3_ERXFIFO.offset000)

  3436. #define FLEXCAN3_ERFFEL1		(IMXRT_FLEXCAN3_ERXFIFO.offset004)

  3437. #define FLEXCAN3_ERFFEL2		(IMXRT_FLEXCAN3_ERXFIFO.offset008)

  3438. #define FLEXCAN3_ERFFEL3		(IMXRT_FLEXCAN3_ERXFIFO.offset00C)

  3439. #define FLEXCAN3_ERFFEL4		(IMXRT_FLEXCAN3_ERXFIFO.offset010)

  3440. #define FLEXCAN3_ERFFEL5		(IMXRT_FLEXCAN3_ERXFIFO.offset014)

  3441. #define FLEXCAN3_ERFFEL6		(IMXRT_FLEXCAN3_ERXFIFO.offset018)

  3442. #define FLEXCAN3_ERFFEL7		(IMXRT_FLEXCAN3_ERXFIFO.offset01C)

  3443. #define FLEXCAN3_ERFFEL8		(IMXRT_FLEXCAN3_ERXFIFO.offset020)

  3444. #define FLEXCAN3_ERFFEL9		(IMXRT_FLEXCAN3_ERXFIFO.offset024)

  3445. #define FLEXCAN3_ERFFEL10		(IMXRT_FLEXCAN3_ERXFIFO.offset028)

  3446. #define FLEXCAN3_ERFFEL11		(IMXRT_FLEXCAN3_ERXFIFO.offset02C)

  3447. #define FLEXCAN3_ERFFEL12		(IMXRT_FLEXCAN3_ERXFIFO.offset030)

  3448. #define FLEXCAN3_ERFFEL13		(IMXRT_FLEXCAN3_ERXFIFO.offset034)

  3449. #define FLEXCAN3_ERFFEL14		(IMXRT_FLEXCAN3_ERXFIFO.offset038)

  3450. #define FLEXCAN3_ERFFEL15		(IMXRT_FLEXCAN3_ERXFIFO.offset03C)

  3451. #define FLEXCAN3_ERFFEL16		(IMXRT_FLEXCAN3_ERXFIFO.offset040)

  3452. #define FLEXCAN3_ERFFEL17		(IMXRT_FLEXCAN3_ERXFIFO.offset044)

  3453. #define FLEXCAN3_ERFFEL18		(IMXRT_FLEXCAN3_ERXFIFO.offset048)

  3454. #define FLEXCAN3_ERFFEL19		(IMXRT_FLEXCAN3_ERXFIFO.offset04C)

  3455. #define FLEXCAN3_ERFFEL20		(IMXRT_FLEXCAN3_ERXFIFO.offset050)

  3456. #define FLEXCAN3_ERFFEL21		(IMXRT_FLEXCAN3_ERXFIFO.offset054)

  3457. #define FLEXCAN3_ERFFEL22		(IMXRT_FLEXCAN3_ERXFIFO.offset058)

  3458. #define FLEXCAN3_ERFFEL23		(IMXRT_FLEXCAN3_ERXFIFO.offset05C)

  3459. #define FLEXCAN3_ERFFEL24		(IMXRT_FLEXCAN3_ERXFIFO.offset060)

  3460. #define FLEXCAN3_ERFFEL25		(IMXRT_FLEXCAN3_ERXFIFO.offset064)

  3461. #define FLEXCAN3_ERFFEL26		(IMXRT_FLEXCAN3_ERXFIFO.offset068)

  3462. #define FLEXCAN3_ERFFEL27		(IMXRT_FLEXCAN3_ERXFIFO.offset06C)

  3463. #define FLEXCAN3_ERFFEL28		(IMXRT_FLEXCAN3_ERXFIFO.offset070)

  3464. #define FLEXCAN3_ERFFEL29		(IMXRT_FLEXCAN3_ERXFIFO.offset074)

  3465. #define FLEXCAN3_ERFFEL30		(IMXRT_FLEXCAN3_ERXFIFO.offset078)

  3466. #define FLEXCAN3_ERFFEL31		(IMXRT_FLEXCAN3_ERXFIFO.offset07C)

  3467. #define FLEXCAN3_ERFFEL32		(IMXRT_FLEXCAN3_ERXFIFO.offset080)

  3468. #define FLEXCAN3_ERFFEL33		(IMXRT_FLEXCAN3_ERXFIFO.offset084)

  3469. #define FLEXCAN3_ERFFEL34		(IMXRT_FLEXCAN3_ERXFIFO.offset088)

  3470. #define FLEXCAN3_ERFFEL35		(IMXRT_FLEXCAN3_ERXFIFO.offset08C)

  3471. #define FLEXCAN3_ERFFEL36		(IMXRT_FLEXCAN3_ERXFIFO.offset090)

  3472. #define FLEXCAN3_ERFFEL37		(IMXRT_FLEXCAN3_ERXFIFO.offset094)

  3473. #define FLEXCAN3_ERFFEL38		(IMXRT_FLEXCAN3_ERXFIFO.offset098)

  3474. #define FLEXCAN3_ERFFEL39		(IMXRT_FLEXCAN3_ERXFIFO.offset09C)

  3475. #define FLEXCAN3_ERFFEL40		(IMXRT_FLEXCAN3_ERXFIFO.offset0A0)

  3476. #define FLEXCAN3_ERFFEL41		(IMXRT_FLEXCAN3_ERXFIFO.offset0A4)

  3477. #define FLEXCAN3_ERFFEL42		(IMXRT_FLEXCAN3_ERXFIFO.offset0A8)

  3478. #define FLEXCAN3_ERFFEL43		(IMXRT_FLEXCAN3_ERXFIFO.offset0AC)

  3479. #define FLEXCAN3_ERFFEL44		(IMXRT_FLEXCAN3_ERXFIFO.offset0B0)

  3480. #define FLEXCAN3_ERFFEL45		(IMXRT_FLEXCAN3_ERXFIFO.offset0B4)

  3481. #define FLEXCAN3_ERFFEL46		(IMXRT_FLEXCAN3_ERXFIFO.offset0B8)

  3482. #define FLEXCAN3_ERFFEL47		(IMXRT_FLEXCAN3_ERXFIFO.offset0BC)

  3483. #define FLEXCAN3_ERFFEL48		(IMXRT_FLEXCAN3_ERXFIFO.offset0C0)

  3484. #define FLEXCAN3_ERFFEL49		(IMXRT_FLEXCAN3_ERXFIFO.offset0C4)

  3485. #define FLEXCAN3_ERFFEL50		(IMXRT_FLEXCAN3_ERXFIFO.offset0C8)

  3486. #define FLEXCAN3_ERFFEL51		(IMXRT_FLEXCAN3_ERXFIFO.offset0CC)

  3487. #define FLEXCAN3_ERFFEL52		(IMXRT_FLEXCAN3_ERXFIFO.offset0D0)

  3488. #define FLEXCAN3_ERFFEL53		(IMXRT_FLEXCAN3_ERXFIFO.offset0D4)

  3489. #define FLEXCAN3_ERFFEL54		(IMXRT_FLEXCAN3_ERXFIFO.offset0D8)

  3490. #define FLEXCAN3_ERFFEL55		(IMXRT_FLEXCAN3_ERXFIFO.offset0DC)

  3491. #define FLEXCAN3_ERFFEL56		(IMXRT_FLEXCAN3_ERXFIFO.offset0E0)

  3492. #define FLEXCAN3_ERFFEL57		(IMXRT_FLEXCAN3_ERXFIFO.offset0E4)

  3493. #define FLEXCAN3_ERFFEL58		(IMXRT_FLEXCAN3_ERXFIFO.offset0E8)

  3494. #define FLEXCAN3_ERFFEL59		(IMXRT_FLEXCAN3_ERXFIFO.offset0EC)

  3495. #define FLEXCAN3_ERFFEL60		(IMXRT_FLEXCAN3_ERXFIFO.offset0F0)

  3496. #define FLEXCAN3_ERFFEL61		(IMXRT_FLEXCAN3_ERXFIFO.offset0F4)

  3497. #define FLEXCAN3_ERFFEL62		(IMXRT_FLEXCAN3_ERXFIFO.offset0F8)

  3498. #define FLEXCAN3_ERFFEL63		(IMXRT_FLEXCAN3_ERXFIFO.offset0FC)

  3499. #define FLEXCAN3_ERFFEL64		(IMXRT_FLEXCAN3_ERXFIFO.offset100)

  3500. #define FLEXCAN3_ERFFEL65		(IMXRT_FLEXCAN3_ERXFIFO.offset104)

  3501. #define FLEXCAN3_ERFFEL66		(IMXRT_FLEXCAN3_ERXFIFO.offset108)

  3502. #define FLEXCAN3_ERFFEL67		(IMXRT_FLEXCAN3_ERXFIFO.offset10C)

  3503. #define FLEXCAN3_ERFFEL68		(IMXRT_FLEXCAN3_ERXFIFO.offset110)

  3504. #define FLEXCAN3_ERFFEL69		(IMXRT_FLEXCAN3_ERXFIFO.offset114)

  3505. #define FLEXCAN3_ERFFEL70		(IMXRT_FLEXCAN3_ERXFIFO.offset118)

  3506. #define FLEXCAN3_ERFFEL71		(IMXRT_FLEXCAN3_ERXFIFO.offset11C)

  3507. #define FLEXCAN3_ERFFEL72		(IMXRT_FLEXCAN3_ERXFIFO.offset120)

  3508. #define FLEXCAN3_ERFFEL73		(IMXRT_FLEXCAN3_ERXFIFO.offset124)

  3509. #define FLEXCAN3_ERFFEL74		(IMXRT_FLEXCAN3_ERXFIFO.offset128)

  3510. #define FLEXCAN3_ERFFEL75		(IMXRT_FLEXCAN3_ERXFIFO.offset12C)

  3511. #define FLEXCAN3_ERFFEL76		(IMXRT_FLEXCAN3_ERXFIFO.offset130)

  3512. #define FLEXCAN3_ERFFEL77		(IMXRT_FLEXCAN3_ERXFIFO.offset134)

  3513. #define FLEXCAN3_ERFFEL78		(IMXRT_FLEXCAN3_ERXFIFO.offset138)

  3514. #define FLEXCAN3_ERFFEL79		(IMXRT_FLEXCAN3_ERXFIFO.offset13C)

  3515. #define FLEXCAN3_ERFFEL80		(IMXRT_FLEXCAN3_ERXFIFO.offset140)

  3516. #define FLEXCAN3_ERFFEL81		(IMXRT_FLEXCAN3_ERXFIFO.offset144)

  3517. #define FLEXCAN3_ERFFEL82		(IMXRT_FLEXCAN3_ERXFIFO.offset148)

  3518. #define FLEXCAN3_ERFFEL83		(IMXRT_FLEXCAN3_ERXFIFO.offset14C)

  3519. #define FLEXCAN3_ERFFEL84		(IMXRT_FLEXCAN3_ERXFIFO.offset150)

  3520. #define FLEXCAN3_ERFFEL85		(IMXRT_FLEXCAN3_ERXFIFO.offset154)

  3521. #define FLEXCAN3_ERFFEL86		(IMXRT_FLEXCAN3_ERXFIFO.offset158)

  3522. #define FLEXCAN3_ERFFEL87		(IMXRT_FLEXCAN3_ERXFIFO.offset15C)

  3523. #define FLEXCAN3_ERFFEL88		(IMXRT_FLEXCAN3_ERXFIFO.offset160)

  3524. #define FLEXCAN3_ERFFEL89		(IMXRT_FLEXCAN3_ERXFIFO.offset164)

  3525. #define FLEXCAN3_ERFFEL90		(IMXRT_FLEXCAN3_ERXFIFO.offset168)

  3526. #define FLEXCAN3_ERFFEL91		(IMXRT_FLEXCAN3_ERXFIFO.offset16C)

  3527. #define FLEXCAN3_ERFFEL92		(IMXRT_FLEXCAN3_ERXFIFO.offset170)

  3528. #define FLEXCAN3_ERFFEL93		(IMXRT_FLEXCAN3_ERXFIFO.offset174)

  3529. #define FLEXCAN3_ERFFEL94		(IMXRT_FLEXCAN3_ERXFIFO.offset178)

  3530. #define FLEXCAN3_ERFFEL95		(IMXRT_FLEXCAN3_ERXFIFO.offset17C)

  3531. #define FLEXCAN3_ERFFEL96		(IMXRT_FLEXCAN3_ERXFIFO.offset180)

  3532. #define FLEXCAN3_ERFFEL97		(IMXRT_FLEXCAN3_ERXFIFO.offset184)

  3533. #define FLEXCAN3_ERFFEL98		(IMXRT_FLEXCAN3_ERXFIFO.offset188)

  3534. #define FLEXCAN3_ERFFEL99		(IMXRT_FLEXCAN3_ERXFIFO.offset18C)

  3535. #define FLEXCAN3_ERFFEL100		(IMXRT_FLEXCAN3_ERXFIFO.offset190)

  3536. #define FLEXCAN3_ERFFEL101		(IMXRT_FLEXCAN3_ERXFIFO.offset194)

  3537. #define FLEXCAN3_ERFFEL102		(IMXRT_FLEXCAN3_ERXFIFO.offset198)

  3538. #define FLEXCAN3_ERFFEL103		(IMXRT_FLEXCAN3_ERXFIFO.offset19C)

  3539. #define FLEXCAN3_ERFFEL104		(IMXRT_FLEXCAN3_ERXFIFO.offset1A0)

  3540. #define FLEXCAN3_ERFFEL105		(IMXRT_FLEXCAN3_ERXFIFO.offset1A4)

  3541. #define FLEXCAN3_ERFFEL106		(IMXRT_FLEXCAN3_ERXFIFO.offset1A8)

  3542. #define FLEXCAN3_ERFFEL107		(IMXRT_FLEXCAN3_ERXFIFO.offset1AC)

  3543. #define FLEXCAN3_ERFFEL108		(IMXRT_FLEXCAN3_ERXFIFO.offset1B0)

  3544. #define FLEXCAN3_ERFFEL109		(IMXRT_FLEXCAN3_ERXFIFO.offset1B4)

  3545. #define FLEXCAN3_ERFFEL110		(IMXRT_FLEXCAN3_ERXFIFO.offset1B8)

  3546. #define FLEXCAN3_ERFFEL111		(IMXRT_FLEXCAN3_ERXFIFO.offset1BC)

  3547. #define FLEXCAN3_ERFFEL112		(IMXRT_FLEXCAN3_ERXFIFO.offset1C0)

  3548. #define FLEXCAN3_ERFFEL113		(IMXRT_FLEXCAN3_ERXFIFO.offset1C4)

  3549. #define FLEXCAN3_ERFFEL114		(IMXRT_FLEXCAN3_ERXFIFO.offset1C8)

  3550. #define FLEXCAN3_ERFFEL115		(IMXRT_FLEXCAN3_ERXFIFO.offset1CC)

  3551. #define FLEXCAN3_ERFFEL116		(IMXRT_FLEXCAN3_ERXFIFO.offset1D0)

  3552. #define FLEXCAN3_ERFFEL117		(IMXRT_FLEXCAN3_ERXFIFO.offset1D4)

  3553. #define FLEXCAN3_ERFFEL118		(IMXRT_FLEXCAN3_ERXFIFO.offset1D8)

  3554. #define FLEXCAN3_ERFFEL119		(IMXRT_FLEXCAN3_ERXFIFO.offset1DC)

  3555. #define FLEXCAN3_ERFFEL120		(IMXRT_FLEXCAN3_ERXFIFO.offset1E0)

  3556. #define FLEXCAN3_ERFFEL121		(IMXRT_FLEXCAN3_ERXFIFO.offset1E4)

  3557. #define FLEXCAN3_ERFFEL122		(IMXRT_FLEXCAN3_ERXFIFO.offset1E8)

  3558. #define FLEXCAN3_ERFFEL123		(IMXRT_FLEXCAN3_ERXFIFO.offset1EC)

  3559. #define FLEXCAN3_ERFFEL124		(IMXRT_FLEXCAN3_ERXFIFO.offset1F0)

  3560. #define FLEXCAN3_ERFFEL125		(IMXRT_FLEXCAN3_ERXFIFO.offset1F4)

  3561. #define FLEXCAN3_ERFFEL126		(IMXRT_FLEXCAN3_ERXFIFO.offset1F8)

  3562. #define FLEXCAN3_ERFFEL127		(IMXRT_FLEXCAN3_ERXFIFO.offset1FC)

  3563. 

  3564. // 50.5.1.1: page 2912

  3565. typedef struct {

  3566.         const   uint32_t VERID;                         // 0x00 (IMXRT_FLEXIO1.offset000)

  3567.         volatile uint32_t PARAM;                        // 0x04 // (IMXRT_FLEXIO1.offset004)

  3568.         volatile uint32_t CTRL;                         // 0x08(IMXRT_FLEXIO1.offset008)

  3569.         volatile uint32_t PIN;                          // 0x0c (IMXRT_FLEXIO1.offset00C)

  3570.         volatile uint32_t SHIFTSTAT;            // 0x10 (IMXRT_FLEXIO1.offset010)

  3571.         volatile uint32_t SHIFTERR;                     // 0x14(IMXRT_FLEXIO1.offset014)

  3572.         volatile uint32_t TIMSTAT;                      // 0x18 (IMXRT_FLEXIO1.offset018)

  3573.         const   uint32_t UNUSED0;                       // 0x1c

  3574.         volatile uint32_t SHIFTSIEN;            // 0x20 (IMXRT_FLEXIO1.offset020)

  3575.         volatile uint32_t SHIFTEIEN;            // 0x24 (IMXRT_FLEXIO1.offset024)

  3576.         volatile uint32_t TIMIEN;                       // 0x28 (IMXRT_FLEXIO1.offset028)

  3577.         const   uint32_t UNUSED1;                       // 0x2c

  3578.         volatile uint32_t SHIFTSDEN;            // 0x30 (IMXRT_FLEXIO1.offset030)

  3579.         const   uint32_t UNUSED2[3];            // 0x34 38 3C

  3580.         volatile uint32_t SHIFTSTATE;           // 0x40 (IMXRT_FLEXIO1.offset040)

  3581.         const   uint32_t UNUSED3[15];           // 0x44..  50... 60... 70...

  3582.         volatile uint32_t SHIFTCTL[4];          // 0x80 84 88 8C

  3583.         const   uint32_t UNUSED4[28];           // 0x90 - 0xfc

  3584.         volatile uint32_t SHIFTCFG[4];          // 0x100 104 108 10C (IMXRT_FLEXIO1.offset100)

  3585.         const   uint32_t UNUSED5[60];           // 0x110 - 0x1FC

  3586.         volatile uint32_t SHIFTBUF[4];          // 0x200 204 208 20c (IMXRT_FLEXIO1.offset200)

  3587.         const   uint32_t UNUSED6[28];           // 

  3588.         volatile uint32_t SHIFTBUFBIS[4];       // 0x280        // (IMXRT_FLEXIO1.offset280)

  3589.         const   uint32_t UNUSED7[28];           // 

  3590.         volatile uint32_t SHIFTBUFBYS[4];       // 0x300 (IMXRT_FLEXIO1.offset300)

  3591.         const   uint32_t UNUSED8[28];           // 

  3592.         volatile uint32_t SHIFTBUFBBS[4];       // 0x380 (IMXRT_FLEXIO1.offset380)

  3593.         const   uint32_t UNUSED9[28];           // 

  3594.         volatile uint32_t TIMCTL[4];            // 0x400 

  3595.         const   uint32_t UNUSED10[28];          // 

  3596.         volatile uint32_t TIMCFG[4];            // 0x480

  3597.         const   uint32_t UNUSED11[28];          // 

  3598.         volatile uint32_t TIMCMP[4];            // 0x500

  3599.         const   uint32_t UNUSED12[28+64];       // 

  3600.         volatile uint32_t SHIFTBUFNBS[4];       // 0x680

  3601.         const   uint32_t UNUSED13[28];          // 

  3602.         volatile uint32_t SHIFTBUFHWS[4];       // 0x700

  3603.         const   uint32_t UNUSED14[28];          // 

  3604.         volatile uint32_t SHIFTBUFNIS[4];       // 0x780

  3605. } IMXRT_FLEXIO_t;

  3606. 

  3607. #define IMXRT_FLEXIO1_S         (*(IMXRT_FLEXIO_t *)0x401AC000)

  3608. #define IMXRT_FLEXIO2_S         (*(IMXRT_FLEXIO_t *)0x401B0000)

  3609. #define IMXRT_FLEXIO3_S         (*(IMXRT_FLEXIO_t *)0x42020000)

  3610. 

  3611. #define IMXRT_FLEXIO1		(*(IMXRT_REGISTER32_t *)0x401AC000)

  3612. #define IMXRT_FLEXIO1_b		(*(IMXRT_REGISTER32_t *)0x401AC400)

  3613. #define FLEXIO1_VERID			(IMXRT_FLEXIO1.offset000)

  3614. #define FLEXIO1_PARAM			(IMXRT_FLEXIO1.offset004)

  3615. #define FLEXIO1_CTRL			(IMXRT_FLEXIO1.offset008)

  3616. #define FLEXIO1_PIN			(IMXRT_FLEXIO1.offset00C)

  3617. #define FLEXIO1_SHIFTSTAT		(IMXRT_FLEXIO1.offset010)

  3618. #define FLEXIO1_SHIFTERR		(IMXRT_FLEXIO1.offset014)

  3619. #define FLEXIO1_TIMSTAT			(IMXRT_FLEXIO1.offset018)

  3620. #define FLEXIO1_SHIFTSIEN		(IMXRT_FLEXIO1.offset020)

  3621. #define FLEXIO1_SHIFTEIEN		(IMXRT_FLEXIO1.offset024)

  3622. #define FLEXIO1_TIMIEN			(IMXRT_FLEXIO1.offset028)

  3623. #define FLEXIO1_SHIFTSDEN		(IMXRT_FLEXIO1.offset030)

  3624. #define FLEXIO1_SHIFTSTATE		(IMXRT_FLEXIO1.offset040)

  3625. #define FLEXIO1_SHIFTCTL0		(IMXRT_FLEXIO1.offset080)

  3626. #define FLEXIO1_SHIFTCTL1		(IMXRT_FLEXIO1.offset084)

  3627. #define FLEXIO1_SHIFTCTL2		(IMXRT_FLEXIO1.offset088)

  3628. #define FLEXIO1_SHIFTCTL3		(IMXRT_FLEXIO1.offset08C)

  3629. #define FLEXIO1_SHIFTCFG0		(IMXRT_FLEXIO1.offset100)

  3630. #define FLEXIO1_SHIFTCFG1		(IMXRT_FLEXIO1.offset104)

  3631. #define FLEXIO1_SHIFTCFG2		(IMXRT_FLEXIO1.offset108)

  3632. #define FLEXIO1_SHIFTCFG3		(IMXRT_FLEXIO1.offset10C)

  3633. #define FLEXIO1_SHIFTBUF0		(IMXRT_FLEXIO1.offset200)

  3634. #define FLEXIO1_SHIFTBUF1		(IMXRT_FLEXIO1.offset204)

  3635. #define FLEXIO1_SHIFTBUF2		(IMXRT_FLEXIO1.offset208)

  3636. #define FLEXIO1_SHIFTBUF3		(IMXRT_FLEXIO1.offset20C)

  3637. #define FLEXIO1_SHIFTBUFBIS0		(IMXRT_FLEXIO1.offset280)

  3638. #define FLEXIO1_SHIFTBUFBIS1		(IMXRT_FLEXIO1.offset284)

  3639. #define FLEXIO1_SHIFTBUFBIS2		(IMXRT_FLEXIO1.offset288)

  3640. #define FLEXIO1_SHIFTBUFBIS3		(IMXRT_FLEXIO1.offset28C)

  3641. #define FLEXIO1_SHIFTBUFBYS0		(IMXRT_FLEXIO1.offset300)

  3642. #define FLEXIO1_SHIFTBUFBYS1		(IMXRT_FLEXIO1.offset304)

  3643. #define FLEXIO1_SHIFTBUFBYS2		(IMXRT_FLEXIO1.offset308)

  3644. #define FLEXIO1_SHIFTBUFBYS3		(IMXRT_FLEXIO1.offset30C)

  3645. #define FLEXIO1_SHIFTBUFBBS0		(IMXRT_FLEXIO1.offset380)

  3646. #define FLEXIO1_SHIFTBUFBBS1		(IMXRT_FLEXIO1.offset384)

  3647. #define FLEXIO1_SHIFTBUFBBS2		(IMXRT_FLEXIO1.offset388)

  3648. #define FLEXIO1_SHIFTBUFBBS3		(IMXRT_FLEXIO1.offset38C)

  3649. #define FLEXIO1_TIMCTL0			(IMXRT_FLEXIO1_b.offset000)

  3650. #define FLEXIO1_TIMCTL1			(IMXRT_FLEXIO1_b.offset004)

  3651. #define FLEXIO1_TIMCTL2			(IMXRT_FLEXIO1_b.offset008)

  3652. #define FLEXIO1_TIMCTL3			(IMXRT_FLEXIO1_b.offset00C)

  3653. #define FLEXIO1_TIMCFG0			(IMXRT_FLEXIO1_b.offset080)

  3654. #define FLEXIO1_TIMCFG1			(IMXRT_FLEXIO1_b.offset084)

  3655. #define FLEXIO1_TIMCFG2			(IMXRT_FLEXIO1_b.offset088)

  3656. #define FLEXIO1_TIMCFG3			(IMXRT_FLEXIO1_b.offset08C)

  3657. #define FLEXIO1_TIMCMP0			(IMXRT_FLEXIO1_b.offset100)

  3658. #define FLEXIO1_TIMCMP1			(IMXRT_FLEXIO1_b.offset104)

  3659. #define FLEXIO1_TIMCMP2			(IMXRT_FLEXIO1_b.offset108)

  3660. #define FLEXIO1_TIMCMP3			(IMXRT_FLEXIO1_b.offset10C)

  3661. #define FLEXIO1_SHIFTBUFNBS0		(IMXRT_FLEXIO1_b.offset280)

  3662. #define FLEXIO1_SHIFTBUFNBS1		(IMXRT_FLEXIO1_b.offset284)

  3663. #define FLEXIO1_SHIFTBUFNBS2		(IMXRT_FLEXIO1_b.offset288)

  3664. #define FLEXIO1_SHIFTBUFNBS3		(IMXRT_FLEXIO1_b.offset28C)

  3665. #define FLEXIO1_SHIFTBUFHWS0		(IMXRT_FLEXIO1_b.offset300)

  3666. #define FLEXIO1_SHIFTBUFHWS1		(IMXRT_FLEXIO1_b.offset304)

  3667. #define FLEXIO1_SHIFTBUFHWS2		(IMXRT_FLEXIO1_b.offset308)

  3668. #define FLEXIO1_SHIFTBUFHWS3		(IMXRT_FLEXIO1_b.offset30C)

  3669. #define FLEXIO1_SHIFTBUFNIS0		(IMXRT_FLEXIO1_b.offset380)

  3670. #define FLEXIO1_SHIFTBUFNIS1		(IMXRT_FLEXIO1_b.offset384)

  3671. #define FLEXIO1_SHIFTBUFNIS2		(IMXRT_FLEXIO1_b.offset388)

  3672. #define FLEXIO1_SHIFTBUFNIS3		(IMXRT_FLEXIO1_b.offset38C)

  3673. #define IMXRT_FLEXIO2		(*(IMXRT_REGISTER32_t *)0x401B0000)

  3674. #define IMXRT_FLEXIO2_b		(*(IMXRT_REGISTER32_t *)0x401B0400)

  3675. #define FLEXIO2_VERID			(IMXRT_FLEXIO2.offset000)

  3676. #define FLEXIO2_PARAM			(IMXRT_FLEXIO2.offset004)

  3677. #define FLEXIO2_CTRL			(IMXRT_FLEXIO2.offset008)

  3678. #define FLEXIO2_PIN			(IMXRT_FLEXIO2.offset00C)

  3679. #define FLEXIO2_SHIFTSTAT		(IMXRT_FLEXIO2.offset010)

  3680. #define FLEXIO2_SHIFTERR		(IMXRT_FLEXIO2.offset014)

  3681. #define FLEXIO2_TIMSTAT			(IMXRT_FLEXIO2.offset018)

  3682. #define FLEXIO2_SHIFTSIEN		(IMXRT_FLEXIO2.offset020)

  3683. #define FLEXIO2_SHIFTEIEN		(IMXRT_FLEXIO2.offset024)

  3684. #define FLEXIO2_TIMIEN			(IMXRT_FLEXIO2.offset028)

  3685. #define FLEXIO2_SHIFTSDEN		(IMXRT_FLEXIO2.offset030)

  3686. #define FLEXIO2_SHIFTSTATE		(IMXRT_FLEXIO2.offset040)

  3687. #define FLEXIO2_SHIFTCTL0		(IMXRT_FLEXIO2.offset080)

  3688. #define FLEXIO2_SHIFTCTL1		(IMXRT_FLEXIO2.offset084)

  3689. #define FLEXIO2_SHIFTCTL2		(IMXRT_FLEXIO2.offset088)

  3690. #define FLEXIO2_SHIFTCTL3		(IMXRT_FLEXIO2.offset08C)

  3691. #define FLEXIO2_SHIFTCFG0		(IMXRT_FLEXIO2.offset100)

  3692. #define FLEXIO2_SHIFTCFG1		(IMXRT_FLEXIO2.offset104)

  3693. #define FLEXIO2_SHIFTCFG2		(IMXRT_FLEXIO2.offset108)

  3694. #define FLEXIO2_SHIFTCFG3		(IMXRT_FLEXIO2.offset10C)

  3695. #define FLEXIO2_SHIFTBUF0		(IMXRT_FLEXIO2.offset200)

  3696. #define FLEXIO2_SHIFTBUF1		(IMXRT_FLEXIO2.offset204)

  3697. #define FLEXIO2_SHIFTBUF2		(IMXRT_FLEXIO2.offset208)

  3698. #define FLEXIO2_SHIFTBUF3		(IMXRT_FLEXIO2.offset20C)

  3699. #define FLEXIO2_SHIFTBUFBIS0		(IMXRT_FLEXIO2.offset280)

  3700. #define FLEXIO2_SHIFTBUFBIS1		(IMXRT_FLEXIO2.offset284)

  3701. #define FLEXIO2_SHIFTBUFBIS2		(IMXRT_FLEXIO2.offset288)

  3702. #define FLEXIO2_SHIFTBUFBIS3		(IMXRT_FLEXIO2.offset28C)

  3703. #define FLEXIO2_SHIFTBUFBYS0		(IMXRT_FLEXIO2.offset300)

  3704. #define FLEXIO2_SHIFTBUFBYS1		(IMXRT_FLEXIO2.offset304)

  3705. #define FLEXIO2_SHIFTBUFBYS2		(IMXRT_FLEXIO2.offset308)

  3706. #define FLEXIO2_SHIFTBUFBYS3		(IMXRT_FLEXIO2.offset30C)

  3707. #define FLEXIO2_SHIFTBUFBBS0		(IMXRT_FLEXIO2.offset380)

  3708. #define FLEXIO2_SHIFTBUFBBS1		(IMXRT_FLEXIO2.offset384)

  3709. #define FLEXIO2_SHIFTBUFBBS2		(IMXRT_FLEXIO2.offset388)

  3710. #define FLEXIO2_SHIFTBUFBBS3		(IMXRT_FLEXIO2.offset38C)

  3711. #define FLEXIO2_TIMCTL0			(IMXRT_FLEXIO2_b.offset000)

  3712. #define FLEXIO2_TIMCTL1			(IMXRT_FLEXIO2_b.offset004)

  3713. #define FLEXIO2_TIMCTL2			(IMXRT_FLEXIO2_b.offset008)

  3714. #define FLEXIO2_TIMCTL3			(IMXRT_FLEXIO2_b.offset00C)

  3715. #define FLEXIO2_TIMCFG0			(IMXRT_FLEXIO2_b.offset080)

  3716. #define FLEXIO2_TIMCFG1			(IMXRT_FLEXIO2_b.offset084)

  3717. #define FLEXIO2_TIMCFG2			(IMXRT_FLEXIO2_b.offset088)

  3718. #define FLEXIO2_TIMCFG3			(IMXRT_FLEXIO2_b.offset08C)

  3719. #define FLEXIO2_TIMCMP0			(IMXRT_FLEXIO2_b.offset100)

  3720. #define FLEXIO2_TIMCMP1			(IMXRT_FLEXIO2_b.offset104)

  3721. #define FLEXIO2_TIMCMP2			(IMXRT_FLEXIO2_b.offset108)

  3722. #define FLEXIO2_TIMCMP3			(IMXRT_FLEXIO2_b.offset10C)

  3723. #define FLEXIO2_SHIFTBUFNBS0		(IMXRT_FLEXIO2_b.offset280)

  3724. #define FLEXIO2_SHIFTBUFNBS1		(IMXRT_FLEXIO2_b.offset284)

  3725. #define FLEXIO2_SHIFTBUFNBS2		(IMXRT_FLEXIO2_b.offset288)

  3726. #define FLEXIO2_SHIFTBUFNBS3		(IMXRT_FLEXIO2_b.offset28C)

  3727. #define FLEXIO2_SHIFTBUFHWS0		(IMXRT_FLEXIO2_b.offset300)

  3728. #define FLEXIO2_SHIFTBUFHWS1		(IMXRT_FLEXIO2_b.offset304)

  3729. #define FLEXIO2_SHIFTBUFHWS2		(IMXRT_FLEXIO2_b.offset308)

  3730. #define FLEXIO2_SHIFTBUFHWS3		(IMXRT_FLEXIO2_b.offset30C)

  3731. #define FLEXIO2_SHIFTBUFNIS0		(IMXRT_FLEXIO2_b.offset380)

  3732. #define FLEXIO2_SHIFTBUFNIS1		(IMXRT_FLEXIO2_b.offset384)

  3733. #define FLEXIO2_SHIFTBUFNIS2		(IMXRT_FLEXIO2_b.offset388)

  3734. #define FLEXIO2_SHIFTBUFNIS3		(IMXRT_FLEXIO2_b.offset38C)

  3735. // FLEXIO3 only present in RT1062

  3736. #define IMXRT_FLEXIO3		(*(IMXRT_REGISTER32_t *)0x42020000)

  3737. #define IMXRT_FLEXIO3_b		(*(IMXRT_REGISTER32_t *)0x42020400)

  3738. #define FLEXIO3_VERID			(IMXRT_FLEXIO3.offset000)

  3739. #define FLEXIO3_PARAM			(IMXRT_FLEXIO3.offset004)

  3740. #define FLEXIO3_CTRL			(IMXRT_FLEXIO3.offset008)

  3741. #define FLEXIO3_PIN			(IMXRT_FLEXIO3.offset00C)

  3742. #define FLEXIO3_SHIFTSTAT		(IMXRT_FLEXIO3.offset010)

  3743. #define FLEXIO3_SHIFTERR		(IMXRT_FLEXIO3.offset014)

  3744. #define FLEXIO3_TIMSTAT			(IMXRT_FLEXIO3.offset018)

  3745. #define FLEXIO3_SHIFTSIEN		(IMXRT_FLEXIO3.offset020)

  3746. #define FLEXIO3_SHIFTEIEN		(IMXRT_FLEXIO3.offset024)

  3747. #define FLEXIO3_TIMIEN			(IMXRT_FLEXIO3.offset028)

  3748. #define FLEXIO3_SHIFTSDEN		(IMXRT_FLEXIO3.offset030)

  3749. #define FLEXIO3_SHIFTSTATE		(IMXRT_FLEXIO3.offset040)

  3750. #define FLEXIO3_SHIFTCTL0		(IMXRT_FLEXIO3.offset080)

  3751. #define FLEXIO3_SHIFTCTL1		(IMXRT_FLEXIO3.offset084)

  3752. #define FLEXIO3_SHIFTCTL2		(IMXRT_FLEXIO3.offset088)

  3753. #define FLEXIO3_SHIFTCTL3		(IMXRT_FLEXIO3.offset08C)

  3754. #define FLEXIO3_SHIFTCFG0		(IMXRT_FLEXIO3.offset100)

  3755. #define FLEXIO3_SHIFTCFG1		(IMXRT_FLEXIO3.offset104)

  3756. #define FLEXIO3_SHIFTCFG2		(IMXRT_FLEXIO3.offset108)

  3757. #define FLEXIO3_SHIFTCFG3		(IMXRT_FLEXIO3.offset10C)

  3758. #define FLEXIO3_SHIFTBUF0		(IMXRT_FLEXIO3.offset200)

  3759. #define FLEXIO3_SHIFTBUF1		(IMXRT_FLEXIO3.offset204)

  3760. #define FLEXIO3_SHIFTBUF2		(IMXRT_FLEXIO3.offset208)

  3761. #define FLEXIO3_SHIFTBUF3		(IMXRT_FLEXIO3.offset20C)

  3762. #define FLEXIO3_SHIFTBUFBIS0		(IMXRT_FLEXIO3.offset280)

  3763. #define FLEXIO3_SHIFTBUFBIS1		(IMXRT_FLEXIO3.offset284)

  3764. #define FLEXIO3_SHIFTBUFBIS2		(IMXRT_FLEXIO3.offset288)

  3765. #define FLEXIO3_SHIFTBUFBIS3		(IMXRT_FLEXIO3.offset28C)

  3766. #define FLEXIO3_SHIFTBUFBYS0		(IMXRT_FLEXIO3.offset300)

  3767. #define FLEXIO3_SHIFTBUFBYS1		(IMXRT_FLEXIO3.offset304)

  3768. #define FLEXIO3_SHIFTBUFBYS2		(IMXRT_FLEXIO3.offset308)

  3769. #define FLEXIO3_SHIFTBUFBYS3		(IMXRT_FLEXIO3.offset30C)

  3770. #define FLEXIO3_SHIFTBUFBBS0		(IMXRT_FLEXIO3.offset380)

  3771. #define FLEXIO3_SHIFTBUFBBS1		(IMXRT_FLEXIO3.offset384)

  3772. #define FLEXIO3_SHIFTBUFBBS2		(IMXRT_FLEXIO3.offset388)

  3773. #define FLEXIO3_SHIFTBUFBBS3		(IMXRT_FLEXIO3.offset38C)

  3774. #define FLEXIO3_TIMCTL0			(IMXRT_FLEXIO3_b.offset000)

  3775. #define FLEXIO3_TIMCTL1			(IMXRT_FLEXIO3_b.offset004)

  3776. #define FLEXIO3_TIMCTL2			(IMXRT_FLEXIO3_b.offset008)

  3777. #define FLEXIO3_TIMCTL3			(IMXRT_FLEXIO3_b.offset00C)

  3778. #define FLEXIO3_TIMCFG0			(IMXRT_FLEXIO3_b.offset080)

  3779. #define FLEXIO3_TIMCFG1			(IMXRT_FLEXIO3_b.offset084)

  3780. #define FLEXIO3_TIMCFG2			(IMXRT_FLEXIO3_b.offset088)

  3781. #define FLEXIO3_TIMCFG3			(IMXRT_FLEXIO3_b.offset08C)

  3782. #define FLEXIO3_TIMCMP0			(IMXRT_FLEXIO3_b.offset100)

  3783. #define FLEXIO3_TIMCMP1			(IMXRT_FLEXIO3_b.offset104)

  3784. #define FLEXIO3_TIMCMP2			(IMXRT_FLEXIO3_b.offset108)

  3785. #define FLEXIO3_TIMCMP3			(IMXRT_FLEXIO3_b.offset10C)

  3786. #define FLEXIO3_SHIFTBUFNBS0		(IMXRT_FLEXIO3_b.offset280)

  3787. #define FLEXIO3_SHIFTBUFNBS1		(IMXRT_FLEXIO3_b.offset284)

  3788. #define FLEXIO3_SHIFTBUFNBS2		(IMXRT_FLEXIO3_b.offset288)

  3789. #define FLEXIO3_SHIFTBUFNBS3		(IMXRT_FLEXIO3_b.offset28C)

  3790. #define FLEXIO3_SHIFTBUFHWS0		(IMXRT_FLEXIO3_b.offset300)

  3791. #define FLEXIO3_SHIFTBUFHWS1		(IMXRT_FLEXIO3_b.offset304)

  3792. #define FLEXIO3_SHIFTBUFHWS2		(IMXRT_FLEXIO3_b.offset308)

  3793. #define FLEXIO3_SHIFTBUFHWS3		(IMXRT_FLEXIO3_b.offset30C)

  3794. #define FLEXIO3_SHIFTBUFNIS0		(IMXRT_FLEXIO3_b.offset380)

  3795. #define FLEXIO3_SHIFTBUFNIS1		(IMXRT_FLEXIO3_b.offset384)

  3796. #define FLEXIO3_SHIFTBUFNIS2		(IMXRT_FLEXIO3_b.offset388)

  3797. #define FLEXIO3_SHIFTBUFNIS3		(IMXRT_FLEXIO3_b.offset38C)

  3798. #define FLEXIO_CTRL_DOZEN			((uint32_t)(1<<31))

  3799. #define FLEXIO_CTRL_DBGE			((uint32_t)(1<<30))

  3800. #define FLEXIO_CTRL_FASTACC			((uint32_t)(1<<2))

  3801. #define FLEXIO_CTRL_SWRST			((uint32_t)(1<<1))

  3802. #define FLEXIO_CTRL_FLEXEN			((uint32_t)(1<<0))

  3803. #define FLEXIO_SHIFTCTL_TIMSEL(n)		((uint32_t)(((n) & 0x03) << 24))

  3804. #define FLEXIO_SHIFTCTL_TIMPOL			((uint32_t)(1<<23))

  3805. #define FLEXIO_SHIFTCTL_PINCFG(n)		((uint32_t)(((n) & 0x03) << 16))

  3806. #define FLEXIO_SHIFTCTL_PINSEL(n)		((uint32_t)(((n) & 0x1F) << 8))

  3807. #define FLEXIO_SHIFTCTL_PINPOL			((uint32_t)(1<<7))

  3808. #define FLEXIO_SHIFTCTL_SMOD(n)			((uint32_t)(((n) & 0x07) << 0))

  3809. #define FLEXIO_SHIFTCFG_PWIDTH(n)		((uint32_t)(((n) & 0x1F) << 16))

  3810. #define FLEXIO_SHIFTCFG_INSRC			((uint32_t)(1<<8))

  3811. #define FLEXIO_SHIFTCFG_SSTOP(n)		((uint32_t)(((n) & 0x03) << 4))

  3812. #define FLEXIO_SHIFTCFG_SSTART(n)		((uint32_t)(((n) & 0x03) << 0))

  3813. #define FLEXIO_TIMCTL_TRGSEL(n)			((uint32_t)(((n) & 0x3F) << 24))

  3814. #define FLEXIO_TIMCTL_TRGPOL			((uint32_t)(1<<23))

  3815. #define FLEXIO_TIMCTL_TRGSRC			((uint32_t)(1<<22))

  3816. #define FLEXIO_TIMCTL_PINCFG(n)			((uint32_t)(((n) & 0x03) << 16))

  3817. #define FLEXIO_TIMCTL_PINSEL(n)			((uint32_t)(((n) & 0x1F) << 8))

  3818. #define FLEXIO_TIMCTL_PINPOL			((uint32_t)(1<<7))

  3819. #define FLEXIO_TIMCTL_TIMOD(n)			((uint32_t)(((n) & 0x03) << 0))

  3820. #define FLEXIO_TIMCFG_TIMOUT(n)			((uint32_t)(((n) & 0x03) << 24))

  3821. #define FLEXIO_TIMCFG_TIMDEC(n)			((uint32_t)(((n) & 0x03) << 20))

  3822. #define FLEXIO_TIMCFG_TIMRST(n)			((uint32_t)(((n) & 0x07) << 16))

  3823. #define FLEXIO_TIMCFG_TIMDIS(n)			((uint32_t)(((n) & 0x07) << 12))

  3824. #define FLEXIO_TIMCFG_TIMENA(n)			((uint32_t)(((n) & 0x07) << 8))

  3825. #define FLEXIO_TIMCFG_TSTOP(n)			((uint32_t)(((n) & 0x03) << 4))

  3826. #define FLEXIO_TIMCFG_TSTART			((uint32_t)(1<<1))

  3827. 

  3828. // 55.8.1: page 3074

  3829. typedef struct {

  3830. 	struct {

  3831. 		volatile uint16_t CNT;

  3832. 		volatile uint16_t INIT;

  3833. 		volatile uint16_t CTRL2;

  3834. 		volatile uint16_t CTRL;

  3835. 		volatile uint16_t unused1;

  3836. 		volatile uint16_t VAL0;

  3837. 		volatile uint16_t FRACVAL1;

  3838. 		volatile uint16_t VAL1;

  3839. 		volatile uint16_t FRACVAL2;

  3840. 		volatile uint16_t VAL2;

  3841. 		volatile uint16_t FRACVAL3;

  3842. 		volatile uint16_t VAL3;

  3843. 		volatile uint16_t FRACVAL4;

  3844. 		volatile uint16_t VAL4;

  3845. 		volatile uint16_t FRACVAL5;

  3846. 		volatile uint16_t VAL5;

  3847. 		volatile uint16_t FRCTRL;

  3848. 		volatile uint16_t OCTRL;

  3849. 		volatile uint16_t STS;

  3850. 		volatile uint16_t INTEN;

  3851. 		volatile uint16_t DMAEN;

  3852. 		volatile uint16_t TCTRL;

  3853. 		volatile uint16_t DISMAP0;

  3854. 		volatile uint16_t DISMAP1;

  3855. 		volatile uint16_t DTCNT0;

  3856. 		volatile uint16_t DTCNT1;

  3857. 		volatile uint16_t CAPTCTRLA;

  3858. 		volatile uint16_t CAPTCOMPA;

  3859. 		volatile uint16_t CAPTCTRLB;

  3860. 		volatile uint16_t CAPTCOMPB;

  3861. 		volatile uint16_t CAPTCTRLX;

  3862. 		volatile uint16_t CAPTCOMPX;

  3863. 		volatile uint16_t CVAL0;

  3864. 		volatile uint16_t CVAL0CYC;

  3865. 		volatile uint16_t CVAL1;

  3866. 		volatile uint16_t CVAL1CYC;

  3867. 		volatile uint16_t CVAL2;

  3868. 		volatile uint16_t CVAL2CYC;

  3869. 		volatile uint16_t CVAL3;

  3870. 		volatile uint16_t CVAL3CYC;

  3871. 		volatile uint16_t CVAL4;

  3872. 		volatile uint16_t CVAL4CYC;

  3873. 		volatile uint16_t CVAL5;

  3874. 		volatile uint16_t CVAL5CYC;

  3875. 		volatile uint16_t unused2;

  3876. 		volatile uint16_t unused3;

  3877. 		volatile uint16_t unused4;

  3878. 		volatile uint16_t unused5;

  3879. 	} SM[4];

  3880. 	volatile uint16_t OUTEN;

  3881. 	volatile uint16_t MASK;

  3882. 	volatile uint16_t SWCOUT;

  3883. 	volatile uint16_t DTSRCSEL;

  3884. 	volatile uint16_t MCTRL;

  3885. 	volatile uint16_t MCTRL2;

  3886. 	volatile uint16_t FCTRL0;

  3887. 	volatile uint16_t FSTS0;

  3888. 	volatile uint16_t FFILT0;

  3889. 	volatile uint16_t FTST0;

  3890. 	volatile uint16_t FCTRL20;

  3891. } IMXRT_FLEXPWM_t;

  3892. #define IMXRT_FLEXPWM1		(*(IMXRT_FLEXPWM_t *)0x403DC000)

  3893. #define IMXRT_FLEXPWM2		(*(IMXRT_FLEXPWM_t *)0x403E0000)

  3894. #define IMXRT_FLEXPWM3		(*(IMXRT_FLEXPWM_t *)0x403E4000)

  3895. #define IMXRT_FLEXPWM4		(*(IMXRT_FLEXPWM_t *)0x403E8000)

  3896. #define FLEXPWM1_SM0CNT			(IMXRT_FLEXPWM1.SM[0].CNT)

  3897. #define FLEXPWM1_SM0INIT		(IMXRT_FLEXPWM1.SM[0].INIT)

  3898. #define FLEXPWM1_SM0CTRL2		(IMXRT_FLEXPWM1.SM[0].CTRL2)

  3899. #define FLEXPWM1_SM0CTRL		(IMXRT_FLEXPWM1.SM[0].CTRL)

  3900. #define FLEXPWM1_SM0VAL0		(IMXRT_FLEXPWM1.SM[0].VAL0)

  3901. #define FLEXPWM1_SM0FRACVAL1		(IMXRT_FLEXPWM1.SM[0].FRACVAL1)

  3902. #define FLEXPWM1_SM0VAL1		(IMXRT_FLEXPWM1.SM[0].VAL1)

  3903. #define FLEXPWM1_SM0FRACVAL2		(IMXRT_FLEXPWM1.SM[0].FRACVAL2)

  3904. #define FLEXPWM1_SM0VAL2		(IMXRT_FLEXPWM1.SM[0].VAL2)

  3905. #define FLEXPWM1_SM0FRACVAL3		(IMXRT_FLEXPWM1.SM[0].FRACVAL3)

  3906. #define FLEXPWM1_SM0VAL3		(IMXRT_FLEXPWM1.SM[0].VAL3)

  3907. #define FLEXPWM1_SM0FRACVAL4		(IMXRT_FLEXPWM1.SM[0].FRACVAL4)

  3908. #define FLEXPWM1_SM0VAL4		(IMXRT_FLEXPWM1.SM[0].VAL4)

  3909. #define FLEXPWM1_SM0FRACVAL5		(IMXRT_FLEXPWM1.SM[0].FRACVAL5)

  3910. #define FLEXPWM1_SM0VAL5		(IMXRT_FLEXPWM1.SM[0].VAL5)

  3911. #define FLEXPWM1_SM0FRCTRL		(IMXRT_FLEXPWM1.SM[0].FRCTRL)

  3912. #define FLEXPWM1_SM0OCTRL		(IMXRT_FLEXPWM1.SM[0].OCTRL)

  3913. #define FLEXPWM1_SM0STS			(IMXRT_FLEXPWM1.SM[0].STS)

  3914. #define FLEXPWM1_SM0INTEN		(IMXRT_FLEXPWM1.SM[0].INTEN)

  3915. #define FLEXPWM1_SM0DMAEN		(IMXRT_FLEXPWM1.SM[0].DMAEN)

  3916. #define FLEXPWM1_SM0TCTRL		(IMXRT_FLEXPWM1.SM[0].TCTRL)

  3917. #define FLEXPWM1_SM0DISMAP0		(IMXRT_FLEXPWM1.SM[0].DISMAP0)

  3918. #define FLEXPWM1_SM0DISMAP1		(IMXRT_FLEXPWM1.SM[0].DISMAP1)

  3919. #define FLEXPWM1_SM0DTCNT0		(IMXRT_FLEXPWM1.SM[0].DTCNT0)

  3920. #define FLEXPWM1_SM0DTCNT1		(IMXRT_FLEXPWM1.SM[0].DTCNT1)

  3921. #define FLEXPWM1_SM0CAPTCTRLA		(IMXRT_FLEXPWM1.SM[0].CAPTCTRLA)

  3922. #define FLEXPWM1_SM0CAPTCOMPA		(IMXRT_FLEXPWM1.SM[0].CAPTCOMPA)

  3923. #define FLEXPWM1_SM0CAPTCTRLB		(IMXRT_FLEXPWM1.SM[0].CAPTCTRLB)

  3924. #define FLEXPWM1_SM0CAPTCOMPB		(IMXRT_FLEXPWM1.SM[0].CAPTCOMPB)

  3925. #define FLEXPWM1_SM0CAPTCTRLX		(IMXRT_FLEXPWM1.SM[0].CAPTCTRLX)

  3926. #define FLEXPWM1_SM0CAPTCOMPX		(IMXRT_FLEXPWM1.SM[0].CAPTCOMPX)

  3927. #define FLEXPWM1_SM0CVAL0		(IMXRT_FLEXPWM1.SM[0].CVAL0)

  3928. #define FLEXPWM1_SM0CVAL0CYC		(IMXRT_FLEXPWM1.SM[0].CVAL0CYC)

  3929. #define FLEXPWM1_SM0CVAL1		(IMXRT_FLEXPWM1.SM[0].CVAL1)

  3930. #define FLEXPWM1_SM0CVAL1CYC		(IMXRT_FLEXPWM1.SM[0].CVAL1CYC)

  3931. #define FLEXPWM1_SM0CVAL2		(IMXRT_FLEXPWM1.SM[0].CVAL2)

  3932. #define FLEXPWM1_SM0CVAL2CYC		(IMXRT_FLEXPWM1.SM[0].CVAL2CYC)

  3933. #define FLEXPWM1_SM0CVAL3		(IMXRT_FLEXPWM1.SM[0].CVAL3)

  3934. #define FLEXPWM1_SM0CVAL3CYC		(IMXRT_FLEXPWM1.SM[0].CVAL3CYC)

  3935. #define FLEXPWM1_SM0CVAL4		(IMXRT_FLEXPWM1.SM[0].CVAL4)

  3936. #define FLEXPWM1_SM0CVAL4CYC		(IMXRT_FLEXPWM1.SM[0].CVAL4CYC)

  3937. #define FLEXPWM1_SM0CVAL5		(IMXRT_FLEXPWM1.SM[0].CVAL5)

  3938. #define FLEXPWM1_SM0CVAL5CYC		(IMXRT_FLEXPWM1.SM[0].CVAL5CYC)

  3939. #define FLEXPWM1_SM1CNT			(IMXRT_FLEXPWM1.SM[1].CNT)

  3940. #define FLEXPWM1_SM1INIT		(IMXRT_FLEXPWM1.SM[1].INIT)

  3941. #define FLEXPWM1_SM1CTRL2		(IMXRT_FLEXPWM1.SM[1].CTRL2)

  3942. #define FLEXPWM1_SM1CTRL		(IMXRT_FLEXPWM1.SM[1].CTRL)

  3943. #define FLEXPWM1_SM1VAL0		(IMXRT_FLEXPWM1.SM[1].VAL0)

  3944. #define FLEXPWM1_SM1FRACVAL1		(IMXRT_FLEXPWM1.SM[1].FRACVAL1)

  3945. #define FLEXPWM1_SM1VAL1		(IMXRT_FLEXPWM1.SM[1].VAL1)

  3946. #define FLEXPWM1_SM1FRACVAL2		(IMXRT_FLEXPWM1.SM[1].FRACVAL2)

  3947. #define FLEXPWM1_SM1VAL2		(IMXRT_FLEXPWM1.SM[1].VAL2)

  3948. #define FLEXPWM1_SM1FRACVAL3		(IMXRT_FLEXPWM1.SM[1].FRACVAL3)

  3949. #define FLEXPWM1_SM1VAL3		(IMXRT_FLEXPWM1.SM[1].VAL3)

  3950. #define FLEXPWM1_SM1FRACVAL4		(IMXRT_FLEXPWM1.SM[1].FRACVAL4)

  3951. #define FLEXPWM1_SM1VAL4		(IMXRT_FLEXPWM1.SM[1].VAL4)

  3952. #define FLEXPWM1_SM1FRACVAL5		(IMXRT_FLEXPWM1.SM[1].FRACVAL5)

  3953. #define FLEXPWM1_SM1VAL5		(IMXRT_FLEXPWM1.SM[1].VAL5)

  3954. #define FLEXPWM1_SM1FRCTRL		(IMXRT_FLEXPWM1.SM[1].FRCTRL)

  3955. #define FLEXPWM1_SM1OCTRL		(IMXRT_FLEXPWM1.SM[1].OCTRL)

  3956. #define FLEXPWM1_SM1STS			(IMXRT_FLEXPWM1.SM[1].STS)

  3957. #define FLEXPWM1_SM1INTEN		(IMXRT_FLEXPWM1.SM[1].INTEN)

  3958. #define FLEXPWM1_SM1DMAEN		(IMXRT_FLEXPWM1.SM[1].DMAEN)

  3959. #define FLEXPWM1_SM1TCTRL		(IMXRT_FLEXPWM1.SM[1].TCTRL)

  3960. #define FLEXPWM1_SM1DISMAP0		(IMXRT_FLEXPWM1.SM[1].DISMAP0)

  3961. #define FLEXPWM1_SM1DISMAP1		(IMXRT_FLEXPWM1.SM[1].DISMAP1)

  3962. #define FLEXPWM1_SM1DTCNT0		(IMXRT_FLEXPWM1.SM[1].DTCNT0)

  3963. #define FLEXPWM1_SM1DTCNT1		(IMXRT_FLEXPWM1.SM[1].DTCNT1)

  3964. #define FLEXPWM1_SM1CAPTCTRLA		(IMXRT_FLEXPWM1.SM[1].CAPTCTRLA)

  3965. #define FLEXPWM1_SM1CAPTCOMPA		(IMXRT_FLEXPWM1.SM[1].CAPTCOMPA)

  3966. #define FLEXPWM1_SM1CAPTCTRLB		(IMXRT_FLEXPWM1.SM[1].CAPTCTRLB)

  3967. #define FLEXPWM1_SM1CAPTCOMPB		(IMXRT_FLEXPWM1.SM[1].CAPTCOMPB)

  3968. #define FLEXPWM1_SM1CAPTCTRLX		(IMXRT_FLEXPWM1.SM[1].CAPTCTRLX)

  3969. #define FLEXPWM1_SM1CAPTCOMPX		(IMXRT_FLEXPWM1.SM[1].CAPTCOMPX)

  3970. #define FLEXPWM1_SM1CVAL0		(IMXRT_FLEXPWM1.SM[1].CVAL0)

  3971. #define FLEXPWM1_SM1CVAL0CYC		(IMXRT_FLEXPWM1.SM[1].CVAL0CYC)

  3972. #define FLEXPWM1_SM1CVAL1		(IMXRT_FLEXPWM1.SM[1].CVAL1)

  3973. #define FLEXPWM1_SM1CVAL1CYC		(IMXRT_FLEXPWM1.SM[1].CVAL1CYC)

  3974. #define FLEXPWM1_SM1CVAL2		(IMXRT_FLEXPWM1.SM[1].CVAL2)

  3975. #define FLEXPWM1_SM1CVAL2CYC		(IMXRT_FLEXPWM1.SM[1].CVAL2CYC)

  3976. #define FLEXPWM1_SM1CVAL3		(IMXRT_FLEXPWM1.SM[1].CVAL3)

  3977. #define FLEXPWM1_SM1CVAL3CYC		(IMXRT_FLEXPWM1.SM[1].CVAL3CYC)

  3978. #define FLEXPWM1_SM1CVAL4		(IMXRT_FLEXPWM1.SM[1].CVAL4)

  3979. #define FLEXPWM1_SM1CVAL4CYC		(IMXRT_FLEXPWM1.SM[1].CVAL4CYC)

  3980. #define FLEXPWM1_SM1CVAL5		(IMXRT_FLEXPWM1.SM[1].CVAL5)

  3981. #define FLEXPWM1_SM1CVAL5CYC		(IMXRT_FLEXPWM1.SM[1].CVAL5CYC)

  3982. #define FLEXPWM1_SM2CNT			(IMXRT_FLEXPWM1.SM[2].CNT)

  3983. #define FLEXPWM1_SM2INIT		(IMXRT_FLEXPWM1.SM[2].INIT)

  3984. #define FLEXPWM1_SM2CTRL2		(IMXRT_FLEXPWM1.SM[2].CTRL2)

  3985. #define FLEXPWM1_SM2CTRL		(IMXRT_FLEXPWM1.SM[2].CTRL)

  3986. #define FLEXPWM1_SM2VAL0		(IMXRT_FLEXPWM1.SM[2].VAL0)

  3987. #define FLEXPWM1_SM2FRACVAL1		(IMXRT_FLEXPWM1.SM[2].FRACVAL1)

  3988. #define FLEXPWM1_SM2VAL1		(IMXRT_FLEXPWM1.SM[2].VAL1)

  3989. #define FLEXPWM1_SM2FRACVAL2		(IMXRT_FLEXPWM1.SM[2].FRACVAL2)

  3990. #define FLEXPWM1_SM2VAL2		(IMXRT_FLEXPWM1.SM[2].VAL2)

  3991. #define FLEXPWM1_SM2FRACVAL3		(IMXRT_FLEXPWM1.SM[2].FRACVAL3)

  3992. #define FLEXPWM1_SM2VAL3		(IMXRT_FLEXPWM1.SM[2].VAL3)

  3993. #define FLEXPWM1_SM2FRACVAL4		(IMXRT_FLEXPWM1.SM[2].FRACVAL4)

  3994. #define FLEXPWM1_SM2VAL4		(IMXRT_FLEXPWM1.SM[2].VAL4)

  3995. #define FLEXPWM1_SM2FRACVAL5		(IMXRT_FLEXPWM1.SM[2].FRACVAL5)

  3996. #define FLEXPWM1_SM2VAL5		(IMXRT_FLEXPWM1.SM[2].VAL5)

  3997. #define FLEXPWM1_SM2FRCTRL		(IMXRT_FLEXPWM1.SM[2].FRCTRL)

  3998. #define FLEXPWM1_SM2OCTRL		(IMXRT_FLEXPWM1.SM[2].OCTRL)

  3999. #define FLEXPWM1_SM2STS			(IMXRT_FLEXPWM1.SM[2].STS)

  4000. #define FLEXPWM1_SM2INTEN		(IMXRT_FLEXPWM1.SM[2].INTEN)

  4001. #define FLEXPWM1_SM2DMAEN		(IMXRT_FLEXPWM1.SM[2].DMAEN)

  4002. #define FLEXPWM1_SM2TCTRL		(IMXRT_FLEXPWM1.SM[2].TCTRL)

  4003. #define FLEXPWM1_SM2DISMAP0		(IMXRT_FLEXPWM1.SM[2].DISMAP0)

  4004. #define FLEXPWM1_SM2DISMAP1		(IMXRT_FLEXPWM1.SM[2].DISMAP1)

  4005. #define FLEXPWM1_SM2DTCNT0		(IMXRT_FLEXPWM1.SM[2].DTCNT0)

  4006. #define FLEXPWM1_SM2DTCNT1		(IMXRT_FLEXPWM1.SM[2].DTCNT1)

  4007. #define FLEXPWM1_SM2CAPTCTRLA		(IMXRT_FLEXPWM1.SM[2].CAPTCTRLA)

  4008. #define FLEXPWM1_SM2CAPTCOMPA		(IMXRT_FLEXPWM1.SM[2].CAPTCOMPA)

  4009. #define FLEXPWM1_SM2CAPTCTRLB		(IMXRT_FLEXPWM1.SM[2].CAPTCTRLB)

  4010. #define FLEXPWM1_SM2CAPTCOMPB		(IMXRT_FLEXPWM1.SM[2].CAPTCOMPB)

  4011. #define FLEXPWM1_SM2CAPTCTRLX		(IMXRT_FLEXPWM1.SM[2].CAPTCTRLX)

  4012. #define FLEXPWM1_SM2CAPTCOMPX		(IMXRT_FLEXPWM1.SM[2].CAPTCOMPX)

  4013. #define FLEXPWM1_SM2CVAL0		(IMXRT_FLEXPWM1.SM[2].CVAL0)

  4014. #define FLEXPWM1_SM2CVAL0CYC		(IMXRT_FLEXPWM1.SM[2].CVAL0CYC)

  4015. #define FLEXPWM1_SM2CVAL1		(IMXRT_FLEXPWM1.SM[2].CVAL1)

  4016. #define FLEXPWM1_SM2CVAL1CYC		(IMXRT_FLEXPWM1.SM[2].CVAL1CYC)

  4017. #define FLEXPWM1_SM2CVAL2		(IMXRT_FLEXPWM1.SM[2].CVAL2)

  4018. #define FLEXPWM1_SM2CVAL2CYC		(IMXRT_FLEXPWM1.SM[2].CVAL2CYC)

  4019. #define FLEXPWM1_SM2CVAL3		(IMXRT_FLEXPWM1.SM[2].CVAL3)

  4020. #define FLEXPWM1_SM2CVAL3CYC		(IMXRT_FLEXPWM1.SM[2].CVAL3CYC)

  4021. #define FLEXPWM1_SM2CVAL4		(IMXRT_FLEXPWM1.SM[2].CVAL4)

  4022. #define FLEXPWM1_SM2CVAL4CYC		(IMXRT_FLEXPWM1.SM[2].CVAL4CYC)

  4023. #define FLEXPWM1_SM2CVAL5		(IMXRT_FLEXPWM1.SM[2].CVAL5)

  4024. #define FLEXPWM1_SM2CVAL5CYC		(IMXRT_FLEXPWM1.SM[2].CVAL5CYC)

  4025. #define FLEXPWM1_SM3CNT			(IMXRT_FLEXPWM1.SM[3].CNT)

  4026. #define FLEXPWM1_SM3INIT		(IMXRT_FLEXPWM1.SM[3].INIT)

  4027. #define FLEXPWM1_SM3CTRL2		(IMXRT_FLEXPWM1.SM[3].CTRL2)

  4028. #define FLEXPWM1_SM3CTRL		(IMXRT_FLEXPWM1.SM[3].CTRL)

  4029. #define FLEXPWM1_SM3VAL0		(IMXRT_FLEXPWM1.SM[3].VAL0)

  4030. #define FLEXPWM1_SM3FRACVAL1		(IMXRT_FLEXPWM1.SM[3].FRACVAL1)

  4031. #define FLEXPWM1_SM3VAL1		(IMXRT_FLEXPWM1.SM[3].VAL1)

  4032. #define FLEXPWM1_SM3FRACVAL2		(IMXRT_FLEXPWM1.SM[3].FRACVAL2)

  4033. #define FLEXPWM1_SM3VAL2		(IMXRT_FLEXPWM1.SM[3].VAL2)

  4034. #define FLEXPWM1_SM3FRACVAL3		(IMXRT_FLEXPWM1.SM[3].FRACVAL3)

  4035. #define FLEXPWM1_SM3VAL3		(IMXRT_FLEXPWM1.SM[3].VAL3)

  4036. #define FLEXPWM1_SM3FRACVAL4		(IMXRT_FLEXPWM1.SM[3].FRACVAL4)

  4037. #define FLEXPWM1_SM3VAL4		(IMXRT_FLEXPWM1.SM[3].VAL4)

  4038. #define FLEXPWM1_SM3FRACVAL5		(IMXRT_FLEXPWM1.SM[3].FRACVAL5)

  4039. #define FLEXPWM1_SM3VAL5		(IMXRT_FLEXPWM1.SM[3].VAL5)

  4040. #define FLEXPWM1_SM3FRCTRL		(IMXRT_FLEXPWM1.SM[3].FRCTRL)

  4041. #define FLEXPWM1_SM3OCTRL		(IMXRT_FLEXPWM1.SM[3].OCTRL)

  4042. #define FLEXPWM1_SM3STS			(IMXRT_FLEXPWM1.SM[3].STS)

  4043. #define FLEXPWM1_SM3INTEN		(IMXRT_FLEXPWM1.SM[3].INTEN)

  4044. #define FLEXPWM1_SM3DMAEN		(IMXRT_FLEXPWM1.SM[3].DMAEN)

  4045. #define FLEXPWM1_SM3TCTRL		(IMXRT_FLEXPWM1.SM[3].TCTRL)

  4046. #define FLEXPWM1_SM3DISMAP0		(IMXRT_FLEXPWM1.SM[3].DISMAP0)

  4047. #define FLEXPWM1_SM3DISMAP1		(IMXRT_FLEXPWM1.SM[3].DISMAP1)

  4048. #define FLEXPWM1_SM3DTCNT0		(IMXRT_FLEXPWM1.SM[3].DTCNT0)

  4049. #define FLEXPWM1_SM3DTCNT1		(IMXRT_FLEXPWM1.SM[3].DTCNT1)

  4050. #define FLEXPWM1_SM3CAPTCTRLA		(IMXRT_FLEXPWM1.SM[3].CAPTCTRLA)

  4051. #define FLEXPWM1_SM3CAPTCOMPA		(IMXRT_FLEXPWM1.SM[3].CAPTCOMPA)

  4052. #define FLEXPWM1_SM3CAPTCTRLB		(IMXRT_FLEXPWM1.SM[3].CAPTCTRLB)

  4053. #define FLEXPWM1_SM3CAPTCOMPB		(IMXRT_FLEXPWM1.SM[3].CAPTCOMPB)

  4054. #define FLEXPWM1_SM3CAPTCTRLX		(IMXRT_FLEXPWM1.SM[3].CAPTCTRLX)

  4055. #define FLEXPWM1_SM3CAPTCOMPX		(IMXRT_FLEXPWM1.SM[3].CAPTCOMPX)

  4056. #define FLEXPWM1_SM3CVAL0		(IMXRT_FLEXPWM1.SM[3].CVAL0)

  4057. #define FLEXPWM1_SM3CVAL0CYC		(IMXRT_FLEXPWM1.SM[3].CVAL0CYC)

  4058. #define FLEXPWM1_SM3CVAL1		(IMXRT_FLEXPWM1.SM[3].CVAL1)

  4059. #define FLEXPWM1_SM3CVAL1CYC		(IMXRT_FLEXPWM1.SM[3].CVAL1CYC)

  4060. #define FLEXPWM1_SM3CVAL2		(IMXRT_FLEXPWM1.SM[3].CVAL2)

  4061. #define FLEXPWM1_SM3CVAL2CYC		(IMXRT_FLEXPWM1.SM[3].CVAL2CYC)

  4062. #define FLEXPWM1_SM3CVAL3		(IMXRT_FLEXPWM1.SM[3].CVAL3)

  4063. #define FLEXPWM1_SM3CVAL3CYC		(IMXRT_FLEXPWM1.SM[3].CVAL3CYC)

  4064. #define FLEXPWM1_SM3CVAL4		(IMXRT_FLEXPWM1.SM[3].CVAL4)

  4065. #define FLEXPWM1_SM3CVAL4CYC		(IMXRT_FLEXPWM1.SM[3].CVAL4CYC)

  4066. #define FLEXPWM1_SM3CVAL5		(IMXRT_FLEXPWM1.SM[3].CVAL5)

  4067. #define FLEXPWM1_SM3CVAL5CYC		(IMXRT_FLEXPWM1.SM[3].CVAL5CYC)

  4068. #define FLEXPWM1_OUTEN			(IMXRT_FLEXPWM1.OUTEN)

  4069. #define FLEXPWM1_MASK			(IMXRT_FLEXPWM1.MASK)

  4070. #define FLEXPWM1_SWCOUT			(IMXRT_FLEXPWM1.SWCOUT)

  4071. #define FLEXPWM1_DTSRCSEL		(IMXRT_FLEXPWM1.DTSRCSEL)

  4072. #define FLEXPWM1_MCTRL			(IMXRT_FLEXPWM1.MCTRL)

  4073. #define FLEXPWM1_MCTRL2			(IMXRT_FLEXPWM1.MCTRL2)

  4074. #define FLEXPWM1_FCTRL0			(IMXRT_FLEXPWM1.FCTRL0)

  4075. #define FLEXPWM1_FSTS0			(IMXRT_FLEXPWM1.FSTS0)

  4076. #define FLEXPWM1_FFILT0			(IMXRT_FLEXPWM1.FFILT0)

  4077. #define FLEXPWM1_FTST0			(IMXRT_FLEXPWM1.FTST0)

  4078. #define FLEXPWM1_FCTRL20		(IMXRT_FLEXPWM1.FCTRL20)

  4079. #define FLEXPWM2_SM0CNT			(IMXRT_FLEXPWM2.SM[0].CNT)

  4080. #define FLEXPWM2_SM0INIT		(IMXRT_FLEXPWM2.SM[0].INIT)

  4081. #define FLEXPWM2_SM0CTRL2		(IMXRT_FLEXPWM2.SM[0].CTRL2)

  4082. #define FLEXPWM2_SM0CTRL		(IMXRT_FLEXPWM2.SM[0].CTRL)

  4083. #define FLEXPWM2_SM0VAL0		(IMXRT_FLEXPWM2.SM[0].VAL0)

  4084. #define FLEXPWM2_SM0FRACVAL1		(IMXRT_FLEXPWM2.SM[0].FRACVAL1)

  4085. #define FLEXPWM2_SM0VAL1		(IMXRT_FLEXPWM2.SM[0].VAL1)

  4086. #define FLEXPWM2_SM0FRACVAL2		(IMXRT_FLEXPWM2.SM[0].FRACVAL2)

  4087. #define FLEXPWM2_SM0VAL2		(IMXRT_FLEXPWM2.SM[0].VAL2)

  4088. #define FLEXPWM2_SM0FRACVAL3		(IMXRT_FLEXPWM2.SM[0].FRACVAL3)

  4089. #define FLEXPWM2_SM0VAL3		(IMXRT_FLEXPWM2.SM[0].VAL3)

  4090. #define FLEXPWM2_SM0FRACVAL4		(IMXRT_FLEXPWM2.SM[0].FRACVAL4)

  4091. #define FLEXPWM2_SM0VAL4		(IMXRT_FLEXPWM2.SM[0].VAL4)

  4092. #define FLEXPWM2_SM0FRACVAL5		(IMXRT_FLEXPWM2.SM[0].FRACVAL5)

  4093. #define FLEXPWM2_SM0VAL5		(IMXRT_FLEXPWM2.SM[0].VAL5)

  4094. #define FLEXPWM2_SM0FRCTRL		(IMXRT_FLEXPWM2.SM[0].FRCTRL)

  4095. #define FLEXPWM2_SM0OCTRL		(IMXRT_FLEXPWM2.SM[0].OCTRL)

  4096. #define FLEXPWM2_SM0STS			(IMXRT_FLEXPWM2.SM[0].STS)

  4097. #define FLEXPWM2_SM0INTEN		(IMXRT_FLEXPWM2.SM[0].INTEN)

  4098. #define FLEXPWM2_SM0DMAEN		(IMXRT_FLEXPWM2.SM[0].DMAEN)

  4099. #define FLEXPWM2_SM0TCTRL		(IMXRT_FLEXPWM2.SM[0].TCTRL)

  4100. #define FLEXPWM2_SM0DISMAP0		(IMXRT_FLEXPWM2.SM[0].DISMAP0)

  4101. #define FLEXPWM2_SM0DISMAP1		(IMXRT_FLEXPWM2.SM[0].DISMAP1)

  4102. #define FLEXPWM2_SM0DTCNT0		(IMXRT_FLEXPWM2.SM[0].DTCNT0)

  4103. #define FLEXPWM2_SM0DTCNT1		(IMXRT_FLEXPWM2.SM[0].DTCNT1)

  4104. #define FLEXPWM2_SM0CAPTCTRLA		(IMXRT_FLEXPWM2.SM[0].CAPTCTRLA)

  4105. #define FLEXPWM2_SM0CAPTCOMPA		(IMXRT_FLEXPWM2.SM[0].CAPTCOMPA)

  4106. #define FLEXPWM2_SM0CAPTCTRLB		(IMXRT_FLEXPWM2.SM[0].CAPTCTRLB)

  4107. #define FLEXPWM2_SM0CAPTCOMPB		(IMXRT_FLEXPWM2.SM[0].CAPTCOMPB)

  4108. #define FLEXPWM2_SM0CAPTCTRLX		(IMXRT_FLEXPWM2.SM[0].CAPTCTRLX)

  4109. #define FLEXPWM2_SM0CAPTCOMPX		(IMXRT_FLEXPWM2.SM[0].CAPTCOMPX)

  4110. #define FLEXPWM2_SM0CVAL0		(IMXRT_FLEXPWM2.SM[0].CVAL0)

  4111. #define FLEXPWM2_SM0CVAL0CYC		(IMXRT_FLEXPWM2.SM[0].CVAL0CYC)

  4112. #define FLEXPWM2_SM0CVAL1		(IMXRT_FLEXPWM2.SM[0].CVAL1)

  4113. #define FLEXPWM2_SM0CVAL1CYC		(IMXRT_FLEXPWM2.SM[0].CVAL1CYC)

  4114. #define FLEXPWM2_SM0CVAL2		(IMXRT_FLEXPWM2.SM[0].CVAL2)

  4115. #define FLEXPWM2_SM0CVAL2CYC		(IMXRT_FLEXPWM2.SM[0].CVAL2CYC)

  4116. #define FLEXPWM2_SM0CVAL3		(IMXRT_FLEXPWM2.SM[0].CVAL3)

  4117. #define FLEXPWM2_SM0CVAL3CYC		(IMXRT_FLEXPWM2.SM[0].CVAL3CYC)

  4118. #define FLEXPWM2_SM0CVAL4		(IMXRT_FLEXPWM2.SM[0].CVAL4)

  4119. #define FLEXPWM2_SM0CVAL4CYC		(IMXRT_FLEXPWM2.SM[0].CVAL4CYC)

  4120. #define FLEXPWM2_SM0CVAL5		(IMXRT_FLEXPWM2.SM[0].CVAL5)

  4121. #define FLEXPWM2_SM0CVAL5CYC		(IMXRT_FLEXPWM2.SM[0].CVAL5CYC)

  4122. #define FLEXPWM2_SM1CNT			(IMXRT_FLEXPWM2.SM[1].CNT)

  4123. #define FLEXPWM2_SM1INIT		(IMXRT_FLEXPWM2.SM[1].INIT)

  4124. #define FLEXPWM2_SM1CTRL2		(IMXRT_FLEXPWM2.SM[1].CTRL2)

  4125. #define FLEXPWM2_SM1CTRL		(IMXRT_FLEXPWM2.SM[1].CTRL)

  4126. #define FLEXPWM2_SM1VAL0		(IMXRT_FLEXPWM2.SM[1].VAL0)

  4127. #define FLEXPWM2_SM1FRACVAL1		(IMXRT_FLEXPWM2.SM[1].FRACVAL1)

  4128. #define FLEXPWM2_SM1VAL1		(IMXRT_FLEXPWM2.SM[1].VAL1)

  4129. #define FLEXPWM2_SM1FRACVAL2		(IMXRT_FLEXPWM2.SM[1].FRACVAL2)

  4130. #define FLEXPWM2_SM1VAL2		(IMXRT_FLEXPWM2.SM[1].VAL2)

  4131. #define FLEXPWM2_SM1FRACVAL3		(IMXRT_FLEXPWM2.SM[1].FRACVAL3)

  4132. #define FLEXPWM2_SM1VAL3		(IMXRT_FLEXPWM2.SM[1].VAL3)

  4133. #define FLEXPWM2_SM1FRACVAL4		(IMXRT_FLEXPWM2.SM[1].FRACVAL4)

  4134. #define FLEXPWM2_SM1VAL4		(IMXRT_FLEXPWM2.SM[1].VAL4)

  4135. #define FLEXPWM2_SM1FRACVAL5		(IMXRT_FLEXPWM2.SM[1].FRACVAL5)

  4136. #define FLEXPWM2_SM1VAL5		(IMXRT_FLEXPWM2.SM[1].VAL5)

  4137. #define FLEXPWM2_SM1FRCTRL		(IMXRT_FLEXPWM2.SM[1].FRCTRL)

  4138. #define FLEXPWM2_SM1OCTRL		(IMXRT_FLEXPWM2.SM[1].OCTRL)

  4139. #define FLEXPWM2_SM1STS			(IMXRT_FLEXPWM2.SM[1].STS)

  4140. #define FLEXPWM2_SM1INTEN		(IMXRT_FLEXPWM2.SM[1].INTEN)

  4141. #define FLEXPWM2_SM1DMAEN		(IMXRT_FLEXPWM2.SM[1].DMAEN)

  4142. #define FLEXPWM2_SM1TCTRL		(IMXRT_FLEXPWM2.SM[1].TCTRL)

  4143. #define FLEXPWM2_SM1DISMAP0		(IMXRT_FLEXPWM2.SM[1].DISMAP0)

  4144. #define FLEXPWM2_SM1DISMAP1		(IMXRT_FLEXPWM2.SM[1].DISMAP1)

  4145. #define FLEXPWM2_SM1DTCNT0		(IMXRT_FLEXPWM2.SM[1].DTCNT0)

  4146. #define FLEXPWM2_SM1DTCNT1		(IMXRT_FLEXPWM2.SM[1].DTCNT1)

  4147. #define FLEXPWM2_SM1CAPTCTRLA		(IMXRT_FLEXPWM2.SM[1].CAPTCTRLA)

  4148. #define FLEXPWM2_SM1CAPTCOMPA		(IMXRT_FLEXPWM2.SM[1].CAPTCOMPA)

  4149. #define FLEXPWM2_SM1CAPTCTRLB		(IMXRT_FLEXPWM2.SM[1].CAPTCTRLB)

  4150. #define FLEXPWM2_SM1CAPTCOMPB		(IMXRT_FLEXPWM2.SM[1].CAPTCOMPB)

  4151. #define FLEXPWM2_SM1CAPTCTRLX		(IMXRT_FLEXPWM2.SM[1].CAPTCTRLX)

  4152. #define FLEXPWM2_SM1CAPTCOMPX		(IMXRT_FLEXPWM2.SM[1].CAPTCOMPX)

  4153. #define FLEXPWM2_SM1CVAL0		(IMXRT_FLEXPWM2.SM[1].CVAL0)

  4154. #define FLEXPWM2_SM1CVAL0CYC		(IMXRT_FLEXPWM2.SM[1].CVAL0CYC)

  4155. #define FLEXPWM2_SM1CVAL1		(IMXRT_FLEXPWM2.SM[1].CVAL1)

  4156. #define FLEXPWM2_SM1CVAL1CYC		(IMXRT_FLEXPWM2.SM[1].CVAL1CYC)

  4157. #define FLEXPWM2_SM1CVAL2		(IMXRT_FLEXPWM2.SM[1].CVAL2)

  4158. #define FLEXPWM2_SM1CVAL2CYC		(IMXRT_FLEXPWM2.SM[1].CVAL2CYC)

  4159. #define FLEXPWM2_SM1CVAL3		(IMXRT_FLEXPWM2.SM[1].CVAL3)

  4160. #define FLEXPWM2_SM1CVAL3CYC		(IMXRT_FLEXPWM2.SM[1].CVAL3CYC)

  4161. #define FLEXPWM2_SM1CVAL4		(IMXRT_FLEXPWM2.SM[1].CVAL4)

  4162. #define FLEXPWM2_SM1CVAL4CYC		(IMXRT_FLEXPWM2.SM[1].CVAL4CYC)

  4163. #define FLEXPWM2_SM1CVAL5		(IMXRT_FLEXPWM2.SM[1].CVAL5)

  4164. #define FLEXPWM2_SM1CVAL5CYC		(IMXRT_FLEXPWM2.SM[1].CVAL5CYC)

  4165. #define FLEXPWM2_SM2CNT			(IMXRT_FLEXPWM2.SM[2].CNT)

  4166. #define FLEXPWM2_SM2INIT		(IMXRT_FLEXPWM2.SM[2].INIT)

  4167. #define FLEXPWM2_SM2CTRL2		(IMXRT_FLEXPWM2.SM[2].CTRL2)

  4168. #define FLEXPWM2_SM2CTRL		(IMXRT_FLEXPWM2.SM[2].CTRL)

  4169. #define FLEXPWM2_SM2VAL0		(IMXRT_FLEXPWM2.SM[2].VAL0)

  4170. #define FLEXPWM2_SM2FRACVAL1		(IMXRT_FLEXPWM2.SM[2].FRACVAL1)

  4171. #define FLEXPWM2_SM2VAL1		(IMXRT_FLEXPWM2.SM[2].VAL1)

  4172. #define FLEXPWM2_SM2FRACVAL2		(IMXRT_FLEXPWM2.SM[2].FRACVAL2)

  4173. #define FLEXPWM2_SM2VAL2		(IMXRT_FLEXPWM2.SM[2].VAL2)

  4174. #define FLEXPWM2_SM2FRACVAL3		(IMXRT_FLEXPWM2.SM[2].FRACVAL3)

  4175. #define FLEXPWM2_SM2VAL3		(IMXRT_FLEXPWM2.SM[2].VAL3)

  4176. #define FLEXPWM2_SM2FRACVAL4		(IMXRT_FLEXPWM2.SM[2].FRACVAL4)

  4177. #define FLEXPWM2_SM2VAL4		(IMXRT_FLEXPWM2.SM[2].VAL4)

  4178. #define FLEXPWM2_SM2FRACVAL5		(IMXRT_FLEXPWM2.SM[2].FRACVAL5)

  4179. #define FLEXPWM2_SM2VAL5		(IMXRT_FLEXPWM2.SM[2].VAL5)

  4180. #define FLEXPWM2_SM2FRCTRL		(IMXRT_FLEXPWM2.SM[2].FRCTRL)

  4181. #define FLEXPWM2_SM2OCTRL		(IMXRT_FLEXPWM2.SM[2].OCTRL)

  4182. #define FLEXPWM2_SM2STS			(IMXRT_FLEXPWM2.SM[2].STS)

  4183. #define FLEXPWM2_SM2INTEN		(IMXRT_FLEXPWM2.SM[2].INTEN)

  4184. #define FLEXPWM2_SM2DMAEN		(IMXRT_FLEXPWM2.SM[2].DMAEN)

  4185. #define FLEXPWM2_SM2TCTRL		(IMXRT_FLEXPWM2.SM[2].TCTRL)

  4186. #define FLEXPWM2_SM2DISMAP0		(IMXRT_FLEXPWM2.SM[2].DISMAP0)

  4187. #define FLEXPWM2_SM2DISMAP1		(IMXRT_FLEXPWM2.SM[2].DISMAP1)

  4188. #define FLEXPWM2_SM2DTCNT0		(IMXRT_FLEXPWM2.SM[2].DTCNT0)

  4189. #define FLEXPWM2_SM2DTCNT1		(IMXRT_FLEXPWM2.SM[2].DTCNT1)

  4190. #define FLEXPWM2_SM2CAPTCTRLA		(IMXRT_FLEXPWM2.SM[2].CAPTCTRLA)

  4191. #define FLEXPWM2_SM2CAPTCOMPA		(IMXRT_FLEXPWM2.SM[2].CAPTCOMPA)

  4192. #define FLEXPWM2_SM2CAPTCTRLB		(IMXRT_FLEXPWM2.SM[2].CAPTCTRLB)

  4193. #define FLEXPWM2_SM2CAPTCOMPB		(IMXRT_FLEXPWM2.SM[2].CAPTCOMPB)

  4194. #define FLEXPWM2_SM2CAPTCTRLX		(IMXRT_FLEXPWM2.SM[2].CAPTCTRLX)

  4195. #define FLEXPWM2_SM2CAPTCOMPX		(IMXRT_FLEXPWM2.SM[2].CAPTCOMPX)

  4196. #define FLEXPWM2_SM2CVAL0		(IMXRT_FLEXPWM2.SM[2].CVAL0)

  4197. #define FLEXPWM2_SM2CVAL0CYC		(IMXRT_FLEXPWM2.SM[2].CVAL0CYC)

  4198. #define FLEXPWM2_SM2CVAL1		(IMXRT_FLEXPWM2.SM[2].CVAL1)

  4199. #define FLEXPWM2_SM2CVAL1CYC		(IMXRT_FLEXPWM2.SM[2].CVAL1CYC)

  4200. #define FLEXPWM2_SM2CVAL2		(IMXRT_FLEXPWM2.SM[2].CVAL2)

  4201. #define FLEXPWM2_SM2CVAL2CYC		(IMXRT_FLEXPWM2.SM[2].CVAL2CYC)

  4202. #define FLEXPWM2_SM2CVAL3		(IMXRT_FLEXPWM2.SM[2].CVAL3)

  4203. #define FLEXPWM2_SM2CVAL3CYC		(IMXRT_FLEXPWM2.SM[2].CVAL3CYC)

  4204. #define FLEXPWM2_SM2CVAL4		(IMXRT_FLEXPWM2.SM[2].CVAL4)

  4205. #define FLEXPWM2_SM2CVAL4CYC		(IMXRT_FLEXPWM2.SM[2].CVAL4CYC)

  4206. #define FLEXPWM2_SM2CVAL5		(IMXRT_FLEXPWM2.SM[2].CVAL5)

  4207. #define FLEXPWM2_SM2CVAL5CYC		(IMXRT_FLEXPWM2.SM[2].CVAL5CYC)

  4208. #define FLEXPWM2_SM3CNT			(IMXRT_FLEXPWM2.SM[3].CNT)

  4209. #define FLEXPWM2_SM3INIT		(IMXRT_FLEXPWM2.SM[3].INIT)

  4210. #define FLEXPWM2_SM3CTRL2		(IMXRT_FLEXPWM2.SM[3].CTRL2)

  4211. #define FLEXPWM2_SM3CTRL		(IMXRT_FLEXPWM2.SM[3].CTRL)

  4212. #define FLEXPWM2_SM3VAL0		(IMXRT_FLEXPWM2.SM[3].VAL0)

  4213. #define FLEXPWM2_SM3FRACVAL1		(IMXRT_FLEXPWM2.SM[3].FRACVAL1)

  4214. #define FLEXPWM2_SM3VAL1		(IMXRT_FLEXPWM2.SM[3].VAL1)

  4215. #define FLEXPWM2_SM3FRACVAL2		(IMXRT_FLEXPWM2.SM[3].FRACVAL2)

  4216. #define FLEXPWM2_SM3VAL2		(IMXRT_FLEXPWM2.SM[3].VAL2)

  4217. #define FLEXPWM2_SM3FRACVAL3		(IMXRT_FLEXPWM2.SM[3].FRACVAL3)

  4218. #define FLEXPWM2_SM3VAL3		(IMXRT_FLEXPWM2.SM[3].VAL3)

  4219. #define FLEXPWM2_SM3FRACVAL4		(IMXRT_FLEXPWM2.SM[3].FRACVAL4)

  4220. #define FLEXPWM2_SM3VAL4		(IMXRT_FLEXPWM2.SM[3].VAL4)

  4221. #define FLEXPWM2_SM3FRACVAL5		(IMXRT_FLEXPWM2.SM[3].FRACVAL5)

  4222. #define FLEXPWM2_SM3VAL5		(IMXRT_FLEXPWM2.SM[3].VAL5)

  4223. #define FLEXPWM2_SM3FRCTRL		(IMXRT_FLEXPWM2.SM[3].FRCTRL)

  4224. #define FLEXPWM2_SM3OCTRL		(IMXRT_FLEXPWM2.SM[3].OCTRL)

  4225. #define FLEXPWM2_SM3STS			(IMXRT_FLEXPWM2.SM[3].STS)

  4226. #define FLEXPWM2_SM3INTEN		(IMXRT_FLEXPWM2.SM[3].INTEN)

  4227. #define FLEXPWM2_SM3DMAEN		(IMXRT_FLEXPWM2.SM[3].DMAEN)

  4228. #define FLEXPWM2_SM3TCTRL		(IMXRT_FLEXPWM2.SM[3].TCTRL)

  4229. #define FLEXPWM2_SM3DISMAP0		(IMXRT_FLEXPWM2.SM[3].DISMAP0)

  4230. #define FLEXPWM2_SM3DISMAP1		(IMXRT_FLEXPWM2.SM[3].DISMAP1)

  4231. #define FLEXPWM2_SM3DTCNT0		(IMXRT_FLEXPWM2.SM[3].DTCNT0)

  4232. #define FLEXPWM2_SM3DTCNT1		(IMXRT_FLEXPWM2.SM[3].DTCNT1)

  4233. #define FLEXPWM2_SM3CAPTCTRLA		(IMXRT_FLEXPWM2.SM[3].CAPTCTRLA)

  4234. #define FLEXPWM2_SM3CAPTCOMPA		(IMXRT_FLEXPWM2.SM[3].CAPTCOMPA)

  4235. #define FLEXPWM2_SM3CAPTCTRLB		(IMXRT_FLEXPWM2.SM[3].CAPTCTRLB)

  4236. #define FLEXPWM2_SM3CAPTCOMPB		(IMXRT_FLEXPWM2.SM[3].CAPTCOMPB)

  4237. #define FLEXPWM2_SM3CAPTCTRLX		(IMXRT_FLEXPWM2.SM[3].CAPTCTRLX)

  4238. #define FLEXPWM2_SM3CAPTCOMPX		(IMXRT_FLEXPWM2.SM[3].CAPTCOMPX)

  4239. #define FLEXPWM2_SM3CVAL0		(IMXRT_FLEXPWM2.SM[3].CVAL0)

  4240. #define FLEXPWM2_SM3CVAL0CYC		(IMXRT_FLEXPWM2.SM[3].CVAL0CYC)

  4241. #define FLEXPWM2_SM3CVAL1		(IMXRT_FLEXPWM2.SM[3].CVAL1)

  4242. #define FLEXPWM2_SM3CVAL1CYC		(IMXRT_FLEXPWM2.SM[3].CVAL1CYC)

  4243. #define FLEXPWM2_SM3CVAL2		(IMXRT_FLEXPWM2.SM[3].CVAL2)

  4244. #define FLEXPWM2_SM3CVAL2CYC		(IMXRT_FLEXPWM2.SM[3].CVAL2CYC)

  4245. #define FLEXPWM2_SM3CVAL3		(IMXRT_FLEXPWM2.SM[3].CVAL3)

  4246. #define FLEXPWM2_SM3CVAL3CYC		(IMXRT_FLEXPWM2.SM[3].CVAL3CYC)

  4247. #define FLEXPWM2_SM3CVAL4		(IMXRT_FLEXPWM2.SM[3].CVAL4)

  4248. #define FLEXPWM2_SM3CVAL4CYC		(IMXRT_FLEXPWM2.SM[3].CVAL4CYC)

  4249. #define FLEXPWM2_SM3CVAL5		(IMXRT_FLEXPWM2.SM[3].CVAL5)

  4250. #define FLEXPWM2_SM3CVAL5CYC		(IMXRT_FLEXPWM2.SM[3].CVAL5CYC)

  4251. #define FLEXPWM2_OUTEN			(IMXRT_FLEXPWM2.OUTEN)

  4252. #define FLEXPWM2_MASK			(IMXRT_FLEXPWM2.MASK)

  4253. #define FLEXPWM2_SWCOUT			(IMXRT_FLEXPWM2.SWCOUT)

  4254. #define FLEXPWM2_DTSRCSEL		(IMXRT_FLEXPWM2.DTSRCSEL)

  4255. #define FLEXPWM2_MCTRL			(IMXRT_FLEXPWM2.MCTRL)

  4256. #define FLEXPWM2_MCTRL2			(IMXRT_FLEXPWM2.MCTRL2)

  4257. #define FLEXPWM2_FCTRL0			(IMXRT_FLEXPWM2.FCTRL0)

  4258. #define FLEXPWM2_FSTS0			(IMXRT_FLEXPWM2.FSTS0)

  4259. #define FLEXPWM2_FFILT0			(IMXRT_FLEXPWM2.FFILT0)

  4260. #define FLEXPWM2_FTST0			(IMXRT_FLEXPWM2.FTST0)

  4261. #define FLEXPWM2_FCTRL20		(IMXRT_FLEXPWM2.FCTRL20)

  4262. #define FLEXPWM3_SM0CNT			(IMXRT_FLEXPWM3.SM[0].CNT)

  4263. #define FLEXPWM3_SM0INIT		(IMXRT_FLEXPWM3.SM[0].INIT)

  4264. #define FLEXPWM3_SM0CTRL2		(IMXRT_FLEXPWM3.SM[0].CTRL2)

  4265. #define FLEXPWM3_SM0CTRL		(IMXRT_FLEXPWM3.SM[0].CTRL)

  4266. #define FLEXPWM3_SM0VAL0		(IMXRT_FLEXPWM3.SM[0].VAL0)

  4267. #define FLEXPWM3_SM0FRACVAL1		(IMXRT_FLEXPWM3.SM[0].FRACVAL1)

  4268. #define FLEXPWM3_SM0VAL1		(IMXRT_FLEXPWM3.SM[0].VAL1)

  4269. #define FLEXPWM3_SM0FRACVAL2		(IMXRT_FLEXPWM3.SM[0].FRACVAL2)

  4270. #define FLEXPWM3_SM0VAL2		(IMXRT_FLEXPWM3.SM[0].VAL2)

  4271. #define FLEXPWM3_SM0FRACVAL3		(IMXRT_FLEXPWM3.SM[0].FRACVAL3)

  4272. #define FLEXPWM3_SM0VAL3		(IMXRT_FLEXPWM3.SM[0].VAL3)

  4273. #define FLEXPWM3_SM0FRACVAL4		(IMXRT_FLEXPWM3.SM[0].FRACVAL4)

  4274. #define FLEXPWM3_SM0VAL4		(IMXRT_FLEXPWM3.SM[0].VAL4)

  4275. #define FLEXPWM3_SM0FRACVAL5		(IMXRT_FLEXPWM3.SM[0].FRACVAL5)

  4276. #define FLEXPWM3_SM0VAL5		(IMXRT_FLEXPWM3.SM[0].VAL5)

  4277. #define FLEXPWM3_SM0FRCTRL		(IMXRT_FLEXPWM3.SM[0].FRCTRL)

  4278. #define FLEXPWM3_SM0OCTRL		(IMXRT_FLEXPWM3.SM[0].OCTRL)

  4279. #define FLEXPWM3_SM0STS			(IMXRT_FLEXPWM3.SM[0].STS)

  4280. #define FLEXPWM3_SM0INTEN		(IMXRT_FLEXPWM3.SM[0].INTEN)

  4281. #define FLEXPWM3_SM0DMAEN		(IMXRT_FLEXPWM3.SM[0].DMAEN)

  4282. #define FLEXPWM3_SM0TCTRL		(IMXRT_FLEXPWM3.SM[0].TCTRL)

  4283. #define FLEXPWM3_SM0DISMAP0		(IMXRT_FLEXPWM3.SM[0].DISMAP0)

  4284. #define FLEXPWM3_SM0DISMAP1		(IMXRT_FLEXPWM3.SM[0].DISMAP1)

  4285. #define FLEXPWM3_SM0DTCNT0		(IMXRT_FLEXPWM3.SM[0].DTCNT0)

  4286. #define FLEXPWM3_SM0DTCNT1		(IMXRT_FLEXPWM3.SM[0].DTCNT1)

  4287. #define FLEXPWM3_SM0CAPTCTRLA		(IMXRT_FLEXPWM3.SM[0].CAPTCTRLA)

  4288. #define FLEXPWM3_SM0CAPTCOMPA		(IMXRT_FLEXPWM3.SM[0].CAPTCOMPA)

  4289. #define FLEXPWM3_SM0CAPTCTRLB		(IMXRT_FLEXPWM3.SM[0].CAPTCTRLB)

  4290. #define FLEXPWM3_SM0CAPTCOMPB		(IMXRT_FLEXPWM3.SM[0].CAPTCOMPB)

  4291. #define FLEXPWM3_SM0CAPTCTRLX		(IMXRT_FLEXPWM3.SM[0].CAPTCTRLX)

  4292. #define FLEXPWM3_SM0CAPTCOMPX		(IMXRT_FLEXPWM3.SM[0].CAPTCOMPX)

  4293. #define FLEXPWM3_SM0CVAL0		(IMXRT_FLEXPWM3.SM[0].CVAL0)

  4294. #define FLEXPWM3_SM0CVAL0CYC		(IMXRT_FLEXPWM3.SM[0].CVAL0CYC)

  4295. #define FLEXPWM3_SM0CVAL1		(IMXRT_FLEXPWM3.SM[0].CVAL1)

  4296. #define FLEXPWM3_SM0CVAL1CYC		(IMXRT_FLEXPWM3.SM[0].CVAL1CYC)

  4297. #define FLEXPWM3_SM0CVAL2		(IMXRT_FLEXPWM3.SM[0].CVAL2)

  4298. #define FLEXPWM3_SM0CVAL2CYC		(IMXRT_FLEXPWM3.SM[0].CVAL2CYC)

  4299. #define FLEXPWM3_SM0CVAL3		(IMXRT_FLEXPWM3.SM[0].CVAL3)

  4300. #define FLEXPWM3_SM0CVAL3CYC		(IMXRT_FLEXPWM3.SM[0].CVAL3CYC)

  4301. #define FLEXPWM3_SM0CVAL4		(IMXRT_FLEXPWM3.SM[0].CVAL4)

  4302. #define FLEXPWM3_SM0CVAL4CYC		(IMXRT_FLEXPWM3.SM[0].CVAL4CYC)

  4303. #define FLEXPWM3_SM0CVAL5		(IMXRT_FLEXPWM3.SM[0].CVAL5)

  4304. #define FLEXPWM3_SM0CVAL5CYC		(IMXRT_FLEXPWM3.SM[0].CVAL5CYC)

  4305. #define FLEXPWM3_SM1CNT			(IMXRT_FLEXPWM3.SM[1].CNT)

  4306. #define FLEXPWM3_SM1INIT		(IMXRT_FLEXPWM3.SM[1].INIT)

  4307. #define FLEXPWM3_SM1CTRL2		(IMXRT_FLEXPWM3.SM[1].CTRL2)

  4308. #define FLEXPWM3_SM1CTRL		(IMXRT_FLEXPWM3.SM[1].CTRL)

  4309. #define FLEXPWM3_SM1VAL0		(IMXRT_FLEXPWM3.SM[1].VAL0)

  4310. #define FLEXPWM3_SM1FRACVAL1		(IMXRT_FLEXPWM3.SM[1].FRACVAL1)

  4311. #define FLEXPWM3_SM1VAL1		(IMXRT_FLEXPWM3.SM[1].VAL1)

  4312. #define FLEXPWM3_SM1FRACVAL2		(IMXRT_FLEXPWM3.SM[1].FRACVAL2)

  4313. #define FLEXPWM3_SM1VAL2		(IMXRT_FLEXPWM3.SM[1].VAL2)

  4314. #define FLEXPWM3_SM1FRACVAL3		(IMXRT_FLEXPWM3.SM[1].FRACVAL3)

  4315. #define FLEXPWM3_SM1VAL3		(IMXRT_FLEXPWM3.SM[1].VAL3)

  4316. #define FLEXPWM3_SM1FRACVAL4		(IMXRT_FLEXPWM3.SM[1].FRACVAL4)

  4317. #define FLEXPWM3_SM1VAL4		(IMXRT_FLEXPWM3.SM[1].VAL4)

  4318. #define FLEXPWM3_SM1FRACVAL5		(IMXRT_FLEXPWM3.SM[1].FRACVAL5)

  4319. #define FLEXPWM3_SM1VAL5		(IMXRT_FLEXPWM3.SM[1].VAL5)

  4320. #define FLEXPWM3_SM1FRCTRL		(IMXRT_FLEXPWM3.SM[1].FRCTRL)

  4321. #define FLEXPWM3_SM1OCTRL		(IMXRT_FLEXPWM3.SM[1].OCTRL)

  4322. #define FLEXPWM3_SM1STS			(IMXRT_FLEXPWM3.SM[1].STS)

  4323. #define FLEXPWM3_SM1INTEN		(IMXRT_FLEXPWM3.SM[1].INTEN)

  4324. #define FLEXPWM3_SM1DMAEN		(IMXRT_FLEXPWM3.SM[1].DMAEN)

  4325. #define FLEXPWM3_SM1TCTRL		(IMXRT_FLEXPWM3.SM[1].TCTRL)

  4326. #define FLEXPWM3_SM1DISMAP0		(IMXRT_FLEXPWM3.SM[1].DISMAP0)

  4327. #define FLEXPWM3_SM1DISMAP1		(IMXRT_FLEXPWM3.SM[1].DISMAP1)

  4328. #define FLEXPWM3_SM1DTCNT0		(IMXRT_FLEXPWM3.SM[1].DTCNT0)

  4329. #define FLEXPWM3_SM1DTCNT1		(IMXRT_FLEXPWM3.SM[1].DTCNT1)

  4330. #define FLEXPWM3_SM1CAPTCTRLA		(IMXRT_FLEXPWM3.SM[1].CAPTCTRLA)

  4331. #define FLEXPWM3_SM1CAPTCOMPA		(IMXRT_FLEXPWM3.SM[1].CAPTCOMPA)

  4332. #define FLEXPWM3_SM1CAPTCTRLB		(IMXRT_FLEXPWM3.SM[1].CAPTCTRLB)

  4333. #define FLEXPWM3_SM1CAPTCOMPB		(IMXRT_FLEXPWM3.SM[1].CAPTCOMPB)

  4334. #define FLEXPWM3_SM1CAPTCTRLX		(IMXRT_FLEXPWM3.SM[1].CAPTCTRLX)

  4335. #define FLEXPWM3_SM1CAPTCOMPX		(IMXRT_FLEXPWM3.SM[1].CAPTCOMPX)

  4336. #define FLEXPWM3_SM1CVAL0		(IMXRT_FLEXPWM3.SM[1].CVAL0)

  4337. #define FLEXPWM3_SM1CVAL0CYC		(IMXRT_FLEXPWM3.SM[1].CVAL0CYC)

  4338. #define FLEXPWM3_SM1CVAL1		(IMXRT_FLEXPWM3.SM[1].CVAL1)

  4339. #define FLEXPWM3_SM1CVAL1CYC		(IMXRT_FLEXPWM3.SM[1].CVAL1CYC)

  4340. #define FLEXPWM3_SM1CVAL2		(IMXRT_FLEXPWM3.SM[1].CVAL2)

  4341. #define FLEXPWM3_SM1CVAL2CYC		(IMXRT_FLEXPWM3.SM[1].CVAL2CYC)

  4342. #define FLEXPWM3_SM1CVAL3		(IMXRT_FLEXPWM3.SM[1].CVAL3)

  4343. #define FLEXPWM3_SM1CVAL3CYC		(IMXRT_FLEXPWM3.SM[1].CVAL3CYC)

  4344. #define FLEXPWM3_SM1CVAL4		(IMXRT_FLEXPWM3.SM[1].CVAL4)

  4345. #define FLEXPWM3_SM1CVAL4CYC		(IMXRT_FLEXPWM3.SM[1].CVAL4CYC)

  4346. #define FLEXPWM3_SM1CVAL5		(IMXRT_FLEXPWM3.SM[1].CVAL5)

  4347. #define FLEXPWM3_SM1CVAL5CYC		(IMXRT_FLEXPWM3.SM[1].CVAL5CYC)

  4348. #define FLEXPWM3_SM2CNT			(IMXRT_FLEXPWM3.SM[2].CNT)

  4349. #define FLEXPWM3_SM2INIT		(IMXRT_FLEXPWM3.SM[2].INIT)

  4350. #define FLEXPWM3_SM2CTRL2		(IMXRT_FLEXPWM3.SM[2].CTRL2)

  4351. #define FLEXPWM3_SM2CTRL		(IMXRT_FLEXPWM3.SM[2].CTRL)

  4352. #define FLEXPWM3_SM2VAL0		(IMXRT_FLEXPWM3.SM[2].VAL0)

  4353. #define FLEXPWM3_SM2FRACVAL1		(IMXRT_FLEXPWM3.SM[2].FRACVAL1)

  4354. #define FLEXPWM3_SM2VAL1		(IMXRT_FLEXPWM3.SM[2].VAL1)

  4355. #define FLEXPWM3_SM2FRACVAL2		(IMXRT_FLEXPWM3.SM[2].FRACVAL2)

  4356. #define FLEXPWM3_SM2VAL2		(IMXRT_FLEXPWM3.SM[2].VAL2)

  4357. #define FLEXPWM3_SM2FRACVAL3		(IMXRT_FLEXPWM3.SM[2].FRACVAL3)

  4358. #define FLEXPWM3_SM2VAL3		(IMXRT_FLEXPWM3.SM[2].VAL3)

  4359. #define FLEXPWM3_SM2FRACVAL4		(IMXRT_FLEXPWM3.SM[2].FRACVAL4)

  4360. #define FLEXPWM3_SM2VAL4		(IMXRT_FLEXPWM3.SM[2].VAL4)

  4361. #define FLEXPWM3_SM2FRACVAL5		(IMXRT_FLEXPWM3.SM[2].FRACVAL5)

  4362. #define FLEXPWM3_SM2VAL5		(IMXRT_FLEXPWM3.SM[2].VAL5)

  4363. #define FLEXPWM3_SM2FRCTRL		(IMXRT_FLEXPWM3.SM[2].FRCTRL)

  4364. #define FLEXPWM3_SM2OCTRL		(IMXRT_FLEXPWM3.SM[2].OCTRL)

  4365. #define FLEXPWM3_SM2STS			(IMXRT_FLEXPWM3.SM[2].STS)

  4366. #define FLEXPWM3_SM2INTEN		(IMXRT_FLEXPWM3.SM[2].INTEN)

  4367. #define FLEXPWM3_SM2DMAEN		(IMXRT_FLEXPWM3.SM[2].DMAEN)

  4368. #define FLEXPWM3_SM2TCTRL		(IMXRT_FLEXPWM3.SM[2].TCTRL)

  4369. #define FLEXPWM3_SM2DISMAP0		(IMXRT_FLEXPWM3.SM[2].DISMAP0)

  4370. #define FLEXPWM3_SM2DISMAP1		(IMXRT_FLEXPWM3.SM[2].DISMAP1)

  4371. #define FLEXPWM3_SM2DTCNT0		(IMXRT_FLEXPWM3.SM[2].DTCNT0)

  4372. #define FLEXPWM3_SM2DTCNT1		(IMXRT_FLEXPWM3.SM[2].DTCNT1)

  4373. #define FLEXPWM3_SM2CAPTCTRLA		(IMXRT_FLEXPWM3.SM[2].CAPTCTRLA)

  4374. #define FLEXPWM3_SM2CAPTCOMPA		(IMXRT_FLEXPWM3.SM[2].CAPTCOMPA)

  4375. #define FLEXPWM3_SM2CAPTCTRLB		(IMXRT_FLEXPWM3.SM[2].CAPTCTRLB)

  4376. #define FLEXPWM3_SM2CAPTCOMPB		(IMXRT_FLEXPWM3.SM[2].CAPTCOMPB)

  4377. #define FLEXPWM3_SM2CAPTCTRLX		(IMXRT_FLEXPWM3.SM[2].CAPTCTRLX)

  4378. #define FLEXPWM3_SM2CAPTCOMPX		(IMXRT_FLEXPWM3.SM[2].CAPTCOMPX)

  4379. #define FLEXPWM3_SM2CVAL0		(IMXRT_FLEXPWM3.SM[2].CVAL0)

  4380. #define FLEXPWM3_SM2CVAL0CYC		(IMXRT_FLEXPWM3.SM[2].CVAL0CYC)

  4381. #define FLEXPWM3_SM2CVAL1		(IMXRT_FLEXPWM3.SM[2].CVAL1)

  4382. #define FLEXPWM3_SM2CVAL1CYC		(IMXRT_FLEXPWM3.SM[2].CVAL1CYC)

  4383. #define FLEXPWM3_SM2CVAL2		(IMXRT_FLEXPWM3.SM[2].CVAL2)

  4384. #define FLEXPWM3_SM2CVAL2CYC		(IMXRT_FLEXPWM3.SM[2].CVAL2CYC)

  4385. #define FLEXPWM3_SM2CVAL3		(IMXRT_FLEXPWM3.SM[2].CVAL3)

  4386. #define FLEXPWM3_SM2CVAL3CYC		(IMXRT_FLEXPWM3.SM[2].CVAL3CYC)

  4387. #define FLEXPWM3_SM2CVAL4		(IMXRT_FLEXPWM3.SM[2].CVAL4)

  4388. #define FLEXPWM3_SM2CVAL4CYC		(IMXRT_FLEXPWM3.SM[2].CVAL4CYC)

  4389. #define FLEXPWM3_SM2CVAL5		(IMXRT_FLEXPWM3.SM[2].CVAL5)

  4390. #define FLEXPWM3_SM2CVAL5CYC		(IMXRT_FLEXPWM3.SM[2].CVAL5CYC)

  4391. #define FLEXPWM3_SM3CNT			(IMXRT_FLEXPWM3.SM[3].CNT)

  4392. #define FLEXPWM3_SM3INIT		(IMXRT_FLEXPWM3.SM[3].INIT)

  4393. #define FLEXPWM3_SM3CTRL2		(IMXRT_FLEXPWM3.SM[3].CTRL2)

  4394. #define FLEXPWM3_SM3CTRL		(IMXRT_FLEXPWM3.SM[3].CTRL)

  4395. #define FLEXPWM3_SM3VAL0		(IMXRT_FLEXPWM3.SM[3].VAL0)

  4396. #define FLEXPWM3_SM3FRACVAL1		(IMXRT_FLEXPWM3.SM[3].FRACVAL1)

  4397. #define FLEXPWM3_SM3VAL1		(IMXRT_FLEXPWM3.SM[3].VAL1)

  4398. #define FLEXPWM3_SM3FRACVAL2		(IMXRT_FLEXPWM3.SM[3].FRACVAL2)

  4399. #define FLEXPWM3_SM3VAL2		(IMXRT_FLEXPWM3.SM[3].VAL2)

  4400. #define FLEXPWM3_SM3FRACVAL3		(IMXRT_FLEXPWM3.SM[3].FRACVAL3)

  4401. #define FLEXPWM3_SM3VAL3		(IMXRT_FLEXPWM3.SM[3].VAL3)

  4402. #define FLEXPWM3_SM3FRACVAL4		(IMXRT_FLEXPWM3.SM[3].FRACVAL4)

  4403. #define FLEXPWM3_SM3VAL4		(IMXRT_FLEXPWM3.SM[3].VAL4)

  4404. #define FLEXPWM3_SM3FRACVAL5		(IMXRT_FLEXPWM3.SM[3].FRACVAL5)

  4405. #define FLEXPWM3_SM3VAL5		(IMXRT_FLEXPWM3.SM[3].VAL5)

  4406. #define FLEXPWM3_SM3FRCTRL		(IMXRT_FLEXPWM3.SM[3].FRCTRL)

  4407. #define FLEXPWM3_SM3OCTRL		(IMXRT_FLEXPWM3.SM[3].OCTRL)

  4408. #define FLEXPWM3_SM3STS			(IMXRT_FLEXPWM3.SM[3].STS)

  4409. #define FLEXPWM3_SM3INTEN		(IMXRT_FLEXPWM3.SM[3].INTEN)

  4410. #define FLEXPWM3_SM3DMAEN		(IMXRT_FLEXPWM3.SM[3].DMAEN)

  4411. #define FLEXPWM3_SM3TCTRL		(IMXRT_FLEXPWM3.SM[3].TCTRL)

  4412. #define FLEXPWM3_SM3DISMAP0		(IMXRT_FLEXPWM3.SM[3].DISMAP0)

  4413. #define FLEXPWM3_SM3DISMAP1		(IMXRT_FLEXPWM3.SM[3].DISMAP1)

  4414. #define FLEXPWM3_SM3DTCNT0		(IMXRT_FLEXPWM3.SM[3].DTCNT0)

  4415. #define FLEXPWM3_SM3DTCNT1		(IMXRT_FLEXPWM3.SM[3].DTCNT1)

  4416. #define FLEXPWM3_SM3CAPTCTRLA		(IMXRT_FLEXPWM3.SM[3].CAPTCTRLA)

  4417. #define FLEXPWM3_SM3CAPTCOMPA		(IMXRT_FLEXPWM3.SM[3].CAPTCOMPA)

  4418. #define FLEXPWM3_SM3CAPTCTRLB		(IMXRT_FLEXPWM3.SM[3].CAPTCTRLB)

  4419. #define FLEXPWM3_SM3CAPTCOMPB		(IMXRT_FLEXPWM3.SM[3].CAPTCOMPB)

  4420. #define FLEXPWM3_SM3CAPTCTRLX		(IMXRT_FLEXPWM3.SM[3].CAPTCTRLX)

  4421. #define FLEXPWM3_SM3CAPTCOMPX		(IMXRT_FLEXPWM3.SM[3].CAPTCOMPX)

  4422. #define FLEXPWM3_SM3CVAL0		(IMXRT_FLEXPWM3.SM[3].CVAL0)

  4423. #define FLEXPWM3_SM3CVAL0CYC		(IMXRT_FLEXPWM3.SM[3].CVAL0CYC)

  4424. #define FLEXPWM3_SM3CVAL1		(IMXRT_FLEXPWM3.SM[3].CVAL1)

  4425. #define FLEXPWM3_SM3CVAL1CYC		(IMXRT_FLEXPWM3.SM[3].CVAL1CYC)

  4426. #define FLEXPWM3_SM3CVAL2		(IMXRT_FLEXPWM3.SM[3].CVAL2)

  4427. #define FLEXPWM3_SM3CVAL2CYC		(IMXRT_FLEXPWM3.SM[3].CVAL2CYC)

  4428. #define FLEXPWM3_SM3CVAL3		(IMXRT_FLEXPWM3.SM[3].CVAL3)

  4429. #define FLEXPWM3_SM3CVAL3CYC		(IMXRT_FLEXPWM3.SM[3].CVAL3CYC)

  4430. #define FLEXPWM3_SM3CVAL4		(IMXRT_FLEXPWM3.SM[3].CVAL4)

  4431. #define FLEXPWM3_SM3CVAL4CYC		(IMXRT_FLEXPWM3.SM[3].CVAL4CYC)

  4432. #define FLEXPWM3_SM3CVAL5		(IMXRT_FLEXPWM3.SM[3].CVAL5)

  4433. #define FLEXPWM3_SM3CVAL5CYC		(IMXRT_FLEXPWM3.SM[3].CVAL5CYC)

  4434. #define FLEXPWM3_OUTEN			(IMXRT_FLEXPWM3.OUTEN)

  4435. #define FLEXPWM3_MASK			(IMXRT_FLEXPWM3.MASK)

  4436. #define FLEXPWM3_SWCOUT			(IMXRT_FLEXPWM3.SWCOUT)

  4437. #define FLEXPWM3_DTSRCSEL		(IMXRT_FLEXPWM3.DTSRCSEL)

  4438. #define FLEXPWM3_MCTRL			(IMXRT_FLEXPWM3.MCTRL)

  4439. #define FLEXPWM3_MCTRL2			(IMXRT_FLEXPWM3.MCTRL2)

  4440. #define FLEXPWM3_FCTRL0			(IMXRT_FLEXPWM3.FCTRL0)

  4441. #define FLEXPWM3_FSTS0			(IMXRT_FLEXPWM3.FSTS0)

  4442. #define FLEXPWM3_FFILT0			(IMXRT_FLEXPWM3.FFILT0)

  4443. #define FLEXPWM3_FTST0			(IMXRT_FLEXPWM3.FTST0)

  4444. #define FLEXPWM3_FCTRL20		(IMXRT_FLEXPWM3.FCTRL20)

  4445. #define FLEXPWM4_SM0CNT			(IMXRT_FLEXPWM4.SM[0].CNT)

  4446. #define FLEXPWM4_SM0INIT		(IMXRT_FLEXPWM4.SM[0].INIT)

  4447. #define FLEXPWM4_SM0CTRL2		(IMXRT_FLEXPWM4.SM[0].CTRL2)

  4448. #define FLEXPWM4_SM0CTRL		(IMXRT_FLEXPWM4.SM[0].CTRL)

  4449. #define FLEXPWM4_SM0VAL0		(IMXRT_FLEXPWM4.SM[0].VAL0)

  4450. #define FLEXPWM4_SM0FRACVAL1		(IMXRT_FLEXPWM4.SM[0].FRACVAL1)

  4451. #define FLEXPWM4_SM0VAL1		(IMXRT_FLEXPWM4.SM[0].VAL1)

  4452. #define FLEXPWM4_SM0FRACVAL2		(IMXRT_FLEXPWM4.SM[0].FRACVAL2)

  4453. #define FLEXPWM4_SM0VAL2		(IMXRT_FLEXPWM4.SM[0].VAL2)

  4454. #define FLEXPWM4_SM0FRACVAL3		(IMXRT_FLEXPWM4.SM[0].FRACVAL3)

  4455. #define FLEXPWM4_SM0VAL3		(IMXRT_FLEXPWM4.SM[0].VAL3)

  4456. #define FLEXPWM4_SM0FRACVAL4		(IMXRT_FLEXPWM4.SM[0].FRACVAL4)

  4457. #define FLEXPWM4_SM0VAL4		(IMXRT_FLEXPWM4.SM[0].VAL4)

  4458. #define FLEXPWM4_SM0FRACVAL5		(IMXRT_FLEXPWM4.SM[0].FRACVAL5)

  4459. #define FLEXPWM4_SM0VAL5		(IMXRT_FLEXPWM4.SM[0].VAL5)

  4460. #define FLEXPWM4_SM0FRCTRL		(IMXRT_FLEXPWM4.SM[0].FRCTRL)

  4461. #define FLEXPWM4_SM0OCTRL		(IMXRT_FLEXPWM4.SM[0].OCTRL)

  4462. #define FLEXPWM4_SM0STS			(IMXRT_FLEXPWM4.SM[0].STS)

  4463. #define FLEXPWM4_SM0INTEN		(IMXRT_FLEXPWM4.SM[0].INTEN)

  4464. #define FLEXPWM4_SM0DMAEN		(IMXRT_FLEXPWM4.SM[0].DMAEN)

  4465. #define FLEXPWM4_SM0TCTRL		(IMXRT_FLEXPWM4.SM[0].TCTRL)

  4466. #define FLEXPWM4_SM0DISMAP0		(IMXRT_FLEXPWM4.SM[0].DISMAP0)

  4467. #define FLEXPWM4_SM0DISMAP1		(IMXRT_FLEXPWM4.SM[0].DISMAP1)

  4468. #define FLEXPWM4_SM0DTCNT0		(IMXRT_FLEXPWM4.SM[0].DTCNT0)

  4469. #define FLEXPWM4_SM0DTCNT1		(IMXRT_FLEXPWM4.SM[0].DTCNT1)

  4470. #define FLEXPWM4_SM0CAPTCTRLA		(IMXRT_FLEXPWM4.SM[0].CAPTCTRLA)

  4471. #define FLEXPWM4_SM0CAPTCOMPA		(IMXRT_FLEXPWM4.SM[0].CAPTCOMPA)

  4472. #define FLEXPWM4_SM0CAPTCTRLB		(IMXRT_FLEXPWM4.SM[0].CAPTCTRLB)

  4473. #define FLEXPWM4_SM0CAPTCOMPB		(IMXRT_FLEXPWM4.SM[0].CAPTCOMPB)

  4474. #define FLEXPWM4_SM0CAPTCTRLX		(IMXRT_FLEXPWM4.SM[0].CAPTCTRLX)

  4475. #define FLEXPWM4_SM0CAPTCOMPX		(IMXRT_FLEXPWM4.SM[0].CAPTCOMPX)

  4476. #define FLEXPWM4_SM0CVAL0		(IMXRT_FLEXPWM4.SM[0].CVAL0)

  4477. #define FLEXPWM4_SM0CVAL0CYC		(IMXRT_FLEXPWM4.SM[0].CVAL0CYC)

  4478. #define FLEXPWM4_SM0CVAL1		(IMXRT_FLEXPWM4.SM[0].CVAL1)

  4479. #define FLEXPWM4_SM0CVAL1CYC		(IMXRT_FLEXPWM4.SM[0].CVAL1CYC)

  4480. #define FLEXPWM4_SM0CVAL2		(IMXRT_FLEXPWM4.SM[0].CVAL2)

  4481. #define FLEXPWM4_SM0CVAL2CYC		(IMXRT_FLEXPWM4.SM[0].CVAL2CYC)

  4482. #define FLEXPWM4_SM0CVAL3		(IMXRT_FLEXPWM4.SM[0].CVAL3)

  4483. #define FLEXPWM4_SM0CVAL3CYC		(IMXRT_FLEXPWM4.SM[0].CVAL3CYC)

  4484. #define FLEXPWM4_SM0CVAL4		(IMXRT_FLEXPWM4.SM[0].CVAL4)

  4485. #define FLEXPWM4_SM0CVAL4CYC		(IMXRT_FLEXPWM4.SM[0].CVAL4CYC)

  4486. #define FLEXPWM4_SM0CVAL5		(IMXRT_FLEXPWM4.SM[0].CVAL5)

  4487. #define FLEXPWM4_SM0CVAL5CYC		(IMXRT_FLEXPWM4.SM[0].CVAL5CYC)

  4488. #define FLEXPWM4_SM1CNT			(IMXRT_FLEXPWM4.SM[1].CNT)

  4489. #define FLEXPWM4_SM1INIT		(IMXRT_FLEXPWM4.SM[1].INIT)

  4490. #define FLEXPWM4_SM1CTRL2		(IMXRT_FLEXPWM4.SM[1].CTRL2)

  4491. #define FLEXPWM4_SM1CTRL		(IMXRT_FLEXPWM4.SM[1].CTRL)

  4492. #define FLEXPWM4_SM1VAL0		(IMXRT_FLEXPWM4.SM[1].VAL0)

  4493. #define FLEXPWM4_SM1FRACVAL1		(IMXRT_FLEXPWM4.SM[1].FRACVAL1)

  4494. #define FLEXPWM4_SM1VAL1		(IMXRT_FLEXPWM4.SM[1].VAL1)

  4495. #define FLEXPWM4_SM1FRACVAL2		(IMXRT_FLEXPWM4.SM[1].FRACVAL2)

  4496. #define FLEXPWM4_SM1VAL2		(IMXRT_FLEXPWM4.SM[1].VAL2)

  4497. #define FLEXPWM4_SM1FRACVAL3		(IMXRT_FLEXPWM4.SM[1].FRACVAL3)

  4498. #define FLEXPWM4_SM1VAL3		(IMXRT_FLEXPWM4.SM[1].VAL3)

  4499. #define FLEXPWM4_SM1FRACVAL4		(IMXRT_FLEXPWM4.SM[1].FRACVAL4)

  4500. #define FLEXPWM4_SM1VAL4		(IMXRT_FLEXPWM4.SM[1].VAL4)

  4501. #define FLEXPWM4_SM1FRACVAL5		(IMXRT_FLEXPWM4.SM[1].FRACVAL5)

  4502. #define FLEXPWM4_SM1VAL5		(IMXRT_FLEXPWM4.SM[1].VAL5)

  4503. #define FLEXPWM4_SM1FRCTRL		(IMXRT_FLEXPWM4.SM[1].FRCTRL)

  4504. #define FLEXPWM4_SM1OCTRL		(IMXRT_FLEXPWM4.SM[1].OCTRL)

  4505. #define FLEXPWM4_SM1STS			(IMXRT_FLEXPWM4.SM[1].STS)

  4506. #define FLEXPWM4_SM1INTEN		(IMXRT_FLEXPWM4.SM[1].INTEN)

  4507. #define FLEXPWM4_SM1DMAEN		(IMXRT_FLEXPWM4.SM[1].DMAEN)

  4508. #define FLEXPWM4_SM1TCTRL		(IMXRT_FLEXPWM4.SM[1].TCTRL)

  4509. #define FLEXPWM4_SM1DISMAP0		(IMXRT_FLEXPWM4.SM[1].DISMAP0)

  4510. #define FLEXPWM4_SM1DISMAP1		(IMXRT_FLEXPWM4.SM[1].DISMAP1)

  4511. #define FLEXPWM4_SM1DTCNT0		(IMXRT_FLEXPWM4.SM[1].DTCNT0)

  4512. #define FLEXPWM4_SM1DTCNT1		(IMXRT_FLEXPWM4.SM[1].DTCNT1)

  4513. #define FLEXPWM4_SM1CAPTCTRLA		(IMXRT_FLEXPWM4.SM[1].CAPTCTRLA)

  4514. #define FLEXPWM4_SM1CAPTCOMPA		(IMXRT_FLEXPWM4.SM[1].CAPTCOMPA)

  4515. #define FLEXPWM4_SM1CAPTCTRLB		(IMXRT_FLEXPWM4.SM[1].CAPTCTRLB)

  4516. #define FLEXPWM4_SM1CAPTCOMPB		(IMXRT_FLEXPWM4.SM[1].CAPTCOMPB)

  4517. #define FLEXPWM4_SM1CAPTCTRLX		(IMXRT_FLEXPWM4.SM[1].CAPTCTRLX)

  4518. #define FLEXPWM4_SM1CAPTCOMPX		(IMXRT_FLEXPWM4.SM[1].CAPTCOMPX)

  4519. #define FLEXPWM4_SM1CVAL0		(IMXRT_FLEXPWM4.SM[1].CVAL0)

  4520. #define FLEXPWM4_SM1CVAL0CYC		(IMXRT_FLEXPWM4.SM[1].CVAL0CYC)

  4521. #define FLEXPWM4_SM1CVAL1		(IMXRT_FLEXPWM4.SM[1].CVAL1)

  4522. #define FLEXPWM4_SM1CVAL1CYC		(IMXRT_FLEXPWM4.SM[1].CVAL1CYC)

  4523. #define FLEXPWM4_SM1CVAL2		(IMXRT_FLEXPWM4.SM[1].CVAL2)

  4524. #define FLEXPWM4_SM1CVAL2CYC		(IMXRT_FLEXPWM4.SM[1].CVAL2CYC)

  4525. #define FLEXPWM4_SM1CVAL3		(IMXRT_FLEXPWM4.SM[1].CVAL3)

  4526. #define FLEXPWM4_SM1CVAL3CYC		(IMXRT_FLEXPWM4.SM[1].CVAL3CYC)

  4527. #define FLEXPWM4_SM1CVAL4		(IMXRT_FLEXPWM4.SM[1].CVAL4)

  4528. #define FLEXPWM4_SM1CVAL4CYC		(IMXRT_FLEXPWM4.SM[1].CVAL4CYC)

  4529. #define FLEXPWM4_SM1CVAL5		(IMXRT_FLEXPWM4.SM[1].CVAL5)

  4530. #define FLEXPWM4_SM1CVAL5CYC		(IMXRT_FLEXPWM4.SM[1].CVAL5CYC)

  4531. #define FLEXPWM4_SM2CNT			(IMXRT_FLEXPWM4.SM[2].CNT)

  4532. #define FLEXPWM4_SM2INIT		(IMXRT_FLEXPWM4.SM[2].INIT)

  4533. #define FLEXPWM4_SM2CTRL2		(IMXRT_FLEXPWM4.SM[2].CTRL2)

  4534. #define FLEXPWM4_SM2CTRL		(IMXRT_FLEXPWM4.SM[2].CTRL)

  4535. #define FLEXPWM4_SM2VAL0		(IMXRT_FLEXPWM4.SM[2].VAL0)

  4536. #define FLEXPWM4_SM2FRACVAL1		(IMXRT_FLEXPWM4.SM[2].FRACVAL1)

  4537. #define FLEXPWM4_SM2VAL1		(IMXRT_FLEXPWM4.SM[2].VAL1)

  4538. #define FLEXPWM4_SM2FRACVAL2		(IMXRT_FLEXPWM4.SM[2].FRACVAL2)

  4539. #define FLEXPWM4_SM2VAL2		(IMXRT_FLEXPWM4.SM[2].VAL2)

  4540. #define FLEXPWM4_SM2FRACVAL3		(IMXRT_FLEXPWM4.SM[2].FRACVAL3)

  4541. #define FLEXPWM4_SM2VAL3		(IMXRT_FLEXPWM4.SM[2].VAL3)

  4542. #define FLEXPWM4_SM2FRACVAL4		(IMXRT_FLEXPWM4.SM[2].FRACVAL4)

  4543. #define FLEXPWM4_SM2VAL4		(IMXRT_FLEXPWM4.SM[2].VAL4)

  4544. #define FLEXPWM4_SM2FRACVAL5		(IMXRT_FLEXPWM4.SM[2].FRACVAL5)

  4545. #define FLEXPWM4_SM2VAL5		(IMXRT_FLEXPWM4.SM[2].VAL5)

  4546. #define FLEXPWM4_SM2FRCTRL		(IMXRT_FLEXPWM4.SM[2].FRCTRL)

  4547. #define FLEXPWM4_SM2OCTRL		(IMXRT_FLEXPWM4.SM[2].OCTRL)

  4548. #define FLEXPWM4_SM2STS			(IMXRT_FLEXPWM4.SM[2].STS)

  4549. #define FLEXPWM4_SM2INTEN		(IMXRT_FLEXPWM4.SM[2].INTEN)

  4550. #define FLEXPWM4_SM2DMAEN		(IMXRT_FLEXPWM4.SM[2].DMAEN)

  4551. #define FLEXPWM4_SM2TCTRL		(IMXRT_FLEXPWM4.SM[2].TCTRL)

  4552. #define FLEXPWM4_SM2DISMAP0		(IMXRT_FLEXPWM4.SM[2].DISMAP0)

  4553. #define FLEXPWM4_SM2DISMAP1		(IMXRT_FLEXPWM4.SM[2].DISMAP1)

  4554. #define FLEXPWM4_SM2DTCNT0		(IMXRT_FLEXPWM4.SM[2].DTCNT0)

  4555. #define FLEXPWM4_SM2DTCNT1		(IMXRT_FLEXPWM4.SM[2].DTCNT1)

  4556. #define FLEXPWM4_SM2CAPTCTRLA		(IMXRT_FLEXPWM4.SM[2].CAPTCTRLA)

  4557. #define FLEXPWM4_SM2CAPTCOMPA		(IMXRT_FLEXPWM4.SM[2].CAPTCOMPA)

  4558. #define FLEXPWM4_SM2CAPTCTRLB		(IMXRT_FLEXPWM4.SM[2].CAPTCTRLB)

  4559. #define FLEXPWM4_SM2CAPTCOMPB		(IMXRT_FLEXPWM4.SM[2].CAPTCOMPB)

  4560. #define FLEXPWM4_SM2CAPTCTRLX		(IMXRT_FLEXPWM4.SM[2].CAPTCTRLX)

  4561. #define FLEXPWM4_SM2CAPTCOMPX		(IMXRT_FLEXPWM4.SM[2].CAPTCOMPX)

  4562. #define FLEXPWM4_SM2CVAL0		(IMXRT_FLEXPWM4.SM[2].CVAL0)

  4563. #define FLEXPWM4_SM2CVAL0CYC		(IMXRT_FLEXPWM4.SM[2].CVAL0CYC)

  4564. #define FLEXPWM4_SM2CVAL1		(IMXRT_FLEXPWM4.SM[2].CVAL1)

  4565. #define FLEXPWM4_SM2CVAL1CYC		(IMXRT_FLEXPWM4.SM[2].CVAL1CYC)

  4566. #define FLEXPWM4_SM2CVAL2		(IMXRT_FLEXPWM4.SM[2].CVAL2)

  4567. #define FLEXPWM4_SM2CVAL2CYC		(IMXRT_FLEXPWM4.SM[2].CVAL2CYC)

  4568. #define FLEXPWM4_SM2CVAL3		(IMXRT_FLEXPWM4.SM[2].CVAL3)

  4569. #define FLEXPWM4_SM2CVAL3CYC		(IMXRT_FLEXPWM4.SM[2].CVAL3CYC)

  4570. #define FLEXPWM4_SM2CVAL4		(IMXRT_FLEXPWM4.SM[2].CVAL4)

  4571. #define FLEXPWM4_SM2CVAL4CYC		(IMXRT_FLEXPWM4.SM[2].CVAL4CYC)

  4572. #define FLEXPWM4_SM2CVAL5		(IMXRT_FLEXPWM4.SM[2].CVAL5)

  4573. #define FLEXPWM4_SM2CVAL5CYC		(IMXRT_FLEXPWM4.SM[2].CVAL5CYC)

  4574. #define FLEXPWM4_SM3CNT			(IMXRT_FLEXPWM4.SM[3].CNT)

  4575. #define FLEXPWM4_SM3INIT		(IMXRT_FLEXPWM4.SM[3].INIT)

  4576. #define FLEXPWM4_SM3CTRL2		(IMXRT_FLEXPWM4.SM[3].CTRL2)

  4577. #define FLEXPWM4_SM3CTRL		(IMXRT_FLEXPWM4.SM[3].CTRL)

  4578. #define FLEXPWM4_SM3VAL0		(IMXRT_FLEXPWM4.SM[3].VAL0)

  4579. #define FLEXPWM4_SM3FRACVAL1		(IMXRT_FLEXPWM4.SM[3].FRACVAL1)

  4580. #define FLEXPWM4_SM3VAL1		(IMXRT_FLEXPWM4.SM[3].VAL1)

  4581. #define FLEXPWM4_SM3FRACVAL2		(IMXRT_FLEXPWM4.SM[3].FRACVAL2)

  4582. #define FLEXPWM4_SM3VAL2		(IMXRT_FLEXPWM4.SM[3].VAL2)

  4583. #define FLEXPWM4_SM3FRACVAL3		(IMXRT_FLEXPWM4.SM[3].FRACVAL3)

  4584. #define FLEXPWM4_SM3VAL3		(IMXRT_FLEXPWM4.SM[3].VAL3)

  4585. #define FLEXPWM4_SM3FRACVAL4		(IMXRT_FLEXPWM4.SM[3].FRACVAL4)

  4586. #define FLEXPWM4_SM3VAL4		(IMXRT_FLEXPWM4.SM[3].VAL4)

  4587. #define FLEXPWM4_SM3FRACVAL5		(IMXRT_FLEXPWM4.SM[3].FRACVAL5)

  4588. #define FLEXPWM4_SM3VAL5		(IMXRT_FLEXPWM4.SM[3].VAL5)

  4589. #define FLEXPWM4_SM3FRCTRL		(IMXRT_FLEXPWM4.SM[3].FRCTRL)

  4590. #define FLEXPWM4_SM3OCTRL		(IMXRT_FLEXPWM4.SM[3].OCTRL)

  4591. #define FLEXPWM4_SM3STS			(IMXRT_FLEXPWM4.SM[3].STS)

  4592. #define FLEXPWM4_SM3INTEN		(IMXRT_FLEXPWM4.SM[3].INTEN)

  4593. #define FLEXPWM4_SM3DMAEN		(IMXRT_FLEXPWM4.SM[3].DMAEN)

  4594. #define FLEXPWM4_SM3TCTRL		(IMXRT_FLEXPWM4.SM[3].TCTRL)

  4595. #define FLEXPWM4_SM3DISMAP0		(IMXRT_FLEXPWM4.SM[3].DISMAP0)

  4596. #define FLEXPWM4_SM3DISMAP1		(IMXRT_FLEXPWM4.SM[3].DISMAP1)

  4597. #define FLEXPWM4_SM3DTCNT0		(IMXRT_FLEXPWM4.SM[3].DTCNT0)

  4598. #define FLEXPWM4_SM3DTCNT1		(IMXRT_FLEXPWM4.SM[3].DTCNT1)

  4599. #define FLEXPWM4_SM3CAPTCTRLA		(IMXRT_FLEXPWM4.SM[3].CAPTCTRLA)

  4600. #define FLEXPWM4_SM3CAPTCOMPA		(IMXRT_FLEXPWM4.SM[3].CAPTCOMPA)

  4601. #define FLEXPWM4_SM3CAPTCTRLB		(IMXRT_FLEXPWM4.SM[3].CAPTCTRLB)

  4602. #define FLEXPWM4_SM3CAPTCOMPB		(IMXRT_FLEXPWM4.SM[3].CAPTCOMPB)

  4603. #define FLEXPWM4_SM3CAPTCTRLX		(IMXRT_FLEXPWM4.SM[3].CAPTCTRLX)

  4604. #define FLEXPWM4_SM3CAPTCOMPX		(IMXRT_FLEXPWM4.SM[3].CAPTCOMPX)

  4605. #define FLEXPWM4_SM3CVAL0		(IMXRT_FLEXPWM4.SM[3].CVAL0)

  4606. #define FLEXPWM4_SM3CVAL0CYC		(IMXRT_FLEXPWM4.SM[3].CVAL0CYC)

  4607. #define FLEXPWM4_SM3CVAL1		(IMXRT_FLEXPWM4.SM[3].CVAL1)

  4608. #define FLEXPWM4_SM3CVAL1CYC		(IMXRT_FLEXPWM4.SM[3].CVAL1CYC)

  4609. #define FLEXPWM4_SM3CVAL2		(IMXRT_FLEXPWM4.SM[3].CVAL2)

  4610. #define FLEXPWM4_SM3CVAL2CYC		(IMXRT_FLEXPWM4.SM[3].CVAL2CYC)

  4611. #define FLEXPWM4_SM3CVAL3		(IMXRT_FLEXPWM4.SM[3].CVAL3)

  4612. #define FLEXPWM4_SM3CVAL3CYC		(IMXRT_FLEXPWM4.SM[3].CVAL3CYC)

  4613. #define FLEXPWM4_SM3CVAL4		(IMXRT_FLEXPWM4.SM[3].CVAL4)

  4614. #define FLEXPWM4_SM3CVAL4CYC		(IMXRT_FLEXPWM4.SM[3].CVAL4CYC)

  4615. #define FLEXPWM4_SM3CVAL5		(IMXRT_FLEXPWM4.SM[3].CVAL5)

  4616. #define FLEXPWM4_SM3CVAL5CYC		(IMXRT_FLEXPWM4.SM[3].CVAL5CYC)

  4617. #define FLEXPWM4_OUTEN			(IMXRT_FLEXPWM4.OUTEN)

  4618. #define FLEXPWM4_MASK			(IMXRT_FLEXPWM4.MASK)

  4619. #define FLEXPWM4_SWCOUT			(IMXRT_FLEXPWM4.SWCOUT)

  4620. #define FLEXPWM4_DTSRCSEL		(IMXRT_FLEXPWM4.DTSRCSEL)

  4621. #define FLEXPWM4_MCTRL			(IMXRT_FLEXPWM4.MCTRL)

  4622. #define FLEXPWM4_MCTRL2			(IMXRT_FLEXPWM4.MCTRL2)

  4623. #define FLEXPWM4_FCTRL0			(IMXRT_FLEXPWM4.FCTRL0)

  4624. #define FLEXPWM4_FSTS0			(IMXRT_FLEXPWM4.FSTS0)

  4625. #define FLEXPWM4_FFILT0			(IMXRT_FLEXPWM4.FFILT0)

  4626. #define FLEXPWM4_FTST0			(IMXRT_FLEXPWM4.FTST0)

  4627. #define FLEXPWM4_FCTRL20		(IMXRT_FLEXPWM4.FCTRL20)

  4628. // page 3081

  4629. #define FLEXPWM_SMCTRL2_DBGEN			((uint16_t)(1<<15))

  4630. #define FLEXPWM_SMCTRL2_WAITEN			((uint16_t)(1<<14))

  4631. #define FLEXPWM_SMCTRL2_INDEP			((uint16_t)(1<<13))

  4632. #define FLEXPWM_SMCTRL2_PWM23_INIT		((uint16_t)(1<<12))

  4633. #define FLEXPWM_SMCTRL2_PWM45_INIT		((uint16_t)(1<<11))

  4634. #define FLEXPWM_SMCTRL2_PWMX_INIT		((uint16_t)(1<<10))

  4635. #define FLEXPWM_SMCTRL2_INIT_SEL(n)		((uint16_t)(((n) & 0x03) << 8))

  4636. #define FLEXPWM_SMCTRL2_FRCEN			((uint16_t)(1<<7))

  4637. #define FLEXPWM_SMCTRL2_FORCE			((uint16_t)(1<<6))

  4638. #define FLEXPWM_SMCTRL2_FORCE_SEL(n)		((uint16_t)(((n) & 0x07) << 3))

  4639. #define FLEXPWM_SMCTRL2_RELOAD_SEL		((uint16_t)(1<<2))

  4640. #define FLEXPWM_SMCTRL2_CLK_SEL(n)		((uint16_t)(((n) & 0x03) << 0))

  4641. #define FLEXPWM_SMCTRL_LDFQ(n)			((uint16_t)(((n) & 0x0F) << 12))

  4642. #define FLEXPWM_SMCTRL_HALF			((uint16_t)(1<<11))

  4643. #define FLEXPWM_SMCTRL_FULL			((uint16_t)(1<<10))

  4644. #define FLEXPWM_SMCTRL_DT(n)			((uint16_t)(((n) & 0x03) << 8))

  4645. #define FLEXPWM_SMCTRL_COMPMODE			((uint16_t)(1<<7))

  4646. #define FLEXPWM_SMCTRL_PRSC(n)			((uint16_t)(((n) & 0x0F) << 4))

  4647. #define FLEXPWM_SMCTRL_SPLIT			((uint16_t)(1<<3))

  4648. #define FLEXPWM_SMCTRL_LDMOD			((uint16_t)(1<<2))

  4649. #define FLEXPWM_SMCTRL_DBLX			((uint16_t)(1<<1))

  4650. #define FLEXPWM_SMCTRL_DBLEN			((uint16_t)(1<<0))

  4651. #define FLEXPWM_SMFRCTRL_TEST			((uint16_t)(1<<15))

  4652. #define FLEXPWM_SMFRCTRL_FRAC_PU		((uint16_t)(1<<8))

  4653. #define FLEXPWM_SMFRCTRL_FRAC45_EN		((uint16_t)(1<<4))

  4654. #define FLEXPWM_SMFRCTRL_FRAC23_EN		((uint16_t)(1<<2))

  4655. #define FLEXPWM_SMFRCTRL_FRAC1_EN		((uint16_t)(1<<1))

  4656. #define FLEXPWM_SMOCTRL_PWMA_IN			((uint16_t)(1<<15))

  4657. #define FLEXPWM_SMOCTRL_PWMB_IN			((uint16_t)(1<<14))

  4658. #define FLEXPWM_SMOCTRL_PWMX_IN			((uint16_t)(1<<13))

  4659. #define FLEXPWM_SMOCTRL_POLA			((uint16_t)(1<<10))

  4660. #define FLEXPWM_SMOCTRL_POLB			((uint16_t)(1<<9))

  4661. #define FLEXPWM_SMOCTRL_POLX			((uint16_t)(1<<8))

  4662. #define FLEXPWM_SMOCTRL_PWMAFS(n)		((uint16_t)(((n) & 0x03) << 4))

  4663. #define FLEXPWM_SMOCTRL_PWMBFS(n)		((uint16_t)(((n) & 0x03) << 2))

  4664. #define FLEXPWM_SMOCTRL_PWMXFS(n)		((uint16_t)(((n) & 0x03) << 0))

  4665. #define FLEXPWM_SMSTS_RUF			((uint16_t)(1<<14))

  4666. #define FLEXPWM_SMSTS_REF			((uint16_t)(1<<13))

  4667. #define FLEXPWM_SMSTS_RF			((uint16_t)(1<<12))

  4668. #define FLEXPWM_SMSTS_CFA1			((uint16_t)(1<<11))

  4669. #define FLEXPWM_SMSTS_CFA0			((uint16_t)(1<<10))

  4670. #define FLEXPWM_SMSTS_CFB1			((uint16_t)(1<<9))

  4671. #define FLEXPWM_SMSTS_CFB0			((uint16_t)(1<<8))

  4672. #define FLEXPWM_SMSTS_CFX1			((uint16_t)(1<<7))

  4673. #define FLEXPWM_SMSTS_CFX0			((uint16_t)(1<<6))

  4674. #define FLEXPWM_SMSTS_CMPF(n)			((uint16_t)(((n) & 0x3F) << 0))

  4675. #define FLEXPWM_SMINTEN_REIE			((uint16_t)(1<<13))

  4676. #define FLEXPWM_SMINTEN_RIE			((uint16_t)(1<<12))

  4677. #define FLEXPWM_SMINTEN_CA1IE			((uint16_t)(1<<11))

  4678. #define FLEXPWM_SMINTEN_CA0IE			((uint16_t)(1<<10))

  4679. #define FLEXPWM_SMINTEN_CB1IE			((uint16_t)(1<<9))

  4680. #define FLEXPWM_SMINTEN_CB0IE			((uint16_t)(1<<8))

  4681. #define FLEXPWM_SMINTEN_CX1IE			((uint16_t)(1<<7))

  4682. #define FLEXPWM_SMINTEN_CX0IE			((uint16_t)(1<<6))

  4683. #define FLEXPWM_SMINTEN_CMPIE(n)		((uint16_t)(((n) & 0x3F) << 0))

  4684. #define FLEXPWM_SMDMAEN_VALDE			((uint16_t)(1<<9))

  4685. #define FLEXPWM_SMDMAEN_FAND			((uint16_t)(1<<8))

  4686. #define FLEXPWM_SMDMAEN_CAPTDE(n)		((uint16_t)(((n) & 0x03) << 6))

  4687. #define FLEXPWM_SMDMAEN_CA1DE			((uint16_t)(1<<5))

  4688. #define FLEXPWM_SMDMAEN_CA0DE			((uint16_t)(1<<4))

  4689. #define FLEXPWM_SMDMAEN_CB1DE			((uint16_t)(1<<3))

  4690. #define FLEXPWM_SMDMAEN_CB0DE			((uint16_t)(1<<2))

  4691. #define FLEXPWM_SMDMAEN_CX1DE			((uint16_t)(1<<1))

  4692. #define FLEXPWM_SMDMAEN_CX0DE			((uint16_t)(1<<0))

  4693. #define FLEXPWM_SMTCTRL_PWAOT0			((uint16_t)(1<<15))

  4694. #define FLEXPWM_SMTCTRL_PWBOT1			((uint16_t)(1<<14))

  4695. #define FLEXPWM_SMTCTRL_TRGFRQ			((uint16_t)(1<<12))

  4696. #define FLEXPWM_SMTCTRL_OUT_TRIG_EN(n)		((uint16_t)(((n) & 0x3F) << 0))

  4697. #define FLEXPWM_SMDISMAP0_DIS0X(n)		((uint16_t)(((n) & 0x0F) << 8))

  4698. #define FLEXPWM_SMDISMAP0_DIS0B(n)		((uint16_t)(((n) & 0x0F) << 4))

  4699. #define FLEXPWM_SMDISMAP0_DIS0A(n)		((uint16_t)(((n) & 0x0F) << 0))

  4700. #define FLEXPWM_SMDISMAP1_DIS1X(n)		((uint16_t)(((n) & 0x0F) << 8))

  4701. #define FLEXPWM_SMDISMAP1_DIS1B(n)		((uint16_t)(((n) & 0x0F) << 4))

  4702. #define FLEXPWM_SMDISMAP1_DIS1A(n)		((uint16_t)(((n) & 0x0F) << 0))

  4703. #define FLEXPWM_SMCAPTCTRLA_CA1CNT(n)		((uint16_t)(((n) & 0x07) << 13))

  4704. #define FLEXPWM_SMCAPTCTRLA_CA0CNT(n)		((uint16_t)(((n) & 0x07) << 10))

  4705. #define FLEXPWM_SMCAPTCTRLA_CFAWM(n)		((uint16_t)(((n) & 0x03) << 8))

  4706. #define FLEXPWM_SMCAPTCTRLA_EDGCNTA_EN		((uint16_t)(1<<7))

  4707. #define FLEXPWM_SMCAPTCTRLA_INP_SELA		((uint16_t)(1<<6))

  4708. #define FLEXPWM_SMCAPTCTRLA_EDGA1(n)		((uint16_t)(((n) & 0x03) << 4))

  4709. #define FLEXPWM_SMCAPTCTRLA_EDGA0(n)		((uint16_t)(((n) & 0x03) << 2))

  4710. #define FLEXPWM_SMCAPTCTRLA_ONESHOTA		((uint16_t)(1<<1))

  4711. #define FLEXPWM_SMCAPTCTRLA_ARMA		((uint16_t)(1<<0))

  4712. #define FLEXPWM_SMCAPTCOMPA_EDGCNTA(n)		((uint16_t)(((n) & 0xFF) << 8))

  4713. #define FLEXPWM_SMCAPTCOMPA_EDGCMPA(n)		((uint16_t)(((n) & 0xFF) << 0))

  4714. #define FLEXPWM_SMCAPTCTRLB_CB1CNT(n)		((uint16_t)(((n) & 0x07) << 13))

  4715. #define FLEXPWM_SMCAPTCTRLB_CB0CNT(n)		((uint16_t)(((n) & 0x07) << 10))

  4716. #define FLEXPWM_SMCAPTCTRLB_CFBWM(n)		((uint16_t)(((n) & 0x03) << 8))

  4717. #define FLEXPWM_SMCAPTCTRLB_EDGCNTB_EN		((uint16_t)(1<<7))

  4718. #define FLEXPWM_SMCAPTCTRLB_INP_SELB		((uint16_t)(1<<6))

  4719. #define FLEXPWM_SMCAPTCTRLB_EDGB1(n)		((uint16_t)(((n) & 0x03) << 4))

  4720. #define FLEXPWM_SMCAPTCTRLB_EDGB0(n)		((uint16_t)(((n) & 0x03) << 2))

  4721. #define FLEXPWM_SMCAPTCTRLB_ONESHOTB		((uint16_t)(1<<1))

  4722. #define FLEXPWM_SMCAPTCTRLB_ARMB		((uint16_t)(1<<0))

  4723. #define FLEXPWM_SMCAPTCOMPB_EDGCNTB(n)		((uint16_t)(((n) & 0xFF) << 8))

  4724. #define FLEXPWM_SMCAPTCOMPB_EDGCMPB(n)		((uint16_t)(((n) & 0xFF) << 0))

  4725. #define FLEXPWM_SMCAPTCTRLX_CX1CNT(n)		((uint16_t)(((n) & 0x07) << 13))

  4726. #define FLEXPWM_SMCAPTCTRLX_CX0CNT(n)		((uint16_t)(((n) & 0x07) << 10))

  4727. #define FLEXPWM_SMCAPTCTRLX_CFXWM(n)		((uint16_t)(((n) & 0x03) << 8))

  4728. #define FLEXPWM_SMCAPTCTRLX_EDGCNTX_EN 		((uint16_t)(1<<7))

  4729. #define FLEXPWM_SMCAPTCTRLX_INP_SELX		((uint16_t)(1<<6))

  4730. #define FLEXPWM_SMCAPTCTRLX_EDGX1(n)		((uint16_t)(((n) & 0x03) << 4))

  4731. #define FLEXPWM_SMCAPTCTRLX_EDGX0(n)		((uint16_t)(((n) & 0x03) << 2))

  4732. #define FLEXPWM_SMCAPTCTRLX_ONESHOTX		((uint16_t)(1<<1))

  4733. #define FLEXPWM_SMCAPTCTRLX_ARMX		((uint16_t)(1<<0))

  4734. #define FLEXPWM_SMCAPTCOMPX_EDGCNTX(n)		((uint16_t)(((n) & 0xFF) << 8))

  4735. #define FLEXPWM_SMCAPTCOMPX_EDGCMPX(n)		((uint16_t)(((n) & 0xFF) << 0))

  4736. #define FLEXPWM_OUTEN_PWMA_EN(n)		((uint16_t)(((n) & 0x0F) << 8))

  4737. #define FLEXPWM_OUTEN_PWMB_EN(n)		((uint16_t)(((n) & 0x0F) << 4))

  4738. #define FLEXPWM_OUTEN_PWMX_EN(n)		((uint16_t)(((n) & 0x0F) << 0))

  4739. #define FLEXPWM_MASK_UPDATE_MASK(n)		((uint16_t)(((n) & 0x0F) << 12))

  4740. #define FLEXPWM_MASK_MASKA(n)			((uint16_t)(((n) & 0x0F) << 8))

  4741. #define FLEXPWM_MASK_MASKB(n)			((uint16_t)(((n) & 0x0F) << 4))

  4742. #define FLEXPWM_MASK_MASKX(n)			((uint16_t)(((n) & 0x0F) << 0))

  4743. #define FLEXPWM_SWCOUT_SM3OUT23			((uint16_t)(1<<7))

  4744. #define FLEXPWM_SWCOUT_SM3OUT45			((uint16_t)(1<<6))

  4745. #define FLEXPWM_SWCOUT_SM2OUT23			((uint16_t)(1<<5))

  4746. #define FLEXPWM_SWCOUT_SM2OUT45			((uint16_t)(1<<4))

  4747. #define FLEXPWM_SWCOUT_SM1OUT23			((uint16_t)(1<<3))

  4748. #define FLEXPWM_SWCOUT_SM1OUT45			((uint16_t)(1<<2))

  4749. #define FLEXPWM_SWCOUT_SM0OUT23			((uint16_t)(1<<1))

  4750. #define FLEXPWM_SWCOUT_SM0OUT45			((uint16_t)(1<<0))

  4751. #define FLEXPWM_DTSRCSEL_SM3SEL23(n)		((uint16_t)(((n) & 0x03) << 14))

  4752. #define FLEXPWM_DTSRCSEL_SM3SEL45(n)		((uint16_t)(((n) & 0x03) << 12))

  4753. #define FLEXPWM_DTSRCSEL_SM2SEL23(n)		((uint16_t)(((n) & 0x03) << 10))

  4754. #define FLEXPWM_DTSRCSEL_SM2SEL45(n)		((uint16_t)(((n) & 0x03) << 8))

  4755. #define FLEXPWM_DTSRCSEL_SM1SEL23(n)		((uint16_t)(((n) & 0x03) << 6))

  4756. #define FLEXPWM_DTSRCSEL_SM1SEL45(n)		((uint16_t)(((n) & 0x03) << 4))

  4757. #define FLEXPWM_DTSRCSEL_SM0SEL23(n)		((uint16_t)(((n) & 0x03) << 2))

  4758. #define FLEXPWM_DTSRCSEL_SM0SEL45(n)		((uint16_t)(((n) & 0x03) << 0))

  4759. #define FLEXPWM_MCTRL_IPOL(n)			((uint16_t)(((n) & 0x0F) << 12))

  4760. #define FLEXPWM_MCTRL_RUN(n)			((uint16_t)(((n) & 0x0F) << 8))

  4761. #define FLEXPWM_MCTRL_CLDOK(n)			((uint16_t)(((n) & 0x0F) << 4))

  4762. #define FLEXPWM_MCTRL_LDOK(n)			((uint16_t)(((n) & 0x0F) << 0))

  4763. #define FLEXPWM_MCTRL2_MONPLL(n)		((uint16_t)(((n) & 0x03) << 0))

  4764. #define FLEXPWM_FCTRL0_FLVL(n)			((uint16_t)(((n) & 0x0F) << 12))

  4765. #define FLEXPWM_FCTRL0_FAUTO(n)			((uint16_t)(((n) & 0x0F) << 8))

  4766. #define FLEXPWM_FCTRL0_FSAFE(n)			((uint16_t)(((n) & 0x0F) << 4))

  4767. #define FLEXPWM_FCTRL0_FIE(n)			((uint16_t)(((n) & 0x0F) << 0))

  4768. #define FLEXPWM_FSTS0_FHALF(n)			((uint16_t)(((n) & 0x0F) << 12))

  4769. #define FLEXPWM_FSTS0_FFPIN(n)			((uint16_t)(((n) & 0x0F) << 8))

  4770. #define FLEXPWM_FSTS0_FFULL(n)			((uint16_t)(((n) & 0x0F) << 4))

  4771. #define FLEXPWM_FSTS0_FFLAG(n)			((uint16_t)(((n) & 0x0F) << 0))

  4772. #define FLEXPWM_FFILT0_GSTR			((uint16_t)(1<<15))

  4773. #define FLEXPWM_FFILT0_FILT_CNT(n)		((uint16_t)(((n) & 0x07) << 8))

  4774. #define FLEXPWM_FFILT0_FILT_PER(n)		((uint16_t)(((n) & 0xFF) << 0))

  4775. #define FLEXPWM_FTST0_FTEST			((uint16_t)(1<<0))

  4776. #define FLEXPWM_FCTRL20_NOCOMB(n)		((uint16_t)(((n) & 0x0F) << 0))

  4777. 

  4778. // 31.4.1.1: page 1766

  4779. #define IMXRT_FLEXRAM		(*(IMXRT_REGISTER32_t *)0x400B0000)

  4780. #define FLEXRAM_TCM_CTRL		(IMXRT_FLEXRAM.offset000)

  4781. #define FLEXRAM_INT_STATUS		(IMXRT_FLEXRAM.offset010)

  4782. #define FLEXRAM_INT_STAT_EN		(IMXRT_FLEXRAM.offset014)

  4783. #define FLEXRAM_INT_SIG_EN		(IMXRT_FLEXRAM.offset018)

  4784. #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON		((uint32_t)(1<<2))

  4785. #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN		((uint32_t)(1<<1))

  4786. #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN		((uint32_t)(1<<0))

  4787. #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS	((uint32_t)(1<<5))

  4788. #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS	((uint32_t)(1<<4))

  4789. #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS	((uint32_t)(1<<3))

  4790. #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN	((uint32_t)(1<<5))

  4791. #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN	((uint32_t)(1<<4))

  4792. #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN	((uint32_t)(1<<3))

  4793. #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN	((uint32_t)(1<<5))

  4794. #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN	((uint32_t)(1<<4))

  4795. #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN	((uint32_t)(1<<3))

  4796. 

  4797. // 27.7.2.1: page 1695

  4798. #define IMXRT_FLEXSPI		(*(IMXRT_REGISTER32_t *)0x402A8000)

  4799. #define FLEXSPI_MCR0			(IMXRT_FLEXSPI.offset000)

  4800. #define FLEXSPI_MCR0_AHBGRANTWAIT(n)		((uint32_t)(((n) & 0xFF) << 24))

  4801. #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK		((uint32_t)(0xFF << 24))

  4802. #define FLEXSPI_MCR0_IPGRANTWAIT(n)		((uint32_t)(((n) & 0xFF) << 16))

  4803. #define FLEXSPI_MCR0_IPGRANTWAIT_MASK		((uint32_t)(0xFF << 16))

  4804. #define FLEXSPI_MCR0_SCKFREERUNEN		((uint32_t)(1<<14))

  4805. #define FLEXSPI_MCR0_COMBINATIONEN		((uint32_t)(1<<13))

  4806. #define FLEXSPI_MCR0_DOZEEN			((uint32_t)(1<<12))

  4807. #define FLEXSPI_MCR0_HSEN			((uint32_t)(1<<11))

  4808. #define FLEXSPI_MCR0_ATDFEN			((uint32_t)(1<<7))

  4809. #define FLEXSPI_MCR0_ARDFEN			((uint32_t)(1<<6))

  4810. #define FLEXSPI_MCR0_RXCLKSRC(n)		((uint32_t)(((n) & 0x03) << 4))

  4811. #define FLEXSPI_MCR0_RXCLKSRC_MASK		((uint32_t)(0x03 << 4))

  4812. #define FLEXSPI_MCR0_MDIS			((uint32_t)(1<<1))

  4813. #define FLEXSPI_MCR0_SWRESET			((uint32_t)(1<<0))

  4814. #define FLEXSPI_MCR1			(IMXRT_FLEXSPI.offset004)

  4815. #define FLEXSPI_MCR1_SEQWAIT(n)			((uint32_t)(((n) & 0xFFFF) << 16))

  4816. #define FLEXSPI_MCR1_AHBBUSWAIT(n)		((uint32_t)(((n) & 0xFFFF) << 0))

  4817. #define FLEXSPI_MCR2			(IMXRT_FLEXSPI.offset008)

  4818. #define FLEXSPI_MCR2_RESUMEWAIT(n)		((uint32_t)(((n) & 0xFF) << 24))

  4819. #define FLEXSPI_MCR2_RESUMEWAIT_MASK		((uint32_t)(0xFF << 24))

  4820. #define FLEXSPI_MCR2_SCKBDIFFOPT		((uint32_t)(1<<19))

  4821. #define FLEXSPI_MCR2_SAMEDEVICEEN		((uint32_t)(1<<15))

  4822. #define FLEXSPI_MCR2_CLRLEARNPHASE		((uint32_t)(1<<14))

  4823. #define FLEXSPI_MCR2_CLRAHBBUFOPT		((uint32_t)(1<<11))

  4824. #define FLEXSPI_AHBCR			(IMXRT_FLEXSPI.offset00C)

  4825. #define FLEXSPI_AHBCR_READADDROPT		((uint32_t)(1<<6))

  4826. #define FLEXSPI_AHBCR_PREFETCHEN		((uint32_t)(1<<5))

  4827. #define FLEXSPI_AHBCR_BUFFERABLEEN		((uint32_t)(1<<4))

  4828. #define FLEXSPI_AHBCR_CACHABLEEN		((uint32_t)(1<<3))

  4829. #define FLEXSPI_AHBCR_APAREN			((uint32_t)(1<<0))

  4830. #define FLEXSPI_INTEN			(IMXRT_FLEXSPI.offset010)

  4831. #define FLEXSPI_INTEN_SEQTIMEOUTEN		((uint32_t)(1<<11))

  4832. #define FLEXSPI_INTEN_AHBBUSTIMEOUTEN		((uint32_t)(1<<10))

  4833. #define FLEXSPI_INTEN_SCKSTOPBYWREN		((uint32_t)(1<<9))

  4834. #define FLEXSPI_INTEN_SCKSTOPBYRDEN		((uint32_t)(1<<8))

  4835. #define FLEXSPI_INTEN_IPTXWEEN			((uint32_t)(1<<6))

  4836. #define FLEXSPI_INTEN_IPRXWAEN			((uint32_t)(1<<5))

  4837. #define FLEXSPI_INTEN_AHBCMDERREN		((uint32_t)(1<<4))

  4838. #define FLEXSPI_INTEN_IPCMDERREN		((uint32_t)(1<<3))

  4839. #define FLEXSPI_INTEN_AHBCMDGEEN		((uint32_t)(1<<2))

  4840. #define FLEXSPI_INTEN_IPCMDGEEN			((uint32_t)(1<<1))

  4841. #define FLEXSPI_INTEN_IPCMDDONEEN		((uint32_t)(1<<0))

  4842. #define FLEXSPI_INTR			(IMXRT_FLEXSPI.offset014)

  4843. #define FLEXSPI_INTR_SEQTIMEOUT			((uint32_t)(1<<11))

  4844. #define FLEXSPI_INTR_AHBBUSTIMEOUT		((uint32_t)(1<<10))

  4845. #define FLEXSPI_INTR_SCKSTOPBYWR		((uint32_t)(1<<9))

  4846. #define FLEXSPI_INTR_SCKSTOPBYRD		((uint32_t)(1<<8))

  4847. #define FLEXSPI_INTR_IPTXWE			((uint32_t)(1<<6))

  4848. #define FLEXSPI_INTR_IPRXWA			((uint32_t)(1<<5))

  4849. #define FLEXSPI_INTR_AHBCMDERR			((uint32_t)(1<<4))

  4850. #define FLEXSPI_INTR_IPCMDERR			((uint32_t)(1<<3))

  4851. #define FLEXSPI_INTR_AHBCMDGE			((uint32_t)(1<<2))

  4852. #define FLEXSPI_INTR_IPCMDGE			((uint32_t)(1<<1))

  4853. #define FLEXSPI_INTR_IPCMDDONE			((uint32_t)(1<<0))

  4854. #define FLEXSPI_LUTKEY			(IMXRT_FLEXSPI.offset018)

  4855. #define FLEXSPI_LUTKEY_VALUE			((uint32_t)0x5AF05AF0)

  4856. #define FLEXSPI_LUTCR			(IMXRT_FLEXSPI.offset01C)

  4857. #define FLEXSPI_LUTCR_UNLOCK			((uint32_t)(1<<1))

  4858. #define FLEXSPI_LUTCR_LOCK			((uint32_t)(1<<0))

  4859. #define FLEXSPI_AHBRXBUF0CR0		(IMXRT_FLEXSPI.offset020)

  4860. #define FLEXSPI_AHBRXBUF1CR0		(IMXRT_FLEXSPI.offset024)

  4861. #define FLEXSPI_AHBRXBUF2CR0		(IMXRT_FLEXSPI.offset028)

  4862. #define FLEXSPI_AHBRXBUF3CR0		(IMXRT_FLEXSPI.offset02C)

  4863. #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN		((uint32_t)(1<<31))

  4864. #define FLEXSPI_AHBRXBUFCR0_PRIORITY(n)		((uint32_t)(((n) & 0x03) << 24))

  4865. #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK	((uint32_t)((0x03) << 24))

  4866. #define FLEXSPI_AHBRXBUFCR0_MSTRID(n)		((uint32_t)(((n) & 0x0F) << 16))

  4867. #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK		((uint32_t)((0x0F) << 16))

  4868. #define FLEXSPI_AHBRXBUFCR0_BUFSZ(n)		((uint32_t)(((n) & 0xFF) << 0))

  4869. #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK		((uint32_t)((0xFF) << 0))

  4870. #define FLEXSPI_FLSHA1CR0		(IMXRT_FLEXSPI.offset060)

  4871. #define FLEXSPI_FLSHA2CR0		(IMXRT_FLEXSPI.offset064)

  4872. #define FLEXSPI_FLSHB1CR0		(IMXRT_FLEXSPI.offset068)

  4873. #define FLEXSPI_FLSHB2CR0		(IMXRT_FLEXSPI.offset06C)

  4874. #define FLEXSPI_FLSHCR0_FLSHSZ(n)		((uint32_t)(((n) & 0x7FFFFF) << 0))

  4875. #define FLEXSPI_FLSHCR0_FLSHSZ_MASK		((uint32_t)((0x7FFFFF) << 0))

  4876. #define FLEXSPI_FLSHA1CR1		(IMXRT_FLEXSPI.offset070)

  4877. #define FLEXSPI_FLSHA2CR1		(IMXRT_FLEXSPI.offset074)

  4878. #define FLEXSPI_FLSHB1CR1		(IMXRT_FLEXSPI.offset078)

  4879. #define FLEXSPI_FLSHB2CR1		(IMXRT_FLEXSPI.offset07C)

  4880. #define FLEXSPI_FLSHCR1_CSINTERVAL(n)		((uint32_t)(((n) & 0xFFFF) << 16))

  4881. #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK		((uint32_t)((0xFFFF) << 16))

  4882. #define FLEXSPI_FLSHCR1_CSINTERVALUNIT		((uint32_t)(1<<15))

  4883. #define FLEXSPI_FLSHCR1_CAS(n)			((uint32_t)(((n) & 0x0F) << 11))

  4884. #define FLEXSPI_FLSHCR1_WA			((uint32_t)(1<<10))

  4885. #define FLEXSPI_FLSHCR1_TCSH(n)			((uint32_t)(((n) & 0x1F) << 5))

  4886. #define FLEXSPI_FLSHCR1_TCSH_MASK		((uint32_t)((0x1F) << 5))

  4887. #define FLEXSPI_FLSHCR1_TCSS(n)			((uint32_t)(((n) & 0x1F) << 0))

  4888. #define FLEXSPI_FLSHCR1_TCSS_MASK		((uint32_t)((0x1F) << 0))

  4889. #define FLEXSPI_FLSHA1CR2		(IMXRT_FLEXSPI.offset080)

  4890. #define FLEXSPI_FLSHA2CR2		(IMXRT_FLEXSPI.offset084)

  4891. #define FLEXSPI_FLSHB1CR2		(IMXRT_FLEXSPI.offset088)

  4892. #define FLEXSPI_FLSHB2CR2		(IMXRT_FLEXSPI.offset08C)

  4893. #define FLEXSPI_FLSHCR2_CLRINSTRPTR		((uint32_t)(1<<31))

  4894. #define FLEXSPI_FLSHCR2_AWRWAITUNIT(n)		((uint32_t)(((n) & 0x07) << 28))

  4895. #define FLEXSPI_FLSHCR2_AWRWAIT(n)		((uint32_t)(((n) & 0xFFF) << 16))

  4896. #define FLEXSPI_FLSHCR2_AWRSEQNUM(n)		((uint32_t)(((n) & 0x07) << 13))

  4897. #define FLEXSPI_FLSHCR2_AWRSEQID(n)		((uint32_t)(((n) & 0x0F) << 8))

  4898. #define FLEXSPI_FLSHCR2_ARDSEQNUM(n)		((uint32_t)(((n) & 0x07) << 5))

  4899. #define FLEXSPI_FLSHCR2_ARDSEQID(n)		((uint32_t)(((n) & 0x0F) << 0))

  4900. #define FLEXSPI_FLSHCR4			(IMXRT_FLEXSPI.offset094)

  4901. #define FLEXSPI_FLSHCR4_WMENB			((uint32_t)(1<<3))

  4902. #define FLEXSPI_FLSHCR4_WMENA			((uint32_t)(1<<2))

  4903. #define FLEXSPI_FLSHCR4_WMOPT1			((uint32_t)(1<<0))

  4904. #define FLEXSPI_IPCR0			(IMXRT_FLEXSPI.offset0A0)

  4905. #define FLEXSPI_IPCR0_SFAR(n)			((uint32_t)(n))

  4906. #define FLEXSPI_IPCR1			(IMXRT_FLEXSPI.offset0A4)

  4907. #define FLEXSPI_IPCR1_IPAREN			((uint32_t)(1<<31))

  4908. #define FLEXSPI_IPCR1_ISEQNUM(n)		((uint32_t)(((n) & 0x07) << 24))

  4909. #define FLEXSPI_IPCR1_ISEQID(n)			((uint32_t)(((n) & 0x0F) << 16))

  4910. #define FLEXSPI_IPCR1_IDATSZ(n)			((uint32_t)(((n) & 0xFFFF) << 0))

  4911. #define FLEXSPI_IPCMD			(IMXRT_FLEXSPI.offset0B0)

  4912. #define FLEXSPI_IPCMD_TRG			((uint32_t)(1<<0))

  4913. #define FLEXSPI_IPRXFCR			(IMXRT_FLEXSPI.offset0B8)

  4914. #define FLEXSPI_IPRXFCR_RXWMRK(n)		((uint32_t)(((n) & 0x0F) << 2))

  4915. #define FLEXSPI_IPRXFCR_RXDMAEN			((uint32_t)(1<<1))

  4916. #define FLEXSPI_IPRXFCR_CLRIPRXF		((uint32_t)(1<<0))

  4917. #define FLEXSPI_IPTXFCR			(IMXRT_FLEXSPI.offset0BC)

  4918. #define FLEXSPI_IPTXFCR_TXWMRK(n)		((uint32_t)(((n) & 0x0F) << 2))

  4919. #define FLEXSPI_IPTXFCR_TXDMAEN			((uint32_t)(1<<1))

  4920. #define FLEXSPI_IPTXFCR_CLRIPTXF		((uint32_t)(1<<0))

  4921. #define FLEXSPI_DLLACR			(IMXRT_FLEXSPI.offset0C0)

  4922. #define FLEXSPI_DLLBCR			(IMXRT_FLEXSPI.offset0C4)

  4923. #define FLEXSPI_DLLCR_OVRDVAL(n)		((uint32_t)(((n) & 0x3F) << 9))

  4924. #define FLEXSPI_DLLCR_OVRDEN			((uint32_t)(1<<8))

  4925. #define FLEXSPI_DLLCR_SLVDLYTARGET(n)		((uint32_t)(((n) & 0x0F) << 3))

  4926. #define FLEXSPI_DLLCR_DLLRESET			((uint32_t)(1<<1))

  4927. #define FLEXSPI_DLLCR_DLLEN			((uint32_t)(1<<0))

  4928. #define FLEXSPI_STS0			(IMXRT_FLEXSPI.offset0E0)

  4929. #define FLEXSPI_STS0_ARBCMDSRC(n)		((uint32_t)(((n) & 0x03) << 2))

  4930. #define FLEXSPI_STS0_ARBIDLE			((uint32_t)(1<<1))

  4931. #define FLEXSPI_STS0_SEQIDLE			((uint32_t)(1<<0))

  4932. #define FLEXSPI_STS1			(IMXRT_FLEXSPI.offset0E4)

  4933. #define FLEXSPI_STS1_IPCMDERRCODE(n)		((uint32_t)(((n) & 0x0F) << 24))

  4934. #define FLEXSPI_STS1_IPCMDERRID(n)		((uint32_t)(((n) & 0x0F) << 16))

  4935. #define FLEXSPI_STS1_AHBCMDERRCODE(n)		((uint32_t)(((n) & 0x0F) << 8))

  4936. #define FLEXSPI_STS1_AHBCMDERRID(n)		((uint32_t)(((n) & 0x0F) << 0))

  4937. #define FLEXSPI_STS2			(IMXRT_FLEXSPI.offset0E8)

  4938. #define FLEXSPI_STS2_BREFSEL(n)			((uint32_t)(((n) & 0x3F) << 24))

  4939. #define FLEXSPI_STS2_BSLVSEL(n)			((uint32_t)(((n) & 0x3F) << 18))

  4940. #define FLEXSPI_STS2_BREFLOCK			((uint32_t)(1<<17))

  4941. #define FLEXSPI_STS2_BSLVLOCK			((uint32_t)(1<<16))

  4942. #define FLEXSPI_STS2_AREFSEL(n)			((uint32_t)(((n) & 0x3F) << 8))

  4943. #define FLEXSPI_STS2_ASLVSEL(n)			((uint32_t)(((n) & 0x3F) << 2))

  4944. #define FLEXSPI_STS2_AREFLOCK			((uint32_t)(1<<1))

  4945. #define FLEXSPI_STS2_ASLVLOCK			((uint32_t)(1<<0))

  4946. #define FLEXSPI_AHBSPNDSTS		(IMXRT_FLEXSPI.offset0EC)

  4947. #define FLEXSPI_AHBSPNDSTS_DATLFT(n)		((uint32_t)(((n) & 0xFFFF) << 16))

  4948. #define FLEXSPI_AHBSPNDSTS_BUFID(n)		((uint32_t)(((n) & 0x7) << 1))

  4949. #define FLEXSPI_AHBSPNDSTS_ACTIVE		((uint32_t)(1<<0))

  4950. #define FLEXSPI_IPRXFSTS		(IMXRT_FLEXSPI.offset0F0)

  4951. #define FLEXSPI_IPRXFSTS_RDCNTR(n)		((uint32_t)(((n) & 0xFFFF) << 16))

  4952. #define FLEXSPI_IPRXFSTS_FILL(n)		((uint32_t)(((n) & 0xFF) << 0))

  4953. #define FLEXSPI_IPTXFSTS		(IMXRT_FLEXSPI.offset0F4)

  4954. #define FLEXSPI_IPTXFSTS_WRCNTR(n)		((uint32_t)(((n) & 0xFFFF) << 16))

  4955. #define FLEXSPI_IPTXFSTS_FILL(n)		((uint32_t)(((n) & 0xFF) << 0))

  4956. #define FLEXSPI_RFDR0			(IMXRT_FLEXSPI.offset100)

  4957. #define FLEXSPI_RFDR1			(IMXRT_FLEXSPI.offset104)

  4958. #define FLEXSPI_RFDR2			(IMXRT_FLEXSPI.offset108)

  4959. #define FLEXSPI_RFDR3			(IMXRT_FLEXSPI.offset10C)

  4960. #define FLEXSPI_RFDR4			(IMXRT_FLEXSPI.offset110)

  4961. #define FLEXSPI_RFDR5			(IMXRT_FLEXSPI.offset114)

  4962. #define FLEXSPI_RFDR6			(IMXRT_FLEXSPI.offset118)

  4963. #define FLEXSPI_RFDR7			(IMXRT_FLEXSPI.offset11C)

  4964. #define FLEXSPI_RFDR8			(IMXRT_FLEXSPI.offset120)

  4965. #define FLEXSPI_RFDR9			(IMXRT_FLEXSPI.offset124)

  4966. #define FLEXSPI_RFDR10			(IMXRT_FLEXSPI.offset128)

  4967. #define FLEXSPI_RFDR11			(IMXRT_FLEXSPI.offset12C)

  4968. #define FLEXSPI_RFDR12			(IMXRT_FLEXSPI.offset130)

  4969. #define FLEXSPI_RFDR13			(IMXRT_FLEXSPI.offset134)

  4970. #define FLEXSPI_RFDR14			(IMXRT_FLEXSPI.offset138)

  4971. #define FLEXSPI_RFDR15			(IMXRT_FLEXSPI.offset13C)

  4972. #define FLEXSPI_RFDR16			(IMXRT_FLEXSPI.offset140)

  4973. #define FLEXSPI_RFDR17			(IMXRT_FLEXSPI.offset144)

  4974. #define FLEXSPI_RFDR18			(IMXRT_FLEXSPI.offset148)

  4975. #define FLEXSPI_RFDR19			(IMXRT_FLEXSPI.offset14C)

  4976. #define FLEXSPI_RFDR20			(IMXRT_FLEXSPI.offset150)

  4977. #define FLEXSPI_RFDR21			(IMXRT_FLEXSPI.offset154)

  4978. #define FLEXSPI_RFDR22			(IMXRT_FLEXSPI.offset158)

  4979. #define FLEXSPI_RFDR23			(IMXRT_FLEXSPI.offset15C)

  4980. #define FLEXSPI_RFDR24			(IMXRT_FLEXSPI.offset160)

  4981. #define FLEXSPI_RFDR25			(IMXRT_FLEXSPI.offset164)

  4982. #define FLEXSPI_RFDR26			(IMXRT_FLEXSPI.offset168)

  4983. #define FLEXSPI_RFDR27			(IMXRT_FLEXSPI.offset16C)

  4984. #define FLEXSPI_RFDR28			(IMXRT_FLEXSPI.offset170)

  4985. #define FLEXSPI_RFDR29			(IMXRT_FLEXSPI.offset174)

  4986. #define FLEXSPI_RFDR30			(IMXRT_FLEXSPI.offset178)

  4987. #define FLEXSPI_RFDR31			(IMXRT_FLEXSPI.offset17C)

  4988. #define FLEXSPI_TFDR0			(IMXRT_FLEXSPI.offset180)

  4989. #define FLEXSPI_TFDR1			(IMXRT_FLEXSPI.offset184)

  4990. #define FLEXSPI_TFDR2			(IMXRT_FLEXSPI.offset188)

  4991. #define FLEXSPI_TFDR3			(IMXRT_FLEXSPI.offset18C)

  4992. #define FLEXSPI_TFDR4			(IMXRT_FLEXSPI.offset190)

  4993. #define FLEXSPI_TFDR5			(IMXRT_FLEXSPI.offset194)

  4994. #define FLEXSPI_TFDR6			(IMXRT_FLEXSPI.offset198)

  4995. #define FLEXSPI_TFDR7			(IMXRT_FLEXSPI.offset19C)

  4996. #define FLEXSPI_TFDR8			(IMXRT_FLEXSPI.offset1A0)

  4997. #define FLEXSPI_TFDR9			(IMXRT_FLEXSPI.offset1A4)

  4998. #define FLEXSPI_TFDR10			(IMXRT_FLEXSPI.offset1A8)

  4999. #define FLEXSPI_TFDR11			(IMXRT_FLEXSPI.offset1AC)

  5000. #define FLEXSPI_TFDR12			(IMXRT_FLEXSPI.offset1B0)

  5001. #define FLEXSPI_TFDR13			(IMXRT_FLEXSPI.offset1B4)

  5002. #define FLEXSPI_TFDR14			(IMXRT_FLEXSPI.offset1B8)

  5003. #define FLEXSPI_TFDR15			(IMXRT_FLEXSPI.offset1BC)

  5004. #define FLEXSPI_TFDR16			(IMXRT_FLEXSPI.offset1C0)

  5005. #define FLEXSPI_TFDR17			(IMXRT_FLEXSPI.offset1C4)

  5006. #define FLEXSPI_TFDR18			(IMXRT_FLEXSPI.offset1C8)

  5007. #define FLEXSPI_TFDR19			(IMXRT_FLEXSPI.offset1CC)

  5008. #define FLEXSPI_TFDR20			(IMXRT_FLEXSPI.offset1D0)

  5009. #define FLEXSPI_TFDR21			(IMXRT_FLEXSPI.offset1D4)

  5010. #define FLEXSPI_TFDR22			(IMXRT_FLEXSPI.offset1D8)

  5011. #define FLEXSPI_TFDR23			(IMXRT_FLEXSPI.offset1DC)

  5012. #define FLEXSPI_TFDR24			(IMXRT_FLEXSPI.offset1E0)

  5013. #define FLEXSPI_TFDR25			(IMXRT_FLEXSPI.offset1E4)

  5014. #define FLEXSPI_TFDR26			(IMXRT_FLEXSPI.offset1E8)

  5015. #define FLEXSPI_TFDR27			(IMXRT_FLEXSPI.offset1EC)

  5016. #define FLEXSPI_TFDR28			(IMXRT_FLEXSPI.offset1F0)

  5017. #define FLEXSPI_TFDR29			(IMXRT_FLEXSPI.offset1F4)

  5018. #define FLEXSPI_TFDR30			(IMXRT_FLEXSPI.offset1F8)

  5019. #define FLEXSPI_TFDR31			(IMXRT_FLEXSPI.offset1FC)

  5020. #define FLEXSPI_LUT0			(IMXRT_FLEXSPI.offset200)

  5021. #define FLEXSPI_LUT1			(IMXRT_FLEXSPI.offset204)

  5022. #define FLEXSPI_LUT2			(IMXRT_FLEXSPI.offset208)

  5023. #define FLEXSPI_LUT3			(IMXRT_FLEXSPI.offset20C)

  5024. #define FLEXSPI_LUT4			(IMXRT_FLEXSPI.offset210)

  5025. #define FLEXSPI_LUT5			(IMXRT_FLEXSPI.offset214)

  5026. #define FLEXSPI_LUT6			(IMXRT_FLEXSPI.offset218)

  5027. #define FLEXSPI_LUT7			(IMXRT_FLEXSPI.offset21C)

  5028. #define FLEXSPI_LUT8			(IMXRT_FLEXSPI.offset220)

  5029. #define FLEXSPI_LUT9			(IMXRT_FLEXSPI.offset224)

  5030. #define FLEXSPI_LUT10			(IMXRT_FLEXSPI.offset228)

  5031. #define FLEXSPI_LUT11			(IMXRT_FLEXSPI.offset22C)

  5032. #define FLEXSPI_LUT12			(IMXRT_FLEXSPI.offset230)

  5033. #define FLEXSPI_LUT13			(IMXRT_FLEXSPI.offset234)

  5034. #define FLEXSPI_LUT14			(IMXRT_FLEXSPI.offset238)

  5035. #define FLEXSPI_LUT15			(IMXRT_FLEXSPI.offset23C)

  5036. #define FLEXSPI_LUT16			(IMXRT_FLEXSPI.offset240)

  5037. #define FLEXSPI_LUT17			(IMXRT_FLEXSPI.offset244)

  5038. #define FLEXSPI_LUT18			(IMXRT_FLEXSPI.offset248)

  5039. #define FLEXSPI_LUT19			(IMXRT_FLEXSPI.offset24C)

  5040. #define FLEXSPI_LUT20			(IMXRT_FLEXSPI.offset250)

  5041. #define FLEXSPI_LUT21			(IMXRT_FLEXSPI.offset254)

  5042. #define FLEXSPI_LUT22			(IMXRT_FLEXSPI.offset258)

  5043. #define FLEXSPI_LUT23			(IMXRT_FLEXSPI.offset25C)

  5044. #define FLEXSPI_LUT24			(IMXRT_FLEXSPI.offset260)

  5045. #define FLEXSPI_LUT25			(IMXRT_FLEXSPI.offset264)

  5046. #define FLEXSPI_LUT26			(IMXRT_FLEXSPI.offset268)

  5047. #define FLEXSPI_LUT27			(IMXRT_FLEXSPI.offset26C)

  5048. #define FLEXSPI_LUT28			(IMXRT_FLEXSPI.offset270)

  5049. #define FLEXSPI_LUT29			(IMXRT_FLEXSPI.offset274)

  5050. #define FLEXSPI_LUT30			(IMXRT_FLEXSPI.offset278)

  5051. #define FLEXSPI_LUT31			(IMXRT_FLEXSPI.offset27C)

  5052. #define FLEXSPI_LUT32			(IMXRT_FLEXSPI.offset280)

  5053. #define FLEXSPI_LUT33			(IMXRT_FLEXSPI.offset284)

  5054. #define FLEXSPI_LUT34			(IMXRT_FLEXSPI.offset288)

  5055. #define FLEXSPI_LUT35			(IMXRT_FLEXSPI.offset28C)

  5056. #define FLEXSPI_LUT36			(IMXRT_FLEXSPI.offset290)

  5057. #define FLEXSPI_LUT37			(IMXRT_FLEXSPI.offset294)

  5058. #define FLEXSPI_LUT38			(IMXRT_FLEXSPI.offset298)

  5059. #define FLEXSPI_LUT39			(IMXRT_FLEXSPI.offset29C)

  5060. #define FLEXSPI_LUT40			(IMXRT_FLEXSPI.offset2A0)

  5061. #define FLEXSPI_LUT41			(IMXRT_FLEXSPI.offset2A4)

  5062. #define FLEXSPI_LUT42			(IMXRT_FLEXSPI.offset2A8)

  5063. #define FLEXSPI_LUT43			(IMXRT_FLEXSPI.offset2AC)

  5064. #define FLEXSPI_LUT44			(IMXRT_FLEXSPI.offset2B0)

  5065. #define FLEXSPI_LUT45			(IMXRT_FLEXSPI.offset2B4)

  5066. #define FLEXSPI_LUT46			(IMXRT_FLEXSPI.offset2B8)

  5067. #define FLEXSPI_LUT47			(IMXRT_FLEXSPI.offset2BC)

  5068. #define FLEXSPI_LUT48			(IMXRT_FLEXSPI.offset2C0)

  5069. #define FLEXSPI_LUT49			(IMXRT_FLEXSPI.offset2C4)

  5070. #define FLEXSPI_LUT50			(IMXRT_FLEXSPI.offset2C8)

  5071. #define FLEXSPI_LUT51			(IMXRT_FLEXSPI.offset2CC)

  5072. #define FLEXSPI_LUT52			(IMXRT_FLEXSPI.offset2D0)

  5073. #define FLEXSPI_LUT53			(IMXRT_FLEXSPI.offset2D4)

  5074. #define FLEXSPI_LUT54			(IMXRT_FLEXSPI.offset2D8)

  5075. #define FLEXSPI_LUT55			(IMXRT_FLEXSPI.offset2DC)

  5076. #define FLEXSPI_LUT56			(IMXRT_FLEXSPI.offset2E0)

  5077. #define FLEXSPI_LUT57			(IMXRT_FLEXSPI.offset2E4)

  5078. #define FLEXSPI_LUT58			(IMXRT_FLEXSPI.offset2E8)

  5079. #define FLEXSPI_LUT59			(IMXRT_FLEXSPI.offset2EC)

  5080. #define FLEXSPI_LUT60			(IMXRT_FLEXSPI.offset2F0)

  5081. #define FLEXSPI_LUT61			(IMXRT_FLEXSPI.offset2F4)

  5082. #define FLEXSPI_LUT62			(IMXRT_FLEXSPI.offset2F8)

  5083. #define FLEXSPI_LUT63			(IMXRT_FLEXSPI.offset2FC)

  5084. #define FLEXSPI_LUT_OPCODE1(n)			((uint32_t)(((n) & 0x3F) << 26))

  5085. #define FLEXSPI_LUT_NUM_PADS1(n)		((uint32_t)(((n) & 0x03) << 24))

  5086. #define FLEXSPI_LUT_OPERAND1(n)			((uint32_t)(((n) & 0xFF) << 16))

  5087. #define FLEXSPI_LUT_OPCODE0(n)			((uint32_t)(((n) & 0x3F) << 10))

  5088. #define FLEXSPI_LUT_NUM_PADS0(n)		((uint32_t)(((n) & 0x03) << 8))

  5089. #define FLEXSPI_LUT_OPERAND0(n)			((uint32_t)(((n) & 0xFF) << 0))

  5090. #define FLEXSPI_LUT_INSTRUCTION(opcode, pads, operand) ((uint32_t)(\

  5091. 	(((opcode) & 0x3F) << 10) | (((pads) & 0x03) << 8) | ((operand) & 0xFF)))

  5092. // 30.7.8: page 1637

  5093. #define FLEXSPI_LUT_OPCODE_CMD_SDR		0x01

  5094. #define FLEXSPI_LUT_OPCODE_CMD_DDR		0x21

  5095. #define FLEXSPI_LUT_OPCODE_RADDR_SDR		0x02

  5096. #define FLEXSPI_LUT_OPCODE_RADDR_DDR		0x22

  5097. #define FLEXSPI_LUT_OPCODE_CADDR_SDR		0x03

  5098. #define FLEXSPI_LUT_OPCODE_CADDR_DDR		0x23

  5099. #define FLEXSPI_LUT_OPCODE_MODE1_SDR		0x04

  5100. #define FLEXSPI_LUT_OPCODE_MODE1_DDR		0x24

  5101. #define FLEXSPI_LUT_OPCODE_MODE2_SDR		0x05

  5102. #define FLEXSPI_LUT_OPCODE_MODE2_DDR		0x25

  5103. #define FLEXSPI_LUT_OPCODE_MODE4_SDR		0x06

  5104. #define FLEXSPI_LUT_OPCODE_MODE4_DDR		0x26

  5105. #define FLEXSPI_LUT_OPCODE_MODE8_SDR		0x07

  5106. #define FLEXSPI_LUT_OPCODE_MODE8_DDR		0x27

  5107. #define FLEXSPI_LUT_OPCODE_WRITE_SDR		0x08

  5108. #define FLEXSPI_LUT_OPCODE_WRITE_DDR		0x28

  5109. #define FLEXSPI_LUT_OPCODE_READ_SDR		0x09

  5110. #define FLEXSPI_LUT_OPCODE_READ_DDR		0x29

  5111. #define FLEXSPI_LUT_OPCODE_LEARN_SDR		0x0A

  5112. #define FLEXSPI_LUT_OPCODE_LEARN_DDR		0x2A

  5113. #define FLEXSPI_LUT_OPCODE_DATSZ_SDR		0x0B

  5114. #define FLEXSPI_LUT_OPCODE_DATSZ_DDR		0x2B

  5115. #define FLEXSPI_LUT_OPCODE_DUMMY_SDR		0x0C

  5116. #define FLEXSPI_LUT_OPCODE_DUMMY_DDR		0x2C

  5117. #define FLEXSPI_LUT_OPCODE_DUMMY_RWDS_SDR	0x0D

  5118. #define FLEXSPI_LUT_OPCODE_DUMMY_RWDS_DDR	0x2D

  5119. #define FLEXSPI_LUT_OPCODE_JMP_ON_CS		0x1F

  5120. #define FLEXSPI_LUT_OPCODE_STOP			0x00

  5121. #define FLEXSPI_LUT_NUM_PADS_1			0x00

  5122. #define FLEXSPI_LUT_NUM_PADS_2			0x01

  5123. #define FLEXSPI_LUT_NUM_PADS_4			0x02

  5124. #define FLEXSPI_LUT_NUM_PADS_8			0x03

  5125. 

  5126. #define IMXRT_FLEXSPI2		(*(IMXRT_REGISTER32_t *)0x402A4000)

  5127. #define FLEXSPI2_MCR0			(IMXRT_FLEXSPI2.offset000)

  5128. #define FLEXSPI2_MCR1			(IMXRT_FLEXSPI2.offset004)

  5129. #define FLEXSPI2_MCR2			(IMXRT_FLEXSPI2.offset008)

  5130. #define FLEXSPI2_AHBCR			(IMXRT_FLEXSPI2.offset00C)

  5131. #define FLEXSPI2_INTEN			(IMXRT_FLEXSPI2.offset010)

  5132. #define FLEXSPI2_INTR			(IMXRT_FLEXSPI2.offset014)

  5133. #define FLEXSPI2_LUTKEY			(IMXRT_FLEXSPI2.offset018)

  5134. #define FLEXSPI2_LUTCR			(IMXRT_FLEXSPI2.offset01C)

  5135. #define FLEXSPI2_AHBRXBUF0CR0		(IMXRT_FLEXSPI2.offset020)

  5136. #define FLEXSPI2_AHBRXBUF1CR0		(IMXRT_FLEXSPI2.offset024)

  5137. #define FLEXSPI2_AHBRXBUF2CR0		(IMXRT_FLEXSPI2.offset028)

  5138. #define FLEXSPI2_AHBRXBUF3CR0		(IMXRT_FLEXSPI2.offset02C)

  5139. #define FLEXSPI2_FLSHA1CR0		(IMXRT_FLEXSPI2.offset060)

  5140. #define FLEXSPI2_FLSHA2CR0		(IMXRT_FLEXSPI2.offset064)

  5141. #define FLEXSPI2_FLSHB1CR0		(IMXRT_FLEXSPI2.offset068)

  5142. #define FLEXSPI2_FLSHB2CR0		(IMXRT_FLEXSPI2.offset06C)

  5143. #define FLEXSPI2_FLSHA1CR1		(IMXRT_FLEXSPI2.offset070)

  5144. #define FLEXSPI2_FLSHA2CR1		(IMXRT_FLEXSPI2.offset074)

  5145. #define FLEXSPI2_FLSHB1CR1		(IMXRT_FLEXSPI2.offset078)

  5146. #define FLEXSPI2_FLSHB2CR1		(IMXRT_FLEXSPI2.offset07C)

  5147. #define FLEXSPI2_FLSHA1CR2		(IMXRT_FLEXSPI2.offset080)

  5148. #define FLEXSPI2_FLSHA2CR2		(IMXRT_FLEXSPI2.offset084)

  5149. #define FLEXSPI2_FLSHB1CR2		(IMXRT_FLEXSPI2.offset088)

  5150. #define FLEXSPI2_FLSHB2CR2		(IMXRT_FLEXSPI2.offset08C)

  5151. #define FLEXSPI2_FLSHCR4		(IMXRT_FLEXSPI2.offset094)

  5152. #define FLEXSPI2_IPCR0			(IMXRT_FLEXSPI2.offset0A0)

  5153. #define FLEXSPI2_IPCR1			(IMXRT_FLEXSPI2.offset0A4)

  5154. #define FLEXSPI2_IPCMD			(IMXRT_FLEXSPI2.offset0B0)

  5155. #define FLEXSPI2_IPRXFCR		(IMXRT_FLEXSPI2.offset0B8)

  5156. #define FLEXSPI2_IPTXFCR		(IMXRT_FLEXSPI2.offset0BC)

  5157. #define FLEXSPI2_DLLACR			(IMXRT_FLEXSPI2.offset0C0)

  5158. #define FLEXSPI2_DLLBCR			(IMXRT_FLEXSPI2.offset0C4)

  5159. #define FLEXSPI2_STS0			(IMXRT_FLEXSPI2.offset0E0)

  5160. #define FLEXSPI2_STS1			(IMXRT_FLEXSPI2.offset0E4)

  5161. #define FLEXSPI2_STS2			(IMXRT_FLEXSPI2.offset0E8)

  5162. #define FLEXSPI2_AHBSPNDSTS		(IMXRT_FLEXSPI2.offset0EC)

  5163. #define FLEXSPI2_IPRXFSTS		(IMXRT_FLEXSPI2.offset0F0)

  5164. #define FLEXSPI2_IPTXFSTS		(IMXRT_FLEXSPI2.offset0F4)

  5165. #define FLEXSPI2_RFDR0			(IMXRT_FLEXSPI2.offset100)

  5166. #define FLEXSPI2_RFDR1			(IMXRT_FLEXSPI2.offset104)

  5167. #define FLEXSPI2_RFDR2			(IMXRT_FLEXSPI2.offset108)

  5168. #define FLEXSPI2_RFDR3			(IMXRT_FLEXSPI2.offset10C)

  5169. #define FLEXSPI2_RFDR4			(IMXRT_FLEXSPI2.offset110)

  5170. #define FLEXSPI2_RFDR5			(IMXRT_FLEXSPI2.offset114)

  5171. #define FLEXSPI2_RFDR6			(IMXRT_FLEXSPI2.offset118)

  5172. #define FLEXSPI2_RFDR7			(IMXRT_FLEXSPI2.offset11C)

  5173. #define FLEXSPI2_RFDR8			(IMXRT_FLEXSPI2.offset120)

  5174. #define FLEXSPI2_RFDR9			(IMXRT_FLEXSPI2.offset124)

  5175. #define FLEXSPI2_RFDR10			(IMXRT_FLEXSPI2.offset128)

  5176. #define FLEXSPI2_RFDR11			(IMXRT_FLEXSPI2.offset12C)

  5177. #define FLEXSPI2_RFDR12			(IMXRT_FLEXSPI2.offset130)

  5178. #define FLEXSPI2_RFDR13			(IMXRT_FLEXSPI2.offset134)

  5179. #define FLEXSPI2_RFDR14			(IMXRT_FLEXSPI2.offset138)

  5180. #define FLEXSPI2_RFDR15			(IMXRT_FLEXSPI2.offset13C)

  5181. #define FLEXSPI2_RFDR16			(IMXRT_FLEXSPI2.offset140)

  5182. #define FLEXSPI2_RFDR17			(IMXRT_FLEXSPI2.offset144)

  5183. #define FLEXSPI2_RFDR18			(IMXRT_FLEXSPI2.offset148)

  5184. #define FLEXSPI2_RFDR19			(IMXRT_FLEXSPI2.offset14C)

  5185. #define FLEXSPI2_RFDR20			(IMXRT_FLEXSPI2.offset150)

  5186. #define FLEXSPI2_RFDR21			(IMXRT_FLEXSPI2.offset154)

  5187. #define FLEXSPI2_RFDR22			(IMXRT_FLEXSPI2.offset158)

  5188. #define FLEXSPI2_RFDR23			(IMXRT_FLEXSPI2.offset15C)

  5189. #define FLEXSPI2_RFDR24			(IMXRT_FLEXSPI2.offset160)

  5190. #define FLEXSPI2_RFDR25			(IMXRT_FLEXSPI2.offset164)

  5191. #define FLEXSPI2_RFDR26			(IMXRT_FLEXSPI2.offset168)

  5192. #define FLEXSPI2_RFDR27			(IMXRT_FLEXSPI2.offset16C)

  5193. #define FLEXSPI2_RFDR28			(IMXRT_FLEXSPI2.offset170)

  5194. #define FLEXSPI2_RFDR29			(IMXRT_FLEXSPI2.offset174)

  5195. #define FLEXSPI2_RFDR30			(IMXRT_FLEXSPI2.offset178)

  5196. #define FLEXSPI2_RFDR31			(IMXRT_FLEXSPI2.offset17C)

  5197. #define FLEXSPI2_TFDR0			(IMXRT_FLEXSPI2.offset180)

  5198. #define FLEXSPI2_TFDR1			(IMXRT_FLEXSPI2.offset184)

  5199. #define FLEXSPI2_TFDR2			(IMXRT_FLEXSPI2.offset188)

  5200. #define FLEXSPI2_TFDR3			(IMXRT_FLEXSPI2.offset18C)

  5201. #define FLEXSPI2_TFDR4			(IMXRT_FLEXSPI2.offset190)

  5202. #define FLEXSPI2_TFDR5			(IMXRT_FLEXSPI2.offset194)

  5203. #define FLEXSPI2_TFDR6			(IMXRT_FLEXSPI2.offset198)

  5204. #define FLEXSPI2_TFDR7			(IMXRT_FLEXSPI2.offset19C)

  5205. #define FLEXSPI2_TFDR8			(IMXRT_FLEXSPI2.offset1A0)

  5206. #define FLEXSPI2_TFDR9			(IMXRT_FLEXSPI2.offset1A4)

  5207. #define FLEXSPI2_TFDR10			(IMXRT_FLEXSPI2.offset1A8)

  5208. #define FLEXSPI2_TFDR11			(IMXRT_FLEXSPI2.offset1AC)

  5209. #define FLEXSPI2_TFDR12			(IMXRT_FLEXSPI2.offset1B0)

  5210. #define FLEXSPI2_TFDR13			(IMXRT_FLEXSPI2.offset1B4)

  5211. #define FLEXSPI2_TFDR14			(IMXRT_FLEXSPI2.offset1B8)

  5212. #define FLEXSPI2_TFDR15			(IMXRT_FLEXSPI2.offset1BC)

  5213. #define FLEXSPI2_TFDR16			(IMXRT_FLEXSPI2.offset1C0)

  5214. #define FLEXSPI2_TFDR17			(IMXRT_FLEXSPI2.offset1C4)

  5215. #define FLEXSPI2_TFDR18			(IMXRT_FLEXSPI2.offset1C8)

  5216. #define FLEXSPI2_TFDR19			(IMXRT_FLEXSPI2.offset1CC)

  5217. #define FLEXSPI2_TFDR20			(IMXRT_FLEXSPI2.offset1D0)

  5218. #define FLEXSPI2_TFDR21			(IMXRT_FLEXSPI2.offset1D4)

  5219. #define FLEXSPI2_TFDR22			(IMXRT_FLEXSPI2.offset1D8)

  5220. #define FLEXSPI2_TFDR23			(IMXRT_FLEXSPI2.offset1DC)

  5221. #define FLEXSPI2_TFDR24			(IMXRT_FLEXSPI2.offset1E0)

  5222. #define FLEXSPI2_TFDR25			(IMXRT_FLEXSPI2.offset1E4)

  5223. #define FLEXSPI2_TFDR26			(IMXRT_FLEXSPI2.offset1E8)

  5224. #define FLEXSPI2_TFDR27			(IMXRT_FLEXSPI2.offset1EC)

  5225. #define FLEXSPI2_TFDR28			(IMXRT_FLEXSPI2.offset1F0)

  5226. #define FLEXSPI2_TFDR29			(IMXRT_FLEXSPI2.offset1F4)

  5227. #define FLEXSPI2_TFDR30			(IMXRT_FLEXSPI2.offset1F8)

  5228. #define FLEXSPI2_TFDR31			(IMXRT_FLEXSPI2.offset1FC)

  5229. #define FLEXSPI2_LUT0			(IMXRT_FLEXSPI2.offset200)

  5230. #define FLEXSPI2_LUT1			(IMXRT_FLEXSPI2.offset204)

  5231. #define FLEXSPI2_LUT2			(IMXRT_FLEXSPI2.offset208)

  5232. #define FLEXSPI2_LUT3			(IMXRT_FLEXSPI2.offset20C)

  5233. #define FLEXSPI2_LUT4			(IMXRT_FLEXSPI2.offset210)

  5234. #define FLEXSPI2_LUT5			(IMXRT_FLEXSPI2.offset214)

  5235. #define FLEXSPI2_LUT6			(IMXRT_FLEXSPI2.offset218)

  5236. #define FLEXSPI2_LUT7			(IMXRT_FLEXSPI2.offset21C)

  5237. #define FLEXSPI2_LUT8			(IMXRT_FLEXSPI2.offset220)

  5238. #define FLEXSPI2_LUT9			(IMXRT_FLEXSPI2.offset224)

  5239. #define FLEXSPI2_LUT10			(IMXRT_FLEXSPI2.offset228)

  5240. #define FLEXSPI2_LUT11			(IMXRT_FLEXSPI2.offset22C)

  5241. #define FLEXSPI2_LUT12			(IMXRT_FLEXSPI2.offset230)

  5242. #define FLEXSPI2_LUT13			(IMXRT_FLEXSPI2.offset234)

  5243. #define FLEXSPI2_LUT14			(IMXRT_FLEXSPI2.offset238)

  5244. #define FLEXSPI2_LUT15			(IMXRT_FLEXSPI2.offset23C)

  5245. #define FLEXSPI2_LUT16			(IMXRT_FLEXSPI2.offset240)

  5246. #define FLEXSPI2_LUT17			(IMXRT_FLEXSPI2.offset244)

  5247. #define FLEXSPI2_LUT18			(IMXRT_FLEXSPI2.offset248)

  5248. #define FLEXSPI2_LUT19			(IMXRT_FLEXSPI2.offset24C)

  5249. #define FLEXSPI2_LUT20			(IMXRT_FLEXSPI2.offset250)

  5250. #define FLEXSPI2_LUT21			(IMXRT_FLEXSPI2.offset254)

  5251. #define FLEXSPI2_LUT22			(IMXRT_FLEXSPI2.offset258)

  5252. #define FLEXSPI2_LUT23			(IMXRT_FLEXSPI2.offset25C)

  5253. #define FLEXSPI2_LUT24			(IMXRT_FLEXSPI2.offset260)

  5254. #define FLEXSPI2_LUT25			(IMXRT_FLEXSPI2.offset264)

  5255. #define FLEXSPI2_LUT26			(IMXRT_FLEXSPI2.offset268)

  5256. #define FLEXSPI2_LUT27			(IMXRT_FLEXSPI2.offset26C)

  5257. #define FLEXSPI2_LUT28			(IMXRT_FLEXSPI2.offset270)

  5258. #define FLEXSPI2_LUT29			(IMXRT_FLEXSPI2.offset274)

  5259. #define FLEXSPI2_LUT30			(IMXRT_FLEXSPI2.offset278)

  5260. #define FLEXSPI2_LUT31			(IMXRT_FLEXSPI2.offset27C)

  5261. #define FLEXSPI2_LUT32			(IMXRT_FLEXSPI2.offset280)

  5262. #define FLEXSPI2_LUT33			(IMXRT_FLEXSPI2.offset284)

  5263. #define FLEXSPI2_LUT34			(IMXRT_FLEXSPI2.offset288)

  5264. #define FLEXSPI2_LUT35			(IMXRT_FLEXSPI2.offset28C)

  5265. #define FLEXSPI2_LUT36			(IMXRT_FLEXSPI2.offset290)

  5266. #define FLEXSPI2_LUT37			(IMXRT_FLEXSPI2.offset294)

  5267. #define FLEXSPI2_LUT38			(IMXRT_FLEXSPI2.offset298)

  5268. #define FLEXSPI2_LUT39			(IMXRT_FLEXSPI2.offset29C)

  5269. #define FLEXSPI2_LUT40			(IMXRT_FLEXSPI2.offset2A0)

  5270. #define FLEXSPI2_LUT41			(IMXRT_FLEXSPI2.offset2A4)

  5271. #define FLEXSPI2_LUT42			(IMXRT_FLEXSPI2.offset2A8)

  5272. #define FLEXSPI2_LUT43			(IMXRT_FLEXSPI2.offset2AC)

  5273. #define FLEXSPI2_LUT44			(IMXRT_FLEXSPI2.offset2B0)

  5274. #define FLEXSPI2_LUT45			(IMXRT_FLEXSPI2.offset2B4)

  5275. #define FLEXSPI2_LUT46			(IMXRT_FLEXSPI2.offset2B8)

  5276. #define FLEXSPI2_LUT47			(IMXRT_FLEXSPI2.offset2BC)

  5277. #define FLEXSPI2_LUT48			(IMXRT_FLEXSPI2.offset2C0)

  5278. #define FLEXSPI2_LUT49			(IMXRT_FLEXSPI2.offset2C4)

  5279. #define FLEXSPI2_LUT50			(IMXRT_FLEXSPI2.offset2C8)

  5280. #define FLEXSPI2_LUT51			(IMXRT_FLEXSPI2.offset2CC)

  5281. #define FLEXSPI2_LUT52			(IMXRT_FLEXSPI2.offset2D0)

  5282. #define FLEXSPI2_LUT53			(IMXRT_FLEXSPI2.offset2D4)

  5283. #define FLEXSPI2_LUT54			(IMXRT_FLEXSPI2.offset2D8)

  5284. #define FLEXSPI2_LUT55			(IMXRT_FLEXSPI2.offset2DC)

  5285. #define FLEXSPI2_LUT56			(IMXRT_FLEXSPI2.offset2E0)

  5286. #define FLEXSPI2_LUT57			(IMXRT_FLEXSPI2.offset2E4)

  5287. #define FLEXSPI2_LUT58			(IMXRT_FLEXSPI2.offset2E8)

  5288. #define FLEXSPI2_LUT59			(IMXRT_FLEXSPI2.offset2EC)

  5289. #define FLEXSPI2_LUT60			(IMXRT_FLEXSPI2.offset2F0)

  5290. #define FLEXSPI2_LUT61			(IMXRT_FLEXSPI2.offset2F4)

  5291. #define FLEXSPI2_LUT62			(IMXRT_FLEXSPI2.offset2F8)

  5292. #define FLEXSPI2_LUT63			(IMXRT_FLEXSPI2.offset2FC)

  5293. 

  5294. // 17.6: page 1190

  5295. #define IMXRT_GPC		(*(IMXRT_REGISTER32_t *)0x400F4000)

  5296. #define GPC_CNTR			(IMXRT_GPC.offset000)

  5297. #define GPC_IMR1			(IMXRT_GPC.offset008)

  5298. #define GPC_IMR2			(IMXRT_GPC.offset00C)

  5299. #define GPC_IMR3			(IMXRT_GPC.offset010)

  5300. #define GPC_IMR4			(IMXRT_GPC.offset014)

  5301. #define GPC_ISR1			(IMXRT_GPC.offset018)

  5302. #define GPC_ISR2			(IMXRT_GPC.offset01C)

  5303. #define GPC_ISR3			(IMXRT_GPC.offset020)

  5304. #define GPC_ISR4			(IMXRT_GPC.offset024)

  5305. #define GPC_IMR5			(IMXRT_GPC.offset034)

  5306. #define GPC_ISR5			(IMXRT_GPC.offset038)

  5307. #define GPC_CNTR_PDRAM0_PGE			((uint32_t)(1<<22))

  5308. #define GPC_CNTR_MEGA_PUP_REQ			((uint32_t)(1<<3))

  5309. #define GPC_CNTR_MEGA_PDN_REQ			((uint32_t)(1<<2))

  5310. // page 1602

  5311. #define PGC_MEGA_CTRL			(IMXRT_GPC.offset220)

  5312. #define PGC_MEGA_PUPSCR			(IMXRT_GPC.offset224)

  5313. #define PGC_MEGA_PDNSCR			(IMXRT_GPC.offset228)

  5314. #define PGC_MEGA_SR			(IMXRT_GPC.offset22C)

  5315. #define PGC_CPU_CTRL			(IMXRT_GPC.offset2A0)

  5316. #define PGC_CPU_PUPSCR			(IMXRT_GPC.offset2A4)

  5317. #define PGC_CPU_PDNSCR			(IMXRT_GPC.offset2A8)

  5318. #define PGC_CPU_SR			(IMXRT_GPC.offset2AC)

  5319. #define PGC_MEGA_CTRL_PCR			((uint32_t)(1<<0))

  5320. #define PGC_MEGA_PUPSCR_SW2ISO(n)		((uint32_t)(((n) & 0x3F) << 8))

  5321. #define PGC_MEGA_PUPSCR_SW(n)			((uint32_t)(((n) & 0x3F) << 0))

  5322. #define PGC_MEGA_PDNSCR_ISO2SW(n)		((uint32_t)(((n) & 0x3F) << 8))

  5323. #define PGC_MEGA_PDNSCR_ISO(n)			((uint32_t)(((n) & 0x3F) << 0))

  5324. #define PGC_MEGA_SR_PSR				((uint32_t)(1<<0))

  5325. #define PGC_CPU_CTRL_PCR			((uint32_t)(1<<0))

  5326. #define PGC_CPU_PUPSCR_SW2ISO(n)		((uint32_t)(((n) & 0x3F) << 8))

  5327. #define PGC_CPU_PUPSCR_SW(n)			((uint32_t)(((n) & 0x3F) << 0))

  5328. #define PGC_CPU_PDNSCR_ISO2SW(n)		((uint32_t)(((n) & 0x3F) << 8))

  5329. #define PGC_CPU_PDNSCR_ISO(n)			((uint32_t)(((n) & 0x3F) << 0))

  5330. #define PGC_CPU_SR_PSR				((uint32_t)(1<<0))

  5331. 

  5332. // 12.5.1: page 961

  5333. typedef struct {

  5334.         volatile uint32_t DR;                  // 00

  5335.         volatile uint32_t GDIR;                // 04

  5336.         volatile uint32_t PSR;                 // 08

  5337.         volatile uint32_t ICR1;                // 0C

  5338.         volatile uint32_t ICR2;                // 10

  5339.         volatile uint32_t IMR;                 // 14

  5340.         volatile uint32_t ICR;                 // 18

  5341.         volatile uint32_t EDGE_SEL;            // 1C

  5342.         uint32_t          UNUSED[25];          // 20 - 83

  5343.         volatile uint32_t DR_SET;              // 84

  5344.         volatile uint32_t DR_CLEAR;            // 88

  5345.         volatile uint32_t DR_TOGGLE;           // 8C

  5346. 

  5347. } IMXRT_GPIO_t;

  5348. 

  5349. #define IMXRT_GPIO1		(*(IMXRT_GPIO_t *)0x401B8000)

  5350. #define GPIO1_DR			(IMXRT_GPIO1.DR)

  5351. #define GPIO1_GDIR			(IMXRT_GPIO1.GDIR)

  5352. #define GPIO1_PSR			(IMXRT_GPIO1.PSR)

  5353. #define GPIO1_ICR1			(IMXRT_GPIO1.ICR1)

  5354. #define GPIO1_ICR2			(IMXRT_GPIO1.ICR2)

  5355. #define GPIO1_IMR			(IMXRT_GPIO1.IMR)

  5356. #define GPIO1_ISR			(IMXRT_GPIO1.ISR)

  5357. #define GPIO1_EDGE_SEL			(IMXRT_GPIO1.EDGE_SEL)

  5358. #define GPIO1_DR_SET			(IMXRT_GPIO1.DR_SET)

  5359. #define GPIO1_DR_CLEAR			(IMXRT_GPIO1.DR_CLEAR)

  5360. #define GPIO1_DR_TOGGLE			(IMXRT_GPIO1.DR_TOGGLE)

  5361. #define IMXRT_GPIO2		(*(IMXRT_GPIO_t *)0x401BC000)

  5362. #define GPIO2_DR			(IMXRT_GPIO2.DR)

  5363. #define GPIO2_GDIR			(IMXRT_GPIO2.GDIR)

  5364. #define GPIO2_PSR			(IMXRT_GPIO2.PSR)

  5365. #define GPIO2_ICR1			(IMXRT_GPIO2.ICR1)

  5366. #define GPIO2_ICR2			(IMXRT_GPIO2.ICR2)

  5367. #define GPIO2_IMR			(IMXRT_GPIO2.IMR)

  5368. #define GPIO2_ISR			(IMXRT_GPIO2.ISR)

  5369. #define GPIO2_EDGE_SEL			(IMXRT_GPIO2.EDGE_SEL)

  5370. #define GPIO2_DR_SET			(IMXRT_GPIO2.DR_SET)

  5371. #define GPIO2_DR_CLEAR			(IMXRT_GPIO2.DR_CLEAR)

  5372. #define GPIO2_DR_TOGGLE			(IMXRT_GPIO2.DR_TOGGLE)

  5373. #define IMXRT_GPIO3		(*(IMXRT_GPIO_t *)0x401C0000)

  5374. #define GPIO3_DR			(IMXRT_GPIO3.DR)

  5375. #define GPIO3_GDIR			(IMXRT_GPIO3.GDIR)

  5376. #define GPIO3_PSR			(IMXRT_GPIO3.PSR)

  5377. #define GPIO3_ICR1			(IMXRT_GPIO3.ICR1)

  5378. #define GPIO3_ICR2			(IMXRT_GPIO3.ICR2)

  5379. #define GPIO3_IMR			(IMXRT_GPIO3.IMR)

  5380. #define GPIO3_ISR			(IMXRT_GPIO3.ISR)

  5381. #define GPIO3_EDGE_SEL			(IMXRT_GPIO3.EDGE_SEL)

  5382. #define GPIO3_DR_SET			(IMXRT_GPIO3.DR_SET)

  5383. #define GPIO3_DR_CLEAR			(IMXRT_GPIO3.DR_CLEAR)

  5384. #define GPIO3_DR_TOGGLE			(IMXRT_GPIO3.DR_TOGGLE)

  5385. #define IMXRT_GPIO4		(*(IMXRT_GPIO_t *)0x401C4000)

  5386. #define GPIO4_DR			(IMXRT_GPIO4.DR)

  5387. #define GPIO4_GDIR			(IMXRT_GPIO4.GDIR)

  5388. #define GPIO4_PSR			(IMXRT_GPIO4.PSR)

  5389. #define GPIO4_ICR1			(IMXRT_GPIO4.ICR1)

  5390. #define GPIO4_ICR2			(IMXRT_GPIO4.ICR2)

  5391. #define GPIO4_IMR			(IMXRT_GPIO4.IMR)

  5392. #define GPIO4_ISR			(IMXRT_GPIO4.ISR)

  5393. #define GPIO4_EDGE_SEL			(IMXRT_GPIO4.EDGE_SEL)

  5394. #define GPIO4_DR_SET			(IMXRT_GPIO4.DR_SET)

  5395. #define GPIO4_DR_CLEAR			(IMXRT_GPIO4.DR_CLEAR)

  5396. #define GPIO4_DR_TOGGLE			(IMXRT_GPIO4.DR_TOGGLE)

  5397. #define IMXRT_GPIO5		(*(IMXRT_GPIO_t *)0x400C0000)

  5398. #define GPIO5_DR			(IMXRT_GPIO5.DR)

  5399. #define GPIO5_GDIR			(IMXRT_GPIO5.GDIR)

  5400. #define GPIO5_PSR			(IMXRT_GPIO5.PSR)

  5401. #define GPIO5_ICR1			(IMXRT_GPIO5.ICR1)

  5402. #define GPIO5_ICR2			(IMXRT_GPIO5.ICR2)

  5403. #define GPIO5_IMR			(IMXRT_GPIO5.IMR)

  5404. #define GPIO5_ISR			(IMXRT_GPIO5.ISR)

  5405. #define GPIO5_EDGE_SEL			(IMXRT_GPIO5.EDGE_SEL)

  5406. #define GPIO5_DR_SET			(IMXRT_GPIO5.DR_SET)

  5407. #define GPIO5_DR_CLEAR			(IMXRT_GPIO5.DR_CLEAR)

  5408. #define GPIO5_DR_TOGGLE			(IMXRT_GPIO5.DR_TOGGLE)

  5409. #define IMXRT_GPIO6		(*(IMXRT_GPIO_t *)0x42000000)

  5410. #define GPIO6_DR			(IMXRT_GPIO6.DR)

  5411. #define GPIO6_GDIR			(IMXRT_GPIO6.GDIR)

  5412. #define GPIO6_PSR			(IMXRT_GPIO6.PSR)

  5413. #define GPIO6_ICR1			(IMXRT_GPIO6.ICR1)

  5414. #define GPIO6_ICR2			(IMXRT_GPIO6.ICR2)

  5415. #define GPIO6_IMR			(IMXRT_GPIO6.IMR)

  5416. #define GPIO6_ISR			(IMXRT_GPIO6.ISR)

  5417. #define GPIO6_EDGE_SEL			(IMXRT_GPIO6.EDGE_SEL)

  5418. #define GPIO6_DR_SET			(IMXRT_GPIO6.DR_SET)

  5419. #define GPIO6_DR_CLEAR			(IMXRT_GPIO6.DR_CLEAR)

  5420. #define GPIO6_DR_TOGGLE			(IMXRT_GPIO6.DR_TOGGLE)

  5421. #define IMXRT_GPIO7		(*(IMXRT_GPIO_t *)0x42004000)

  5422. #define GPIO7_DR			(IMXRT_GPIO7.DR)

  5423. #define GPIO7_GDIR			(IMXRT_GPIO7.GDIR)

  5424. #define GPIO7_PSR			(IMXRT_GPIO7.PSR)

  5425. #define GPIO7_ICR1			(IMXRT_GPIO7.ICR1)

  5426. #define GPIO7_ICR2			(IMXRT_GPIO7.ICR2)

  5427. #define GPIO7_IMR			(IMXRT_GPIO7.IMR)

  5428. #define GPIO7_ISR			(IMXRT_GPIO7.ISR)

  5429. #define GPIO7_EDGE_SEL			(IMXRT_GPIO7.EDGE_SEL)

  5430. #define GPIO7_DR_SET			(IMXRT_GPIO7.DR_SET)

  5431. #define GPIO7_DR_CLEAR			(IMXRT_GPIO7.DR_CLEAR)

  5432. #define GPIO7_DR_TOGGLE			(IMXRT_GPIO7.DR_TOGGLE)

  5433. #define IMXRT_GPIO8		(*(IMXRT_GPIO_t *)0x42008000)

  5434. #define GPIO8_DR			(IMXRT_GPIO8.DR)

  5435. #define GPIO8_GDIR			(IMXRT_GPIO8.GDIR)

  5436. #define GPIO8_PSR			(IMXRT_GPIO8.PSR)

  5437. #define GPIO8_ICR1			(IMXRT_GPIO8.ICR1)

  5438. #define GPIO8_ICR2			(IMXRT_GPIO8.ICR2)

  5439. #define GPIO8_IMR			(IMXRT_GPIO8.IMR)

  5440. #define GPIO8_ISR			(IMXRT_GPIO8.ISR)

  5441. #define GPIO8_EDGE_SEL			(IMXRT_GPIO8.EDGE_SEL)

  5442. #define GPIO8_DR_SET			(IMXRT_GPIO8.DR_SET)

  5443. #define GPIO8_DR_CLEAR			(IMXRT_GPIO8.DR_CLEAR)

  5444. #define GPIO8_DR_TOGGLE			(IMXRT_GPIO8.DR_TOGGLE)

  5445. #define IMXRT_GPIO9		(*(IMXRT_GPIO_t *)0x4200C000)

  5446. #define GPIO9_DR			(IMXRT_GPIO9.DR)

  5447. #define GPIO9_GDIR			(IMXRT_GPIO9.GDIR)

  5448. #define GPIO9_PSR			(IMXRT_GPIO9.PSR)

  5449. #define GPIO9_ICR1			(IMXRT_GPIO9.ICR1)

  5450. #define GPIO9_ICR2			(IMXRT_GPIO9.ICR2)

  5451. #define GPIO9_IMR			(IMXRT_GPIO9.IMR)

  5452. #define GPIO9_ISR			(IMXRT_GPIO9.ISR)

  5453. #define GPIO9_EDGE_SEL			(IMXRT_GPIO9.EDGE_SEL)

  5454. #define GPIO9_DR_SET			(IMXRT_GPIO9.DR_SET)

  5455. #define GPIO9_DR_CLEAR			(IMXRT_GPIO9.DR_CLEAR)

  5456. #define GPIO9_DR_TOGGLE			(IMXRT_GPIO9.DR_TOGGLE)

  5457. 

  5458. // 52.7: page 2957

  5459. #define IMXRT_GPT1		(*(IMXRT_REGISTER32_t *)0x401EC000)

  5460. #define GPT1_CR				(IMXRT_GPT1.offset000)

  5461. #define GPT1_PR				(IMXRT_GPT1.offset004)

  5462. #define GPT1_SR				(IMXRT_GPT1.offset008)

  5463. #define GPT1_IR				(IMXRT_GPT1.offset00C)

  5464. #define GPT1_OCR1			(IMXRT_GPT1.offset010)

  5465. #define GPT1_OCR2			(IMXRT_GPT1.offset014)

  5466. #define GPT1_OCR3			(IMXRT_GPT1.offset018)

  5467. #define GPT1_ICR1			(IMXRT_GPT1.offset01C)

  5468. #define GPT1_ICR2			(IMXRT_GPT1.offset020)

  5469. #define GPT1_CNT			(IMXRT_GPT1.offset024)

  5470. #define IMXRT_GPT2		(*(IMXRT_REGISTER32_t *)0x401F0000)

  5471. #define GPT2_CR				(IMXRT_GPT2.offset000)

  5472. #define GPT2_PR				(IMXRT_GPT2.offset004)

  5473. #define GPT2_SR				(IMXRT_GPT2.offset008)

  5474. #define GPT2_IR				(IMXRT_GPT2.offset00C)

  5475. #define GPT2_OCR1			(IMXRT_GPT2.offset010)

  5476. #define GPT2_OCR2			(IMXRT_GPT2.offset014)

  5477. #define GPT2_OCR3			(IMXRT_GPT2.offset018)

  5478. #define GPT2_ICR1			(IMXRT_GPT2.offset01C)

  5479. #define GPT2_ICR2			(IMXRT_GPT2.offset020)

  5480. #define GPT2_CNT			(IMXRT_GPT2.offset024)

  5481. #define GPT_CR_FO3				((uint32_t)(1<<31))

  5482. #define GPT_CR_FO2				((uint32_t)(1<<30))

  5483. #define GPT_CR_FO1				((uint32_t)(1<<29))

  5484. #define GPT_CR_OM3(n)				((uint32_t)(((n) & 0x07) << 26))

  5485. #define GPT_CR_OM2(n)				((uint32_t)(((n) & 0x07) << 23))

  5486. #define GPT_CR_OM1(n)				((uint32_t)(((n) & 0x07) << 20))

  5487. #define GPT_CR_IM2(n)				((uint32_t)(((n) & 0x03) << 18))

  5488. #define GPT_CR_IM1(n)				((uint32_t)(((n) & 0x03) << 16))

  5489. #define GPT_CR_SWR				((uint32_t)(1<<15))

  5490. #define GPT_CR_EN_24M				((uint32_t)(1<<10))

  5491. #define GPT_CR_FRR				((uint32_t)(1<<9))

  5492. #define GPT_CR_CLKSRC(n)			((uint32_t)(((n) & 0x07) << 6))

  5493. #define GPT_CR_STOPEN				((uint32_t)(1<<5))

  5494. #define GPT_CR_DOZEEN				((uint32_t)(1<<4))

  5495. #define GPT_CR_WAITEN				((uint32_t)(1<<3))

  5496. #define GPT_CR_DBGEN				((uint32_t)(1<<2))

  5497. #define GPT_CR_ENMOD				((uint32_t)(1<<1))

  5498. #define GPT_CR_EN				((uint32_t)(1<<0))

  5499. #define GPT_PR_PRESCALER24M(n)			((uint32_t)(((n) & 0x0F) << 12))

  5500. #define GPT_PR_PRESCALER(n)			((uint32_t)(((n) & 0xFFF) << 0))

  5501. #define GPT_SR_ROV				((uint32_t)(1<<5))

  5502. #define GPT_SR_IF2				((uint32_t)(1<<4))

  5503. #define GPT_SR_IF1				((uint32_t)(1<<3))

  5504. #define GPT_SR_OF3				((uint32_t)(1<<2))

  5505. #define GPT_SR_OF2				((uint32_t)(1<<1))

  5506. #define GPT_SR_OF1				((uint32_t)(1<<0))

  5507. #define GPT_IR_ROVIE				((uint32_t)(1<<5))

  5508. #define GPT_IR_IF2IE				((uint32_t)(1<<4))

  5509. #define GPT_IR_IF1IE				((uint32_t)(1<<3))

  5510. #define GPT_IR_OF3IE				((uint32_t)(1<<2))

  5511. #define GPT_IR_OF2IE				((uint32_t)(1<<1))

  5512. #define GPT_IR_OF1IE				((uint32_t)(1<<0))

  5513. 

  5514. // 11.4: page 327

  5515. #define IMXRT_IOMUXC_GPR	(*(IMXRT_REGISTER32_t *)0x400AC000)

  5516. #define IOMUXC_GPR_GPR0			(IMXRT_IOMUXC_GPR.offset000)

  5517. #define IOMUXC_GPR_GPR1			(IMXRT_IOMUXC_GPR.offset004)

  5518. #define IOMUXC_GPR_GPR2			(IMXRT_IOMUXC_GPR.offset008)

  5519. #define IOMUXC_GPR_GPR3			(IMXRT_IOMUXC_GPR.offset00C)

  5520. #define IOMUXC_GPR_GPR4			(IMXRT_IOMUXC_GPR.offset010)

  5521. #define IOMUXC_GPR_GPR5			(IMXRT_IOMUXC_GPR.offset014)

  5522. #define IOMUXC_GPR_GPR6			(IMXRT_IOMUXC_GPR.offset018)

  5523. #define IOMUXC_GPR_GPR7			(IMXRT_IOMUXC_GPR.offset01C)

  5524. #define IOMUXC_GPR_GPR8			(IMXRT_IOMUXC_GPR.offset020)

  5525. #define IOMUXC_GPR_GPR9			(IMXRT_IOMUXC_GPR.offset024)

  5526. #define IOMUXC_GPR_GPR10		(IMXRT_IOMUXC_GPR.offset028)

  5527. #define IOMUXC_GPR_GPR11		(IMXRT_IOMUXC_GPR.offset02C)

  5528. #define IOMUXC_GPR_GPR12		(IMXRT_IOMUXC_GPR.offset030)

  5529. #define IOMUXC_GPR_GPR13		(IMXRT_IOMUXC_GPR.offset034)

  5530. #define IOMUXC_GPR_GPR14		(IMXRT_IOMUXC_GPR.offset038)

  5531. #define IOMUXC_GPR_GPR15		(IMXRT_IOMUXC_GPR.offset03C)

  5532. #define IOMUXC_GPR_GPR16		(IMXRT_IOMUXC_GPR.offset040)

  5533. #define IOMUXC_GPR_GPR17		(IMXRT_IOMUXC_GPR.offset044)

  5534. #define IOMUXC_GPR_GPR18		(IMXRT_IOMUXC_GPR.offset048)

  5535. #define IOMUXC_GPR_GPR19		(IMXRT_IOMUXC_GPR.offset04C)

  5536. #define IOMUXC_GPR_GPR20		(IMXRT_IOMUXC_GPR.offset050)

  5537. #define IOMUXC_GPR_GPR21		(IMXRT_IOMUXC_GPR.offset054)

  5538. #define IOMUXC_GPR_GPR22		(IMXRT_IOMUXC_GPR.offset058)

  5539. #define IOMUXC_GPR_GPR23		(IMXRT_IOMUXC_GPR.offset05C)

  5540. #define IOMUXC_GPR_GPR24		(IMXRT_IOMUXC_GPR.offset060)

  5541. #define IOMUXC_GPR_GPR25		(IMXRT_IOMUXC_GPR.offset064)

  5542. #define IOMUXC_GPR_GPR26		(IMXRT_IOMUXC_GPR.offset068)

  5543. #define IOMUXC_GPR_GPR27		(IMXRT_IOMUXC_GPR.offset06C)

  5544. #define IOMUXC_GPR_GPR28		(IMXRT_IOMUXC_GPR.offset070)

  5545. #define IOMUXC_GPR_GPR29		(IMXRT_IOMUXC_GPR.offset074)

  5546. #define IOMUXC_GPR_GPR30		(IMXRT_IOMUXC_GPR.offset078)

  5547. #define IOMUXC_GPR_GPR31		(IMXRT_IOMUXC_GPR.offset07C)

  5548. #define IOMUXC_GPR_GPR32		(IMXRT_IOMUXC_GPR.offset080)

  5549. #define IOMUXC_GPR_GPR33		(IMXRT_IOMUXC_GPR.offset084)

  5550. #define IOMUXC_GPR_GPR34		(IMXRT_IOMUXC_GPR.offset088)

  5551. #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN	((uint32_t)(1<<31))

  5552. #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN	((uint32_t)(1<<23))

  5553. #define IOMUXC_GPR_GPR1_EXC_MON			((uint32_t)(1<<22))

  5554. #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR		((uint32_t)(1<<21))

  5555. #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR		((uint32_t)(1<<20))

  5556. #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR		((uint32_t)(1<<19))

  5557. #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR	((uint32_t)(1<<18))

  5558. #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR	((uint32_t)(1<<17))

  5559. #define IOMUXC_GPR_GPR1_USB_EXP_MODE		((uint32_t)(1<<15))

  5560. #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL		((uint32_t)(1<<14))

  5561. #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL		((uint32_t)(1<<13))

  5562. #define IOMUXC_GPR_GPR1_GINT			((uint32_t)(1<<12))

  5563. #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(n)	((uint32_t)(((n) & 0x03) << 10))

  5564. #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(n)	((uint32_t)(((n) & 0x03) << 8))

  5565. #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(n)	((uint32_t)(((n) & 0x03) << 6))

  5566. #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(n)	((uint32_t)(((n) & 0x07) << 3))

  5567. #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(n)	((uint32_t)(((n) & 0x07) << 0))

  5568. #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK	IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(3)

  5569. #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK	IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(3)

  5570. #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK	IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(3)

  5571. #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK	IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(7)

  5572. #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK	IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(7)

  5573. #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE	((uint32_t)(1<<31))

  5574. #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE	((uint32_t)(1<<30))

  5575. #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE	((uint32_t)(1<<29))

  5576. #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE	((uint32_t)(1<<28))

  5577. #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE		((uint32_t)(1<<26))

  5578. #define IOMUXC_GPR_GPR2_MQS_EN			((uint32_t)(1<<25))

  5579. #define IOMUXC_GPR_GPR2_MQS_SW_RST		((uint32_t)(1<<24))

  5580. #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(n)		((uint32_t)(((n) & 0xFF) << 16))

  5581. #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP	((uint32_t)(1<<14))

  5582. #define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN	((uint32_t)(1<<13))

  5583. #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING	((uint32_t)(1<<12))

  5584. #define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS	((uint32_t)(1<<6))

  5585. #define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN ((uint32_t)(1<<5))

  5586. #define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY	((uint32_t)(1<<4))

  5587. #define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY	((uint32_t)(1<<3))

  5588. #define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN ((uint32_t)(1<<2))

  5589. #define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY ((uint32_t)(1<<1))

  5590. #define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY ((uint32_t)(1<<0))

  5591. #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK	IOMUXC_GPR_GPR2_MQS_CLK_DIV(255)

  5592. #define IOMUXC_GPR_GPR3_AXBS_L_HALTED		((uint32_t)(1<<31))

  5593. #define IOMUXC_GPR_GPR3_OCRAM2_STATUS(n)	((uint32_t)(((n) & 0x0F) << 24))

  5594. #define IOMUXC_GPR_GPR3_OCRAM_STATUS(n)		((uint32_t)(((n) & 0x0F) << 16))

  5595. #define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ		((uint32_t)(1<<15))

  5596. #define IOMUXC_GPR_GPR3_OCRAM2_CTL(n)		((uint32_t)(((n) & 0x0F) << 8))

  5597. #define IOMUXC_GPR_GPR3_DCP_KEY_SEL		((uint32_t)(1<<4))

  5598. #define IOMUXC_GPR_GPR3_OCRAM_CTL(n)		((uint32_t)(((n) & 0x0F) << 0))

  5599. #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK	((uint32_t)(1<<31))

  5600. #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK	((uint32_t)(1<<30))

  5601. #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK	((uint32_t)(1<<29))

  5602. #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK	((uint32_t)(1<<28))

  5603. #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK	((uint32_t)(1<<27))

  5604. #define IOMUXC_GPR_GPR4_PIT_STOP_ACK		((uint32_t)(1<<26))

  5605. #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK		((uint32_t)(1<<25))

  5606. #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK		((uint32_t)(1<<23))

  5607. #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK		((uint32_t)(1<<22))

  5608. #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK		((uint32_t)(1<<21))

  5609. #define IOMUXC_GPR_GPR4_ENET_STOP_ACK		((uint32_t)(1<<20))

  5610. #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK		((uint32_t)(1<<19))

  5611. #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK		((uint32_t)(1<<18))

  5612. #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK		((uint32_t)(1<<17))

  5613. #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK		((uint32_t)(1<<16))

  5614. #define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ	((uint32_t)(1<<15))

  5615. #define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ	((uint32_t)(1<<14))

  5616. #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ	((uint32_t)(1<<13))

  5617. #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ	((uint32_t)(1<<12))

  5618. #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ	((uint32_t)(1<<11))

  5619. #define IOMUXC_GPR_GPR4_PIT_STOP_REQ		((uint32_t)(1<<10))

  5620. #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ		((uint32_t)(1<<9))

  5621. #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ		((uint32_t)(1<<7))

  5622. #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ		((uint32_t)(1<<6))

  5623. #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ		((uint32_t)(1<<5))

  5624. #define IOMUXC_GPR_GPR4_ENET_STOP_REQ		((uint32_t)(1<<4))

  5625. #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ		((uint32_t)(1<<3))

  5626. #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ		((uint32_t)(1<<2))

  5627. #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ		((uint32_t)(1<<1))

  5628. #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ		((uint32_t)(1<<0))

  5629. #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2	((uint32_t)(1<<29))

  5630. #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1	((uint32_t)(1<<28))

  5631. #define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL	((uint32_t)(1<<26))

  5632. #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL	((uint32_t)(1<<25))

  5633. #define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL		((uint32_t)(1<<24))

  5634. #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL		((uint32_t)(1<<23))

  5635. #define IOMUXC_GPR_GPR5_WDOG2_MASK		((uint32_t)(1<<7))

  5636. #define IOMUXC_GPR_GPR5_WDOG1_MASK		((uint32_t)(1<<6))

  5637. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19	((uint32_t)(1<<31))

  5638. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18	((uint32_t)(1<<30))

  5639. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17	((uint32_t)(1<<29))

  5640. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16	((uint32_t)(1<<28))

  5641. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15	((uint32_t)(1<<27))

  5642. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14	((uint32_t)(1<<26))

  5643. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13	((uint32_t)(1<<25))

  5644. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12	((uint32_t)(1<<24))

  5645. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11	((uint32_t)(1<<23))

  5646. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10	((uint32_t)(1<<22))

  5647. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9	((uint32_t)(1<<21))

  5648. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8	((uint32_t)(1<<20))

  5649. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7	((uint32_t)(1<<19))

  5650. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6	((uint32_t)(1<<18))

  5651. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5	((uint32_t)(1<<17))

  5652. #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4	((uint32_t)(1<<16))

  5653. #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL	((uint32_t)(1<<15))

  5654. #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL	((uint32_t)(1<<14))

  5655. #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL	((uint32_t)(1<<13))

  5656. #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL	((uint32_t)(1<<12))

  5657. #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL	((uint32_t)(1<<11))

  5658. #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL	((uint32_t)(1<<10))

  5659. #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL	((uint32_t)(1<<9))

  5660. #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL	((uint32_t)(1<<8))

  5661. #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL	((uint32_t)(1<<7))

  5662. #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL	((uint32_t)(1<<6))

  5663. #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL	((uint32_t)(1<<5))

  5664. #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL	((uint32_t)(1<<4))

  5665. #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL	((uint32_t)(1<<3))

  5666. #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL	((uint32_t)(1<<2))

  5667. #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL	((uint32_t)(1<<1))

  5668. #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL	((uint32_t)(1<<0))

  5669. #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK	((uint32_t)(1<<31))

  5670. #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK	((uint32_t)(1<<30))

  5671. #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK	((uint32_t)(1<<29))

  5672. #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK	((uint32_t)(1<<28))

  5673. #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK	((uint32_t)(1<<27))

  5674. #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK	((uint32_t)(1<<26))

  5675. #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK	((uint32_t)(1<<25))

  5676. #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK	((uint32_t)(1<<24))

  5677. #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK		((uint32_t)(1<<23))

  5678. #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK		((uint32_t)(1<<22))

  5679. #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK		((uint32_t)(1<<21))

  5680. #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK		((uint32_t)(1<<20))

  5681. #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK		((uint32_t)(1<<19))

  5682. #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK		((uint32_t)(1<<18))

  5683. #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK		((uint32_t)(1<<17))

  5684. #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK		((uint32_t)(1<<16))

  5685. #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ	((uint32_t)(1<<15))

  5686. #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ	((uint32_t)(1<<14))

  5687. #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ	((uint32_t)(1<<13))

  5688. #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ	((uint32_t)(1<<12))

  5689. #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ	((uint32_t)(1<<11))

  5690. #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ	((uint32_t)(1<<10))

  5691. #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ	((uint32_t)(1<<9))

  5692. #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ	((uint32_t)(1<<8))

  5693. #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ		((uint32_t)(1<<7))

  5694. #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ		((uint32_t)(1<<6))

  5695. #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ		((uint32_t)(1<<5))

  5696. #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ		((uint32_t)(1<<4))

  5697. #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ		((uint32_t)(1<<3))

  5698. #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ		((uint32_t)(1<<2))

  5699. #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ		((uint32_t)(1<<1))

  5700. #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ		((uint32_t)(1<<0))

  5701. #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE	((uint32_t)(1<<31))

  5702. #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE	((uint32_t)(1<<30))

  5703. #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE	((uint32_t)(1<<29))

  5704. #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE	((uint32_t)(1<<28))

  5705. #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE	((uint32_t)(1<<27))

  5706. #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE	((uint32_t)(1<<26))

  5707. #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE	((uint32_t)(1<<25))

  5708. #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE	((uint32_t)(1<<24))

  5709. #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE	((uint32_t)(1<<23))

  5710. #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE	((uint32_t)(1<<22))

  5711. #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE	((uint32_t)(1<<21))

  5712. #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE	((uint32_t)(1<<20))

  5713. #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE	((uint32_t)(1<<19))

  5714. #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE	((uint32_t)(1<<18))

  5715. #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE	((uint32_t)(1<<17))

  5716. #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE	((uint32_t)(1<<16))

  5717. #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE		((uint32_t)(1<<15))

  5718. #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE	((uint32_t)(1<<14))

  5719. #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE		((uint32_t)(1<<13))

  5720. #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE	((uint32_t)(1<<12))

  5721. #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE		((uint32_t)(1<<11))

  5722. #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE	((uint32_t)(1<<10))

  5723. #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE		((uint32_t)(1<<9))

  5724. #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE	((uint32_t)(1<<8))

  5725. #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE		((uint32_t)(1<<7))

  5726. #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE	((uint32_t)(1<<6))

  5727. #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE		((uint32_t)(1<<5))

  5728. #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE	((uint32_t)(1<<4))

  5729. #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE		((uint32_t)(1<<3))

  5730. #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE	((uint32_t)(1<<2))

  5731. #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE		((uint32_t)(1<<1))

  5732. #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE	((uint32_t)(1<<0))

  5733. #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n)	((uint32_t)(((n) & 0x7F) << 25))

  5734. #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN	((uint32_t)(1<<24))

  5735. #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX	((uint32_t)(1<<20))

  5736. #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP	((uint32_t)(1<<18))

  5737. #define IOMUXC_GPR_GPR10_LOCK_DBG_EN		((uint32_t)(1<<17))

  5738. #define IOMUXC_GPR_GPR10_LOCK_NIDEN		((uint32_t)(1<<16))

  5739. #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(n)	((uint32_t)(((n) & 0x7F) << 9))

  5740. #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN		((uint32_t)(1<<8))

  5741. #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX	((uint32_t)(1<<4))

  5742. #define IOMUXC_GPR_GPR10_SEC_ERR_RESP		((uint32_t)(1<<2))

  5743. #define IOMUXC_GPR_GPR10_DBG_EN			((uint32_t)(1<<1))

  5744. #define IOMUXC_GPR_GPR10_NIDEN			((uint32_t)(1<<0))

  5745. #define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(n)	((uint32_t)(((n) & 0x0F) << 24))

  5746. #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(n)	((uint32_t)(((n) & 0x03) << 22))

  5747. #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(n)	((uint32_t)(((n) & 0x03) << 20))

  5748. #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(n)	((uint32_t)(((n) & 0x03) << 18))

  5749. #define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(n)	((uint32_t)(((n) & 0x03) << 16))

  5750. #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(n)	((uint32_t)(((n) & 0x0F) << 8))

  5751. #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(n)	((uint32_t)(((n) & 0x03) << 6))

  5752. #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(n)	((uint32_t)(((n) & 0x03) << 4))

  5753. #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(n)	((uint32_t)(((n) & 0x03) << 2))

  5754. #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(n)	((uint32_t)(((n) & 0x03) << 0))

  5755. #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE	((uint32_t)(1<<6))

  5756. #define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE	((uint32_t)(1<<5))

  5757. #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE	((uint32_t)(1<<4))

  5758. #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE	((uint32_t)(1<<3))

  5759. #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE	((uint32_t)(1<<2))

  5760. #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE	((uint32_t)(1<<1))

  5761. #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE	((uint32_t)(1<<0))

  5762. #define IOMUXC_GPR_GPR13_CANFD_STOP_ACK		((uint32_t)(1<<20))

  5763. #define IOMUXC_GPR_GPR13_CACHE_USB		((uint32_t)(1<<13))

  5764. #define IOMUXC_GPR_GPR13_CACHE_ENET		((uint32_t)(1<<7))

  5765. #define IOMUXC_GPR_GPR13_CANFD_STOP_REQ		((uint32_t)(1<<4))

  5766. #define IOMUXC_GPR_GPR13_AWCACHE_USDHC		((uint32_t)(1<<1))

  5767. #define IOMUXC_GPR_GPR13_ARCACHE_USDHC		((uint32_t)(1<<0))

  5768. #define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(n)	((uint32_t)(((n) & 0x0F) << 20))

  5769. #define IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(n)	((uint32_t)(((n) & 0x0F) << 16))

  5770. #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN	((uint32_t)(1<<11))

  5771. #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN	((uint32_t)(1<<10))

  5772. #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN	((uint32_t)(1<<9))

  5773. #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN	((uint32_t)(1<<8))

  5774. #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP	((uint32_t)(1<<7))

  5775. #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP	((uint32_t)(1<<6))

  5776. #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP	((uint32_t)(1<<5))

  5777. #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP	((uint32_t)(1<<4))

  5778. #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN	((uint32_t)(1<<3))

  5779. #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN	((uint32_t)(1<<2))

  5780. #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN	((uint32_t)(1<<1))

  5781. #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN	((uint32_t)(1<<0))

  5782. #define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(n)	((uint32_t)(((n) & 0x1FFFFFF) << 7))

  5783. #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL	((uint32_t)(1<<2))

  5784. #define IOMUXC_GPR_GPR16_INIT_DTCM_EN		((uint32_t)(1<<1))

  5785. #define IOMUXC_GPR_GPR16_INIT_ITCM_EN		((uint32_t)(1<<0))

  5786. #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5787. #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT	((uint32_t)(1<<0))

  5788. #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5789. #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP	((uint32_t)(1<<0))

  5790. #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5791. #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT	((uint32_t)(1<<0))

  5792. #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5793. #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP	((uint32_t)(1<<0))

  5794. #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5795. #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT	((uint32_t)(1<<0))

  5796. #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5797. #define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP	((uint32_t)(1<<0))

  5798. #define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5799. #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT	((uint32_t)(1<<0))

  5800. #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(n)	((uint32_t)(((n) & 0x1FFFFFFF) << 3))

  5801. #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP	((uint32_t)(1<<0))

  5802. #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(n)	((uint32_t)(((n) & 0x7F) << 17))

  5803. #define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN	((uint32_t)(1<<16))

  5804. #define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR(n)	((uint32_t)(((n) & 0x7F) << 1))

  5805. #define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN		((uint32_t)(1<<0))

  5806. #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN ((uint32_t)(1<<8))

  5807. #define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(n) ((uint32_t)(((n) & 0xFF) << 0))

  5808. 

  5809. // 11.5: page 380

  5810. #define IMXRT_IOMUXC_SNVS	(*(IMXRT_REGISTER32_t *)0x400A8000)

  5811. #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP		(IMXRT_IOMUXC_SNVS.offset000)

  5812. #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ		(IMXRT_IOMUXC_SNVS.offset004)

  5813. #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ	(IMXRT_IOMUXC_SNVS.offset008)

  5814. #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE		(IMXRT_IOMUXC_SNVS.offset00C)

  5815. #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B		(IMXRT_IOMUXC_SNVS.offset010)

  5816. #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF		(IMXRT_IOMUXC_SNVS.offset014)

  5817. #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP		(IMXRT_IOMUXC_SNVS.offset018)

  5818. #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ		(IMXRT_IOMUXC_SNVS.offset01C)

  5819. #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ	(IMXRT_IOMUXC_SNVS.offset020)

  5820. 

  5821. // 11.6: page 399

  5822. #define IMXRT_IOMUXC_SNVS_GPR	(*(IMXRT_REGISTER32_t *)0x400A4000)

  5823. #define IOMUXC_SNVS_GPR_GPR0		(IMXRT_IOMUXC_SNVS_GPR.offset000)

  5824. #define IOMUXC_SNVS_GPR_GPR1		(IMXRT_IOMUXC_SNVS_GPR.offset004)

  5825. #define IOMUXC_SNVS_GPR_GPR2		(IMXRT_IOMUXC_SNVS_GPR.offset008)

  5826. #define IOMUXC_SNVS_GPR_GPR3		(IMXRT_IOMUXC_SNVS_GPR.offset00C)

  5827. 

  5828. // 11.7: page 403

  5829. #define IMXRT_IOMUXC		(*(IMXRT_REGISTER32_t *)0x401F8000)

  5830. #define IMXRT_IOMUXC_b		(*(IMXRT_REGISTER32_t *)0x401F8400)

  5831. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00	(IMXRT_IOMUXC.offset014)

  5832. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01	(IMXRT_IOMUXC.offset018)

  5833. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02	(IMXRT_IOMUXC.offset01C)

  5834. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03	(IMXRT_IOMUXC.offset020)

  5835. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04	(IMXRT_IOMUXC.offset024)

  5836. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05	(IMXRT_IOMUXC.offset028)

  5837. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06	(IMXRT_IOMUXC.offset02C)

  5838. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07	(IMXRT_IOMUXC.offset030)

  5839. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08	(IMXRT_IOMUXC.offset034)

  5840. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09	(IMXRT_IOMUXC.offset038)

  5841. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10	(IMXRT_IOMUXC.offset03C)

  5842. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11	(IMXRT_IOMUXC.offset040)

  5843. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12	(IMXRT_IOMUXC.offset044)

  5844. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13	(IMXRT_IOMUXC.offset048)

  5845. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14	(IMXRT_IOMUXC.offset04C)

  5846. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15	(IMXRT_IOMUXC.offset050)

  5847. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16	(IMXRT_IOMUXC.offset054)

  5848. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17	(IMXRT_IOMUXC.offset058)

  5849. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18	(IMXRT_IOMUXC.offset05C)

  5850. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19	(IMXRT_IOMUXC.offset060)

  5851. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20	(IMXRT_IOMUXC.offset064)

  5852. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21	(IMXRT_IOMUXC.offset068)

  5853. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22	(IMXRT_IOMUXC.offset06C)

  5854. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23	(IMXRT_IOMUXC.offset070)

  5855. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24	(IMXRT_IOMUXC.offset074)

  5856. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25	(IMXRT_IOMUXC.offset078)

  5857. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26	(IMXRT_IOMUXC.offset07C)

  5858. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27	(IMXRT_IOMUXC.offset080)

  5859. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28	(IMXRT_IOMUXC.offset084)

  5860. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29	(IMXRT_IOMUXC.offset088)

  5861. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30	(IMXRT_IOMUXC.offset08C)

  5862. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31	(IMXRT_IOMUXC.offset090)

  5863. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32	(IMXRT_IOMUXC.offset094)

  5864. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33	(IMXRT_IOMUXC.offset098)

  5865. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34	(IMXRT_IOMUXC.offset09C)

  5866. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35	(IMXRT_IOMUXC.offset0A0)

  5867. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36	(IMXRT_IOMUXC.offset0A4)

  5868. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37	(IMXRT_IOMUXC.offset0A8)

  5869. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38	(IMXRT_IOMUXC.offset0AC)

  5870. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39	(IMXRT_IOMUXC.offset0B0)

  5871. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40	(IMXRT_IOMUXC.offset0B4)

  5872. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41	(IMXRT_IOMUXC.offset0B8)

  5873. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00	(IMXRT_IOMUXC.offset0BC)

  5874. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01	(IMXRT_IOMUXC.offset0C0)

  5875. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02	(IMXRT_IOMUXC.offset0C4)

  5876. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03	(IMXRT_IOMUXC.offset0C8)

  5877. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04	(IMXRT_IOMUXC.offset0CC)

  5878. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05	(IMXRT_IOMUXC.offset0D0)

  5879. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06	(IMXRT_IOMUXC.offset0D4)

  5880. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07	(IMXRT_IOMUXC.offset0D8)

  5881. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08	(IMXRT_IOMUXC.offset0DC)

  5882. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09	(IMXRT_IOMUXC.offset0E0)

  5883. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10	(IMXRT_IOMUXC.offset0E4)

  5884. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11	(IMXRT_IOMUXC.offset0E8)

  5885. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12	(IMXRT_IOMUXC.offset0EC)

  5886. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13	(IMXRT_IOMUXC.offset0F0)

  5887. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14	(IMXRT_IOMUXC.offset0F4)

  5888. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15	(IMXRT_IOMUXC.offset0F8)

  5889. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00	(IMXRT_IOMUXC.offset0FC)

  5890. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01	(IMXRT_IOMUXC.offset100)

  5891. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02	(IMXRT_IOMUXC.offset104)

  5892. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03	(IMXRT_IOMUXC.offset108)

  5893. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04	(IMXRT_IOMUXC.offset10C)

  5894. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05	(IMXRT_IOMUXC.offset110)

  5895. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06	(IMXRT_IOMUXC.offset114)

  5896. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07	(IMXRT_IOMUXC.offset118)

  5897. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08	(IMXRT_IOMUXC.offset11C)

  5898. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09	(IMXRT_IOMUXC.offset120)

  5899. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10	(IMXRT_IOMUXC.offset124)

  5900. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11	(IMXRT_IOMUXC.offset128)

  5901. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12	(IMXRT_IOMUXC.offset12C)

  5902. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13	(IMXRT_IOMUXC.offset130)

  5903. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14	(IMXRT_IOMUXC.offset134)

  5904. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15	(IMXRT_IOMUXC.offset138)

  5905. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00	(IMXRT_IOMUXC.offset13C)

  5906. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01	(IMXRT_IOMUXC.offset140)

  5907. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02	(IMXRT_IOMUXC.offset144)

  5908. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03	(IMXRT_IOMUXC.offset148)

  5909. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04	(IMXRT_IOMUXC.offset14C)

  5910. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05	(IMXRT_IOMUXC.offset150)

  5911. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06	(IMXRT_IOMUXC.offset154)

  5912. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07	(IMXRT_IOMUXC.offset158)

  5913. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08	(IMXRT_IOMUXC.offset15C)

  5914. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09	(IMXRT_IOMUXC.offset160)

  5915. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10	(IMXRT_IOMUXC.offset164)

  5916. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11	(IMXRT_IOMUXC.offset168)

  5917. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12	(IMXRT_IOMUXC.offset16C)

  5918. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13	(IMXRT_IOMUXC.offset170)

  5919. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14	(IMXRT_IOMUXC.offset174)

  5920. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15	(IMXRT_IOMUXC.offset178)

  5921. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00	(IMXRT_IOMUXC.offset17C)

  5922. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01	(IMXRT_IOMUXC.offset180)

  5923. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02	(IMXRT_IOMUXC.offset184)

  5924. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03	(IMXRT_IOMUXC.offset188)

  5925. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04	(IMXRT_IOMUXC.offset18C)

  5926. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05	(IMXRT_IOMUXC.offset190)

  5927. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06	(IMXRT_IOMUXC.offset194)

  5928. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07	(IMXRT_IOMUXC.offset198)

  5929. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08	(IMXRT_IOMUXC.offset19C)

  5930. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09	(IMXRT_IOMUXC.offset1A0)

  5931. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10	(IMXRT_IOMUXC.offset1A4)

  5932. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11	(IMXRT_IOMUXC.offset1A8)

  5933. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12	(IMXRT_IOMUXC.offset1AC)

  5934. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13	(IMXRT_IOMUXC.offset1B0)

  5935. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14	(IMXRT_IOMUXC.offset1B4)

  5936. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15	(IMXRT_IOMUXC.offset1B8)

  5937. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00	(IMXRT_IOMUXC.offset1BC)

  5938. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01	(IMXRT_IOMUXC.offset1C0)

  5939. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02	(IMXRT_IOMUXC.offset1C4)

  5940. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03	(IMXRT_IOMUXC.offset1C8)

  5941. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04	(IMXRT_IOMUXC.offset1CC)

  5942. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05	(IMXRT_IOMUXC.offset1D0)

  5943. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00	(IMXRT_IOMUXC.offset1D4)

  5944. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01	(IMXRT_IOMUXC.offset1D8)

  5945. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02	(IMXRT_IOMUXC.offset1DC)

  5946. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03	(IMXRT_IOMUXC.offset1E0)

  5947. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04	(IMXRT_IOMUXC.offset1E4)

  5948. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05	(IMXRT_IOMUXC.offset1E8)

  5949. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06	(IMXRT_IOMUXC.offset1EC)

  5950. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07	(IMXRT_IOMUXC.offset1F0)

  5951. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08	(IMXRT_IOMUXC.offset1F4)

  5952. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09	(IMXRT_IOMUXC.offset1F8)

  5953. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10	(IMXRT_IOMUXC.offset1FC)

  5954. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11	(IMXRT_IOMUXC.offset200)

  5955. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00	(IMXRT_IOMUXC.offset204)

  5956. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01	(IMXRT_IOMUXC.offset208)

  5957. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02	(IMXRT_IOMUXC.offset20C)

  5958. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03	(IMXRT_IOMUXC.offset210)

  5959. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04	(IMXRT_IOMUXC.offset214)

  5960. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05	(IMXRT_IOMUXC.offset218)

  5961. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06	(IMXRT_IOMUXC.offset21C)

  5962. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07	(IMXRT_IOMUXC.offset220)

  5963. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08	(IMXRT_IOMUXC.offset224)

  5964. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09	(IMXRT_IOMUXC.offset228)

  5965. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10	(IMXRT_IOMUXC.offset22C)

  5966. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11	(IMXRT_IOMUXC.offset230)

  5967. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12	(IMXRT_IOMUXC.offset234)

  5968. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13	(IMXRT_IOMUXC.offset238)

  5969. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14	(IMXRT_IOMUXC.offset23C)

  5970. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15	(IMXRT_IOMUXC.offset240)

  5971. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16	(IMXRT_IOMUXC.offset244)

  5972. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17	(IMXRT_IOMUXC.offset248)

  5973. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18	(IMXRT_IOMUXC.offset24C)

  5974. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19	(IMXRT_IOMUXC.offset250)

  5975. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20	(IMXRT_IOMUXC.offset254)

  5976. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21	(IMXRT_IOMUXC.offset258)

  5977. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22	(IMXRT_IOMUXC.offset25C)

  5978. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23	(IMXRT_IOMUXC.offset260)

  5979. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24	(IMXRT_IOMUXC.offset264)

  5980. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25	(IMXRT_IOMUXC.offset268)

  5981. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26	(IMXRT_IOMUXC.offset26C)

  5982. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27	(IMXRT_IOMUXC.offset270)

  5983. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28	(IMXRT_IOMUXC.offset274)

  5984. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29	(IMXRT_IOMUXC.offset278)

  5985. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30	(IMXRT_IOMUXC.offset27C)

  5986. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31	(IMXRT_IOMUXC.offset280)

  5987. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32	(IMXRT_IOMUXC.offset284)

  5988. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33	(IMXRT_IOMUXC.offset288)

  5989. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34	(IMXRT_IOMUXC.offset28C)

  5990. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35	(IMXRT_IOMUXC.offset290)

  5991. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36	(IMXRT_IOMUXC.offset294)

  5992. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37	(IMXRT_IOMUXC.offset298)

  5993. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38	(IMXRT_IOMUXC.offset29C)

  5994. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39	(IMXRT_IOMUXC.offset2A0)

  5995. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40	(IMXRT_IOMUXC.offset2A4)

  5996. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41	(IMXRT_IOMUXC.offset2A8)

  5997. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00	(IMXRT_IOMUXC.offset2AC)

  5998. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01	(IMXRT_IOMUXC.offset2B0)

  5999. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02	(IMXRT_IOMUXC.offset2B4)

  6000. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03	(IMXRT_IOMUXC.offset2B8)

  6001. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04	(IMXRT_IOMUXC.offset2BC)

  6002. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05	(IMXRT_IOMUXC.offset2C0)

  6003. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06	(IMXRT_IOMUXC.offset2C4)

  6004. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07	(IMXRT_IOMUXC.offset2C8)

  6005. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08	(IMXRT_IOMUXC.offset2CC)

  6006. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09	(IMXRT_IOMUXC.offset2D0)

  6007. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10	(IMXRT_IOMUXC.offset2D4)

  6008. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11	(IMXRT_IOMUXC.offset2D8)

  6009. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12	(IMXRT_IOMUXC.offset2DC)

  6010. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13	(IMXRT_IOMUXC.offset2E0)

  6011. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14	(IMXRT_IOMUXC.offset2E4)

  6012. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15	(IMXRT_IOMUXC.offset2E8)

  6013. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00	(IMXRT_IOMUXC.offset2EC)

  6014. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01	(IMXRT_IOMUXC.offset2F0)

  6015. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02	(IMXRT_IOMUXC.offset2F4)

  6016. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03	(IMXRT_IOMUXC.offset2F8)

  6017. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04	(IMXRT_IOMUXC.offset2FC)

  6018. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05	(IMXRT_IOMUXC.offset300)

  6019. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06	(IMXRT_IOMUXC.offset304)

  6020. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07	(IMXRT_IOMUXC.offset308)

  6021. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08	(IMXRT_IOMUXC.offset30C)

  6022. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09	(IMXRT_IOMUXC.offset310)

  6023. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10	(IMXRT_IOMUXC.offset314)

  6024. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11	(IMXRT_IOMUXC.offset318)

  6025. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12	(IMXRT_IOMUXC.offset31C)

  6026. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13	(IMXRT_IOMUXC.offset320)

  6027. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14	(IMXRT_IOMUXC.offset324)

  6028. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15	(IMXRT_IOMUXC.offset328)

  6029. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00	(IMXRT_IOMUXC.offset32C)

  6030. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01	(IMXRT_IOMUXC.offset330)

  6031. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02	(IMXRT_IOMUXC.offset334)

  6032. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03	(IMXRT_IOMUXC.offset338)

  6033. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04	(IMXRT_IOMUXC.offset33C)

  6034. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05	(IMXRT_IOMUXC.offset340)

  6035. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06	(IMXRT_IOMUXC.offset344)

  6036. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07	(IMXRT_IOMUXC.offset348)

  6037. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08	(IMXRT_IOMUXC.offset34C)

  6038. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09	(IMXRT_IOMUXC.offset350)

  6039. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10	(IMXRT_IOMUXC.offset354)

  6040. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11	(IMXRT_IOMUXC.offset358)

  6041. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12	(IMXRT_IOMUXC.offset35C)

  6042. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13	(IMXRT_IOMUXC.offset360)

  6043. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14	(IMXRT_IOMUXC.offset364)

  6044. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15	(IMXRT_IOMUXC.offset368)

  6045. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00	(IMXRT_IOMUXC.offset36C)

  6046. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01	(IMXRT_IOMUXC.offset370)

  6047. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02	(IMXRT_IOMUXC.offset374)

  6048. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03	(IMXRT_IOMUXC.offset378)

  6049. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04	(IMXRT_IOMUXC.offset37C)

  6050. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05	(IMXRT_IOMUXC.offset380)

  6051. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06	(IMXRT_IOMUXC.offset384)

  6052. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07	(IMXRT_IOMUXC.offset388)

  6053. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08	(IMXRT_IOMUXC.offset38C)

  6054. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09	(IMXRT_IOMUXC.offset390)

  6055. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10	(IMXRT_IOMUXC.offset394)

  6056. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11	(IMXRT_IOMUXC.offset398)

  6057. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12	(IMXRT_IOMUXC.offset39C)

  6058. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13	(IMXRT_IOMUXC.offset3A0)

  6059. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14	(IMXRT_IOMUXC.offset3A4)

  6060. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15	(IMXRT_IOMUXC.offset3A8)

  6061. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00	(IMXRT_IOMUXC.offset3AC)

  6062. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01	(IMXRT_IOMUXC.offset3B0)

  6063. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02	(IMXRT_IOMUXC.offset3B4)

  6064. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03	(IMXRT_IOMUXC.offset3B8)

  6065. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04	(IMXRT_IOMUXC.offset3BC)

  6066. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05	(IMXRT_IOMUXC.offset3C0)

  6067. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00	(IMXRT_IOMUXC.offset3C4)

  6068. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01	(IMXRT_IOMUXC.offset3C8)

  6069. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02	(IMXRT_IOMUXC.offset3CC)

  6070. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03	(IMXRT_IOMUXC.offset3D0)

  6071. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04	(IMXRT_IOMUXC.offset3D4)

  6072. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05	(IMXRT_IOMUXC.offset3D8)

  6073. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06	(IMXRT_IOMUXC.offset3DC)

  6074. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07	(IMXRT_IOMUXC.offset3E0)

  6075. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08	(IMXRT_IOMUXC.offset3E4)

  6076. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09	(IMXRT_IOMUXC.offset3E8)

  6077. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10	(IMXRT_IOMUXC.offset3EC)

  6078. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11	(IMXRT_IOMUXC.offset3F0)

  6079. #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT	(IMXRT_IOMUXC.offset3F4)

  6080. #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT	(IMXRT_IOMUXC.offset3F8)

  6081. #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT	(IMXRT_IOMUXC.offset3FC)

  6082. #define IOMUXC_CSI_DATA02_SELECT_INPUT		(IMXRT_IOMUXC_b.offset000)

  6083. #define IOMUXC_CSI_DATA03_SELECT_INPUT		(IMXRT_IOMUXC_b.offset004)

  6084. #define IOMUXC_CSI_DATA04_SELECT_INPUT		(IMXRT_IOMUXC_b.offset008)

  6085. #define IOMUXC_CSI_DATA05_SELECT_INPUT		(IMXRT_IOMUXC_b.offset00C)

  6086. #define IOMUXC_CSI_DATA06_SELECT_INPUT		(IMXRT_IOMUXC_b.offset010)

  6087. #define IOMUXC_CSI_DATA07_SELECT_INPUT		(IMXRT_IOMUXC_b.offset014)

  6088. #define IOMUXC_CSI_DATA08_SELECT_INPUT		(IMXRT_IOMUXC_b.offset018)

  6089. #define IOMUXC_CSI_DATA09_SELECT_INPUT		(IMXRT_IOMUXC_b.offset01C)

  6090. #define IOMUXC_CSI_HSYNC_SELECT_INPUT		(IMXRT_IOMUXC_b.offset020)

  6091. #define IOMUXC_CSI_PIXCLK_SELECT_INPUT		(IMXRT_IOMUXC_b.offset024)

  6092. #define IOMUXC_CSI_VSYNC_SELECT_INPUT		(IMXRT_IOMUXC_b.offset028)

  6093. #define IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT	(IMXRT_IOMUXC_b.offset02C)

  6094. #define IOMUXC_ENET_MDIO_SELECT_INPUT		(IMXRT_IOMUXC_b.offset030)

  6095. #define IOMUXC_ENET0_RXDATA_SELECT_INPUT	(IMXRT_IOMUXC_b.offset034)

  6096. #define IOMUXC_ENET1_RXDATA_SELECT_INPUT	(IMXRT_IOMUXC_b.offset038)

  6097. #define IOMUXC_ENET_RXEN_SELECT_INPUT		(IMXRT_IOMUXC_b.offset03C)

  6098. #define IOMUXC_ENET_RXERR_SELECT_INPUT		(IMXRT_IOMUXC_b.offset040)

  6099. #define IOMUXC_ENET0_TIMER_SELECT_INPUT		(IMXRT_IOMUXC_b.offset044)

  6100. #define IOMUXC_ENET_TXCLK_SELECT_INPUT		(IMXRT_IOMUXC_b.offset048)

  6101. #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset04C)

  6102. #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset050)

  6103. #define IOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset054)

  6104. #define IOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset058)

  6105. #define IOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset05C)

  6106. #define IOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset060)

  6107. #define IOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset064)

  6108. #define IOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset068)

  6109. #define IOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset06C)

  6110. #define IOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset070)

  6111. #define IOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset074)

  6112. #define IOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset078)

  6113. #define IOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset07C)

  6114. #define IOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset080)

  6115. #define IOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset084)

  6116. #define IOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset088)

  6117. #define IOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset09C)

  6118. #define IOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset090)

  6119. #define IOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset094)

  6120. #define IOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset098)

  6121. #define IOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset09C)

  6122. #define IOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0A0)

  6123. #define IOMUXC_FLEXSPIA_DQS_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0A4)

  6124. #define IOMUXC_FLEXSPIA_DATA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0A8)

  6125. #define IOMUXC_FLEXSPIA_DATA1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0AC)

  6126. #define IOMUXC_FLEXSPIA_DATA2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0B0)

  6127. #define IOMUXC_FLEXSPIA_DATA3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0B4)

  6128. #define IOMUXC_FLEXSPIB_DATA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0B8)

  6129. #define IOMUXC_FLEXSPIB_DATA1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0BC)

  6130. #define IOMUXC_FLEXSPIB_DATA2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0C0)

  6131. #define IOMUXC_FLEXSPIB_DATA3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0C4)

  6132. #define IOMUXC_FLEXSPIA_SCK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset0C8)

  6133. #define IOMUXC_LPI2C1_SCL_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0CC)

  6134. #define IOMUXC_LPI2C1_SDA_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0D0)

  6135. #define IOMUXC_LPI2C2_SCL_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0D4)

  6136. #define IOMUXC_LPI2C2_SDA_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0D8)

  6137. #define IOMUXC_LPI2C3_SCL_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0DC)

  6138. #define IOMUXC_LPI2C3_SDA_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0E0)

  6139. #define IOMUXC_LPI2C4_SCL_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0E4)

  6140. #define IOMUXC_LPI2C4_SDA_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0E8)

  6141. #define IOMUXC_LPSPI1_PCS0_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0EC)

  6142. #define IOMUXC_LPSPI1_SCK_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0F0)

  6143. #define IOMUXC_LPSPI1_SDI_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0F4)

  6144. #define IOMUXC_LPSPI1_SDO_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0F8)

  6145. #define IOMUXC_LPSPI2_PCS0_SELECT_INPUT		(IMXRT_IOMUXC_b.offset0FC)

  6146. #define IOMUXC_LPSPI2_SCK_SELECT_INPUT		(IMXRT_IOMUXC_b.offset100)

  6147. #define IOMUXC_LPSPI2_SDI_SELECT_INPUT		(IMXRT_IOMUXC_b.offset104)

  6148. #define IOMUXC_LPSPI2_SDO_SELECT_INPUT		(IMXRT_IOMUXC_b.offset108)

  6149. #define IOMUXC_LPSPI3_PCS0_SELECT_INPUT		(IMXRT_IOMUXC_b.offset10C)

  6150. #define IOMUXC_LPSPI3_SCK_SELECT_INPUT		(IMXRT_IOMUXC_b.offset110)

  6151. #define IOMUXC_LPSPI3_SDI_SELECT_INPUT		(IMXRT_IOMUXC_b.offset114)

  6152. #define IOMUXC_LPSPI3_SDO_SELECT_INPUT		(IMXRT_IOMUXC_b.offset118)

  6153. #define IOMUXC_LPSPI4_PCS0_SELECT_INPUT		(IMXRT_IOMUXC_b.offset11C)

  6154. #define IOMUXC_LPSPI4_SCK_SELECT_INPUT		(IMXRT_IOMUXC_b.offset120)

  6155. #define IOMUXC_LPSPI4_SDI_SELECT_INPUT		(IMXRT_IOMUXC_b.offset124)

  6156. #define IOMUXC_LPSPI4_SDO_SELECT_INPUT		(IMXRT_IOMUXC_b.offset128)

  6157. #define IOMUXC_LPUART2_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset12C)

  6158. #define IOMUXC_LPUART2_TX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset130)

  6159. #define IOMUXC_LPUART3_CTS_B_SELECT_INPUT	(IMXRT_IOMUXC_b.offset134)

  6160. #define IOMUXC_LPUART3_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset138)

  6161. #define IOMUXC_LPUART3_TX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset13C)

  6162. #define IOMUXC_LPUART4_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset140)

  6163. #define IOMUXC_LPUART4_TX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset144)

  6164. #define IOMUXC_LPUART5_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset148)

  6165. #define IOMUXC_LPUART5_TX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset14C)

  6166. #define IOMUXC_LPUART6_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset150)

  6167. #define IOMUXC_LPUART6_TX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset154)

  6168. #define IOMUXC_LPUART7_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset158)

  6169. #define IOMUXC_LPUART7_TX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset15C)

  6170. #define IOMUXC_LPUART8_RX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset160)

  6171. #define IOMUXC_LPUART8_TX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset164)

  6172. #define IOMUXC_NMI_GLUE_NMI_SELECT_INPUT	(IMXRT_IOMUXC_b.offset168)

  6173. #define IOMUXC_QTIMER2_TIMER0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset16C)

  6174. #define IOMUXC_QTIMER2_TIMER1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset170)

  6175. #define IOMUXC_QTIMER2_TIMER2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset174)

  6176. #define IOMUXC_QTIMER2_TIMER3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset178)

  6177. #define IOMUXC_QTIMER3_TIMER0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset17C)

  6178. #define IOMUXC_QTIMER3_TIMER1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset180)

  6179. #define IOMUXC_QTIMER3_TIMER2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset184)

  6180. #define IOMUXC_QTIMER3_TIMER3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset188)

  6181. #define IOMUXC_SAI1_MCLK2_SELECT_INPUT		(IMXRT_IOMUXC_b.offset18C)

  6182. #define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset190)

  6183. #define IOMUXC_SAI1_RX_DATA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset194)

  6184. #define IOMUXC_SAI1_RX_DATA1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset198)

  6185. #define IOMUXC_SAI1_RX_DATA2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset19C)

  6186. #define IOMUXC_SAI1_RX_DATA3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1A0)

  6187. #define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1A4)

  6188. #define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1A8)

  6189. #define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1AC)

  6190. #define IOMUXC_SAI2_MCLK2_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1B0)

  6191. #define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1B4)

  6192. #define IOMUXC_SAI2_RX_DATA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1B8)

  6193. #define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1BC)

  6194. #define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1C0)

  6195. #define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1C4)

  6196. #define IOMUXC_SPDIF_IN_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1C8)

  6197. #define IOMUXC_USB_OTG2_OC_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1CC)

  6198. #define IOMUXC_USB_OTG1_OC_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1D0)

  6199. #define IOMUXC_USDHC1_CD_B_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1D4)

  6200. #define IOMUXC_USDHC1_WP_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1D8)

  6201. #define IOMUXC_USDHC2_CLK_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1DC)

  6202. #define IOMUXC_USDHC2_CD_B_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1E0)

  6203. #define IOMUXC_USDHC2_CMD_SELECT_INPUT		(IMXRT_IOMUXC_b.offset1E4)

  6204. #define IOMUXC_USDHC2_DATA0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1E8)

  6205. #define IOMUXC_USDHC2_DATA1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1EC)

  6206. #define IOMUXC_USDHC2_DATA2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1F0)

  6207. #define IOMUXC_USDHC2_DATA3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1F4)

  6208. #define IOMUXC_USDHC2_DATA4_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1F8)

  6209. #define IOMUXC_USDHC2_DATA5_SELECT_INPUT	(IMXRT_IOMUXC_b.offset1FC)

  6210. #define IOMUXC_USDHC2_DATA6_SELECT_INPUT	(IMXRT_IOMUXC_b.offset200)

  6211. #define IOMUXC_USDHC2_DATA7_SELECT_INPUT	(IMXRT_IOMUXC_b.offset204)

  6212. #define IOMUXC_USDHC2_WP_SELECT_INPUT		(IMXRT_IOMUXC_b.offset208)

  6213. #define IOMUXC_XBAR1_IN02_SELECT_INPUT		(IMXRT_IOMUXC_b.offset20C)

  6214. #define IOMUXC_XBAR1_IN03_SELECT_INPUT		(IMXRT_IOMUXC_b.offset210)

  6215. #define IOMUXC_XBAR1_IN04_SELECT_INPUT		(IMXRT_IOMUXC_b.offset214)

  6216. #define IOMUXC_XBAR1_IN05_SELECT_INPUT		(IMXRT_IOMUXC_b.offset218)

  6217. #define IOMUXC_XBAR1_IN06_SELECT_INPUT		(IMXRT_IOMUXC_b.offset21C)

  6218. #define IOMUXC_XBAR1_IN07_SELECT_INPUT		(IMXRT_IOMUXC_b.offset220)

  6219. #define IOMUXC_XBAR1_IN08_SELECT_INPUT		(IMXRT_IOMUXC_b.offset224)

  6220. #define IOMUXC_XBAR1_IN09_SELECT_INPUT		(IMXRT_IOMUXC_b.offset228)

  6221. #define IOMUXC_XBAR1_IN17_SELECT_INPUT		(IMXRT_IOMUXC_b.offset22C)

  6222. #define IOMUXC_XBAR1_IN18_SELECT_INPUT		(IMXRT_IOMUXC_b.offset230)

  6223. #define IOMUXC_XBAR1_IN20_SELECT_INPUT		(IMXRT_IOMUXC_b.offset234)

  6224. #define IOMUXC_XBAR1_IN22_SELECT_INPUT		(IMXRT_IOMUXC_b.offset238)

  6225. #define IOMUXC_XBAR1_IN23_SELECT_INPUT		(IMXRT_IOMUXC_b.offset23C)

  6226. #define IOMUXC_XBAR1_IN24_SELECT_INPUT		(IMXRT_IOMUXC_b.offset240)

  6227. #define IOMUXC_XBAR1_IN14_SELECT_INPUT		(IMXRT_IOMUXC_b.offset244)

  6228. #define IOMUXC_XBAR1_IN15_SELECT_INPUT		(IMXRT_IOMUXC_b.offset248)

  6229. #define IOMUXC_XBAR1_IN16_SELECT_INPUT		(IMXRT_IOMUXC_b.offset24C)

  6230. #define IOMUXC_XBAR1_IN25_SELECT_INPUT		(IMXRT_IOMUXC_b.offset250)

  6231. #define IOMUXC_XBAR1_IN19_SELECT_INPUT		(IMXRT_IOMUXC_b.offset254)

  6232. #define IOMUXC_XBAR1_IN21_SELECT_INPUT		(IMXRT_IOMUXC_b.offset258)

  6233. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00	(IMXRT_IOMUXC_b.offset25C)

  6234. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01	(IMXRT_IOMUXC_b.offset260)

  6235. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02	(IMXRT_IOMUXC_b.offset264)

  6236. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03	(IMXRT_IOMUXC_b.offset268)

  6237. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04	(IMXRT_IOMUXC_b.offset26C)

  6238. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05	(IMXRT_IOMUXC_b.offset270)

  6239. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06	(IMXRT_IOMUXC_b.offset274)

  6240. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07	(IMXRT_IOMUXC_b.offset278)

  6241. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08	(IMXRT_IOMUXC_b.offset27C)

  6242. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09	(IMXRT_IOMUXC_b.offset280)

  6243. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10	(IMXRT_IOMUXC_b.offset284)

  6244. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11	(IMXRT_IOMUXC_b.offset288)

  6245. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12	(IMXRT_IOMUXC_b.offset28C)

  6246. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13	(IMXRT_IOMUXC_b.offset290)

  6247. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00	(IMXRT_IOMUXC_b.offset294)

  6248. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01	(IMXRT_IOMUXC_b.offset298)

  6249. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02	(IMXRT_IOMUXC_b.offset29C)

  6250. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03	(IMXRT_IOMUXC_b.offset2A0)

  6251. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04	(IMXRT_IOMUXC_b.offset2A4)

  6252. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05	(IMXRT_IOMUXC_b.offset2A8)

  6253. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06	(IMXRT_IOMUXC_b.offset2AC)

  6254. #define IOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07	(IMXRT_IOMUXC_b.offset2B0)

  6255. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00	(IMXRT_IOMUXC_b.offset2B4)

  6256. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01	(IMXRT_IOMUXC_b.offset2B8)

  6257. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02	(IMXRT_IOMUXC_b.offset2BC)

  6258. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03	(IMXRT_IOMUXC_b.offset2C0)

  6259. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04	(IMXRT_IOMUXC_b.offset2C4)

  6260. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05	(IMXRT_IOMUXC_b.offset2C8)

  6261. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06	(IMXRT_IOMUXC_b.offset2CC)

  6262. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07	(IMXRT_IOMUXC_b.offset2D0)

  6263. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08	(IMXRT_IOMUXC_b.offset2D4)

  6264. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09	(IMXRT_IOMUXC_b.offset2D8)

  6265. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10	(IMXRT_IOMUXC_b.offset2DC)

  6266. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11	(IMXRT_IOMUXC_b.offset2E0)

  6267. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12	(IMXRT_IOMUXC_b.offset2E4)

  6268. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13	(IMXRT_IOMUXC_b.offset2E8)

  6269. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00	(IMXRT_IOMUXC_b.offset2EC)

  6270. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01	(IMXRT_IOMUXC_b.offset2F0)

  6271. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02	(IMXRT_IOMUXC_b.offset2F4)

  6272. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03	(IMXRT_IOMUXC_b.offset2F8)

  6273. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04	(IMXRT_IOMUXC_b.offset2FC)

  6274. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05	(IMXRT_IOMUXC_b.offset300)

  6275. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06	(IMXRT_IOMUXC_b.offset304)

  6276. #define IOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07	(IMXRT_IOMUXC_b.offset308)

  6277. #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT	(IMXRT_IOMUXC_b.offset30C)

  6278. #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT	(IMXRT_IOMUXC_b.offset310)

  6279. #define IOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0	(IMXRT_IOMUXC_b.offset314)

  6280. #define IOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1	(IMXRT_IOMUXC_b.offset318)

  6281. #define IOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT	(IMXRT_IOMUXC_b.offset31C)

  6282. #define IOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT	(IMXRT_IOMUXC_b.offset320)

  6283. #define IOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0	(IMXRT_IOMUXC_b.offset324)

  6284. #define IOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset328)

  6285. #define IOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT	(IMXRT_IOMUXC_b.offset32C)

  6286. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset330)

  6287. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset334)

  6288. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset338)

  6289. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset33C)

  6290. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT	(IMXRT_IOMUXC_b.offset340)

  6291. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT	(IMXRT_IOMUXC_b.offset344)

  6292. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT	(IMXRT_IOMUXC_b.offset348)

  6293. #define IOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT	(IMXRT_IOMUXC_b.offset34C)

  6294. #define IOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT	(IMXRT_IOMUXC_b.offset350)

  6295. #define IOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT	(IMXRT_IOMUXC_b.offset354)

  6296. #define IOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT		(IMXRT_IOMUXC_b.offset358)

  6297. #define IOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT		(IMXRT_IOMUXC_b.offset35C)

  6298. #define IOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT		(IMXRT_IOMUXC_b.offset360)

  6299. #define IOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT		(IMXRT_IOMUXC_b.offset364)

  6300. #define IOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT		(IMXRT_IOMUXC_b.offset368)

  6301. #define IOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT		(IMXRT_IOMUXC_b.offset36C)

  6302. #define IOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2	(IMXRT_IOMUXC_b.offset370)

  6303. #define IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset374)

  6304. #define IOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0	(IMXRT_IOMUXC_b.offset378)

  6305. #define IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT	(IMXRT_IOMUXC_b.offset37C)

  6306. #define IOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT	(IMXRT_IOMUXC_b.offset380)

  6307. #define IOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT	(IMXRT_IOMUXC_b.offset384)

  6308. #define IOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT		(IMXRT_IOMUXC_b.offset388)

  6309. #define IOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT		(IMXRT_IOMUXC_b.offset38C)

  6310. #define IOMUXC_PAD_SRE					((uint32_t)(1<<0))

  6311. #define IOMUXC_PAD_DSE(n)				((uint32_t)(((n) & 0x07) << 3))

  6312. #define IOMUXC_PAD_SPEED(n)				((uint32_t)(((n) & 0x03) << 6))

  6313. #define IOMUXC_PAD_ODE					((uint32_t)(1<<11))

  6314. #define IOMUXC_PAD_PKE					((uint32_t)(1<<12))

  6315. #define IOMUXC_PAD_PUE					((uint32_t)(1<<13))

  6316. #define IOMUXC_PAD_PUS(n)				((uint32_t)(((n) & 0x03) << 14))

  6317. #define IOMUXC_PAD_HYS					((uint32_t)(1<<16))

  6318. 

  6319. // 46.7: page 2732

  6320. #define IMXRT_KPP		(*(IMXRT_REGISTER16_t *)0x401FC000)

  6321. #define KPP_KPCR			(IMXRT_KPP.offset000)

  6322. #define KPP_KPSR			(IMXRT_KPP.offset002)

  6323. #define KPP_KDDR			(IMXRT_KPP.offset004)

  6324. #define KPP_KPDR			(IMXRT_KPP.offset006)

  6325. 

  6326. // 35.7: page 1860

  6327. #define IMXRT_LCDIF		(*(IMXRT_REGISTER32_t *)0x402B8000)

  6328. #define LCDIF_CTRL			(IMXRT_LCDIF.offset000)

  6329. #define LCDIF_CTRL_SET			(IMXRT_LCDIF.offset004)

  6330. #define LCDIF_CTRL_CLR			(IMXRT_LCDIF.offset008)

  6331. #define LCDIF_CTRL_TOG			(IMXRT_LCDIF.offset00C)

  6332. #define LCDIF_CTRL1			(IMXRT_LCDIF.offset010)

  6333. #define LCDIF_CTRL1_SET			(IMXRT_LCDIF.offset014)

  6334. #define LCDIF_CTRL1_CLR			(IMXRT_LCDIF.offset018)

  6335. #define LCDIF_CTRL1_TOG			(IMXRT_LCDIF.offset01C)

  6336. #define LCDIF_CTRL2			(IMXRT_LCDIF.offset020)

  6337. #define LCDIF_CTRL2_SET			(IMXRT_LCDIF.offset024)

  6338. #define LCDIF_CTRL2_CLR			(IMXRT_LCDIF.offset028)

  6339. #define LCDIF_CTRL2_TOG			(IMXRT_LCDIF.offset02C)

  6340. #define LCDIF_TRANSFER_COUNT		(IMXRT_LCDIF.offset030)

  6341. #define LCDIF_CUR_BUF			(IMXRT_LCDIF.offset040)

  6342. #define LCDIF_NEXT_BUF			(IMXRT_LCDIF.offset050)

  6343. #define LCDIF_VDCTRL0			(IMXRT_LCDIF.offset070)

  6344. #define LCDIF_VDCTRL0_SET		(IMXRT_LCDIF.offset074)

  6345. #define LCDIF_VDCTRL0_CLR		(IMXRT_LCDIF.offset078)

  6346. #define LCDIF_VDCTRL0_TOG		(IMXRT_LCDIF.offset07C)

  6347. #define LCDIF_VDCTRL1			(IMXRT_LCDIF.offset080)

  6348. #define LCDIF_VDCTRL2			(IMXRT_LCDIF.offset090)

  6349. #define LCDIF_VDCTRL3			(IMXRT_LCDIF.offset0A0)

  6350. #define LCDIF_VDCTRL4			(IMXRT_LCDIF.offset0B0)

  6351. #define LCDIF_BM_ERROR_STAT		(IMXRT_LCDIF.offset190)

  6352. #define LCDIF_CRC_STAT			(IMXRT_LCDIF.offset1A0)

  6353. #define LCDIF_STAT			(IMXRT_LCDIF.offset1B0)

  6354. #define LCDIF_THRES			(IMXRT_LCDIF.offset200)

  6355. #define LCDIF_AS_CTRL			(IMXRT_LCDIF.offset210)

  6356. #define LCDIF_AS_BUF			(IMXRT_LCDIF.offset220)

  6357. #define LCDIF_AS_NEXT_BUF		(IMXRT_LCDIF.offset230)

  6358. #define LCDIF_AS_CLRKEYLOW		(IMXRT_LCDIF.offset240)

  6359. #define LCDIF_AS_CLRKEYHIGH		(IMXRT_LCDIF.offset250)

  6360. #define LCDIF_PIGEONCTRL0		(IMXRT_LCDIF.offset380)

  6361. #define LCDIF_PIGEONCTRL0_SET		(IMXRT_LCDIF.offset384)

  6362. #define LCDIF_PIGEONCTRL0_CLR		(IMXRT_LCDIF.offset388)

  6363. #define LCDIF_PIGEONCTRL0_TOG		(IMXRT_LCDIF.offset38C)

  6364. #define LCDIF_PIGEONCTRL1		(IMXRT_LCDIF.offset390)

  6365. #define LCDIF_PIGEONCTRL1_SET		(IMXRT_LCDIF.offset394)

  6366. #define LCDIF_PIGEONCTRL1_CLR		(IMXRT_LCDIF.offset398)

  6367. #define LCDIF_PIGEONCTRL1_TOG		(IMXRT_LCDIF.offset39C)

  6368. #define LCDIF_PIGEONCTRL2		(IMXRT_LCDIF.offset3A0)

  6369. #define LCDIF_PIGEONCTRL2_SET		(IMXRT_LCDIF.offset3A4)

  6370. #define LCDIF_PIGEONCTRL2_CLR		(IMXRT_LCDIF.offset3A8)

  6371. #define LCDIF_PIGEONCTRL2_TOG		(IMXRT_LCDIF.offset3AC)

  6372. #define IMXRT_LCDIF_b		(*(IMXRT_REGISTER32_t *)0x402B8800)

  6373. #define LCDIF_PIGEON_0_0		(IMXRT_LCDIF_b.offset000)

  6374. #define LCDIF_PIGEON_0_1		(IMXRT_LCDIF_b.offset010)

  6375. #define LCDIF_PIGEON_0_2		(IMXRT_LCDIF_b.offset020)

  6376. #define LCDIF_PIGEON_1_0		(IMXRT_LCDIF_b.offset040)

  6377. #define LCDIF_PIGEON_1_1		(IMXRT_LCDIF_b.offset050)

  6378. #define LCDIF_PIGEON_1_2		(IMXRT_LCDIF_b.offset060)

  6379. #define LCDIF_PIGEON_2_0		(IMXRT_LCDIF_b.offset080)

  6380. #define LCDIF_PIGEON_2_1		(IMXRT_LCDIF_b.offset090)

  6381. #define LCDIF_PIGEON_2_2		(IMXRT_LCDIF_b.offset0A0)

  6382. #define LCDIF_PIGEON_3_0		(IMXRT_LCDIF_b.offset0C0)

  6383. #define LCDIF_PIGEON_3_1		(IMXRT_LCDIF_b.offset0D0)

  6384. #define LCDIF_PIGEON_3_2		(IMXRT_LCDIF_b.offset0E0)

  6385. #define LCDIF_PIGEON_4_0		(IMXRT_LCDIF_b.offset100)

  6386. #define LCDIF_PIGEON_4_1		(IMXRT_LCDIF_b.offset110)

  6387. #define LCDIF_PIGEON_4_2		(IMXRT_LCDIF_b.offset120)

  6388. #define LCDIF_PIGEON_5_0		(IMXRT_LCDIF_b.offset140)

  6389. #define LCDIF_PIGEON_5_1		(IMXRT_LCDIF_b.offset150)

  6390. #define LCDIF_PIGEON_5_2		(IMXRT_LCDIF_b.offset160)

  6391. #define LCDIF_PIGEON_6_0		(IMXRT_LCDIF_b.offset180)

  6392. #define LCDIF_PIGEON_6_1		(IMXRT_LCDIF_b.offset190)

  6393. #define LCDIF_PIGEON_6_2		(IMXRT_LCDIF_b.offset1A0)

  6394. #define LCDIF_PIGEON_7_0		(IMXRT_LCDIF_b.offset1C0)

  6395. #define LCDIF_PIGEON_7_1		(IMXRT_LCDIF_b.offset1D0)

  6396. #define LCDIF_PIGEON_7_2		(IMXRT_LCDIF_b.offset1E0)

  6397. #define LCDIF_PIGEON_8_0		(IMXRT_LCDIF_b.offset200)

  6398. #define LCDIF_PIGEON_8_1		(IMXRT_LCDIF_b.offset210)

  6399. #define LCDIF_PIGEON_8_2		(IMXRT_LCDIF_b.offset220)

  6400. #define LCDIF_PIGEON_9_0		(IMXRT_LCDIF_b.offset240)

  6401. #define LCDIF_PIGEON_9_1		(IMXRT_LCDIF_b.offset250)

  6402. #define LCDIF_PIGEON_9_2		(IMXRT_LCDIF_b.offset260)

  6403. #define LCDIF_PIGEON_10_0		(IMXRT_LCDIF_b.offset280)

  6404. #define LCDIF_PIGEON_10_1		(IMXRT_LCDIF_b.offset290)

  6405. #define LCDIF_PIGEON_10_2		(IMXRT_LCDIF_b.offset2A0)

  6406. #define LCDIF_PIGEON_11_0		(IMXRT_LCDIF_b.offset2C0)

  6407. #define LCDIF_PIGEON_11_1		(IMXRT_LCDIF_b.offset2D0)

  6408. #define LCDIF_PIGEON_11_2		(IMXRT_LCDIF_b.offset2E0)

  6409. 

  6410. // 47.4.1.1: page 2758

  6411. typedef struct {

  6412. 	const uint32_t VERID;

  6413. 	const uint32_t PARAM;

  6414. 	const uint32_t unused1;

  6415. 	const uint32_t unused2;

  6416. 	volatile uint32_t MCR;			// 010

  6417. 	volatile uint32_t MSR;			// 014

  6418. 	volatile uint32_t MIER;			// 018

  6419. 	volatile uint32_t MDER;			// 01C

  6420. 	volatile uint32_t MCFGR0;		// 020

  6421. 	volatile uint32_t MCFGR1;		// 024

  6422. 	volatile uint32_t MCFGR2;		// 028

  6423. 	volatile uint32_t MCFGR3;		// 02C

  6424. 	volatile uint32_t unused3[4];

  6425. 	volatile uint32_t MDMR;			// 040

  6426. 	volatile uint32_t unused4;

  6427. 	volatile uint32_t MCCR0;		// 048

  6428. 	volatile uint32_t unused5;

  6429. 	volatile uint32_t MCCR1;		// 050

  6430. 	volatile uint32_t unused6;

  6431. 	volatile uint32_t MFCR;			// 058

  6432. 	volatile uint32_t MFSR;			// 05C

  6433. 	volatile uint32_t MTDR;			// 060

  6434. 	volatile uint32_t unused7[3];

  6435. 	volatile uint32_t MRDR;			// 070

  6436. 	volatile uint32_t unused8[39];

  6437. 	volatile uint32_t SCR;			// 110

  6438. 	volatile uint32_t SSR;			// 114

  6439. 	volatile uint32_t SIER;			// 118

  6440. 	volatile uint32_t SDER;			// 11C

  6441. 	volatile uint32_t unused9;

  6442. 	volatile uint32_t SCFGR1;		// 124

  6443. 	volatile uint32_t SCFGR2;		// 128

  6444. 	volatile uint32_t unused10[5];

  6445. 	volatile uint32_t SAMR;			// 140

  6446. 	volatile uint32_t unused11[3];

  6447. 	volatile uint32_t SASR;			// 150

  6448. 	volatile uint32_t unused12[3];

  6449. 	volatile uint32_t STAR;			// 154

  6450. 	volatile uint32_t unused13[3];

  6451. 	volatile uint32_t STDR;			// 160

  6452. 	volatile uint32_t unused14[3];

  6453. 	volatile uint32_t SRDR;			// 170

  6454. } IMXRT_LPI2C_t;

  6455. #define IMXRT_LPI2C1		(*(IMXRT_LPI2C_t *)0x403F0000)

  6456. #define LPI2C1_VERID			(IMXRT_LPI2C1.VERID)

  6457. #define LPI2C1_PARAM			(IMXRT_LPI2C1.PARAM)

  6458. #define LPI2C1_MCR			(IMXRT_LPI2C1.MCR)

  6459. #define LPI2C1_MSR			(IMXRT_LPI2C1.MSR)

  6460. #define LPI2C1_MIER			(IMXRT_LPI2C1.MIER)

  6461. #define LPI2C1_MDER			(IMXRT_LPI2C1.MDER)

  6462. #define LPI2C1_MCFGR0			(IMXRT_LPI2C1.MCFGR0)

  6463. #define LPI2C1_MCFGR1			(IMXRT_LPI2C1.MCFGR1)

  6464. #define LPI2C1_MCFGR2			(IMXRT_LPI2C1.MCFGR2)

  6465. #define LPI2C1_MCFGR3			(IMXRT_LPI2C1.MCFGR3)

  6466. #define LPI2C1_MDMR			(IMXRT_LPI2C1.MDMR)

  6467. #define LPI2C1_MCCR0			(IMXRT_LPI2C1.MCCR0)

  6468. #define LPI2C1_MCCR1			(IMXRT_LPI2C1.MCCR1)

  6469. #define LPI2C1_MFCR			(IMXRT_LPI2C1.MFCR)

  6470. #define LPI2C1_MFSR			(IMXRT_LPI2C1.MFSR)

  6471. #define LPI2C1_MTDR			(IMXRT_LPI2C1.MTDR)

  6472. #define LPI2C1_MRDR			(IMXRT_LPI2C1.MRDR)

  6473. #define LPI2C1_SCR			(IMXRT_LPI2C1.SCR)

  6474. #define LPI2C1_SSR			(IMXRT_LPI2C1.SSR)

  6475. #define LPI2C1_SIER			(IMXRT_LPI2C1.SIER)

  6476. #define LPI2C1_SDER			(IMXRT_LPI2C1.SDER)

  6477. #define LPI2C1_SCFGR1			(IMXRT_LPI2C1.SCFGR1)

  6478. #define LPI2C1_SCFGR2			(IMXRT_LPI2C1.SCFGR2)

  6479. #define LPI2C1_SAMR			(IMXRT_LPI2C1.SAMR)

  6480. #define LPI2C1_SASR			(IMXRT_LPI2C1.SASR)

  6481. #define LPI2C1_STAR			(IMXRT_LPI2C1.STAR)

  6482. #define LPI2C1_STDR			(IMXRT_LPI2C1.STDR)

  6483. #define LPI2C1_SRDR			(IMXRT_LPI2C1.SRDR)

  6484. #define IMXRT_LPI2C2		(*(IMXRT_LPI2C_t *)0x403F4000)

  6485. #define LPI2C2_VERID			(IMXRT_LPI2C2.VERID)

  6486. #define LPI2C2_PARAM			(IMXRT_LPI2C2.PARAM)

  6487. #define LPI2C2_MCR			(IMXRT_LPI2C2.MCR)

  6488. #define LPI2C2_MSR			(IMXRT_LPI2C2.MSR)

  6489. #define LPI2C2_MIER			(IMXRT_LPI2C2.MIER)

  6490. #define LPI2C2_MDER			(IMXRT_LPI2C2.MDER)

  6491. #define LPI2C2_MCFGR0			(IMXRT_LPI2C2.MCFGR0)

  6492. #define LPI2C2_MCFGR1			(IMXRT_LPI2C2.MCFGR1)

  6493. #define LPI2C2_MCFGR2			(IMXRT_LPI2C2.MCFGR2)

  6494. #define LPI2C2_MCFGR3			(IMXRT_LPI2C2.MCFGR3)

  6495. #define LPI2C2_MDMR			(IMXRT_LPI2C2.MDMR)

  6496. #define LPI2C2_MCCR0			(IMXRT_LPI2C2.MCCR0)

  6497. #define LPI2C2_MCCR1			(IMXRT_LPI2C2.MCCR1)

  6498. #define LPI2C2_MFCR			(IMXRT_LPI2C2.MFCR)

  6499. #define LPI2C2_MFSR			(IMXRT_LPI2C2.MFSR)

  6500. #define LPI2C2_MTDR			(IMXRT_LPI2C2.MTDR)

  6501. #define LPI2C2_MRDR			(IMXRT_LPI2C2.MRDR)

  6502. #define LPI2C2_SCR			(IMXRT_LPI2C2.SCR)

  6503. #define LPI2C2_SSR			(IMXRT_LPI2C2.SSR)

  6504. #define LPI2C2_SIER			(IMXRT_LPI2C2.SIER)

  6505. #define LPI2C2_SDER			(IMXRT_LPI2C2.SDER)

  6506. #define LPI2C2_SCFGR1			(IMXRT_LPI2C2.SCFGR1)

  6507. #define LPI2C2_SCFGR2			(IMXRT_LPI2C2.SCFGR2)

  6508. #define LPI2C2_SAMR			(IMXRT_LPI2C2.SAMR)

  6509. #define LPI2C2_SASR			(IMXRT_LPI2C2.SASR)

  6510. #define LPI2C2_STAR			(IMXRT_LPI2C2.STAR)

  6511. #define LPI2C2_STDR			(IMXRT_LPI2C2.STDR)

  6512. #define LPI2C2_SRDR			(IMXRT_LPI2C2.SRDR)

  6513. #define IMXRT_LPI2C3		(*(IMXRT_LPI2C_t *)0x403F8000)

  6514. #define LPI2C3_VERID			(IMXRT_LPI2C3.VERID)

  6515. #define LPI2C3_PARAM			(IMXRT_LPI2C3.PARAM)

  6516. #define LPI2C3_MCR			(IMXRT_LPI2C3.MCR)

  6517. #define LPI2C3_MSR			(IMXRT_LPI2C3.MSR)

  6518. #define LPI2C3_MIER			(IMXRT_LPI2C3.MIER)

  6519. #define LPI2C3_MDER			(IMXRT_LPI2C3.MDER)

  6520. #define LPI2C3_MCFGR0			(IMXRT_LPI2C3.MCFGR0)

  6521. #define LPI2C3_MCFGR1			(IMXRT_LPI2C3.MCFGR1)

  6522. #define LPI2C3_MCFGR2			(IMXRT_LPI2C3.MCFGR2)

  6523. #define LPI2C3_MCFGR3			(IMXRT_LPI2C3.MCFGR3)

  6524. #define LPI2C3_MDMR			(IMXRT_LPI2C3.MDMR)

  6525. #define LPI2C3_MCCR0			(IMXRT_LPI2C3.MCCR0)

  6526. #define LPI2C3_MCCR1			(IMXRT_LPI2C3.MCCR1)

  6527. #define LPI2C3_MFCR			(IMXRT_LPI2C3.MFCR)

  6528. #define LPI2C3_MFSR			(IMXRT_LPI2C3.MFSR)

  6529. #define LPI2C3_MTDR			(IMXRT_LPI2C3.MTDR)

  6530. #define LPI2C3_MRDR			(IMXRT_LPI2C3.MRDR)

  6531. #define LPI2C3_SCR			(IMXRT_LPI2C3.SCR)

  6532. #define LPI2C3_SSR			(IMXRT_LPI2C3.SSR)

  6533. #define LPI2C3_SIER			(IMXRT_LPI2C3.SIER)

  6534. #define LPI2C3_SDER			(IMXRT_LPI2C3.SDER)

  6535. #define LPI2C3_SCFGR1			(IMXRT_LPI2C3.SCFGR1)

  6536. #define LPI2C3_SCFGR2			(IMXRT_LPI2C3.SCFGR2)

  6537. #define LPI2C3_SAMR			(IMXRT_LPI2C3.SAMR)

  6538. #define LPI2C3_SASR			(IMXRT_LPI2C3.SASR)

  6539. #define LPI2C3_STAR			(IMXRT_LPI2C3.STAR)

  6540. #define LPI2C3_STDR			(IMXRT_LPI2C3.STDR)

  6541. #define LPI2C3_SRDR			(IMXRT_LPI2C3.SRDR)

  6542. #define IMXRT_LPI2C4		(*(IMXRT_LPI2C_t *)0x403FC000)

  6543. #define LPI2C4_VERID			(IMXRT_LPI2C4.VERID)

  6544. #define LPI2C4_PARAM			(IMXRT_LPI2C4.PARAM)

  6545. #define LPI2C4_MCR			(IMXRT_LPI2C4.MCR)

  6546. #define LPI2C4_MSR			(IMXRT_LPI2C4.MSR)

  6547. #define LPI2C4_MIER			(IMXRT_LPI2C4.MIER)

  6548. #define LPI2C4_MDER			(IMXRT_LPI2C4.MDER)

  6549. #define LPI2C4_MCFGR0			(IMXRT_LPI2C4.MCFGR0)

  6550. #define LPI2C4_MCFGR1			(IMXRT_LPI2C4.MCFGR1)

  6551. #define LPI2C4_MCFGR2			(IMXRT_LPI2C4.MCFGR2)

  6552. #define LPI2C4_MCFGR3			(IMXRT_LPI2C4.MCFGR3)

  6553. #define LPI2C4_MDMR			(IMXRT_LPI2C4.MDMR)

  6554. #define LPI2C4_MCCR0			(IMXRT_LPI2C4.MCCR0)

  6555. #define LPI2C4_MCCR1			(IMXRT_LPI2C4.MCCR1)

  6556. #define LPI2C4_MFCR			(IMXRT_LPI2C4.MFCR)

  6557. #define LPI2C4_MFSR			(IMXRT_LPI2C4.MFSR)

  6558. #define LPI2C4_MTDR			(IMXRT_LPI2C4.MTDR)

  6559. #define LPI2C4_MRDR			(IMXRT_LPI2C4.MRDR)

  6560. #define LPI2C4_SCR			(IMXRT_LPI2C4.SCR)

  6561. #define LPI2C4_SSR			(IMXRT_LPI2C4.SSR)

  6562. #define LPI2C4_SIER			(IMXRT_LPI2C4.SIER)

  6563. #define LPI2C4_SDER			(IMXRT_LPI2C4.SDER)

  6564. #define LPI2C4_SCFGR1			(IMXRT_LPI2C4.SCFGR1)

  6565. #define LPI2C4_SCFGR2			(IMXRT_LPI2C4.SCFGR2)

  6566. #define LPI2C4_SAMR			(IMXRT_LPI2C4.SAMR)

  6567. #define LPI2C4_SASR			(IMXRT_LPI2C4.SASR)

  6568. #define LPI2C4_STAR			(IMXRT_LPI2C4.STAR)

  6569. #define LPI2C4_STDR			(IMXRT_LPI2C4.STDR)

  6570. #define LPI2C4_SRDR			(IMXRT_LPI2C4.SRDR)

  6571. #define LPI2C_MCR_RRF				((uint32_t)(1<<9))

  6572. #define LPI2C_MCR_RTF				((uint32_t)(1<<8))

  6573. #define LPI2C_MCR_DBGEN				((uint32_t)(1<<3))

  6574. #define LPI2C_MCR_DOZEN				((uint32_t)(1<<2))

  6575. #define LPI2C_MCR_RST				((uint32_t)(1<<1))

  6576. #define LPI2C_MCR_MEN				((uint32_t)(1<<0))

  6577. #define LPI2C_MSR_BBF				((uint32_t)(1<<25))

  6578. #define LPI2C_MSR_MBF				((uint32_t)(1<<24))

  6579. #define LPI2C_MSR_DMF				((uint32_t)(1<<14))

  6580. #define LPI2C_MSR_PLTF				((uint32_t)(1<<13))

  6581. #define LPI2C_MSR_FEF				((uint32_t)(1<<12))

  6582. #define LPI2C_MSR_ALF				((uint32_t)(1<<11))

  6583. #define LPI2C_MSR_NDF				((uint32_t)(1<<10))

  6584. #define LPI2C_MSR_SDF				((uint32_t)(1<<9))

  6585. #define LPI2C_MSR_EPF				((uint32_t)(1<<8))

  6586. #define LPI2C_MSR_RDF				((uint32_t)(1<<1))

  6587. #define LPI2C_MSR_TDF				((uint32_t)(1<<0))

  6588. #define LPI2C_MIER_DMIE				((uint32_t)(1<<14))

  6589. #define LPI2C_MIER_PLTIE			((uint32_t)(1<<13))

  6590. #define LPI2C_MIER_FEIE				((uint32_t)(1<<12))

  6591. #define LPI2C_MIER_ALIE				((uint32_t)(1<<11))

  6592. #define LPI2C_MIER_NDIE				((uint32_t)(1<<10))

  6593. #define LPI2C_MIER_SDIE				((uint32_t)(1<<9))

  6594. #define LPI2C_MIER_EPIE				((uint32_t)(1<<8))

  6595. #define LPI2C_MIER_RDIE				((uint32_t)(1<<1))

  6596. #define LPI2C_MIER_TDIE				((uint32_t)(1<<0))

  6597. #define LPI2C_MDER_RDDE				((uint32_t)(1<<1))

  6598. #define LPI2C_MDER_TDDE				((uint32_t)(1<<0))

  6599. #define LPI2C_MCFGR0_RDMO			((uint32_t)(1<<9))

  6600. #define LPI2C_MCFGR0_CIRFIFO			((uint32_t)(1<<8))

  6601. #define LPI2C_MCFGR0_HRSEL			((uint32_t)(1<<2))

  6602. #define LPI2C_MCFGR0_HRPOL			((uint32_t)(1<<1))

  6603. #define LPI2C_MCFGR0_HREN			((uint32_t)(1<<0))

  6604. #define LPI2C_MCFGR1_PINCFG(n)			((uint32_t)(((n) & 0x07) << 24))

  6605. #define LPI2C_MCFGR1_MATCFG(n)			((uint32_t)(((n) & 0x07) << 16))

  6606. #define LPI2C_MCFGR1_TIMECFG			((uint32_t)(1<<10))

  6607. #define LPI2C_MCFGR1_IGNACK			((uint32_t)(1<<9))

  6608. #define LPI2C_MCFGR1_AUTOSTOP			((uint32_t)(1<<8))

  6609. #define LPI2C_MCFGR1_PRESCALE(n)		((uint32_t)(((n) & 0x07) << 0))

  6610. #define LPI2C_MCFGR2_FILTSDA(n)			((uint32_t)(((n) & 0x0F) << 24))

  6611. #define LPI2C_MCFGR2_FILTSCL(n)			((uint32_t)(((n) & 0x0F) << 16))

  6612. #define LPI2C_MCFGR2_BUSIDLE(n)			((uint32_t)(((n) & 0xFFF) << 0))

  6613. #define LPI2C_MCFGR3_PINLOW(n)			((uint32_t)(((n) & 0xFFF) << 8))

  6614. #define LPI2C_MDMR_MATCH1(n)			((uint32_t)(((n) & 0xFF) << 16))

  6615. #define LPI2C_MDMR_MATCH0(n)			((uint32_t)(((n) & 0xFF) << 0))

  6616. #define LPI2C_MCCR0_DATAVD(n)			((uint32_t)(((n) & 0x3F) << 24))

  6617. #define LPI2C_MCCR0_SETHOLD(n)			((uint32_t)(((n) & 0x3F) << 16))

  6618. #define LPI2C_MCCR0_CLKHI(n)			((uint32_t)(((n) & 0x3F) << 8))

  6619. #define LPI2C_MCCR0_CLKLO(n)			((uint32_t)(((n) & 0x3F) << 0))

  6620. #define LPI2C_MCCR1_DATAVD(n)			((uint32_t)(((n) & 0x3F) << 24))

  6621. #define LPI2C_MCCR1_SETHOLD(n)			((uint32_t)(((n) & 0x3F) << 16))

  6622. #define LPI2C_MCCR1_CLKHI(n)			((uint32_t)(((n) & 0x3F) << 8))

  6623. #define LPI2C_MCCR1_CLKLO(n)			((uint32_t)(((n) & 0x3F) << 0))

  6624. #define LPI2C_MFCR_RXWATER(n)			((uint32_t)(((n) & 0x03) << 16))

  6625. #define LPI2C_MFCR_TXWATER(n)			((uint32_t)(((n) & 0x03) << 0))

  6626. #define LPI2C_MFSR_RXCOUNT(n)			((uint32_t)(((n) & 0x07) << 16))

  6627. #define LPI2C_MFSR_TXCOUNT(n)			((uint32_t)(((n) & 0x07) << 16))

  6628. #define LPI2C_MTDR_CMD(n)			((uint32_t)(((n) & 0x07) << 8))

  6629. #define LPI2C_MTDR_CMD_TRANSMIT			((uint32_t)(0 << 8))

  6630. #define LPI2C_MTDR_CMD_RECEIVE			((uint32_t)(1 << 8))

  6631. #define LPI2C_MTDR_CMD_STOP			((uint32_t)(2 << 8))

  6632. #define LPI2C_MTDR_CMD_DISCARD			((uint32_t)(3 << 8))

  6633. #define LPI2C_MTDR_CMD_START			((uint32_t)(4 << 8))

  6634. #define LPI2C_MTDR_CMD_START_NACK		((uint32_t)(5 << 8))

  6635. #define LPI2C_MTDR_CMD_HS_START			((uint32_t)(6 << 8))

  6636. #define LPI2C_MTDR_CMD_HS_START_NAcK		((uint32_t)(7 << 8))

  6637. #define LPI2C_MTDR_DATA(n)			((uint32_t)(((n) & 0xFF) << 0))

  6638. #define LPI2C_MRDR_RXEMPTY			((uint32_t)(1<<14))

  6639. #define LPI2C_MRDR_DATA(n)			((uint32_t)(((n) & 0xFF) << 0))

  6640. #define LPI2C_SCR_RRF				((uint32_t)(1<<9))

  6641. #define LPI2C_SCR_RTF				((uint32_t)(1<<8))

  6642. #define LPI2C_SCR_FILTDZ			((uint32_t)(1<<5))

  6643. #define LPI2C_SCR_FILTEN			((uint32_t)(1<<4))

  6644. #define LPI2C_SCR_RST				((uint32_t)(1<<1))

  6645. #define LPI2C_SCR_SEN				((uint32_t)(1<<0))

  6646. #define LPI2C_SSR_BBF				((uint32_t)(1<<25))

  6647. #define LPI2C_SSR_SBF				((uint32_t)(1<<24))

  6648. #define LPI2C_SSR_SARF				((uint32_t)(1<<15))

  6649. #define LPI2C_SSR_GCF				((uint32_t)(1<<14))

  6650. #define LPI2C_SSR_AM1F				((uint32_t)(1<<13))

  6651. #define LPI2C_SSR_AM0F				((uint32_t)(1<<12))

  6652. #define LPI2C_SSR_FEF				((uint32_t)(1<<11))

  6653. #define LPI2C_SSR_BEF				((uint32_t)(1<<10))

  6654. #define LPI2C_SSR_SDF				((uint32_t)(1<<9))

  6655. #define LPI2C_SSR_RSF				((uint32_t)(1<<8))

  6656. #define LPI2C_SSR_TAF				((uint32_t)(1<<3))

  6657. #define LPI2C_SSR_AVF				((uint32_t)(1<<2))

  6658. #define LPI2C_SSR_RDF				((uint32_t)(1<<1))

  6659. #define LPI2C_SSR_TDF				((uint32_t)(1<<0))

  6660. #define LPI2C_SIER_SARIE			((uint32_t)(1<<25))

  6661. #define LPI2C_SIER_GCIE				((uint32_t)(1<<24))

  6662. #define LPI2C_SIER_AM1F				((uint32_t)(1<<13))

  6663. #define LPI2C_SIER_AM0IE			((uint32_t)(1<<12))

  6664. #define LPI2C_SIER_FEIE				((uint32_t)(1<<11))

  6665. #define LPI2C_SIER_BEIE				((uint32_t)(1<<10))

  6666. #define LPI2C_SIER_SDIE				((uint32_t)(1<<9))

  6667. #define LPI2C_SIER_RSIE				((uint32_t)(1<<8))

  6668. #define LPI2C_SIER_TAIE				((uint32_t)(1<<3))

  6669. #define LPI2C_SIER_AVIE				((uint32_t)(1<<2))

  6670. #define LPI2C_SIER_RDIE				((uint32_t)(1<<1))

  6671. #define LPI2C_SIER_TDIE				((uint32_t)(1<<0))

  6672. #define LPI2C_SDER_AVDE				((uint32_t)(1<<2))

  6673. #define LPI2C_SDER_RDDE				((uint32_t)(1<<1))

  6674. #define LPI2C_SDER_TDDE				((uint32_t)(1<<0))

  6675. #define LPI2C_SCFGR1_ADDRCFG(n)			((uint32_t)(((n) & 0x07) << 16))

  6676. #define LPI2C_SCFGR1_HSMEN			((uint32_t)(1<<13))

  6677. #define LPI2C_SCFGR1_IGNACK			((uint32_t)(1<<12))

  6678. #define LPI2C_SCFGR1_RXCFG			((uint32_t)(1<<11))

  6679. #define LPI2C_SCFGR1_TXCFG			((uint32_t)(1<<10))

  6680. #define LPI2C_SCFGR1_SAEN			((uint32_t)(1<<9))

  6681. #define LPI2C_SCFGR1_GCEN			((uint32_t)(1<<8))

  6682. #define LPI2C_SCFGR1_ACKSTALL			((uint32_t)(1<<3))

  6683. #define LPI2C_SCFGR1_TXDSTALL			((uint32_t)(1<<2))

  6684. #define LPI2C_SCFGR1_RXSTALL			((uint32_t)(1<<1))

  6685. #define LPI2C_SCFGR1_ADRSTALL			((uint32_t)(1<<0))

  6686. #define LPI2C_SCFGR2_FILTSDA(n)			((uint32_t)(((n) & 0x0F) << 24))

  6687. #define LPI2C_SCFGR2_FILTSCL(n)			((uint32_t)(((n) & 0x0F) << 16))

  6688. #define LPI2C_SCFGR2_DATAVD(n)			((uint32_t)(((n) & 0x3F) << 8))

  6689. #define LPI2C_SCFGR2_CLKHOLD(n)			((uint32_t)(((n) & 0x0F) << 0))

  6690. #define LPI2C_SAMR_ADDR1(n)			((uint32_t)(((n) & 0x7F) << 17))

  6691. #define LPI2C_SAMR_ADDR0(n)			((uint32_t)(((n) & 0x7F) << 1))

  6692. #define LPI2C_SASR_ANV				((uint32_t)(1<<14))

  6693. #define LPI2C_SASR_RADDR(n)			((uint32_t)(((n) & 0x7FF) << 0))

  6694. #define LPI2C_STAR_TXNACK			((uint32_t)(1<<0))

  6695. #define LPI2C_STDR_DATA(n)			((uint32_t)(((n) & 0xFF) << 0))

  6696. #define LPI2C_SRDR_SOF				((uint32_t)(1<<15))

  6697. #define LPI2C_SRDR_RXEMPTY			((uint32_t)(1<<14))

  6698. #define LPI2C_SRDR_DATA(n)			((uint32_t)(((n) & 0xFF) << 0))

  6699. 

  6700. // 48.4.1.1: page 2810

  6701. typedef struct {

  6702.         const uint32_t VERID;           // 0

  6703.         const uint32_t PARAM;           // 0x04

  6704.         const uint32_t UNUSED0;         // 0x08

  6705.         const uint32_t UNUSED1;         // 0x0c

  6706.         volatile uint32_t CR;           // 0x10

  6707.         volatile uint32_t SR;           // 0x14

  6708.         volatile uint32_t IER;          // 0x18

  6709.         volatile uint32_t DER;          // 0x1c

  6710.         volatile uint32_t CFGR0;        // 0x20

  6711.         volatile uint32_t CFGR1;        // 0x24

  6712.         const uint32_t UNUSED3;         // 0x28

  6713.         const uint32_t UNUSED4;         // 0x2c

  6714.         volatile uint32_t DMR0;         // 0x30

  6715.         volatile uint32_t DMR1;         // 0x34

  6716.         const uint32_t UNUSED5;         // 0x38

  6717.         const uint32_t UNUSED6;         // 0x3c

  6718.         volatile uint32_t CCR;          // 0x40

  6719.         const uint32_t UNUSED7;         // 0x44

  6720.         const uint32_t UNUSED8;         // 0x48

  6721.         const uint32_t UNUSED9;         // 0x4c

  6722.         const uint32_t UNUSED10;        // 0x50

  6723.         const uint32_t UNUSED11;        // 0x54

  6724.         volatile uint32_t FCR;          // 0x58

  6725.         volatile uint32_t FSR;          // 0x5C

  6726.         volatile uint32_t TCR;          // 0x60

  6727.         volatile uint32_t TDR;          // 0x64

  6728.         const uint32_t UNUSED12;        // 0x68

  6729.         const uint32_t UNUSED13;        // 0x6c

  6730.         volatile uint32_t RSR;          // 0x70

  6731.         volatile uint32_t RDR;          // 0x74

  6732. } IMXRT_LPSPI_t;

  6733. 

  6734. #define IMXRT_LPSPI1		(*(IMXRT_REGISTER32_t *)0x40394000)

  6735. #define IMXRT_LPSPI1_S          (*(IMXRT_LPSPI_t *)0x40394000)

  6736. #define LPSPI1_VERID			(IMXRT_LPSPI1.offset000)

  6737. #define LPSPI1_PARAM			(IMXRT_LPSPI1.offset004)

  6738. #define LPSPI1_CR			(IMXRT_LPSPI1.offset010)

  6739. #define LPSPI1_SR			(IMXRT_LPSPI1.offset014)

  6740. #define LPSPI1_IER			(IMXRT_LPSPI1.offset018)

  6741. #define LPSPI1_DER			(IMXRT_LPSPI1.offset01C)

  6742. #define LPSPI1_CFGR0			(IMXRT_LPSPI1.offset020)

  6743. #define LPSPI1_CFGR1			(IMXRT_LPSPI1.offset024)

  6744. #define LPSPI1_DMR0			(IMXRT_LPSPI1.offset030)

  6745. #define LPSPI1_DMR1			(IMXRT_LPSPI1.offset034)

  6746. #define LPSPI1_CCR			(IMXRT_LPSPI1.offset040)

  6747. #define LPSPI1_FCR			(IMXRT_LPSPI1.offset058)

  6748. #define LPSPI1_FSR			(IMXRT_LPSPI1.offset05C)

  6749. #define LPSPI1_TCR			(IMXRT_LPSPI1.offset060)

  6750. #define LPSPI1_TDR			(IMXRT_LPSPI1.offset064)

  6751. #define LPSPI1_RSR			(IMXRT_LPSPI1.offset070)

  6752. #define LPSPI1_RDR			(IMXRT_LPSPI1.offset074)

  6753. #define IMXRT_LPSPI2		(*(IMXRT_REGISTER32_t *)0x40398000)

  6754. #define IMXRT_LPSPI2_S          (*(IMXRT_LPSPI_t *)0x40398000)

  6755. #define LPSPI2_VERID			(IMXRT_LPSPI2.offset000)

  6756. #define LPSPI2_PARAM			(IMXRT_LPSPI2.offset004)

  6757. #define LPSPI2_CR			(IMXRT_LPSPI2.offset010)

  6758. #define LPSPI2_SR			(IMXRT_LPSPI2.offset014)

  6759. #define LPSPI2_IER			(IMXRT_LPSPI2.offset018)

  6760. #define LPSPI2_DER			(IMXRT_LPSPI2.offset01C)

  6761. #define LPSPI2_CFGR0			(IMXRT_LPSPI2.offset020)

  6762. #define LPSPI2_CFGR1			(IMXRT_LPSPI2.offset024)

  6763. #define LPSPI2_DMR0			(IMXRT_LPSPI2.offset030)

  6764. #define LPSPI2_DMR1			(IMXRT_LPSPI2.offset034)

  6765. #define LPSPI2_CCR			(IMXRT_LPSPI2.offset040)

  6766. #define LPSPI2_FCR			(IMXRT_LPSPI2.offset058)

  6767. #define LPSPI2_FSR			(IMXRT_LPSPI2.offset05C)

  6768. #define LPSPI2_TCR			(IMXRT_LPSPI2.offset060)

  6769. #define LPSPI2_TDR			(IMXRT_LPSPI2.offset064)

  6770. #define LPSPI2_RSR			(IMXRT_LPSPI2.offset070)

  6771. #define LPSPI2_RDR			(IMXRT_LPSPI2.offset074)

  6772. #define IMXRT_LPSPI3		(*(IMXRT_REGISTER32_t *)0x4039C000)

  6773. #define IMXRT_LPSPI3_S          (*(IMXRT_LPSPI_t *)0x4039C000)

  6774. #define LPSPI3_VERID			(IMXRT_LPSPI3.offset000)

  6775. #define LPSPI3_PARAM			(IMXRT_LPSPI3.offset004)

  6776. #define LPSPI3_CR			(IMXRT_LPSPI3.offset010)

  6777. #define LPSPI3_SR			(IMXRT_LPSPI3.offset014)

  6778. #define LPSPI3_IER			(IMXRT_LPSPI3.offset018)

  6779. #define LPSPI3_DER			(IMXRT_LPSPI3.offset01C)

  6780. #define LPSPI3_CFGR0			(IMXRT_LPSPI3.offset020)

  6781. #define LPSPI3_CFGR1			(IMXRT_LPSPI3.offset024)

  6782. #define LPSPI3_DMR0			(IMXRT_LPSPI3.offset030)

  6783. #define LPSPI3_DMR1			(IMXRT_LPSPI3.offset034)

  6784. #define LPSPI3_CCR			(IMXRT_LPSPI3.offset040)

  6785. #define LPSPI3_FCR			(IMXRT_LPSPI3.offset058)

  6786. #define LPSPI3_FSR			(IMXRT_LPSPI3.offset05C)

  6787. #define LPSPI3_TCR			(IMXRT_LPSPI3.offset060)

  6788. #define LPSPI3_TDR			(IMXRT_LPSPI3.offset064)

  6789. #define LPSPI3_RSR			(IMXRT_LPSPI3.offset070)

  6790. #define LPSPI3_RDR			(IMXRT_LPSPI3.offset074)

  6791. #define IMXRT_LPSPI4		(*(IMXRT_REGISTER32_t *)0x403A0000)

  6792. #define IMXRT_LPSPI4_S          (*(IMXRT_LPSPI_t *)0x403A0000)

  6793. #define LPSPI4_VERID			(IMXRT_LPSPI4.offset000)

  6794. #define LPSPI4_PARAM			(IMXRT_LPSPI4.offset004)

  6795. #define LPSPI4_CR			(IMXRT_LPSPI4.offset010)

  6796. #define LPSPI4_SR			(IMXRT_LPSPI4.offset014)

  6797. #define LPSPI4_IER			(IMXRT_LPSPI4.offset018)

  6798. #define LPSPI4_DER			(IMXRT_LPSPI4.offset01C)

  6799. #define LPSPI4_CFGR0			(IMXRT_LPSPI4.offset020)

  6800. #define LPSPI4_CFGR1			(IMXRT_LPSPI4.offset024)

  6801. #define LPSPI4_DMR0			(IMXRT_LPSPI4.offset030)

  6802. #define LPSPI4_DMR1			(IMXRT_LPSPI4.offset034)

  6803. #define LPSPI4_CCR			(IMXRT_LPSPI4.offset040)

  6804. #define LPSPI4_FCR			(IMXRT_LPSPI4.offset058)

  6805. #define LPSPI4_FSR			(IMXRT_LPSPI4.offset05C)

  6806. #define LPSPI4_TCR			(IMXRT_LPSPI4.offset060)

  6807. #define LPSPI4_TDR			(IMXRT_LPSPI4.offset064)

  6808. #define LPSPI4_RSR			(IMXRT_LPSPI4.offset070)

  6809. #define LPSPI4_RDR			(IMXRT_LPSPI4.offset074)

  6810. #define LPSPI_CR_RRF				((uint32_t)(1<<9))

  6811. #define LPSPI_CR_RTF				((uint32_t)(1<<8))

  6812. #define LPSPI_CR_DBGEN				((uint32_t)(1<<3))

  6813. #define LPSPI_CR_DOZEN				((uint32_t)(1<<2))

  6814. #define LPSPI_CR_RST				((uint32_t)(1<<1))

  6815. #define LPSPI_CR_MEN				((uint32_t)(1<<0))

  6816. #define LPSPI_SR_MBF				((uint32_t)(1<<24))

  6817. #define LPSPI_SR_DMF				((uint32_t)(1<<13))

  6818. #define LPSPI_SR_REF				((uint32_t)(1<<12))

  6819. #define LPSPI_SR_TEF				((uint32_t)(1<<11))

  6820. #define LPSPI_SR_TCF				((uint32_t)(1<<10))

  6821. #define LPSPI_SR_FCF				((uint32_t)(1<<9))

  6822. #define LPSPI_SR_WCF				((uint32_t)(1<<8))

  6823. #define LPSPI_SR_RDF				((uint32_t)(1<<1))

  6824. #define LPSPI_SR_TDF				((uint32_t)(1<<0))

  6825. #define LPSPI_IER_DMIE				((uint32_t)(1<<13))

  6826. #define LPSPI_IER_REIE				((uint32_t)(1<<12))

  6827. #define LPSPI_IER_TEIE				((uint32_t)(1<<11))

  6828. #define LPSPI_IER_TCIE				((uint32_t)(1<<10))

  6829. #define LPSPI_IER_FCIE				((uint32_t)(1<<9))

  6830. #define LPSPI_IER_WCIE				((uint32_t)(1<<8))

  6831. #define LPSPI_IER_RDIE				((uint32_t)(1<<1))

  6832. #define LPSPI_IER_TDIE				((uint32_t)(1<<0))

  6833. #define LPSPI_DER_RDDE				((uint32_t)(1<<1))

  6834. #define LPSPI_DER_TDDE				((uint32_t)(1<<0))

  6835. #define LPSPI_CFGR0_RDMO			((uint32_t)(1<<9))

  6836. #define LPSPI_CFGR0_CIRFIFO			((uint32_t)(1<<8))

  6837. #define LPSPI_CFGR0_HRSEL			((uint32_t)(1<<2))

  6838. #define LPSPI_CFGR0_HRPOL			((uint32_t)(1<<1))

  6839. #define LPSPI_CFGR0_HREN			((uint32_t)(1<<0))

  6840. #define LPSPI_CFGR1_PCSCFG			((uint32_t)(1<<27))

  6841. #define LPSPI_CFGR1_OUTCFG			((uint32_t)(1<<26))

  6842. #define LPSPI_CFGR1_PINCFG(n)			((uint32_t)(((n) & 0x03) << 24))

  6843. #define LPSPI_CFGR1_MATCFG(n)			((uint32_t)(((n) & 0x07) << 16))

  6844. #define LPSPI_CFGR1_PCSPOL(n)			((uint32_t)(((n) & 0x0F) << 8))

  6845. #define LPSPI_CFGR1_NOSTALL			((uint32_t)(1<<3))

  6846. #define LPSPI_CFGR1_AUTOPCS			((uint32_t)(1<<2))

  6847. #define LPSPI_CFGR1_SAMPLE			((uint32_t)(1<<1))

  6848. #define LPSPI_CFGR1_MASTER			((uint32_t)(1<<0))

  6849. #define LPSPI_CCR_SCKPCS(n)			((uint32_t)(((n) & 0xFF) << 24))

  6850. #define LPSPI_CCR_PCSSCK(n)			((uint32_t)(((n) & 0xFF) << 16))

  6851. #define LPSPI_CCR_DBT(n)			((uint32_t)(((n) & 0xFF) << 8))

  6852. #define LPSPI_CCR_SCKDIV(n)			((uint32_t)(((n) & 0xFF) << 0))

  6853. #define LPSPI_FCR_RXWATER(n)			((uint32_t)(((n) & 0x0F) << 16))

  6854. #define LPSPI_FCR_TXWATER(n)			((uint32_t)(((n) & 0x0F) << 0))

  6855. #define LPSPI_FSR_RXCOUNT(n)			((uint32_t)(((n) & 0x1F) << 16))

  6856. #define LPSPI_FSR_TXCOUNT(n)			((uint32_t)(((n) & 0x1F) << 0))

  6857. #define LPSPI_TCR_CPOL				((uint32_t)(1<<31))

  6858. #define LPSPI_TCR_CPHA				((uint32_t)(1<<30))

  6859. #define LPSPI_TCR_PRESCALE(n)			((uint32_t)(((n) & 0x07) << 27))

  6860. #define LPSPI_TCR_PCS(n)			((uint32_t)(((n) & 0x03) << 24))

  6861. #define LPSPI_TCR_LSBF				((uint32_t)(1<<23))

  6862. #define LPSPI_TCR_BYSW				((uint32_t)(1<<22))

  6863. #define LPSPI_TCR_CONT				((uint32_t)(1<<21))

  6864. #define LPSPI_TCR_CONTC				((uint32_t)(1<<20))

  6865. #define LPSPI_TCR_RXMSK				((uint32_t)(1<<19))

  6866. #define LPSPI_TCR_TXMSK				((uint32_t)(1<<18))

  6867. #define LPSPI_TCR_WIDTH(n)			((uint32_t)(((n) & 0x03) << 16))

  6868. #define LPSPI_TCR_FRAMESZ(n)			((uint32_t)(((n) & 0xFFF) << 0))

  6869. #define LPSPI_RSR_RXEMPTY			((uint32_t)(1<<1))

  6870. #define LPSPI_RSR_SOF				((uint32_t)(1<<0))

  6871. 

  6872. // 49.4.1.1: page 2854

  6873. typedef struct {

  6874. 	const uint32_t VERID;

  6875. 	const uint32_t PARAM;

  6876. 	volatile uint32_t GLOBAL;

  6877. 	volatile uint32_t PINCFG;

  6878. 	volatile uint32_t BAUD;

  6879. 	volatile uint32_t STAT;

  6880. 	volatile uint32_t CTRL;

  6881. 	volatile uint32_t DATA;

  6882. 	volatile uint32_t MATCH;

  6883. 	volatile uint32_t MODIR;

  6884. 	volatile uint32_t FIFO;

  6885. 	volatile uint32_t WATER;

  6886. } IMXRT_LPUART_t;

  6887. #define IMXRT_LPUART1		(*(IMXRT_LPUART_t *)0x40184000)

  6888. #define LPUART1_VERID			(IMXRT_LPUART1.VERID)

  6889. #define LPUART1_PARAM			(IMXRT_LPUART1.PARAM)

  6890. #define LPUART1_GLOBAL			(IMXRT_LPUART1.GLOBAL)

  6891. #define LPUART1_PINCFG			(IMXRT_LPUART1.PINCFG)

  6892. #define LPUART1_BAUD			(IMXRT_LPUART1.BAUD)

  6893. #define LPUART1_STAT			(IMXRT_LPUART1.STAT)

  6894. #define LPUART1_CTRL			(IMXRT_LPUART1.CTRL)

  6895. #define LPUART1_DATA			(IMXRT_LPUART1.DATA)

  6896. #define LPUART1_MATCH			(IMXRT_LPUART1.MATCH)

  6897. #define LPUART1_MODIR			(IMXRT_LPUART1.MODIR)

  6898. #define LPUART1_FIFO			(IMXRT_LPUART1.FIFO)

  6899. #define LPUART1_WATER			(IMXRT_LPUART1.WATER)

  6900. #define IMXRT_LPUART2		(*(IMXRT_LPUART_t *)0x40188000)

  6901. #define LPUART2_VERID			(IMXRT_LPUART2.VERID)

  6902. #define LPUART2_PARAM			(IMXRT_LPUART2.PARAM)

  6903. #define LPUART2_GLOBAL			(IMXRT_LPUART2.GLOBAL)

  6904. #define LPUART2_PINCFG			(IMXRT_LPUART2.PINCFG)

  6905. #define LPUART2_BAUD			(IMXRT_LPUART2.BAUD)

  6906. #define LPUART2_STAT			(IMXRT_LPUART2.STAT)

  6907. #define LPUART2_CTRL			(IMXRT_LPUART2.CTRL)

  6908. #define LPUART2_DATA			(IMXRT_LPUART2.DATA)

  6909. #define LPUART2_MATCH			(IMXRT_LPUART2.MATCH)

  6910. #define LPUART2_MODIR			(IMXRT_LPUART2.MODIR)

  6911. #define LPUART2_FIFO			(IMXRT_LPUART2.FIFO)

  6912. #define LPUART2_WATER			(IMXRT_LPUART2.WATER)

  6913. #define IMXRT_LPUART3		(*(IMXRT_LPUART_t *)0x4018C000)

  6914. #define LPUART3_VERID			(IMXRT_LPUART3.VERID)

  6915. #define LPUART3_PARAM			(IMXRT_LPUART3.PARAM)

  6916. #define LPUART3_GLOBAL			(IMXRT_LPUART3.GLOBAL)

  6917. #define LPUART3_PINCFG			(IMXRT_LPUART3.PINCFG)

  6918. #define LPUART3_BAUD			(IMXRT_LPUART3.BAUD)

  6919. #define LPUART3_STAT			(IMXRT_LPUART3.STAT)

  6920. #define LPUART3_CTRL			(IMXRT_LPUART3.CTRL)

  6921. #define LPUART3_DATA			(IMXRT_LPUART3.DATA)

  6922. #define LPUART3_MATCH			(IMXRT_LPUART3.MATCH)

  6923. #define LPUART3_MODIR			(IMXRT_LPUART3.MODIR)

  6924. #define LPUART3_FIFO			(IMXRT_LPUART3.FIFO)

  6925. #define LPUART3_WATER			(IMXRT_LPUART3.WATER)

  6926. #define IMXRT_LPUART4		(*(IMXRT_LPUART_t *)0x40190000)

  6927. #define LPUART4_VERID			(IMXRT_LPUART4.VERID)

  6928. #define LPUART4_PARAM			(IMXRT_LPUART4.PARAM)

  6929. #define LPUART4_GLOBAL			(IMXRT_LPUART4.GLOBAL)

  6930. #define LPUART4_PINCFG			(IMXRT_LPUART4.PINCFG)

  6931. #define LPUART4_BAUD			(IMXRT_LPUART4.BAUD)

  6932. #define LPUART4_STAT			(IMXRT_LPUART4.STAT)

  6933. #define LPUART4_CTRL			(IMXRT_LPUART4.CTRL)

  6934. #define LPUART4_DATA			(IMXRT_LPUART4.DATA)

  6935. #define LPUART4_MATCH			(IMXRT_LPUART4.MATCH)

  6936. #define LPUART4_MODIR			(IMXRT_LPUART4.MODIR)

  6937. #define LPUART4_FIFO			(IMXRT_LPUART4.FIFO)

  6938. #define LPUART4_WATER			(IMXRT_LPUART4.WATER)

  6939. #define IMXRT_LPUART5		(*(IMXRT_LPUART_t *)0x40194000)

  6940. #define LPUART5_VERID			(IMXRT_LPUART5.VERID)

  6941. #define LPUART5_PARAM			(IMXRT_LPUART5.PARAM)

  6942. #define LPUART5_GLOBAL			(IMXRT_LPUART5.GLOBAL)

  6943. #define LPUART5_PINCFG			(IMXRT_LPUART5.PINCFG)

  6944. #define LPUART5_BAUD			(IMXRT_LPUART5.BAUD)

  6945. #define LPUART5_STAT			(IMXRT_LPUART5.STAT)

  6946. #define LPUART5_CTRL			(IMXRT_LPUART5.CTRL)

  6947. #define LPUART5_DATA			(IMXRT_LPUART5.DATA)

  6948. #define LPUART5_MATCH			(IMXRT_LPUART5.MATCH)

  6949. #define LPUART5_MODIR			(IMXRT_LPUART5.MODIR)

  6950. #define LPUART5_FIFO			(IMXRT_LPUART5.FIFO)

  6951. #define LPUART5_WATER			(IMXRT_LPUART5.WATER)

  6952. #define IMXRT_LPUART6		(*(IMXRT_LPUART_t *)0x40198000)

  6953. #define LPUART6_VERID			(IMXRT_LPUART6.VERID)

  6954. #define LPUART6_PARAM			(IMXRT_LPUART6.PARAM)

  6955. #define LPUART6_GLOBAL			(IMXRT_LPUART6.GLOBAL)

  6956. #define LPUART6_PINCFG			(IMXRT_LPUART6.PINCFG)

  6957. #define LPUART6_BAUD			(IMXRT_LPUART6.BAUD)

  6958. #define LPUART6_STAT			(IMXRT_LPUART6.STAT)

  6959. #define LPUART6_CTRL			(IMXRT_LPUART6.CTRL)

  6960. #define LPUART6_DATA			(IMXRT_LPUART6.DATA)

  6961. #define LPUART6_MATCH			(IMXRT_LPUART6.MATCH)

  6962. #define LPUART6_MODIR			(IMXRT_LPUART6.MODIR)

  6963. #define LPUART6_FIFO			(IMXRT_LPUART6.FIFO)

  6964. #define LPUART6_WATER			(IMXRT_LPUART6.WATER)

  6965. #define IMXRT_LPUART7		(*(IMXRT_LPUART_t *)0x4019C000)

  6966. #define LPUART7_VERID			(IMXRT_LPUART7.VERID)

  6967. #define LPUART7_PARAM			(IMXRT_LPUART7.PARAM)

  6968. #define LPUART7_GLOBAL			(IMXRT_LPUART7.GLOBAL)

  6969. #define LPUART7_PINCFG			(IMXRT_LPUART7.PINCFG)

  6970. #define LPUART7_BAUD			(IMXRT_LPUART7.BAUD)

  6971. #define LPUART7_STAT			(IMXRT_LPUART7.STAT)

  6972. #define LPUART7_CTRL			(IMXRT_LPUART7.CTRL)

  6973. #define LPUART7_DATA			(IMXRT_LPUART7.DATA)

  6974. #define LPUART7_MATCH			(IMXRT_LPUART7.MATCH)

  6975. #define LPUART7_MODIR			(IMXRT_LPUART7.MODIR)

  6976. #define LPUART7_FIFO			(IMXRT_LPUART7.FIFO)

  6977. #define LPUART7_WATER			(IMXRT_LPUART7.WATER)

  6978. #define IMXRT_LPUART8		(*(IMXRT_LPUART_t *)0x401A0000)

  6979. #define LPUART8_VERID			(IMXRT_LPUART8.VERID)

  6980. #define LPUART8_PARAM			(IMXRT_LPUART8.PARAM)

  6981. #define LPUART8_GLOBAL			(IMXRT_LPUART8.GLOBAL)

  6982. #define LPUART8_PINCFG			(IMXRT_LPUART8.PINCFG)

  6983. #define LPUART8_BAUD			(IMXRT_LPUART8.BAUD)

  6984. #define LPUART8_STAT			(IMXRT_LPUART8.STAT)

  6985. #define LPUART8_CTRL			(IMXRT_LPUART8.CTRL)

  6986. #define LPUART8_DATA			(IMXRT_LPUART8.DATA)

  6987. #define LPUART8_MATCH			(IMXRT_LPUART8.MATCH)

  6988. #define LPUART8_MODIR			(IMXRT_LPUART8.MODIR)

  6989. #define LPUART8_FIFO			(IMXRT_LPUART8.FIFO)

  6990. #define LPUART8_WATER			(IMXRT_LPUART8.WATER)

  6991. #define LPUART_VERID_MAJOR(n)			((uint32_t)(((n) & 0xFF) << 24))

  6992. #define LPUART_VERID_MINOR(n)			((uint32_t)(((n) & 0xFF) << 16))

  6993. #define LPUART_VERID_FEATURE(n)			((uint32_t)(((n) & 0xFFFF) << 0))

  6994. #define LPUART_PARAM_RXFIFO(n)			((uint32_t)(((n) & 0xFF) << 8))

  6995. #define LPUART_PARAM_TXFIFO(n)			((uint32_t)(((n) & 0xFF) << 0))

  6996. #define LPUART_GLOBAL_RST			((uint32_t)(1<<1))

  6997. #define LPUART_PINCFG_TRGSEL(n)			((uint32_t)(((n) & 0x03) << 0))

  6998. #define LPUART_BAUD_MAEN1			((uint32_t)(1<<31))

  6999. #define LPUART_BAUD_MAEN2			((uint32_t)(1<<30))

  7000. #define LPUART_BAUD_M10				((uint32_t)(1<<29))

  7001. #define LPUART_BAUD_OSR(n)			((uint32_t)(((n) & 0x1F) << 24))

  7002. #define LPUART_BAUD_TDMAE			((uint32_t)(1<<23))

  7003. #define LPUART_BAUD_RDMAE			((uint32_t)(1<<21))

  7004. #define LPUART_BAUD_MATCFG(n)			((uint32_t)(((n) & 0x03) << 18))

  7005. #define LPUART_BAUD_BOTHEDGE			((uint32_t)(1<<17))

  7006. #define LPUART_BAUD_RESYNCDIS			((uint32_t)(1<<16))

  7007. #define LPUART_BAUD_LBKDIE			((uint32_t)(1<<15))

  7008. #define LPUART_BAUD_RXEDGIE			((uint32_t)(1<<14))

  7009. #define LPUART_BAUD_SBNS			((uint32_t)(1<<13))

  7010. #define LPUART_BAUD_SBR(n)			((uint32_t)(((n) & 0x01FFF) << 0))

  7011. #define LPUART_STAT_LBKDIF			((uint32_t)(1<<31))

  7012. #define LPUART_STAT_RXEDGIF			((uint32_t)(1<<30))

  7013. #define LPUART_STAT_MSBF			((uint32_t)(1<<29))

  7014. #define LPUART_STAT_RXINV			((uint32_t)(1<<28))

  7015. #define LPUART_STAT_RWUID			((uint32_t)(1<<27))

  7016. #define LPUART_STAT_BRK13			((uint32_t)(1<<26))

  7017. #define LPUART_STAT_LBKDE			((uint32_t)(1<<25))

  7018. #define LPUART_STAT_RAF				((uint32_t)(1<<24))

  7019. #define LPUART_STAT_TDRE			((uint32_t)(1<<23))

  7020. #define LPUART_STAT_TC				((uint32_t)(1<<22))

  7021. #define LPUART_STAT_RDRF			((uint32_t)(1<<21))

  7022. #define LPUART_STAT_IDLE			((uint32_t)(1<<20))

  7023. #define LPUART_STAT_OR				((uint32_t)(1<<19))

  7024. #define LPUART_STAT_NF				((uint32_t)(1<<18))

  7025. #define LPUART_STAT_FE				((uint32_t)(1<<17))

  7026. #define LPUART_STAT_PF				((uint32_t)(1<<16))

  7027. #define LPUART_STAT_MA1F			((uint32_t)(1<<15))

  7028. #define LPUART_STAT_MA2F			((uint32_t)(1<<14))

  7029. #define LPUART_CTRL_R8T9			((uint32_t)(1<<31))

  7030. #define LPUART_CTRL_R9T8			((uint32_t)(1<<30))

  7031. #define LPUART_CTRL_TXDIR			((uint32_t)(1<<29))

  7032. #define LPUART_CTRL_TXINV			((uint32_t)(1<<28))

  7033. #define LPUART_CTRL_ORIE			((uint32_t)(1<<27))

  7034. #define LPUART_CTRL_NEIE			((uint32_t)(1<<26))

  7035. #define LPUART_CTRL_FEIE			((uint32_t)(1<<25))

  7036. #define LPUART_CTRL_PEIE			((uint32_t)(1<<24))

  7037. #define LPUART_CTRL_TIE				((uint32_t)(1<<23))

  7038. #define LPUART_CTRL_TCIE			((uint32_t)(1<<22))

  7039. #define LPUART_CTRL_RIE				((uint32_t)(1<<21))

  7040. #define LPUART_CTRL_ILIE			((uint32_t)(1<<20))

  7041. #define LPUART_CTRL_TE				((uint32_t)(1<<19))

  7042. #define LPUART_CTRL_RE				((uint32_t)(1<<18))

  7043. #define LPUART_CTRL_RWU				((uint32_t)(1<<17))

  7044. #define LPUART_CTRL_SBK				((uint32_t)(1<<16))

  7045. #define LPUART_CTRL_MA1IE			((uint32_t)(1<<15))

  7046. #define LPUART_CTRL_MA2IE			((uint32_t)(1<<14))

  7047. #define LPUART_CTRL_M7				((uint32_t)(1<<11))

  7048. #define LPUART_CTRL_IDLECFG(n)			((uint32_t)(((n) & 0x07) << 8))

  7049. #define LPUART_CTRL_LOOPS			((uint32_t)(1<<7))

  7050. #define LPUART_CTRL_DOZEEN			((uint32_t)(1<<6))

  7051. #define LPUART_CTRL_RSRC			((uint32_t)(1<<5))

  7052. #define LPUART_CTRL_M				((uint32_t)(1<<4))

  7053. #define LPUART_CTRL_WAKE			((uint32_t)(1<<3))

  7054. #define LPUART_CTRL_ILT				((uint32_t)(1<<2))

  7055. #define LPUART_CTRL_PE				((uint32_t)(1<<1))

  7056. #define LPUART_CTRL_PT				((uint32_t)(1<<0))

  7057. #define LPUART_DATA_NOISY			((uint32_t)(1<<15))

  7058. #define LPUART_DATA_PARITYE			((uint32_t)(1<<14))

  7059. #define LPUART_DATA_FRETSC			((uint32_t)(1<<13))

  7060. #define LPUART_DATA_RXEMPT			((uint32_t)(1<<12))

  7061. #define LPUART_DATA_IDLINE			((uint32_t)(1<<11))

  7062. #define LPUART_MATCH_MA2(n)			((uint32_t)(((n) & 0x3FF) << 16))

  7063. #define LPUART_MATCH_MA1(n)			((uint32_t)(((n) & 0x3FF) << 0))

  7064. #define LPUART_MODIR_IREN			((uint32_t)(1<<18))

  7065. #define LPUART_MODIR_TNP(n)			((uint32_t)(((n) & 0x03) << 16))

  7066. #define LPUART_MODIR_RTSWATER(n)		((uint32_t)(((n) & 0x03) << 8))

  7067. #define LPUART_MODIR_TXCTSSRC			((uint32_t)(1<<5))

  7068. #define LPUART_MODIR_TXCTSC			((uint32_t)(1<<4))

  7069. #define LPUART_MODIR_RXRTSE			((uint32_t)(1<<3))

  7070. #define LPUART_MODIR_TXRTSPOL			((uint32_t)(1<<2))

  7071. #define LPUART_MODIR_TXRTSE			((uint32_t)(1<<1))

  7072. #define LPUART_MODIR_TXCTSE			((uint32_t)(1<<0))

  7073. #define LPUART_FIFO_TXEMPT			((uint32_t)(1<<23))

  7074. #define LPUART_FIFO_RXEMPT			((uint32_t)(1<<22))

  7075. #define LPUART_FIFO_TXOF			((uint32_t)(1<<17))

  7076. #define LPUART_FIFO_RXUF			((uint32_t)(1<<16))

  7077. #define LPUART_FIFO_TXFLUSH			((uint32_t)(1<<15))

  7078. #define LPUART_FIFO_RXFLUSH			((uint32_t)(1<<14))

  7079. #define LPUART_FIFO_RXIDEN(n)			((uint32_t)(((n) & 0x07) << 10))

  7080. #define LPUART_FIFO_TXOFE			((uint32_t)(1<<9))

  7081. #define LPUART_FIFO_RXUFE			((uint32_t)(1<<8))

  7082. #define LPUART_FIFO_TXFE			((uint32_t)(1<<7))

  7083. #define LPUART_FIFO_TXFIFOSIZE(n)		((uint32_t)(((n) & 0x07) << 4))

  7084. #define LPUART_FIFO_RXFE			((uint32_t)(1<<3))

  7085. #define LPUART_FIFO_RXFIFOSIZE(n)		((uint32_t)(((n) & 0x07) << 0))

  7086. #define LPUART_WATER_RXCOUNT(n)			((uint32_t)(((n) & 0x07) << 24))

  7087. #define LPUART_WATER_RXWATER(n)			((uint32_t)(((n) & 0x03) << 16))

  7088. #define LPUART_WATER_TXCOUNT(n)			((uint32_t)(((n) & 0x07) << 8))

  7089. #define LPUART_WATER_TXWATER(n)			((uint32_t)(((n) & 0x03) << 0))

  7090. 

  7091. 

  7092. // 23.6.1.1: page 1331

  7093. #define IMXRT_OCOTP		(*(IMXRT_REGISTER32_t *)0x401F4000)

  7094. #define HW_OCOTP_CTRL			(IMXRT_OCOTP.offset000)

  7095. #define HW_OCOTP_CTRL_SET		(IMXRT_OCOTP.offset004)

  7096. #define HW_OCOTP_CTRL_CLR		(IMXRT_OCOTP.offset008)

  7097. #define HW_OCOTP_CTRL_TOG		(IMXRT_OCOTP.offset00C)

  7098. #define HW_OCOTP_TIMING			(IMXRT_OCOTP.offset010)

  7099. #define HW_OCOTP_DATA			(IMXRT_OCOTP.offset020)

  7100. #define HW_OCOTP_READ_CTRL		(IMXRT_OCOTP.offset030)

  7101. #define HW_OCOTP_READ_FUSE_DATA		(IMXRT_OCOTP.offset040)

  7102. #define HW_OCOTP_SW_STICKY		(IMXRT_OCOTP.offset050)

  7103. #define HW_OCOTP_SCS			(IMXRT_OCOTP.offset060)

  7104. #define HW_OCOTP_SCS_SET		(IMXRT_OCOTP.offset064)

  7105. #define HW_OCOTP_SCS_CLR		(IMXRT_OCOTP.offset068)

  7106. #define HW_OCOTP_SCS_TOG		(IMXRT_OCOTP.offset06C)

  7107. #define HW_OCOTP_VERSION		(IMXRT_OCOTP.offset090)

  7108. #define HW_OCOTP_TIMING2		(IMXRT_OCOTP.offset100)

  7109. #define HW_OCOTP_CTRL_WR_UNLOCK(n)		((uint32_t)(((n) & 0xFFFF) << 16))

  7110. #define HW_OCOTP_CTRL_RELOAD_SHADOWS		((uint32_t)(1<<10))

  7111. #define HW_OCOTP_CTRL_ERROR			((uint32_t)(1<<9))

  7112. #define HW_OCOTP_CTRL_BUSY			((uint32_t)(1<<8))

  7113. #define HW_OCOTP_CTRL_ADDR(n)			((uint32_t)(((n) & 0x3F) << 0))

  7114. #define HW_OCOTP_TIMING_WAIT(n)			((uint32_t)(((n) & 0x3F) << 22))

  7115. #define HW_OCOTP_TIMING_STROBE_READ(n)		((uint32_t)(((n) & 0x3F) << 16))

  7116. #define HW_OCOTP_TIMING_RELAX(n)		((uint32_t)(((n) & 0x0F) << 12))

  7117. #define HW_OCOTP_TIMING_STROBE_PROG(n)		((uint32_t)(((n) & 0xFFF) << 0))

  7118. #define HW_OCOTP_READ_CTRL_READ_FUSE		((uint32_t)(1<<0))

  7119. #define HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE	((uint32_t)(1<<4))

  7120. #define HW_OCOTP_SW_STICKY_BLOCK_ROM_PART	((uint32_t)(1<<3))

  7121. #define HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK	((uint32_t)(1<<2))

  7122. #define HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK	((uint32_t)(1<<1))

  7123. #define HW_OCOTP_SW_STICKY_BLOCK_DTCP_KEY	((uint32_t)(1<<0))

  7124. #define HW_OCOTP_SCS_LOCK			((uint32_t)(1<<31))

  7125. #define HW_OCOTP_SCS_HAB_JDE			((uint32_t)(1<<0))

  7126. #define HW_OCOTP_TIMING2_RELAX1(n)		((uint32_t)(((n) & 0x7F) << 24))

  7127. #define HW_OCOTP_TIMING2_RELAX_READ(n)		((uint32_t)(((n) & 0x3F) << 16))

  7128. #define HW_OCOTP_TIMING2_RELAX_PROG(n)		((uint32_t)(((n) & 0xFFF) << 0))

  7129. #define IMXRT_OCOTP_VALUE	(*(IMXRT_REGISTER32_t *)0x401F4400)

  7130. #define HW_OCOTP_LOCK			(IMXRT_OCOTP_VALUE.offset000)

  7131. #define HW_OCOTP_CFG0			(IMXRT_OCOTP_VALUE.offset010)

  7132. #define HW_OCOTP_CFG1			(IMXRT_OCOTP_VALUE.offset020)

  7133. #define HW_OCOTP_CFG2			(IMXRT_OCOTP_VALUE.offset030)

  7134. #define HW_OCOTP_CFG3			(IMXRT_OCOTP_VALUE.offset040)

  7135. #define HW_OCOTP_CFG4			(IMXRT_OCOTP_VALUE.offset050)

  7136. #define HW_OCOTP_CFG5			(IMXRT_OCOTP_VALUE.offset060)

  7137. #define HW_OCOTP_CFG6			(IMXRT_OCOTP_VALUE.offset070)

  7138. #define HW_OCOTP_MEM0			(IMXRT_OCOTP_VALUE.offset080)

  7139. #define HW_OCOTP_MEM1			(IMXRT_OCOTP_VALUE.offset090)

  7140. #define HW_OCOTP_MEM2			(IMXRT_OCOTP_VALUE.offset0A0)

  7141. #define HW_OCOTP_MEM3			(IMXRT_OCOTP_VALUE.offset0B0)

  7142. #define HW_OCOTP_MEM4			(IMXRT_OCOTP_VALUE.offset0C0)

  7143. #define HW_OCOTP_ANA0			(IMXRT_OCOTP_VALUE.offset0D0)

  7144. #define HW_OCOTP_ANA1			(IMXRT_OCOTP_VALUE.offset0E0)

  7145. #define HW_OCOTP_ANA2			(IMXRT_OCOTP_VALUE.offset0F0)

  7146. #define HW_OCOTP_OTPMK0			(IMXRT_OCOTP_VALUE.offset100)

  7147. #define HW_OCOTP_OTPMK1			(IMXRT_OCOTP_VALUE.offset110)

  7148. #define HW_OCOTP_OTPMK2			(IMXRT_OCOTP_VALUE.offset120)

  7149. #define HW_OCOTP_OTPMK3			(IMXRT_OCOTP_VALUE.offset130)

  7150. #define HW_OCOTP_OTPMK4			(IMXRT_OCOTP_VALUE.offset140)

  7151. #define HW_OCOTP_OTPMK5			(IMXRT_OCOTP_VALUE.offset150)

  7152. #define HW_OCOTP_OTPMK6			(IMXRT_OCOTP_VALUE.offset160)

  7153. #define HW_OCOTP_OTPMK7			(IMXRT_OCOTP_VALUE.offset170)

  7154. #define HW_OCOTP_SRK0			(IMXRT_OCOTP_VALUE.offset180)

  7155. #define HW_OCOTP_SRK1			(IMXRT_OCOTP_VALUE.offset190)

  7156. #define HW_OCOTP_SRK2			(IMXRT_OCOTP_VALUE.offset1A0)

  7157. #define HW_OCOTP_SRK3			(IMXRT_OCOTP_VALUE.offset1B0)

  7158. #define HW_OCOTP_SRK4			(IMXRT_OCOTP_VALUE.offset1C0)

  7159. #define HW_OCOTP_SRK5			(IMXRT_OCOTP_VALUE.offset1D0)

  7160. #define HW_OCOTP_SRK6			(IMXRT_OCOTP_VALUE.offset1E0)

  7161. #define HW_OCOTP_SRK7			(IMXRT_OCOTP_VALUE.offset1F0)

  7162. #define HW_OCOTP_SJC_RESP0		(IMXRT_OCOTP_VALUE.offset200)

  7163. #define HW_OCOTP_SJC_RESP1		(IMXRT_OCOTP_VALUE.offset210)

  7164. #define HW_OCOTP_MAC0			(IMXRT_OCOTP_VALUE.offset220)

  7165. #define HW_OCOTP_MAC1			(IMXRT_OCOTP_VALUE.offset230)

  7166. #define HW_OCOTP_MAC2			(IMXRT_OCOTP_VALUE.offset240)

  7167. #define HW_OCOTP_GP3			(IMXRT_OCOTP_VALUE.offset250) /* IMXRT1052 */

  7168. #define HW_OCOTP_OTPMK_CRC32		(IMXRT_OCOTP_VALUE.offset250) /* IMXRT1062 */

  7169. #define HW_OCOTP_GP1			(IMXRT_OCOTP_VALUE.offset260)

  7170. #define HW_OCOTP_GP2			(IMXRT_OCOTP_VALUE.offset270)

  7171. #define HW_OCOTP_SW_GP1			(IMXRT_OCOTP_VALUE.offset280)

  7172. #define HW_OCOTP_SW_GP20		(IMXRT_OCOTP_VALUE.offset290)

  7173. #define HW_OCOTP_SW_GP21		(IMXRT_OCOTP_VALUE.offset2A0)

  7174. #define HW_OCOTP_SW_GP22		(IMXRT_OCOTP_VALUE.offset2B0)

  7175. #define HW_OCOTP_SW_GP23		(IMXRT_OCOTP_VALUE.offset2C0)

  7176. #define HW_OCOTP_MISC_CONF0		(IMXRT_OCOTP_VALUE.offset2D0)

  7177. #define HW_OCOTP_MISC_CONF1		(IMXRT_OCOTP_VALUE.offset2E0)

  7178. #define HW_OCOTP_SRK_REVOKE		(IMXRT_OCOTP_VALUE.offset2F0)

  7179. #if defined(__IMXRT1062__)

  7180. #define IMXRT_OCOTP_VALUE2	(*(IMXRT_REGISTER32_t *)0x401F4800)

  7181. #define HW_OCOTP_ROM_PATCH0		(IMXRT_OCOTP_VALUE2.offset000)

  7182. #define HW_OCOTP_ROM_PATCH1		(IMXRT_OCOTP_VALUE2.offset010)

  7183. #define HW_OCOTP_ROM_PATCH2		(IMXRT_OCOTP_VALUE2.offset020)

  7184. #define HW_OCOTP_ROM_PATCH3		(IMXRT_OCOTP_VALUE2.offset030)

  7185. #define HW_OCOTP_ROM_PATCH4		(IMXRT_OCOTP_VALUE2.offset040)

  7186. #define HW_OCOTP_ROM_PATCH5		(IMXRT_OCOTP_VALUE2.offset050)

  7187. #define HW_OCOTP_ROM_PATCH6		(IMXRT_OCOTP_VALUE2.offset060)

  7188. #define HW_OCOTP_ROM_PATCH7		(IMXRT_OCOTP_VALUE2.offset070)

  7189. #define HW_OCOTP_GP30			(IMXRT_OCOTP_VALUE2.offset080)

  7190. #define HW_OCOTP_GP31			(IMXRT_OCOTP_VALUE2.offset090)

  7191. #define HW_OCOTP_GP32			(IMXRT_OCOTP_VALUE2.offset0A0)

  7192. #define HW_OCOTP_GP33			(IMXRT_OCOTP_VALUE2.offset0B0)

  7193. #define HW_OCOTP_GP40			(IMXRT_OCOTP_VALUE2.offset0C0)

  7194. #define HW_OCOTP_GP41			(IMXRT_OCOTP_VALUE2.offset0D0)

  7195. #define HW_OCOTP_GP42			(IMXRT_OCOTP_VALUE2.offset0E0)

  7196. #define HW_OCOTP_GP43			(IMXRT_OCOTP_VALUE2.offset0F0)

  7197. #endif

  7198. 

  7199. // 53.9.1: page 2978

  7200. #define IMXRT_PIT		(*(IMXRT_REGISTER32_t *)0x40084000)

  7201. #define PIT_MCR				(IMXRT_PIT.offset000)

  7202. #define PIT_LTMR64H			(IMXRT_PIT.offset0E0)

  7203. #define PIT_LTMR64L			(IMXRT_PIT.offset0E4)

  7204. typedef struct {

  7205. 	volatile uint32_t LDVAL;

  7206. 	volatile uint32_t CVAL;

  7207. 	volatile uint32_t TCTRL;

  7208. 	volatile uint32_t TFLG;

  7209. } IMXRT_PIT_CHANNEL_t;

  7210. #define IMXRT_PIT_CHANNELS		((IMXRT_PIT_CHANNEL_t *)(&(IMXRT_PIT.offset100)))

  7211. #define PIT_LDVAL0			(IMXRT_PIT.offset100)

  7212. #define PIT_CVAL0			(IMXRT_PIT.offset104)

  7213. #define PIT_TCTRL0			(IMXRT_PIT.offset108)

  7214. #define PIT_TFLG0			(IMXRT_PIT.offset10C)

  7215. #define PIT_LDVAL1			(IMXRT_PIT.offset110)

  7216. #define PIT_CVAL1			(IMXRT_PIT.offset114)

  7217. #define PIT_TCTRL1			(IMXRT_PIT.offset118)

  7218. #define PIT_TFLG1			(IMXRT_PIT.offset11C)

  7219. #define PIT_LDVAL2			(IMXRT_PIT.offset120)

  7220. #define PIT_CVAL2			(IMXRT_PIT.offset124)

  7221. #define PIT_TCTRL2			(IMXRT_PIT.offset128)

  7222. #define PIT_TFLG2			(IMXRT_PIT.offset12C)

  7223. #define PIT_LDVAL3			(IMXRT_PIT.offset130)

  7224. #define PIT_CVAL3			(IMXRT_PIT.offset134)

  7225. #define PIT_TCTRL3			(IMXRT_PIT.offset138)

  7226. #define PIT_TFLG3			(IMXRT_PIT.offset13C)

  7227. #define PIT_MCR_MDIS				((uint32_t)(1<<1))

  7228. #define PIT_MCR_FRZ				((uint32_t)(1<<0))

  7229. #define PIT_TCTRL_CHN				((uint32_t)(1<<2))

  7230. #define PIT_TCTRL_TIE				((uint32_t)(1<<1))

  7231. #define PIT_TCTRL_TEN				((uint32_t)(1<<0))

  7232. #define PIT_TFLG_TIF				((uint32_t)(1<<0))

  7233. 

  7234. // 16.6: page 1160

  7235. #define IMXRT_PMU		(*(IMXRT_REGISTER32_t *)0x400D8000)

  7236. #define PMU_REG_1P1			(IMXRT_PMU.offset110)

  7237. #define PMU_REG_1P1_SET			(IMXRT_PMU.offset114)

  7238. #define PMU_REG_1P1_CLR			(IMXRT_PMU.offset118)

  7239. #define PMU_REG_1P1_TOG			(IMXRT_PMU.offset11C)

  7240. #define PMU_REG_3P0			(IMXRT_PMU.offset120)

  7241. #define PMU_REG_3P0_SET			(IMXRT_PMU.offset124)

  7242. #define PMU_REG_3P0_CLR			(IMXRT_PMU.offset128)

  7243. #define PMU_REG_3P0_TOG			(IMXRT_PMU.offset12C)

  7244. #define PMU_REG_2P5			(IMXRT_PMU.offset130)

  7245. #define PMU_REG_2P5_SET			(IMXRT_PMU.offset134)

  7246. #define PMU_REG_2P5_CLR			(IMXRT_PMU.offset138)

  7247. #define PMU_REG_2P5_TOG			(IMXRT_PMU.offset13C)

  7248. #define PMU_REG_CORE			(IMXRT_PMU.offset140)

  7249. #define PMU_REG_CORE_SET		(IMXRT_PMU.offset144)

  7250. #define PMU_REG_CORE_CLR		(IMXRT_PMU.offset148)

  7251. #define PMU_REG_CORE_TOG		(IMXRT_PMU.offset14C)

  7252. #define PMU_MISC0			(IMXRT_PMU.offset150)

  7253. #define PMU_MISC0_SET			(IMXRT_PMU.offset154)

  7254. #define PMU_MISC0_CLR			(IMXRT_PMU.offset158)

  7255. #define PMU_MISC0_TOG			(IMXRT_PMU.offset15C)

  7256. #define PMU_MISC1			(IMXRT_PMU.offset160)

  7257. #define PMU_MISC1_SET			(IMXRT_PMU.offset164)

  7258. #define PMU_MISC1_CLR			(IMXRT_PMU.offset168)

  7259. #define PMU_MISC1_TOG			(IMXRT_PMU.offset16C)

  7260. #define PMU_MISC2			(IMXRT_PMU.offset170)

  7261. #define PMU_MISC2_SET			(IMXRT_PMU.offset174)

  7262. #define PMU_MISC2_CLR			(IMXRT_PMU.offset178)

  7263. #define PMU_MISC2_TOG			(IMXRT_PMU.offset17C)

  7264. #define PMU_REG_1P1_SELREF_WEAK_LINREG		((uint32_t)(1<<19))

  7265. #define PMU_REG_1P1_ENABLE_WEAK_LINREG		((uint32_t)(1<<18))

  7266. #define PMU_REG_1P1_OK_VDD1P1			((uint32_t)(1<<17))

  7267. #define PMU_REG_1P1_BO_VDD1P1			((uint32_t)(1<<16))

  7268. #define PMU_REG_1P1_OUTPUT_TRG(n)		((uint32_t)(((n) & 0x0F) << 8))

  7269. #define PMU_REG_1P1_BO_OFFSET(n)		((uint32_t)(((n) & 0x07) << 4))

  7270. #define PMU_REG_1P1_ENABLE_PULLDOWN		((uint32_t)(1<<3))

  7271. #define PMU_REG_1P1_ENABLE_ILIMIT		((uint32_t)(1<<2))

  7272. #define PMU_REG_1P1_ENABLE_BO			((uint32_t)(1<<1))

  7273. #define PMU_REG_1P1_ENABLE_LINREG		((uint32_t)(1<<0))

  7274. #define PMU_REG_3P0_OK_VDD3P0			((uint32_t)(1<<17))

  7275. #define PMU_REG_3P0_BO_VDD3P0			((uint32_t)(1<<16))

  7276. #define PMU_REG_3P0_OUTPUT_TRG(n)		((uint32_t)(((n) & 0x1F) << 8))

  7277. #define PMU_REG_3P0_VBUS_SEL			((uint32_t)(1<<7))

  7278. #define PMU_REG_3P0_BO_OFFSET(n)		((uint32_t)(((n) & 0x07) << 4))

  7279. #define PMU_REG_3P0_ENABLE_ILIMIT		((uint32_t)(1<<2))

  7280. #define PMU_REG_3P0_ENABLE_BO			((uint32_t)(1<<1))

  7281. #define PMU_REG_3P0_ENABLE_LINREG		((uint32_t)(1<<0))

  7282. #define PMU_REG_2P5_ENABLE_WEAK_LINREG		((uint32_t)(1<<18))

  7283. #define PMU_REG_2P5_OK_VDD2P5			((uint32_t)(1<<17))

  7284. #define PMU_REG_2P5_BO_VDD2P5			((uint32_t)(1<<16))

  7285. #define PMU_REG_2P5_OUTPUT_TRG(n)		((uint32_t)(((n) & 0x0F) << 8))

  7286. #define PMU_REG_2P5_BO_OFFSET(n)		((uint32_t)(((n) & 0x07) << 4))

  7287. #define PMU_REG_2P5_ENABLE_PULLDOWN		((uint32_t)(1<<3))

  7288. #define PMU_REG_2P5_ENABLE_ILIMIT		((uint32_t)(1<<2))

  7289. #define PMU_REG_2P5_ENABLE_BO			((uint32_t)(1<<1))

  7290. #define PMU_REG_2P5_ENABLE_LINREG		((uint32_t)(1<<0))

  7291. #define PMU_REG_CORE_FET_ODRIVE			((uint32_t)(1<<29))

  7292. #define PMU_REG_CORE_RAMP_RATE(n)		((uint32_t)(((n) & 0x03) << 27))

  7293. #define PMU_REG_CORE_REG2_ADJ(n)		((uint32_t)(((n) & 0x0F) << 23))

  7294. #define PMU_REG_CORE_REG2_TARG(n)		((uint32_t)(((n) & 0x1F) << 18))

  7295. #define PMU_REG_CORE_REG1_ADJ(n)		((uint32_t)(((n) & 0x0F) << 14))

  7296. #define PMU_REG_CORE_REG1_TARG(n)		((uint32_t)(((n) & 0x1F) << 9))

  7297. #define PMU_REG_CORE_REG0_ADJ(n)		((uint32_t)(((n) & 0x0F) << 5))

  7298. #define PMU_REG_CORE_REG0_TARG(n)		((uint32_t)(((n) & 0x1F) << 0))

  7299. #define PMU_MISC0_VID_PLL_PREDIV		((uint32_t)(1<<31))

  7300. #define PMU_MISC0_XTAL_24M_PWD			((uint32_t)(1<<30))

  7301. #define PMU_MISC0_RTC_XTAL_SOURCE		((uint32_t)(1<<29))

  7302. #define PMU_MISC0_CLKGATE_DELAY(n)		((uint32_t)(((n) & 0x07) << 26))

  7303. #define PMU_MISC0_CLKGATE_CTRL			((uint32_t)(1<<25))

  7304. #define PMU_MISC0_OSC_XTALOK_EN			((uint32_t)(1<<16))

  7305. #define PMU_MISC0_OSC_XTALOK			((uint32_t)(1<<15))

  7306. #define PMU_MISC0_OSC_I(n)			((uint32_t)(((n) & 0x03) << 13))

  7307. #define PMU_MISC0_DISCON_HIGH_SNVS		((uint32_t)(1<<12))

  7308. #define PMU_MISC0_STOP_MODE_CONFIG(n)		((uint32_t)(((n) & 0x03) << 10))

  7309. #define PMU_MISC0_REFTOP_VBGUP			((uint32_t)(1<<7))

  7310. #define PMU_MISC0_REFTOP_VBGADJ(n)		((uint32_t)(((n) & 0x07) << 4))

  7311. #define PMU_MISC0_REFTOP_SELFBIASOFF		((uint32_t)(1<<3))

  7312. #define PMU_MISC0_REFTOP_PWD			((uint32_t)(1<<0))

  7313. #define PMU_MISC1_IRQ_DIG_BO			((uint32_t)(1<<31))

  7314. #define PMU_MISC1_IRQ_ANA_BO			((uint32_t)(1<<30))

  7315. #define PMU_MISC1_IRQ_TEMPHIGH			((uint32_t)(1<<29))

  7316. #define PMU_MISC1_IRQ_TEMPLOW			((uint32_t)(1<<28))

  7317. #define PMU_MISC1_IRQ_TEMPPANIC			((uint32_t)(1<<27))

  7318. #define PMU_MISC1_PFD_528_AUTOGATE_EN		((uint32_t)(1<<17))

  7319. #define PMU_MISC1_PFD_480_AUTOGATE_EN		((uint32_t)(1<<16))

  7320. #define PMU_MISC1_LVDSCLK2_IBEN			((uint32_t)(1<<13))

  7321. #define PMU_MISC1_LVDSCLK1_IBEN			((uint32_t)(1<<12))

  7322. #define PMU_MISC1_LVDSCLK2_OBEN			((uint32_t)(1<<11))

  7323. #define PMU_MISC1_LVDSCLK1_OBEN			((uint32_t)(1<<10))

  7324. #define PMU_MISC1_LVDS2_CLK_SEL(n)		((uint32_t)(((n) & 0x1F) << 5))

  7325. #define PMU_MISC1_LVDS1_CLK_SEL(n)		((uint32_t)(((n) & 0x1F) << 0))

  7326. #define PMU_MISC2_VIDEO_DIV(n)			((uint32_t)(((n) & 0x03) << 30))

  7327. #define PMU_MISC2_REG2_STEP_TIME(n)		((uint32_t)(((n) & 0x03) << 28))

  7328. #define PMU_MISC2_REG1_STEP_TIME(n)		((uint32_t)(((n) & 0x03) << 26))

  7329. #define PMU_MISC2_REG0_STEP_TIME(n)		((uint32_t)(((n) & 0x03) << 24))

  7330. #define PMU_MISC2_AUDIO_DIV_MSB			((uint32_t)(1<<23))

  7331. #define PMU_MISC2_REG2_OK			((uint32_t)(1<<22))

  7332. #define PMU_MISC2_REG2_ENABLE_BO		((uint32_t)(1<<21))

  7333. #define PMU_MISC2_REG2_BO_STATUS		((uint32_t)(1<<19))

  7334. #define PMU_MISC2_REG2_BO_OFFSET(n)		((uint32_t)(((n) & 0x07) << 16))

  7335. #define PMU_MISC2_AUDIO_DIV_LSB			((uint32_t)(1<<15))

  7336. #define PMU_MISC2_REG1_ENABLE_BO		((uint32_t)(1<<13))

  7337. #define PMU_MISC2_REG1_BO_STATUS		((uint32_t)(1<<11))

  7338. #define PMU_MISC2_REG1_BO_OFFSET(n)		((uint32_t)(((n) & 0x07) << 8))

  7339. #define PMU_MISC2_PLL3_DISABLE			((uint32_t)(1<<7))

  7340. #define PMU_MISC2_REG0_ENABLE_BO		((uint32_t)(1<<5))

  7341. #define PMU_MISC2_REG0_BO_STATUS		((uint32_t)(1<<3))

  7342. #define PMU_MISC2_REG0_BO_OFFSET(n)		((uint32_t)(((n) & 0x07) << 0))

  7343. 

  7344. // 36.8: page 1923

  7345. #define IMXRT_PXP		(*(IMXRT_REGISTER32_t *)0x402B4000)

  7346. #define IMXRT_PXP_b		(*(IMXRT_REGISTER32_t *)0x402B4400)

  7347. #define PXP_CTRL			(IMXRT_PXP.offset000)

  7348. #define PXP_CTRL_SET			(IMXRT_PXP.offset004)

  7349. #define PXP_CTRL_CLR			(IMXRT_PXP.offset008)

  7350. #define PXP_CTRL_TOG			(IMXRT_PXP.offset00C)

  7351. #define PXP_STAT			(IMXRT_PXP.offset010)

  7352. #define PXP_STAT_SET			(IMXRT_PXP.offset014)

  7353. #define PXP_STAT_CLR			(IMXRT_PXP.offset018)

  7354. #define PXP_STAT_TOG			(IMXRT_PXP.offset01C)

  7355. #define PXP_OUT_CTRL			(IMXRT_PXP.offset020)

  7356. #define PXP_OUT_CTRL_SET		(IMXRT_PXP.offset024)

  7357. #define PXP_OUT_CTRL_CLR		(IMXRT_PXP.offset028)

  7358. #define PXP_OUT_CTRL_TOG		(IMXRT_PXP.offset02C)

  7359. #define PXP_OUT_BUF			(IMXRT_PXP.offset030)

  7360. #define PXP_OUT_BUF2			(IMXRT_PXP.offset040)

  7361. #define PXP_OUT_PITCH			(IMXRT_PXP.offset050)

  7362. #define PXP_OUT_LRC			(IMXRT_PXP.offset060)

  7363. #define PXP_OUT_PS_ULC			(IMXRT_PXP.offset070)

  7364. #define PXP_OUT_PS_LRC			(IMXRT_PXP.offset080)

  7365. #define PXP_OUT_AS_ULC			(IMXRT_PXP.offset090)

  7366. #define PXP_OUT_AS_LRC			(IMXRT_PXP.offset0A0)

  7367. #define PXP_PS_CTRL			(IMXRT_PXP.offset0B0)

  7368. #define PXP_PS_CTRL_SET			(IMXRT_PXP.offset0B4)

  7369. #define PXP_PS_CTRL_CLR			(IMXRT_PXP.offset0B8)

  7370. #define PXP_PS_CTRL_TOG			(IMXRT_PXP.offset0BC)

  7371. #define PXP_PS_BUF			(IMXRT_PXP.offset0C0)

  7372. #define PXP_PS_UBUF			(IMXRT_PXP.offset0D0)

  7373. #define PXP_PS_VBUF			(IMXRT_PXP.offset0E0)

  7374. #define PXP_PS_PITCH			(IMXRT_PXP.offset0F0)

  7375. #define PXP_PS_BACKGROUND_0		(IMXRT_PXP.offset100)

  7376. #define PXP_PS_SCALE			(IMXRT_PXP.offset110)

  7377. #define PXP_PS_OFFSET			(IMXRT_PXP.offset120)

  7378. #define PXP_PS_CLRKEYLOW_0		(IMXRT_PXP.offset130)

  7379. #define PXP_PS_CLRKEYHIGH_0		(IMXRT_PXP.offset140)

  7380. #define PXP_AS_CTRL			(IMXRT_PXP.offset150)

  7381. #define PXP_AS_BUF			(IMXRT_PXP.offset160)

  7382. #define PXP_AS_PITCH			(IMXRT_PXP.offset170)

  7383. #define PXP_AS_CLRKEYLOW_0		(IMXRT_PXP.offset180)

  7384. #define PXP_AS_CLRKEYHIGH_0		(IMXRT_PXP.offset190)

  7385. #define PXP_CSC1_COEF0			(IMXRT_PXP.offset1A0)

  7386. #define PXP_CSC1_COEF1			(IMXRT_PXP.offset1B0)

  7387. #define PXP_CSC1_COEF2			(IMXRT_PXP.offset1C0)

  7388. #define PXP_POWER			(IMXRT_PXP_b.offset000)

  7389. #define PXP_PORTER_DUFF_CTRL		(IMXRT_PXP_b.offset040)

  7390. 

  7391. // 54.6: page 2990

  7392. typedef struct

  7393. {

  7394.    volatile uint16_t COMP1;

  7395.    volatile uint16_t COMP2;

  7396.    volatile uint16_t CAPT;

  7397.    volatile uint16_t LOAD;

  7398.    volatile uint16_t HOLD;

  7399.    volatile uint16_t CNTR;

  7400.    volatile uint16_t CTRL;

  7401.    volatile uint16_t SCTRL;

  7402.    volatile uint16_t CMPLD1;

  7403.    volatile uint16_t CMPLD2;

  7404.    volatile uint16_t CSCTRL;

  7405.    volatile uint16_t FILT;

  7406.    volatile uint16_t DMA;

  7407.    volatile uint16_t unused1[3];

  7408. } IMXRT_TMR_CH_t;

  7409. typedef struct

  7410. {

  7411.    union {

  7412.       IMXRT_TMR_CH_t CH[4];

  7413.       struct

  7414.       {

  7415.          volatile uint16_t unused2[15];

  7416.          volatile uint16_t ENBL;

  7417.       };

  7418.    };

  7419. } IMXRT_TMR_t;

  7420. #define IMXRT_TMR1		(*(IMXRT_TMR_t *)0x401DC000)

  7421. #define TMR1_COMP10			(IMXRT_TMR1.CH[0].COMP1)

  7422. #define TMR1_COMP20			(IMXRT_TMR1.CH[0].COMP2)

  7423. #define TMR1_CAPT0			(IMXRT_TMR1.CH[0].CAPT)

  7424. #define TMR1_LOAD0			(IMXRT_TMR1.CH[0].LOAD)

  7425. #define TMR1_HOLD0			(IMXRT_TMR1.CH[0].HOLD)

  7426. #define TMR1_CNTR0			(IMXRT_TMR1.CH[0].CNTR)

  7427. #define TMR1_CTRL0			(IMXRT_TMR1.CH[0].CTRL)

  7428. #define TMR1_SCTRL0			(IMXRT_TMR1.CH[0].SCTRL)

  7429. #define TMR1_CMPLD10			(IMXRT_TMR1.CH[0].CMPLD1)

  7430. #define TMR1_CMPLD20			(IMXRT_TMR1.CH[0].CMPLD2)

  7431. #define TMR1_CSCTRL0			(IMXRT_TMR1.CH[0].CSCTRL)

  7432. #define TMR1_FILT0			(IMXRT_TMR1.CH[0].FILT)

  7433. #define TMR1_DMA0			(IMXRT_TMR1.CH[0].DMA)

  7434. #define TMR1_ENBL			(IMXRT_TMR1.ENBL)

  7435. #define TMR1_COMP11			(IMXRT_TMR1.CH[1].COMP1)

  7436. #define TMR1_COMP21			(IMXRT_TMR1.CH[1].COMP2)

  7437. #define TMR1_CAPT1			(IMXRT_TMR1.CH[1].CAPT)

  7438. #define TMR1_LOAD1			(IMXRT_TMR1.CH[1].LOAD)

  7439. #define TMR1_HOLD1			(IMXRT_TMR1.CH[1].HOLD)

  7440. #define TMR1_CNTR1			(IMXRT_TMR1.CH[1].CNTR)

  7441. #define TMR1_CTRL1			(IMXRT_TMR1.CH[1].CTRL)

  7442. #define TMR1_SCTRL1			(IMXRT_TMR1.CH[1].SCTRL)

  7443. #define TMR1_CMPLD11			(IMXRT_TMR1.CH[1].CMPLD1)

  7444. #define TMR1_CMPLD21			(IMXRT_TMR1.CH[1].CMPLD2)

  7445. #define TMR1_CSCTRL1			(IMXRT_TMR1.CH[1].CSCTRL)

  7446. #define TMR1_FILT1			(IMXRT_TMR1.CH[1].FILT)

  7447. #define TMR1_DMA1			(IMXRT_TMR1.CH[1].DMA)

  7448. #define TMR1_COMP12			(IMXRT_TMR1.CH[2].COMP1)

  7449. #define TMR1_COMP22			(IMXRT_TMR1.CH[2].COMP2)

  7450. #define TMR1_CAPT2			(IMXRT_TMR1.CH[2].CAPT)

  7451. #define TMR1_LOAD2			(IMXRT_TMR1.CH[2].LOAD)

  7452. #define TMR1_HOLD2			(IMXRT_TMR1.CH[2].HOLD)

  7453. #define TMR1_CNTR2			(IMXRT_TMR1.CH[2].CNTR)

  7454. #define TMR1_CTRL2			(IMXRT_TMR1.CH[2].CTRL)

  7455. #define TMR1_SCTRL2			(IMXRT_TMR1.CH[2].SCTRL)

  7456. #define TMR1_CMPLD12			(IMXRT_TMR1.CH[2].CMPLD1)

  7457. #define TMR1_CMPLD22			(IMXRT_TMR1.CH[2].CMPLD2)

  7458. #define TMR1_CSCTRL2			(IMXRT_TMR1.CH[2].CSCTRL)

  7459. #define TMR1_FILT2			(IMXRT_TMR1.CH[2].FILT)

  7460. #define TMR1_DMA2			(IMXRT_TMR1.CH[2].DMA)

  7461. #define TMR1_COMP13			(IMXRT_TMR1.CH[3].COMP1)

  7462. #define TMR1_COMP23			(IMXRT_TMR1.CH[3].COMP2)

  7463. #define TMR1_CAPT3			(IMXRT_TMR1.CH[3].CAPT)

  7464. #define TMR1_LOAD3			(IMXRT_TMR1.CH[3].LOAD)

  7465. #define TMR1_HOLD3			(IMXRT_TMR1.CH[3].HOLD)

  7466. #define TMR1_CNTR3			(IMXRT_TMR1.CH[3].CNTR)

  7467. #define TMR1_CTRL3			(IMXRT_TMR1.CH[3].CTRL)

  7468. #define TMR1_SCTRL3			(IMXRT_TMR1.CH[3].SCTRL)

  7469. #define TMR1_CMPLD13			(IMXRT_TMR1.CH[3].CMPLD1)

  7470. #define TMR1_CMPLD23			(IMXRT_TMR1.CH[3].CMPLD2)

  7471. #define TMR1_CSCTRL3			(IMXRT_TMR1.CH[3].CSCTRL)

  7472. #define TMR1_FILT3			(IMXRT_TMR1.CH[3].FILT)

  7473. #define TMR1_DMA3			(IMXRT_TMR1.CH[3].DMA)

  7474. #define IMXRT_TMR2		(*(IMXRT_TMR_t *)0x401E0000)

  7475. #define TMR2_COMP10			(IMXRT_TMR2.CH[0].COMP1)

  7476. #define TMR2_COMP20			(IMXRT_TMR2.CH[0].COMP2)

  7477. #define TMR2_CAPT0			(IMXRT_TMR2.CH[0].CAPT)

  7478. #define TMR2_LOAD0			(IMXRT_TMR2.CH[0].LOAD)

  7479. #define TMR2_HOLD0			(IMXRT_TMR2.CH[0].HOLD)

  7480. #define TMR2_CNTR0			(IMXRT_TMR2.CH[0].CNTR)

  7481. #define TMR2_CTRL0			(IMXRT_TMR2.CH[0].CTRL)

  7482. #define TMR2_SCTRL0			(IMXRT_TMR2.CH[0].SCTRL)

  7483. #define TMR2_CMPLD10			(IMXRT_TMR2.CH[0].CMPLD1)

  7484. #define TMR2_CMPLD20			(IMXRT_TMR2.CH[0].CMPLD2)

  7485. #define TMR2_CSCTRL0			(IMXRT_TMR2.CH[0].CSCTRL)

  7486. #define TMR2_FILT0			(IMXRT_TMR2.CH[0].FILT)

  7487. #define TMR2_DMA0			(IMXRT_TMR2.CH[0].DMA)

  7488. #define TMR2_ENBL			(IMXRT_TMR2.ENBL)

  7489. #define TMR2_COMP11			(IMXRT_TMR2.CH[1].COMP1)

  7490. #define TMR2_COMP21			(IMXRT_TMR2.CH[1].COMP2)

  7491. #define TMR2_CAPT1			(IMXRT_TMR2.CH[1].CAPT)

  7492. #define TMR2_LOAD1			(IMXRT_TMR2.CH[1].LOAD)

  7493. #define TMR2_HOLD1			(IMXRT_TMR2.CH[1].HOLD)

  7494. #define TMR2_CNTR1			(IMXRT_TMR2.CH[1].CNTR)

  7495. #define TMR2_CTRL1			(IMXRT_TMR2.CH[1].CTRL)

  7496. #define TMR2_SCTRL1			(IMXRT_TMR2.CH[1].SCTRL)

  7497. #define TMR2_CMPLD11			(IMXRT_TMR2.CH[1].CMPLD1)

  7498. #define TMR2_CMPLD21			(IMXRT_TMR2.CH[1].CMPLD2)

  7499. #define TMR2_CSCTRL1			(IMXRT_TMR2.CH[1].CSCTRL)

  7500. #define TMR2_FILT1			(IMXRT_TMR2.CH[1].FILT)

  7501. #define TMR2_DMA1			(IMXRT_TMR2.CH[1].DMA)

  7502. #define TMR2_COMP12			(IMXRT_TMR2.CH[2].COMP1)

  7503. #define TMR2_COMP22			(IMXRT_TMR2.CH[2].COMP2)

  7504. #define TMR2_CAPT2			(IMXRT_TMR2.CH[2].CAPT)

  7505. #define TMR2_LOAD2			(IMXRT_TMR2.CH[2].LOAD)

  7506. #define TMR2_HOLD2			(IMXRT_TMR2.CH[2].HOLD)

  7507. #define TMR2_CNTR2			(IMXRT_TMR2.CH[2].CNTR)

  7508. #define TMR2_CTRL2			(IMXRT_TMR2.CH[2].CTRL)

  7509. #define TMR2_SCTRL2			(IMXRT_TMR2.CH[2].SCTRL)

  7510. #define TMR2_CMPLD12			(IMXRT_TMR2.CH[2].CMPLD1)

  7511. #define TMR2_CMPLD22			(IMXRT_TMR2.CH[2].CMPLD2)

  7512. #define TMR2_CSCTRL2			(IMXRT_TMR2.CH[2].CSCTRL)

  7513. #define TMR2_FILT2			(IMXRT_TMR2.CH[2].FILT)

  7514. #define TMR2_DMA2			(IMXRT_TMR2.CH[2].DMA)

  7515. #define TMR2_COMP13			(IMXRT_TMR2.CH[3].COMP1)

  7516. #define TMR2_COMP23			(IMXRT_TMR2.CH[3].COMP2)

  7517. #define TMR2_CAPT3			(IMXRT_TMR2.CH[3].CAPT)

  7518. #define TMR2_LOAD3			(IMXRT_TMR2.CH[3].LOAD)

  7519. #define TMR2_HOLD3			(IMXRT_TMR2.CH[3].HOLD)

  7520. #define TMR2_CNTR3			(IMXRT_TMR2.CH[3].CNTR)

  7521. #define TMR2_CTRL3			(IMXRT_TMR2.CH[3].CTRL)

  7522. #define TMR2_SCTRL3			(IMXRT_TMR2.CH[3].SCTRL)

  7523. #define TMR2_CMPLD13			(IMXRT_TMR2.CH[3].CMPLD1)

  7524. #define TMR2_CMPLD23			(IMXRT_TMR2.CH[3].CMPLD2)

  7525. #define TMR2_CSCTRL3			(IMXRT_TMR2.CH[3].CSCTRL)

  7526. #define TMR2_FILT3			(IMXRT_TMR2.CH[3].FILT)

  7527. #define TMR2_DMA3			(IMXRT_TMR2.CH[3].DMA)

  7528. #define IMXRT_TMR3		(*(IMXRT_TMR_t *)0x401E4000)

  7529. #define TMR3_COMP10			(IMXRT_TMR3.CH[0].COMP1)

  7530. #define TMR3_COMP20			(IMXRT_TMR3.CH[0].COMP2)

  7531. #define TMR3_CAPT0			(IMXRT_TMR3.CH[0].CAPT)

  7532. #define TMR3_LOAD0			(IMXRT_TMR3.CH[0].LOAD)

  7533. #define TMR3_HOLD0			(IMXRT_TMR3.CH[0].HOLD)

  7534. #define TMR3_CNTR0			(IMXRT_TMR3.CH[0].CNTR)

  7535. #define TMR3_CTRL0			(IMXRT_TMR3.CH[0].CTRL)

  7536. #define TMR3_SCTRL0			(IMXRT_TMR3.CH[0].SCTRL)

  7537. #define TMR3_CMPLD10			(IMXRT_TMR3.CH[0].CMPLD1)

  7538. #define TMR3_CMPLD20			(IMXRT_TMR3.CH[0].CMPLD2)

  7539. #define TMR3_CSCTRL0			(IMXRT_TMR3.CH[0].CSCTRL)

  7540. #define TMR3_FILT0			(IMXRT_TMR3.CH[0].FILT)

  7541. #define TMR3_DMA0			(IMXRT_TMR3.CH[0].DMA)

  7542. #define TMR3_ENBL			(IMXRT_TMR3.ENBL)

  7543. #define TMR3_COMP11			(IMXRT_TMR3.CH[1].COMP1)

  7544. #define TMR3_COMP21			(IMXRT_TMR3.CH[1].COMP2)

  7545. #define TMR3_CAPT1			(IMXRT_TMR3.CH[1].CAPT)

  7546. #define TMR3_LOAD1			(IMXRT_TMR3.CH[1].LOAD)

  7547. #define TMR3_HOLD1			(IMXRT_TMR3.CH[1].HOLD)

  7548. #define TMR3_CNTR1			(IMXRT_TMR3.CH[1].CNTR)

  7549. #define TMR3_CTRL1			(IMXRT_TMR3.CH[1].CTRL)

  7550. #define TMR3_SCTRL1			(IMXRT_TMR3.CH[1].SCTRL)

  7551. #define TMR3_CMPLD11			(IMXRT_TMR3.CH[1].CMPLD1)

  7552. #define TMR3_CMPLD21			(IMXRT_TMR3.CH[1].CMPLD2)

  7553. #define TMR3_CSCTRL1			(IMXRT_TMR3.CH[1].CSCTRL)

  7554. #define TMR3_FILT1			(IMXRT_TMR3.CH[1].FILT)

  7555. #define TMR3_DMA1			(IMXRT_TMR3.CH[1].DMA)

  7556. #define TMR3_COMP12			(IMXRT_TMR3.CH[2].COMP1)

  7557. #define TMR3_COMP22			(IMXRT_TMR3.CH[2].COMP2)

  7558. #define TMR3_CAPT2			(IMXRT_TMR3.CH[2].CAPT)

  7559. #define TMR3_LOAD2			(IMXRT_TMR3.CH[2].LOAD)

  7560. #define TMR3_HOLD2			(IMXRT_TMR3.CH[2].HOLD)

  7561. #define TMR3_CNTR2			(IMXRT_TMR3.CH[2].CNTR)

  7562. #define TMR3_CTRL2			(IMXRT_TMR3.CH[2].CTRL)

  7563. #define TMR3_SCTRL2			(IMXRT_TMR3.CH[2].SCTRL)

  7564. #define TMR3_CMPLD12			(IMXRT_TMR3.CH[2].CMPLD1)

  7565. #define TMR3_CMPLD22			(IMXRT_TMR3.CH[2].CMPLD2)

  7566. #define TMR3_CSCTRL2			(IMXRT_TMR3.CH[2].CSCTRL)

  7567. #define TMR3_FILT2			(IMXRT_TMR3.CH[2].FILT)

  7568. #define TMR3_DMA2			(IMXRT_TMR3.CH[2].DMA)

  7569. #define TMR3_COMP13			(IMXRT_TMR3.CH[3].COMP1)

  7570. #define TMR3_COMP23			(IMXRT_TMR3.CH[3].COMP2)

  7571. #define TMR3_CAPT3			(IMXRT_TMR3.CH[3].CAPT)

  7572. #define TMR3_LOAD3			(IMXRT_TMR3.CH[3].LOAD)

  7573. #define TMR3_HOLD3			(IMXRT_TMR3.CH[3].HOLD)

  7574. #define TMR3_CNTR3			(IMXRT_TMR3.CH[3].CNTR)

  7575. #define TMR3_CTRL3			(IMXRT_TMR3.CH[3].CTRL)

  7576. #define TMR3_SCTRL3			(IMXRT_TMR3.CH[3].SCTRL)

  7577. #define TMR3_CMPLD13			(IMXRT_TMR3.CH[3].CMPLD1)

  7578. #define TMR3_CMPLD23			(IMXRT_TMR3.CH[3].CMPLD2)

  7579. #define TMR3_CSCTRL3			(IMXRT_TMR3.CH[3].CSCTRL)

  7580. #define TMR3_FILT3			(IMXRT_TMR3.CH[3].FILT)

  7581. #define TMR3_DMA3			(IMXRT_TMR3.CH[3].DMA)

  7582. #define IMXRT_TMR4		(*(IMXRT_TMR_t *)0x401E8000)

  7583. #define TMR4_COMP10			(IMXRT_TMR4.CH[0].COMP1)

  7584. #define TMR4_COMP20			(IMXRT_TMR4.CH[0].COMP2)

  7585. #define TMR4_CAPT0			(IMXRT_TMR4.CH[0].CAPT)

  7586. #define TMR4_LOAD0			(IMXRT_TMR4.CH[0].LOAD)

  7587. #define TMR4_HOLD0			(IMXRT_TMR4.CH[0].HOLD)

  7588. #define TMR4_CNTR0			(IMXRT_TMR4.CH[0].CNTR)

  7589. #define TMR4_CTRL0			(IMXRT_TMR4.CH[0].CTRL)

  7590. #define TMR4_SCTRL0			(IMXRT_TMR4.CH[0].SCTRL)

  7591. #define TMR4_CMPLD10			(IMXRT_TMR4.CH[0].CMPLD1)

  7592. #define TMR4_CMPLD20			(IMXRT_TMR4.CH[0].CMPLD2)

  7593. #define TMR4_CSCTRL0			(IMXRT_TMR4.CH[0].CSCTRL)

  7594. #define TMR4_FILT0			(IMXRT_TMR4.CH[0].FILT)

  7595. #define TMR4_DMA0			(IMXRT_TMR4.CH[0].DMA)

  7596. #define TMR4_ENBL			(IMXRT_TMR4.ENBL)

  7597. #define TMR4_COMP11			(IMXRT_TMR4.CH[1].COMP1)

  7598. #define TMR4_COMP21			(IMXRT_TMR4.CH[1].COMP2)

  7599. #define TMR4_CAPT1			(IMXRT_TMR4.CH[1].CAPT)

  7600. #define TMR4_LOAD1			(IMXRT_TMR4.CH[1].LOAD)

  7601. #define TMR4_HOLD1			(IMXRT_TMR4.CH[1].HOLD)

  7602. #define TMR4_CNTR1			(IMXRT_TMR4.CH[1].CNTR)

  7603. #define TMR4_CTRL1			(IMXRT_TMR4.CH[1].CTRL)

  7604. #define TMR4_SCTRL1			(IMXRT_TMR4.CH[1].SCTRL)

  7605. #define TMR4_CMPLD11			(IMXRT_TMR4.CH[1].CMPLD1)

  7606. #define TMR4_CMPLD21			(IMXRT_TMR4.CH[1].CMPLD2)

  7607. #define TMR4_CSCTRL1			(IMXRT_TMR4.CH[1].CSCTRL)

  7608. #define TMR4_FILT1			(IMXRT_TMR4.CH[1].FILT)

  7609. #define TMR4_DMA1			(IMXRT_TMR4.CH[1].DMA)

  7610. #define TMR4_COMP12			(IMXRT_TMR4.CH[2].COMP1)

  7611. #define TMR4_COMP22			(IMXRT_TMR4.CH[2].COMP2)

  7612. #define TMR4_CAPT2			(IMXRT_TMR4.CH[2].CAPT)

  7613. #define TMR4_LOAD2			(IMXRT_TMR4.CH[2].LOAD)

  7614. #define TMR4_HOLD2			(IMXRT_TMR4.CH[2].HOLD)

  7615. #define TMR4_CNTR2			(IMXRT_TMR4.CH[2].CNTR)

  7616. #define TMR4_CTRL2			(IMXRT_TMR4.CH[2].CTRL)

  7617. #define TMR4_SCTRL2			(IMXRT_TMR4.CH[2].SCTRL)

  7618. #define TMR4_CMPLD12			(IMXRT_TMR4.CH[2].CMPLD1)

  7619. #define TMR4_CMPLD22			(IMXRT_TMR4.CH[2].CMPLD2)

  7620. #define TMR4_CSCTRL2			(IMXRT_TMR4.CH[2].CSCTRL)

  7621. #define TMR4_FILT2			(IMXRT_TMR4.CH[2].FILT)

  7622. #define TMR4_DMA2			(IMXRT_TMR4.CH[2].DMA)

  7623. #define TMR4_COMP13			(IMXRT_TMR4.CH[3].COMP1)

  7624. #define TMR4_COMP23			(IMXRT_TMR4.CH[3].COMP2)

  7625. #define TMR4_CAPT3			(IMXRT_TMR4.CH[3].CAPT)

  7626. #define TMR4_LOAD3			(IMXRT_TMR4.CH[3].LOAD)

  7627. #define TMR4_HOLD3			(IMXRT_TMR4.CH[3].HOLD)

  7628. #define TMR4_CNTR3			(IMXRT_TMR4.CH[3].CNTR)

  7629. #define TMR4_CTRL3			(IMXRT_TMR4.CH[3].CTRL)

  7630. #define TMR4_SCTRL3			(IMXRT_TMR4.CH[3].SCTRL)

  7631. #define TMR4_CMPLD13			(IMXRT_TMR4.CH[3].CMPLD1)

  7632. #define TMR4_CMPLD23			(IMXRT_TMR4.CH[3].CMPLD2)

  7633. #define TMR4_CSCTRL3			(IMXRT_TMR4.CH[3].CSCTRL)

  7634. #define TMR4_FILT3			(IMXRT_TMR4.CH[3].FILT)

  7635. #define TMR4_DMA3			(IMXRT_TMR4.CH[3].DMA)

  7636. #define TMR_CTRL_CM(n)				((uint16_t)(((n) & 0x07) << 13))

  7637. #define TMR_CTRL_PCS(n)				((uint16_t)(((n) & 0x0F) << 9))

  7638. #define TMR_CTRL_SCS(n)				((uint16_t)(((n) & 0x03) << 7))

  7639. #define TMR_CTRL_ONCE				((uint16_t)(1<<6))

  7640. #define TMR_CTRL_LENGTH				((uint16_t)(1<<5))

  7641. #define TMR_CTRL_DIR				((uint16_t)(1<<4))

  7642. #define TMR_CTRL_COINIT				((uint16_t)(1<<3))

  7643. #define TMR_CTRL_OUTMODE(n)			((uint16_t)(((n) & 0x07) << 0))

  7644. #define TMR_SCTRL_TCF				((uint16_t)(1<<15))

  7645. #define TMR_SCTRL_TCFIE				((uint16_t)(1<<14))

  7646. #define TMR_SCTRL_TOF				((uint16_t)(1<<13))

  7647. #define TMR_SCTRL_TOFIE				((uint16_t)(1<<12))

  7648. #define TMR_SCTRL_IEF				((uint16_t)(1<<11))

  7649. #define TMR_SCTRL_IEFIE				((uint16_t)(1<<10))

  7650. #define TMR_SCTRL_IPS				((uint16_t)(1<<9))

  7651. #define TMR_SCTRL_INPUT				((uint16_t)(1<<8))

  7652. #define TMR_SCTRL_CAPTURE_MODE(n)		((uint16_t)(((n) & 0x03) << 6))

  7653. #define TMR_SCTRL_MSTR				((uint16_t)(1<<5))

  7654. #define TMR_SCTRL_EEOF				((uint16_t)(1<<4))

  7655. #define TMR_SCTRL_VAL				((uint16_t)(1<<3))

  7656. #define TMR_SCTRL_FORCE				((uint16_t)(1<<2))

  7657. #define TMR_SCTRL_OPS				((uint16_t)(1<<1))

  7658. #define TMR_SCTRL_OEN				((uint16_t)(1<<0))

  7659. #define TMR_CSCTRL_DBG_EN(n)			((uint16_t)(((n) & 0x03) << 14))

  7660. #define TMR_CSCTRL_FAULT			((uint16_t)(1<<13))

  7661. #define TMR_CSCTRL_ALT_LOAD			((uint16_t)(1<<12))

  7662. #define TMR_CSCTRL_ROC				((uint16_t)(1<<11))

  7663. #define TMR_CSCTRL_TCI				((uint16_t)(1<<10))

  7664. #define TMR_CSCTRL_UP				((uint16_t)(1<<9))

  7665. #define TMR_CSCTRL_TCF2EN			((uint16_t)(1<<7))

  7666. #define TMR_CSCTRL_TCF1EN			((uint16_t)(1<<6))

  7667. #define TMR_CSCTRL_TCF2				((uint16_t)(1<<5))

  7668. #define TMR_CSCTRL_TCF1				((uint16_t)(1<<4))

  7669. #define TMR_CSCTRL_CL2(n)			((uint16_t)(((n) & 0x03) << 2))

  7670. #define TMR_CSCTRL_CL1(n)			((uint16_t)(((n) & 0x03) << 0))

  7671. #define TMR_FILT_FILT_CNT(n)			((uint16_t)(((n) & 0x07) << 8))

  7672. #define TMR_FILT_FILT_PER(n)			((uint16_t)(((n) & 0xFF) << 0))

  7673. #define TMR_DMA_CMPLD2DE			((uint16_t)(1<<2))

  7674. #define TMR_DMA_CMPLD1DE			((uint16_t)(1<<1))

  7675. #define TMR_DMA_IEFDE				((uint16_t)(1<<0))

  7676. 

  7677. // 38.5.1.1: page 1981

  7678. #define IMXRT_I2S1		(*(IMXRT_REGISTER32_t *)0x40384000)

  7679. #define I2S1_VERID			(IMXRT_I2S1.offset000)

  7680. #define I2S1_PARAM			(IMXRT_I2S1.offset004)

  7681. #define I2S1_TCSR			(IMXRT_I2S1.offset008)

  7682. #define I2S1_TCR1			(IMXRT_I2S1.offset00C)

  7683. #define I2S1_TCR2			(IMXRT_I2S1.offset010)

  7684. #define I2S1_TCR3			(IMXRT_I2S1.offset014)

  7685. #define I2S1_TCR4			(IMXRT_I2S1.offset018)

  7686. #define I2S1_TCR5			(IMXRT_I2S1.offset01C)

  7687. #define I2S1_TDR0			(IMXRT_I2S1.offset020)

  7688. #define I2S1_TDR1			(IMXRT_I2S1.offset024)

  7689. #define I2S1_TDR2			(IMXRT_I2S1.offset028)

  7690. #define I2S1_TDR3			(IMXRT_I2S1.offset02C)

  7691. #define I2S1_TFR0			(IMXRT_I2S1.offset040)

  7692. #define I2S1_TFR1			(IMXRT_I2S1.offset044)

  7693. #define I2S1_TFR2			(IMXRT_I2S1.offset048)

  7694. #define I2S1_TFR3			(IMXRT_I2S1.offset04C)

  7695. #define I2S1_TMR			(IMXRT_I2S1.offset060)

  7696. #define I2S1_RCSR			(IMXRT_I2S1.offset088)

  7697. #define I2S1_RCR1			(IMXRT_I2S1.offset08C)

  7698. #define I2S1_RCR2			(IMXRT_I2S1.offset090)

  7699. #define I2S1_RCR3			(IMXRT_I2S1.offset094)

  7700. #define I2S1_RCR4			(IMXRT_I2S1.offset098)

  7701. #define I2S1_RCR5			(IMXRT_I2S1.offset09C)

  7702. #define I2S1_RDR0			(IMXRT_I2S1.offset0A0)

  7703. #define I2S1_RDR1			(IMXRT_I2S1.offset0A4)

  7704. #define I2S1_RDR2			(IMXRT_I2S1.offset0A8)

  7705. #define I2S1_RDR3			(IMXRT_I2S1.offset0AC)

  7706. #define I2S1_RFR0			(IMXRT_I2S1.offset0C0)

  7707. #define I2S1_RFR1			(IMXRT_I2S1.offset0C4)

  7708. #define I2S1_RFR2			(IMXRT_I2S1.offset0C8)

  7709. #define I2S1_RFR3			(IMXRT_I2S1.offset0CC)

  7710. #define I2S1_RMR			(IMXRT_I2S1.offset0E0)

  7711. #define IMXRT_I2S2		(*(IMXRT_REGISTER32_t *)0x40388000)

  7712. #define I2S2_VERID			(IMXRT_I2S2.offset000)

  7713. #define I2S2_PARAM			(IMXRT_I2S2.offset004)

  7714. #define I2S2_TCSR			(IMXRT_I2S2.offset008)

  7715. #define I2S2_TCR1			(IMXRT_I2S2.offset00C)

  7716. #define I2S2_TCR2			(IMXRT_I2S2.offset010)

  7717. #define I2S2_TCR3			(IMXRT_I2S2.offset014)

  7718. #define I2S2_TCR4			(IMXRT_I2S2.offset018)

  7719. #define I2S2_TCR5			(IMXRT_I2S2.offset01C)

  7720. #define I2S2_TDR0			(IMXRT_I2S2.offset020)

  7721. #define I2S2_TDR1			(IMXRT_I2S2.offset024)

  7722. #define I2S2_TDR2			(IMXRT_I2S2.offset028)

  7723. #define I2S2_TDR3			(IMXRT_I2S2.offset02C)

  7724. #define I2S2_TFR0			(IMXRT_I2S2.offset040)

  7725. #define I2S2_TFR1			(IMXRT_I2S2.offset044)

  7726. #define I2S2_TFR2			(IMXRT_I2S2.offset048)

  7727. #define I2S2_TFR3			(IMXRT_I2S2.offset04C)

  7728. #define I2S2_TMR			(IMXRT_I2S2.offset060)

  7729. #define I2S2_RCSR			(IMXRT_I2S2.offset088)

  7730. #define I2S2_RCR1			(IMXRT_I2S2.offset08C)

  7731. #define I2S2_RCR2			(IMXRT_I2S2.offset090)

  7732. #define I2S2_RCR3			(IMXRT_I2S2.offset094)

  7733. #define I2S2_RCR4			(IMXRT_I2S2.offset098)

  7734. #define I2S2_RCR5			(IMXRT_I2S2.offset09C)

  7735. #define I2S2_RDR0			(IMXRT_I2S2.offset0A0)

  7736. #define I2S2_RDR1			(IMXRT_I2S2.offset0A4)

  7737. #define I2S2_RDR2			(IMXRT_I2S2.offset0A8)

  7738. #define I2S2_RDR3			(IMXRT_I2S2.offset0AC)

  7739. #define I2S2_RFR0			(IMXRT_I2S2.offset0C0)

  7740. #define I2S2_RFR1			(IMXRT_I2S2.offset0C4)

  7741. #define I2S2_RFR2			(IMXRT_I2S2.offset0C8)

  7742. #define I2S2_RFR3			(IMXRT_I2S2.offset0CC)

  7743. #define I2S2_RMR			(IMXRT_I2S2.offset0E0)

  7744. #define IMXRT_I2S3		(*(IMXRT_REGISTER32_t *)0x4038C000)

  7745. #define I2S3_VERID			(IMXRT_I2S3.offset000)

  7746. #define I2S3_PARAM			(IMXRT_I2S3.offset004)

  7747. #define I2S3_TCSR			(IMXRT_I2S3.offset008)

  7748. #define I2S3_TCR1			(IMXRT_I2S3.offset00C)

  7749. #define I2S3_TCR2			(IMXRT_I2S3.offset010)

  7750. #define I2S3_TCR3			(IMXRT_I2S3.offset014)

  7751. #define I2S3_TCR4			(IMXRT_I2S3.offset018)

  7752. #define I2S3_TCR5			(IMXRT_I2S3.offset01C)

  7753. #define I2S3_TDR0			(IMXRT_I2S3.offset020)

  7754. #define I2S3_TDR1			(IMXRT_I2S3.offset024)

  7755. #define I2S3_TDR2			(IMXRT_I2S3.offset028)

  7756. #define I2S3_TDR3			(IMXRT_I2S3.offset02C)

  7757. #define I2S3_TFR0			(IMXRT_I2S3.offset040)

  7758. #define I2S3_TFR1			(IMXRT_I2S3.offset044)

  7759. #define I2S3_TFR2			(IMXRT_I2S3.offset048)

  7760. #define I2S3_TFR3			(IMXRT_I2S3.offset04C)

  7761. #define I2S3_TMR			(IMXRT_I2S3.offset060)

  7762. #define I2S3_RCSR			(IMXRT_I2S3.offset088)

  7763. #define I2S3_RCR1			(IMXRT_I2S3.offset08C)

  7764. #define I2S3_RCR2			(IMXRT_I2S3.offset090)

  7765. #define I2S3_RCR3			(IMXRT_I2S3.offset094)

  7766. #define I2S3_RCR4			(IMXRT_I2S3.offset098)

  7767. #define I2S3_RCR5			(IMXRT_I2S3.offset09C)

  7768. #define I2S3_RDR0			(IMXRT_I2S3.offset0A0)

  7769. #define I2S3_RDR1			(IMXRT_I2S3.offset0A4)

  7770. #define I2S3_RDR2			(IMXRT_I2S3.offset0A8)

  7771. #define I2S3_RDR3			(IMXRT_I2S3.offset0AC)

  7772. #define I2S3_RFR0			(IMXRT_I2S3.offset0C0)

  7773. #define I2S3_RFR1			(IMXRT_I2S3.offset0C4)

  7774. #define I2S3_RFR2			(IMXRT_I2S3.offset0C8)

  7775. #define I2S3_RFR3			(IMXRT_I2S3.offset0CC)

  7776. #define I2S3_RMR			(IMXRT_I2S3.offset0E0)

  7777. 

  7778. #define I2S_RCR1_RFW(n)			((uint32_t)n & 0x1f)	// Receive FIFO watermark

  7779. #define I2S_RCR2_DIV(n)			((uint32_t)n & 0xff)	// Bit clock divide by (DIV+1)*2

  7780. #define I2S_RCR2_BCD			((uint32_t)1<<24)	// Bit clock direction

  7781. #define I2S_RCR2_MSEL(n)		((uint32_t)(n & 3)<<26)	// MCLK select, 0=bus clock, 1=I2S0_MCLK

  7782. #define I2S_RCR2_SYNC(n)		((uint32_t)(n & 3)<<30)	// 0=async 1=sync with trasmitter

  7783. #define I2S_RCR3_RCE			((uint32_t)0x10000)	// receive channel enable

  7784. #define I2S_RCR3_RCE_2CH		((uint32_t)0x30000)

  7785. #define I2S_RCR3_RCE_3CH		((uint32_t)0x70000)

  7786. #define I2S_RCR3_RCE_4CH		((uint32_t)0xF0000)

  7787. #define I2S_RCR4_FSD			((uint32_t)1)		// Frame Sync Direction

  7788. #define I2S_RCR4_FSP			((uint32_t)1<<1)

  7789. #define I2S_RCR4_FSE			((uint32_t)8)		// Frame Sync Early

  7790. #define I2S_RCR4_MF			((uint32_t)0x10)	// MSB First

  7791. #define I2S_RCR4_SYWD(n)		((uint32_t)(n & 0x1f)<<8)	// Sync Width

  7792. #define I2S_RCR4_FRSZ(n)		((uint32_t)(n & 0x0f)<<16)	// Frame Size

  7793. #define I2S_RCR4_FCONT			((uint32_t)1<<28)	// FIFO Continue on Error

  7794. #define I2S_RCR5_FBT(n)			((uint32_t)(n & 0x1f)<<8)	// First Bit Shifted

  7795. #define I2S_RCR5_W0W(n)			((uint32_t)(n & 0x1f)<<16)	// Word 0 Width

  7796. #define I2S_RCR5_WNW(n)			((uint32_t)(n & 0x1f)<<24)	// Word N Width

  7797. #define I2S_RCR2_BCP			((uint32_t)1<<25)

  7798. #define I2S_RCSR_RE			((uint32_t)0x80000000)	// Receiver Enable

  7799. #define I2S_RCSR_FR			((uint32_t)0x02000000)	// FIFO Reset

  7800. #define I2S_RCSR_FRDE			((uint32_t)0x00000001)	// FIFO Request DMA Enable

  7801. #define I2S_RCSR_BCE			((uint32_t)0x10000000)	// Bit Clock Enable

  7802. #define I2S_TCR1_RFW(n)			((uint32_t)n & 0x1f)	// Receive FIFO watermark

  7803. #define I2S_TCR2_DIV(n)			((uint32_t)n & 0xff)	// Bit clock divide by (DIV+1)*2

  7804. #define I2S_TCR2_BCD			((uint32_t)1<<24)	// Bit clock direction

  7805. #define I2S_TCR2_MSEL(n)		((uint32_t)(n & 3)<<26)	// MCLK select, 0=bus clock, 1=I2S0_MCLK

  7806. #define I2S_TCR2_SYNC(n)		((uint32_t)(n & 3)<<30)	// 0=async 1=sync with receiver

  7807. #define I2S_TCR3_TCE			((uint32_t)0x10000)	// receive channel enable

  7808. #define I2S_TCR3_TCE_2CH		((uint32_t)0x30000)

  7809. #define I2S_TCR3_TCE_3CH		((uint32_t)0x70000)

  7810. #define I2S_TCR3_TCE_4CH		((uint32_t)0xF0000)

  7811. #define I2S_TCR4_FSD			((uint32_t)1)		// Frame Sync Direction

  7812. #define I2S_TCR4_FSP			((uint32_t)1<<1)

  7813. #define I2S_TCR4_FSE			((uint32_t)8)		// Frame Sync Early

  7814. #define I2S_TCR4_MF			((uint32_t)0x10)	// MSB First

  7815. #define I2S_TCR4_SYWD(n)		((uint32_t)(n & 0x1f)<<8)	// Sync Width

  7816. #define I2S_TCR4_FRSZ(n)		((uint32_t)(n & 0x0f)<<16)	// Frame Size

  7817. #define I2S_TCR4_FCONT			((uint32_t)1<<28)	// FIFO Continue on Error

  7818. #define I2S_TCR5_FBT(n)			((uint32_t)(n & 0x1f)<<8) 	// First Bit Shifted

  7819. #define I2S_TCR5_W0W(n)			((uint32_t)(n & 0x1f)<<16)	// Word 0 Width

  7820. #define I2S_TCR5_WNW(n)			((uint32_t)(n & 0x1f)<<24)	// Word N Width

  7821. #define I2S_TCR2_BCP			((uint32_t)1<<25)

  7822. #define I2S_TCSR_TE			((uint32_t)0x80000000)		// Receiver Enable

  7823. #define I2S_TCSR_BCE			((uint32_t)0x10000000)	// Bit Clock Enable

  7824. #define I2S_TCSR_FR			((uint32_t)0x02000000)	// FIFO Reset

  7825. #define I2S_TCSR_FRDE			((uint32_t)0x00000001)	// FIFO Request DMA Enable

  7826. 

  7827. 

  7828. 

  7829. 

  7830. 

  7831. // 25.4.1.1: page 1385

  7832. #define IMXRT_SEMC		(*(IMXRT_REGISTER32_t *)0x402F0000)

  7833. #define SEMC_MCR			(IMXRT_SEMC.offset000)

  7834. #define SEMC_IOCR			(IMXRT_SEMC.offset004)

  7835. #define SEMC_BMCR0			(IMXRT_SEMC.offset008)

  7836. #define SEMC_BMCR1			(IMXRT_SEMC.offset00C)

  7837. #define SEMC_BR0			(IMXRT_SEMC.offset010)

  7838. #define SEMC_BR1			(IMXRT_SEMC.offset014)

  7839. #define SEMC_BR2			(IMXRT_SEMC.offset018)

  7840. #define SEMC_BR3			(IMXRT_SEMC.offset01C)

  7841. #define SEMC_BR4			(IMXRT_SEMC.offset020)

  7842. #define SEMC_BR5			(IMXRT_SEMC.offset024)

  7843. #define SEMC_BR6			(IMXRT_SEMC.offset028)

  7844. #define SEMC_BR7			(IMXRT_SEMC.offset02C)

  7845. #define SEMC_BR8			(IMXRT_SEMC.offset030)

  7846. #define SEMC_INTEN			(IMXRT_SEMC.offset038)

  7847. #define SEMC_INTR			(IMXRT_SEMC.offset03C)

  7848. #define SEMC_SDRAMCR0			(IMXRT_SEMC.offset040)

  7849. #define SEMC_SDRAMCR1			(IMXRT_SEMC.offset044)

  7850. #define SEMC_SDRAMCR2			(IMXRT_SEMC.offset048)

  7851. #define SEMC_SDRAMCR3			(IMXRT_SEMC.offset04C)

  7852. #define SEMC_NANDCR0			(IMXRT_SEMC.offset050)

  7853. #define SEMC_NANDCR1			(IMXRT_SEMC.offset054)

  7854. #define SEMC_NANDCR2			(IMXRT_SEMC.offset058)

  7855. #define SEMC_NANDCR3			(IMXRT_SEMC.offset05C)

  7856. #define SEMC_ORCR0			(IMXRT_SEMC.offset060)

  7857. #define SEMC_ORCR1			(IMXRT_SEMC.offset064)

  7858. #define SEMC_ORCR2			(IMXRT_SEMC.offset068)

  7859. #define SEMC_ORCR3			(IMXRT_SEMC.offset06C)

  7860. #define SEMC_SRAMCR0			(IMXRT_SEMC.offset070)

  7861. #define SEMC_SRAMCR1			(IMXRT_SEMC.offset074)

  7862. #define SEMC_SRAMCR2			(IMXRT_SEMC.offset078)

  7863. #define SEMC_SRAMCR3			(IMXRT_SEMC.offset07C)

  7864. #define SEMC_DBICR0			(IMXRT_SEMC.offset080)

  7865. #define SEMC_DBICR1			(IMXRT_SEMC.offset084)

  7866. #define SEMC_IPCR0			(IMXRT_SEMC.offset090)

  7867. #define SEMC_IPCR1			(IMXRT_SEMC.offset094)

  7868. #define SEMC_IPCR2			(IMXRT_SEMC.offset098)

  7869. #define SEMC_IPCMD			(IMXRT_SEMC.offset09C)

  7870. #define SEMC_IPTXDAT			(IMXRT_SEMC.offset0A0)

  7871. #define SEMC_IPRXDAT			(IMXRT_SEMC.offset0B0)

  7872. #define SEMC_STS0			(IMXRT_SEMC.offset0C0)

  7873. #define SEMC_STS1			(IMXRT_SEMC.offset0C4)

  7874. #define SEMC_STS2			(IMXRT_SEMC.offset0C8)

  7875. #define SEMC_STS3			(IMXRT_SEMC.offset0CC)

  7876. #define SEMC_STS4			(IMXRT_SEMC.offset0D0)

  7877. #define SEMC_STS5			(IMXRT_SEMC.offset0D4)

  7878. #define SEMC_STS6			(IMXRT_SEMC.offset0D8)

  7879. #define SEMC_STS7			(IMXRT_SEMC.offset0DC)

  7880. #define SEMC_STS8			(IMXRT_SEMC.offset0E0)

  7881. #define SEMC_STS9			(IMXRT_SEMC.offset0E4)

  7882. #define SEMC_STS10			(IMXRT_SEMC.offset0E8)

  7883. #define SEMC_STS11			(IMXRT_SEMC.offset0EC)

  7884. #define SEMC_STS12			(IMXRT_SEMC.offset0F0)

  7885. #define SEMC_STS13			(IMXRT_SEMC.offset0F4)

  7886. #define SEMC_STS14			(IMXRT_SEMC.offset0F8)

  7887. #define SEMC_STS15			(IMXRT_SEMC.offset0FC)

  7888. 

  7889. // 20.6.1: page 1242

  7890. #define IMXRT_SNVS		(*(IMXRT_REGISTER32_t *)0x400D4000)

  7891. #define SNVS_HPLR			(IMXRT_SNVS.offset000)

  7892. #define SNVS_HPCOMR			(IMXRT_SNVS.offset004)

  7893. #define SNVS_HPCR			(IMXRT_SNVS.offset008)

  7894. #define SNVS_HPSICR			(IMXRT_SNVS.offset00C)

  7895. #define SNVS_HPSVCR			(IMXRT_SNVS.offset010)

  7896. #define SNVS_HPSR			(IMXRT_SNVS.offset014)

  7897. #define SNVS_HPSVSR			(IMXRT_SNVS.offset018)

  7898. #define SNVS_HPHACIVR			(IMXRT_SNVS.offset01C)

  7899. #define SNVS_HPHACR			(IMXRT_SNVS.offset020)

  7900. #define SNVS_HPRTCMR			(IMXRT_SNVS.offset024)

  7901. #define SNVS_HPRTCLR			(IMXRT_SNVS.offset028)

  7902. #define SNVS_HPTAMR			(IMXRT_SNVS.offset02C)

  7903. #define SNVS_HPTALR			(IMXRT_SNVS.offset030)

  7904. #define SNVS_LPLR			(IMXRT_SNVS.offset034)

  7905. #define SNVS_LPCR			(IMXRT_SNVS.offset038)

  7906. #define SNVS_LPMKCR			(IMXRT_SNVS.offset03C)

  7907. #define SNVS_LPSVCR			(IMXRT_SNVS.offset040)

  7908. #define SNVS_LPTDCR			(IMXRT_SNVS.offset048)

  7909. #define SNVS_LPSR			(IMXRT_SNVS.offset04C)

  7910. #define SNVS_LPSRTCMR			(IMXRT_SNVS.offset050)

  7911. #define SNVS_LPSRTCLR			(IMXRT_SNVS.offset054)

  7912. #define SNVS_LPTAR			(IMXRT_SNVS.offset058)

  7913. #define SNVS_LPSMCMR			(IMXRT_SNVS.offset05C)

  7914. #define SNVS_LPSMCLR			(IMXRT_SNVS.offset060)

  7915. #define SNVS_LPPGDR			(IMXRT_SNVS.offset064)

  7916. #define SNVS_LPGPR			(IMXRT_SNVS.offset068)

  7917. #define IMXRT_SNVS_b		(*(IMXRT_REGISTER32_t *)0x400D4800)

  7918. #define SNVS_HPVIDR1			(IMXRT_SNVS_b.offset3F8)

  7919. #define SNVS_HPVIDR2			(IMXRT_SNVS_b.offset3FC)

  7920. #define SNVS_HPCR_BTN_MASK		((uint32_t)(1 << 27))

  7921. #define SNVS_HPCR_BTN_CONFIG(n)		((uint32_t)(((n) & 0x07) << 24))

  7922. #define SNVS_HPCR_HP_TS			((uint32_t)(1 << 16))

  7923. #define SNVS_HPCR_HPCALB_VAL(n)		((uint32_t)(((n) & 0x1F) << 10))

  7924. #define SNVS_HPCR_HPCALB_EN		((uint32_t)(1 << 8))

  7925. #define SNVS_HPCR_PI_FREQ(n)		((uint32_t)(((n) & 0x0F) << 4))

  7926. #define SNVS_HPCR_PI_EN			((uint32_t)(1 << 3))

  7927. #define SNVS_HPCR_DIS_PI		((uint32_t)(1 << 2))

  7928. #define SNVS_HPCR_HPTA_EN		((uint32_t)(1 << 1))

  7929. #define SNVS_HPCR_RTC_EN		((uint32_t)(1 << 0))

  7930. #define SNVS_DEFAULT_PGD_VALUE		(0x41736166U)

  7931. #define SNVS_LPCR_SRTC_ENV		((uint32_t)(1 << 0))

  7932. #define SNVS_LPCR_MC_ENV		((uint32_t)(1 << 2))

  7933. #define SNVS_LPCR_LPWUI_EN		((uint32_t)(1 << 3))

  7934. #define SNVS_LPCR_DP_EN			((uint32_t)(1 << 5))

  7935. #define SNVS_LPCR_TOP			((uint32_t)(1 << 6))

  7936. #define SNVS_LPCR_PWR_GLITCH_EN		((uint32_t)(1 << 7))

  7937. #define SNVS_LPCR_BTN_PRESS_TIME(n)	((uint32_t)(((n) & 0x03) << 16))

  7938. #define SNVS_LPCR_DEBOUNCE(n)		((uint32_t)(((n) & 0x03) << 18))

  7939. #define SNVS_LPCR_ON_TIME(n)		((uint32_t)(((n) & 0x03) << 20))

  7940. #define SNVS_LPCR_PK_EN			((uint32_t)(1 << 22))

  7941. #define SNVS_LPCR_PK_OVERRIDE		((uint32_t)(1 << 23))

  7942. 

  7943. // 40.6: page 2035

  7944. #define IMXRT_SPDIF		(*(IMXRT_REGISTER32_t *)0x40380000)

  7945. #define SPDIF_SCR			(IMXRT_SPDIF.offset000)

  7946. #define SPDIF_SRCD			(IMXRT_SPDIF.offset004)

  7947. #define SPDIF_SRPC			(IMXRT_SPDIF.offset008)

  7948. #define SPDIF_SIE			(IMXRT_SPDIF.offset00C)

  7949. #define SPDIF_SIS			(IMXRT_SPDIF.offset010)

  7950. #define SPDIF_SIC			(IMXRT_SPDIF.offset010)

  7951. #define SPDIF_SRL			(IMXRT_SPDIF.offset014)

  7952. #define SPDIF_SRR			(IMXRT_SPDIF.offset018)

  7953. #define SPDIF_SRCSH			(IMXRT_SPDIF.offset01C)

  7954. #define SPDIF_SRCSL			(IMXRT_SPDIF.offset020)

  7955. #define SPDIF_SRU			(IMXRT_SPDIF.offset024)

  7956. #define SPDIF_SRQ			(IMXRT_SPDIF.offset028)

  7957. #define SPDIF_STL			(IMXRT_SPDIF.offset02C)

  7958. #define SPDIF_STR			(IMXRT_SPDIF.offset030)

  7959. #define SPDIF_STCSCH			(IMXRT_SPDIF.offset034)

  7960. #define SPDIF_STCSCL			(IMXRT_SPDIF.offset038)

  7961. #define SPDIF_SRFM			(IMXRT_SPDIF.offset044)

  7962. #define SPDIF_STC			(IMXRT_SPDIF.offset050)

  7963. #define SPDIF_SCR_RXFIFO_CTR		((uint32_t)(1 << 23))

  7964. #define SPDIF_SCR_RXFIFO_OFF_ON		((uint32_t)(1 << 22))

  7965. #define SPDIF_SCR_RXFIFO_RST		((uint32_t)(1 << 21))

  7966. #define SPDIF_SCR_RXFIFOFULL_SEL(n)	((uint32_t)(((n) & 0x03) << 19))

  7967. #define SPDIF_SCR_RXAUTOSYNC		((uint32_t)(1 << 18))

  7968. #define SPDIF_SCR_TXAUTOSYNC		((uint32_t)(1 << 17))

  7969. #define SPDIF_SCR_TXFIFOEMPTY_SEL(n)	((uint32_t)(((n) & 0x03) << 15))

  7970. #define SPDIF_SCR_LOW_POWER		((uint32_t)(1 << 13))

  7971. #define SPDIF_SCR_SOFT_RESET		((uint32_t)(1 << 12))

  7972. #define SPDIF_SCR_TXFIFO_CTRL(n)	((uint32_t)(((n) & 0x03) << 10))

  7973. #define SPDIF_SCR_DMA_RX_EN		((uint32_t)(1 << 9))

  7974. #define SPDIF_SCR_DMA_TX_EN		((uint32_t)(1 << 8))

  7975. #define SPDIF_SCR_VALCTRL		((uint32_t)(1 << 5))

  7976. #define SPDIF_SCR_TXSEL(n)		((uint32_t)(((n) & 0x07) << 2))

  7977. #define SPDIF_SCR_USRC_SEL(n)		((uint32_t)(((n) & 0x03) << 0))

  7978. #define SPDIF_SRCD_USYNCMODE		((uint32_t)(1 << 1))

  7979. #define SPDIF_SRPC_CLKSRC_SEL(n)	((uint32_t)(((n) & 0x0f) << 7))

  7980. #define SPDIF_SRPC_LOCK			((uint32_t)(1 << 6))

  7981. #define SPDIF_SRPC_GAINSEL(n)		((uint32_t)(((n) & 0x07) << 3))

  7982. #define SPDIF_SIE_LOCK			((uint32_t)(1 << 20))

  7983. #define SPDIF_SIE_TXUNOV		((uint32_t)(1 << 19))

  7984. #define SPDIF_SIE_TXRESYN		((uint32_t)(1 << 18))

  7985. #define SPDIF_SIE_CNEW			((uint32_t)(1 << 17))

  7986. #define SPDIF_SIE_VALNOGOOD		((uint32_t)(1 << 16))

  7987. #define SPDIF_SIE_SYMERR		((uint32_t)(1 << 15))

  7988. #define SPDIF_SIE_BITERR		((uint32_t)(1 << 14))

  7989. #define SPDIF_SIE_URXFUL		((uint32_t)(1 << 10))

  7990. #define SPDIF_SIE_URXOV			((uint32_t)(1 << 9))

  7991. #define SPDIF_SIE_QRXFUL		((uint32_t)(1 << 8))

  7992. #define SPDIF_SIE_QRXOV			((uint32_t)(1 << 7))

  7993. #define SPDIF_SIE_UQSYNC		((uint32_t)(1 << 6))

  7994. #define SPDIF_SIE_UQERR			((uint32_t)(1 << 5))

  7995. #define SPDIF_SIE_RXFIFOUNOV		((uint32_t)(1 << 4))

  7996. #define SPDIF_SIE_RXFIFORESYN		((uint32_t)(1 << 3))

  7997. #define SPDIF_SIE_LOCKLOSS		((uint32_t)(1 << 2))

  7998. #define SPDIF_SIE_TXEM			((uint32_t)(1 << 1))

  7999. #define SPDIF_SIE_RXFIFOFUL		((uint32_t)(1 << 0))

  8000. #define SPDIF_SIS_LOCK			((uint32_t)(1 << 20))

  8001. #define SPDIF_SIS_TXUNOV		((uint32_t)(1 << 19))

  8002. #define SPDIF_SIS_TXRESYN		((uint32_t)(1 << 18))

  8003. #define SPDIF_SIS_CNEW			((uint32_t)(1 << 17))

  8004. #define SPDIF_SIS_VALNOGOOD		((uint32_t)(1 << 16))

  8005. #define SPDIF_SIS_SYMERR		((uint32_t)(1 << 15))

  8006. #define SPDIF_SIS_BITERR		((uint32_t)(1 << 14))

  8007. #define SPDIF_SIS_URXFUL		((uint32_t)(1 << 10))

  8008. #define SPDIF_SIS_URXOV			((uint32_t)(1 << 9))

  8009. #define SPDIF_SIS_QRXFUL		((uint32_t)(1 << 8))

  8010. #define SPDIF_SIS_QRXOV			((uint32_t)(1 << 7))

  8011. #define SPDIF_SIS_UQSYNC		((uint32_t)(1 << 6))

  8012. #define SPDIF_SIS_UQERR			((uint32_t)(1 << 5))

  8013. #define SPDIF_SIS_RXFIFOUNOV		((uint32_t)(1 << 4))

  8014. #define SPDIF_SIS_RXFIFORESYN		((uint32_t)(1 << 3))

  8015. #define SPDIF_SIS_LOCKLOSS		((uint32_t)(1 << 2))

  8016. #define SPDIF_SIS_TXEM			((uint32_t)(1 << 1))

  8017. #define SPDIF_SIS_RXFIFOFUL		((uint32_t)(1 << 0))

  8018. #define SPDIF_SIC_LOCK			((uint32_t)(1 << 20))

  8019. #define SPDIF_SIC_TXUNOV		((uint32_t)(1 << 19))

  8020. #define SPDIF_SIC_TXRESYN		((uint32_t)(1 << 18))

  8021. #define SPDIF_SIC_CNEW			((uint32_t)(1 << 17))

  8022. #define SPDIF_SIC_VALNOGOOD		((uint32_t)(1 << 16))

  8023. #define SPDIF_SIC_SYMERR		((uint32_t)(1 << 15))

  8024. #define SPDIF_SIC_BITERR		((uint32_t)(1 << 14))

  8025. #define SPDIF_SIC_URXFUL		((uint32_t)(1 << 10))

  8026. #define SPDIF_SIC_URXOV			((uint32_t)(1 << 9))

  8027. #define SPDIF_SIC_QRXOV			((uint32_t)(1 << 7))

  8028. #define SPDIF_SIC_UQSYNC		((uint32_t)(1 << 6))

  8029. #define SPDIF_SIC_UQERR			((uint32_t)(1 << 5))

  8030. #define SPDIF_SIC_RXFIFOUNOV		((uint32_t)(1 << 4))

  8031. #define SPDIF_SIC_RXFIFORESYN		((uint32_t)(1 << 3))

  8032. #define SPDIF_SIC_LOCKLOSS		((uint32_t)(1 << 2))

  8033. #define SPDIF_STC_SYSCLK_DF(n)		((uint32_t)(((n) & 0x1ff) << 11))

  8034. #define SPDIF_STC_TXCLK_SOURCE(n)	((uint32_t)(((n) & 0x07) << 8))

  8035. #define SPDIF_STC_TX_ALL_CLK_EN		((uint32_t)(1 << 7))

  8036. #define SPDIF_STC_TXCLK_DF(n)		((uint32_t)(((n) & 0x7f) << 0))

  8037. 

  8038. // 21.8: page 1284

  8039. #define IMXRT_SRC		(*(IMXRT_REGISTER32_t *)0x400F8000)

  8040. #define SRC_SCR				(IMXRT_SRC.offset000)

  8041. #define SRC_SBMR1			(IMXRT_SRC.offset004)

  8042. #define SRC_SRSR			(IMXRT_SRC.offset008)

  8043. #define SRC_SBMR2			(IMXRT_SRC.offset01C)

  8044. /* 

  8045. These register are used by the ROM code and should not be used by application software 

  8046. #define SRC_GPR1			(IMXRT_SRC.offset020) 

  8047. #define SRC_GPR2			(IMXRT_SRC.offset024)

  8048. #define SRC_GPR3			(IMXRT_SRC.offset028)

  8049. #define SRC_GPR4			(IMXRT_SRC.offset02C)

  8050. #define SRC_GPR5			(IMXRT_SRC.offset030)

  8051. #define SRC_GPR6			(IMXRT_SRC.offset034)

  8052. #define SRC_GPR7			(IMXRT_SRC.offset038)

  8053. #define SRC_GPR8			(IMXRT_SRC.offset03C)

  8054. #define SRC_GPR9			(IMXRT_SRC.offset040)

  8055. #define SRC_GPR10			(IMXRT_SRC.offset044)

  8056. */

  8057. #define SRC_SCR_MASK_WDOG3_RST(n)	((uint32_t)(((n) & 0x0f) << 28))

  8058. #define SRC_SCR_DBG_RST_MSK_PG		((uint32_t)(1 << 25))

  8059. #define SRC_SCR_CORE0_DBG_RST		((uint32_t)(1 << 17))

  8060. #define SRC_SCR_CORE0_RST		((uint32_t)(1 << 13))

  8061. #define SRC_SCR_MASK_WDOG_RST(n)	((uint32_t)(((n) & 0x0f) << 7))

  8062. #define SRC_SBMR1_BOOT_CFG4(n)		((uint32_t)(((n) & 0xff) << 24))

  8063. #define SRC_SBMR1_BOOT_CFG3(n)		((uint32_t)(((n) & 0xff) << 16))

  8064. #define SRC_SBMR1_BOOT_CFG2(n)		((uint32_t)(((n) & 0xff) << 8))

  8065. #define SRC_SBMR1_BOOT_CFG1(n)		((uint32_t)(((n) & 0xff) << 0))

  8066. #define SRC_SRSR_TEMPSENSE_RST_B	((uint32_t)(1 << 8))

  8067. #define SRC_SRSR_WDOG3_RST_B		((uint32_t)(1 << 7))

  8068. #define SRC_SRSR_JTAG_SW_RST		((uint32_t)(1 << 6))

  8069. #define SRC_SRSR_JTAG_RST_B		((uint32_t)(1 << 5))

  8070. #define SRC_SRSR_WDOG_RST_B		((uint32_t)(1 << 4))

  8071. #define SRC_SRSR_IPP_USER_RESET_B	((uint32_t)(1 << 3))

  8072. #define SRC_SRSR_CSU_RESET_B		((uint32_t)(1 << 2))

  8073. #define SRC_SRSR_LOCKUP_SYSRESETREQ	((uint32_t)(1 << 1))

  8074. #define SRC_SRSR_IPP_RESET_B		((uint32_t)(1 << 0))

  8075. #define SRC_SBMR2_BMOD(n)		((uint32_t)(((n) & 0x03) << 24))

  8076. #define SRC_SBMR2_BT_FUSE_SEL		((uint32_t)(1 << 4))

  8077. #define SRC_SBMR2_DIR_BT_DIS		((uint32_t)(1 << 3))

  8078. #define SRC_SBMR2_SEC_CONFIG(n)		((uint32_t)(((n) & 0x03) << 0))

  8079. 

  8080. // 19.4: page 1224

  8081. #define IMXRT_TEMPMON		(*(IMXRT_REGISTER32_t *)0x400D8180)

  8082. #define TEMPMON_TEMPSENSE0          (IMXRT_TEMPMON.offset000)

  8083. #define TEMPMON_TEMPSENSE0_SET		(IMXRT_TEMPMON.offset004)

  8084. #define TEMPMON_TEMPSENSE0_CLR		(IMXRT_TEMPMON.offset008)

  8085. #define TEMPMON_TEMPSENSE0_TOG		(IMXRT_TEMPMON.offset08c)

  8086. #define TEMPMON_TEMPSENSE1		    (IMXRT_TEMPMON.offset090)

  8087. #define TEMPMON_TEMPSENSE1_SET		(IMXRT_TEMPMON.offset094)

  8088. #define TEMPMON_TEMPSENSE1_CLR		(IMXRT_TEMPMON.offset098)

  8089. #define TEMPMON_TEMPSENSE1_TOG		(IMXRT_TEMPMON.offset09C)

  8090. #define TEMPMON_TEMPSENSE2		    (IMXRT_TEMPMON.offset110)

  8091. #define TEMPMON_TEMPSENSE2_SET		(IMXRT_TEMPMON.offset114)

  8092. #define TEMPMON_TEMPSENSE2_CLR		(IMXRT_TEMPMON.offset118)

  8093. #define TEMPMON_TEMPSENSE2_TOG		(IMXRT_TEMPMON.offset11C)

  8094. #define TEMPMON_CTRL0_ALARM_VALUE(n)	((uint32_t)(((n) & 0x0fff) << 20))

  8095. #define TEMPMON_CTRL0_TEMP_CNT(n)	((uint32_t)(((n) & 0x0fff) << 8))

  8096. #define TEMPMON_CTRL0_FINISHED		((uint32_t)(1 << 2))

  8097. #define TEMPMON_CTRL0_MEASURE_TEMP	((uint32_t)(1 << 1))

  8098. #define TEMPMON_CTRL0_POWER_DOWN	((uint32_t)(1 << 0))

  8099. #define TEMPMON_CTRL1_MEASURE_FREQ(n)	((uint32_t)(((n) & 0xffff) << 0))

  8100. #define TEMPMON_CTRL2_PANIC_ALARM_VALUE(n)	((uint32_t)(((n) & 0x0fff) << 16))

  8101. #define TEMPMON_CTRL2_LOW_ALARM_VALUE(n)	((uint32_t)(((n) & 0x0fff) << 0))

  8102. 

  8103. #define IMXRT_TRNG		(*(IMXRT_REGISTER32_t *)0x400CC000)

  8104. #define TRNG_MCTL			(IMXRT_TRNG.offset000)

  8105. #define TRNG_SCMISC			(IMXRT_TRNG.offset004)

  8106. #define TRNG_PKRRNG			(IMXRT_TRNG.offset008)

  8107. #define TRNG_PKRMAX			(IMXRT_TRNG.offset00C)

  8108. #define TRNG_PKRSQ			(IMXRT_TRNG.offset00C)

  8109. #define TRNG_SDCTL			(IMXRT_TRNG.offset010)

  8110. #define TRNG_SBLIM			(IMXRT_TRNG.offset014)

  8111. #define TRNG_TOTSAM			(IMXRT_TRNG.offset014)

  8112. #define TRNG_FRQMIN			(IMXRT_TRNG.offset018)

  8113. #define TRNG_FRQCNT			(IMXRT_TRNG.offset01C)

  8114. #define TRNG_FRQMAX			(IMXRT_TRNG.offset01C)

  8115. #define TRNG_SCMC			(IMXRT_TRNG.offset020)

  8116. #define TRNG_SCML			(IMXRT_TRNG.offset020)

  8117. #define TRNG_SCR1C			(IMXRT_TRNG.offset024)

  8118. #define TRNG_SCR1L			(IMXRT_TRNG.offset024)

  8119. #define TRNG_SCR2C			(IMXRT_TRNG.offset028)

  8120. #define TRNG_SCR2L			(IMXRT_TRNG.offset028)

  8121. #define TRNG_SCR3C			(IMXRT_TRNG.offset02C)

  8122. #define TRNG_SCR3L			(IMXRT_TRNG.offset02C)

  8123. #define TRNG_SCR4C			(IMXRT_TRNG.offset030)

  8124. #define TRNG_SCR4L			(IMXRT_TRNG.offset030)

  8125. #define TRNG_SCR5C			(IMXRT_TRNG.offset034)

  8126. #define TRNG_SCR5L			(IMXRT_TRNG.offset034)

  8127. #define TRNG_SCR6PC			(IMXRT_TRNG.offset038)

  8128. #define TRNG_SCR6PL			(IMXRT_TRNG.offset038)

  8129. #define TRNG_STATUS			(IMXRT_TRNG.offset03C)

  8130. #define TRNG_ENT0			(IMXRT_TRNG.offset040)

  8131. #define TRNG_ENT1			(IMXRT_TRNG.offset044)

  8132. #define TRNG_ENT2			(IMXRT_TRNG.offset048)

  8133. #define TRNG_ENT3			(IMXRT_TRNG.offset04C)

  8134. #define TRNG_ENT4			(IMXRT_TRNG.offset050)

  8135. #define TRNG_ENT5			(IMXRT_TRNG.offset054)

  8136. #define TRNG_ENT6			(IMXRT_TRNG.offset058)

  8137. #define TRNG_ENT7			(IMXRT_TRNG.offset05C)

  8138. #define TRNG_ENT8			(IMXRT_TRNG.offset060)

  8139. #define TRNG_ENT9			(IMXRT_TRNG.offset064)

  8140. #define TRNG_ENT10			(IMXRT_TRNG.offset068)

  8141. #define TRNG_ENT11			(IMXRT_TRNG.offset06C)

  8142. #define TRNG_ENT12			(IMXRT_TRNG.offset070)

  8143. #define TRNG_ENT13			(IMXRT_TRNG.offset074)

  8144. #define TRNG_ENT14			(IMXRT_TRNG.offset078)

  8145. #define TRNG_ENT15			(IMXRT_TRNG.offset07C)

  8146. #define TRNG_PKRCNT10			(IMXRT_TRNG.offset080)

  8147. #define TRNG_PKRCNT32			(IMXRT_TRNG.offset084)

  8148. #define TRNG_PKRCNT54			(IMXRT_TRNG.offset088)

  8149. #define TRNG_PKRCNT76			(IMXRT_TRNG.offset08C)

  8150. #define TRNG_PKRCNT98			(IMXRT_TRNG.offset090)

  8151. #define TRNG_PKRCNTBA			(IMXRT_TRNG.offset094)

  8152. #define TRNG_PKRCNTDC			(IMXRT_TRNG.offset098)

  8153. #define TRNG_PKRCNTFE			(IMXRT_TRNG.offset09C)

  8154. #define TRNG_SEC_CFG			(IMXRT_TRNG.offset0A0)

  8155. #define TRNG_INT_CTRL			(IMXRT_TRNG.offset0A4)

  8156. #define TRNG_INT_MASK			(IMXRT_TRNG.offset0A8)

  8157. #define TRNG_INT_STATUS			(IMXRT_TRNG.offset0AC)

  8158. #define TRNG_VID1			(IMXRT_TRNG.offset0F0)

  8159. #define TRNG_MCTL_PRGM			((uint32_t)(1 << 16))

  8160. #define TRNG_MCTL_LRUN_CONT		((uint32_t)(1 << 14))

  8161. #define TRNG_MCTL_TSTOP_OK		((uint32_t)(1 << 13))

  8162. #define TRNG_MCTL_ERR			((uint32_t)(1 << 12))

  8163. #define TRNG_MCTL_TST_OUT		((uint32_t)(1 << 11))

  8164. #define TRNG_MCTL_ENT_VAL		((uint32_t)(1 << 10))

  8165. #define TRNG_MCTL_FCT_VAL		((uint32_t)(1 << 9))

  8166. #define TRNG_MCTL_FCT_FAIL		((uint32_t)(1 << 8))

  8167. #define TRNG_MCTL_FOR_SCLK		((uint32_t)(1 << 7))

  8168. #define TRNG_MCTL_RST_DEF		((uint32_t)(1 << 6))

  8169. #define TRNG_MCTL_TRNG_ACC		((uint32_t)(1 << 5))

  8170. #define TRNG_MCTL_OSC_DIV(n)		((uint32_t)(((n) & 0x03) << 2))

  8171. #define TRNG_MCTL_SAMP_MODE(n)		((uint32_t)(((n) & 0x03) << 0))

  8172. #define TRNG_SCMISC_RTY_CT(n)		((uint32_t)(((n) & 0x0F) << 16))

  8173. #define TRNG_SCMISC_LRUN_MAX(n)		((uint32_t)(((n) & 0xFF) << 0))

  8174. #define TRNG_SDCTL_ENT_DLY(n)		((uint32_t)(((n) & 0xFFFF) << 16))

  8175. #define TRNG_SDCTL_SAMP_SIZE(n)		((uint32_t)(((n) & 0xFFFF) << 0))

  8176. #define TRNG_SCML_MONO_RNG(n)		((uint32_t)(((n) & 0xFFFF) << 16))

  8177. #define TRNG_SCML_MONO_MAX(n)		((uint32_t)(((n) & 0xFFFF) << 0))

  8178. #define TRNG_SCR1L_RUN1_RNG(n)		((uint32_t)(((n) & 0x7FFF) << 16))

  8179. #define TRNG_SCR1L_RUN1_MAX(n)		((uint32_t)(((n) & 0x7FFF) << 0))

  8180. #define TRNG_SCR2L_RUN2_RNG(n)		((uint32_t)(((n) & 0x3FFF) << 16))

  8181. #define TRNG_SCR2L_RUN2_MAX(n)		((uint32_t)(((n) & 0x3FFF) << 0))

  8182. #define TRNG_SCR3L_RUN3_RNG(n)		((uint32_t)(((n) & 0x1FFF) << 16))

  8183. #define TRNG_SCR3L_RUN3_MAX(n)		((uint32_t)(((n) & 0x1FFF) << 0))

  8184. #define TRNG_SCR4L_RUN4_RNG(n)		((uint32_t)(((n) & 0x0FFF) << 16))

  8185. #define TRNG_SCR4L_RUN4_MAX(n)		((uint32_t)(((n) & 0x0FFF) << 0))

  8186. #define TRNG_SCR5L_RUN5_RNG(n)		((uint32_t)(((n) & 0x07FF) << 16))

  8187. #define TRNG_SCR5L_RUN5_MAX(n)		((uint32_t)(((n) & 0x07FF) << 0))

  8188. #define TRNG_SCR6PL_RUN6P_RNG(n)	((uint32_t)(((n) & 0x07FF) << 16))

  8189. #define TRNG_SCR6PL_RUN6P_MAX(n)	((uint32_t)(((n) & 0x07FF) << 0))

  8190. // defaults from NXP's SDK (fsl_trng.c)

  8191. #define TRNG_DEFAULT_ENTROPY_DELAY	3200

  8192. #define TRNG_DEFAULT_SAMPLE_SIZE	2500

  8193. #define TRNG_DEFAULT_SPARSE_BIT_LIMIT	63

  8194. #define TRNG_DEFAULT_RETRY_COUNT	1

  8195. #define TRNG_DEFAULT_RUN_MAX_LIMIT	34

  8196. #define TRNG_DEFAULT_MONOBIT_MAXIMUM	1384

  8197. #define TRNG_DEFAULT_MONOBIT_MINIMUM	(TRNG_DEFAULT_MONOBIT_MAXIMUM - 268)

  8198. #define TRNG_DEFAULT_RUNBIT1_MAXIMUM	405

  8199. #define TRNG_DEFAULT_RUNBIT1_MINIMUM	(TRNG_DEFAULT_RUNBIT1_MAXIMUM - 178)

  8200. #define TRNG_DEFAULT_RUNBIT2_MAXIMUM	220

  8201. #define TRNG_DEFAULT_RUNBIT2_MINIMUM	(TRNG_DEFAULT_RUNBIT2_MAXIMUM - 122)

  8202. #define TRNG_DEFAULT_RUNBIT3_MAXIMUM	125

  8203. #define TRNG_DEFAULT_RUNBIT3_MINIMUM	(TRNG_DEFAULT_RUNBIT3_MAXIMUM - 88)

  8204. #define TRNG_DEFAULT_RUNBIT4_MAXIMUM	75

  8205. #define TRNG_DEFAULT_RUNBIT4_MINIMUM	(TRNG_DEFAULT_RUNBIT4_MAXIMUM - 64)

  8206. #define TRNG_DEFAULT_RUNBIT5_MAXIMUM	47

  8207. #define TRNG_DEFAULT_RUNBIT5_MINIMUM	(TRNG_DEFAULT_RUNBIT5_MAXIMUM - 46)

  8208. #define TRNG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47

  8209. #define TRNG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46)

  8210. #define TRNG_DEFAULT_POKER_MAXIMUM	26912

  8211. #define TRNG_DEFAULT_POKER_MINIMUM	(TRNG_DEFAULT_POKER_MAXIMUM - 2467)

  8212. #define TRNG_DEFAULT_FREQUENCY_MAXIMUM	25600

  8213. #define TRNG_DEFAULT_FREQUENCY_MINIMUM	1600

  8214. 

  8215. 

  8216. // 68.4: page 3406

  8217. #define IMXRT_TSC		(*(IMXRT_REGISTER32_t *)0x400E0000)

  8218. #define TSC_BASIC_SETTING		(IMXRT_TSC.offset000)

  8219. #define TSC_PS_INPUT_BUFFER_ADDR	(IMXRT_TSC.offset010)

  8220. #define TSC_FLOW_CONTROL		(IMXRT_TSC.offset020)

  8221. #define TSC_MEASEURE_VALUE		(IMXRT_TSC.offset030)

  8222. #define TSC_INT_EN			(IMXRT_TSC.offset040)

  8223. #define TSC_INT_SIG_EN			(IMXRT_TSC.offset050)

  8224. #define TSC_INT_STATUS			(IMXRT_TSC.offset060)

  8225. #define TSC_DEBUG_MODE			(IMXRT_TSC.offset070)

  8226. #define TSC_DEBUG_MODE2			(IMXRT_TSC.offset080)

  8227. 

  8228. // 42.5.1.1: page 2212

  8229. #define IMXRT_USB1		(*(IMXRT_REGISTER32_t *)0x402E0000)

  8230. #define USB1_ID				(IMXRT_USB1.offset000)

  8231. #define USB1_HWGENERAL			(IMXRT_USB1.offset004)

  8232. #define USB1_HWHOST			(IMXRT_USB1.offset008)

  8233. #define USB1_HWDEVICE			(IMXRT_USB1.offset00C)

  8234. #define USB1_HWTXBUF			(IMXRT_USB1.offset010)

  8235. #define USB1_HWRXBUF			(IMXRT_USB1.offset014)

  8236. #define USB1_GPTIMER0LD			(IMXRT_USB1.offset080)

  8237. #define USB1_GPTIMER0CTRL		(IMXRT_USB1.offset084)

  8238. #define USB1_GPTIMER1LD			(IMXRT_USB1.offset088)

  8239. #define USB1_GPTIMER1CTRL		(IMXRT_USB1.offset08C)

  8240. #define USB1_SBUSCFG			(IMXRT_USB1.offset090)

  8241. #define USB1_HCIVERSION			(IMXRT_USB1.offset100)

  8242. #define USB1_HCSPARAMS			(IMXRT_USB1.offset104)

  8243. #define USB1_HCCPARAMS			(IMXRT_USB1.offset108)

  8244. #define USB1_DCIVERSION			(IMXRT_USB1.offset120)

  8245. #define USB1_DCCPARAMS			(IMXRT_USB1.offset124)

  8246. #define USB1_USBCMD			(IMXRT_USB1.offset140)

  8247. #define USB1_USBSTS			(IMXRT_USB1.offset144)

  8248. #define USB1_USBINTR			(IMXRT_USB1.offset148)

  8249. #define USB1_FRINDEX			(IMXRT_USB1.offset14C)

  8250. #define USB1_PERIODICLISTBASE		(IMXRT_USB1.offset154)

  8251. #define USB1_DEVICEADDR			(IMXRT_USB1.offset154)

  8252. #define USB1_ASYNCLISTADDR		(IMXRT_USB1.offset158)

  8253. #define USB1_ENDPOINTLISTADDR		(IMXRT_USB1.offset158)

  8254. #define USB1_BURSTSIZE			(IMXRT_USB1.offset160)

  8255. #define USB1_TXFILLTUNING		(IMXRT_USB1.offset164)

  8256. #define USB1_ENDPTNAK			(IMXRT_USB1.offset178)

  8257. #define USB1_ENDPTNAKEN			(IMXRT_USB1.offset17C)

  8258. #define USB1_CONFIGFLAG			(IMXRT_USB1.offset180)

  8259. #define USB1_PORTSC1			(IMXRT_USB1.offset184)

  8260. #define USB1_OTGSC			(IMXRT_USB1.offset1A4)

  8261. #define USB1_USBMODE			(IMXRT_USB1.offset1A8)

  8262. #define USB1_ENDPTSETUPSTAT		(IMXRT_USB1.offset1AC)

  8263. #define USB1_ENDPTPRIME			(IMXRT_USB1.offset1B0)

  8264. #define USB1_ENDPTFLUSH			(IMXRT_USB1.offset1B4)

  8265. #define USB1_ENDPTSTATUS		(IMXRT_USB1.offset1B8)

  8266. #define USB1_ENDPTCOMPLETE		(IMXRT_USB1.offset1BC)

  8267. #define USB1_ENDPTCTRL0			(IMXRT_USB1.offset1C0)

  8268. #define USB1_ENDPTCTRL1			(IMXRT_USB1.offset1C4)

  8269. #define USB1_ENDPTCTRL2			(IMXRT_USB1.offset1C8)

  8270. #define USB1_ENDPTCTRL3			(IMXRT_USB1.offset1CC)

  8271. #define USB1_ENDPTCTRL4			(IMXRT_USB1.offset1D0)

  8272. #define USB1_ENDPTCTRL5			(IMXRT_USB1.offset1D4)

  8273. #define USB1_ENDPTCTRL6			(IMXRT_USB1.offset1D8)

  8274. #define USB1_ENDPTCTRL7			(IMXRT_USB1.offset1DC)

  8275. #define IMXRT_USB2		(*(IMXRT_REGISTER32_t *)0x402E0200)

  8276. #define USB2_ID				(IMXRT_USB2.offset000)

  8277. #define USB2_HWGENERAL			(IMXRT_USB2.offset004)

  8278. #define USB2_HWHOST			(IMXRT_USB2.offset008)

  8279. #define USB2_HWDEVICE			(IMXRT_USB2.offset00C)

  8280. #define USB2_HWTXBUF			(IMXRT_USB2.offset010)

  8281. #define USB2_HWRXBUF			(IMXRT_USB2.offset014)

  8282. #define USB2_GPTIMER0LD			(IMXRT_USB2.offset080)

  8283. #define USB2_GPTIMER0CTRL		(IMXRT_USB2.offset084)

  8284. #define USB2_GPTIMER1LD			(IMXRT_USB2.offset088)

  8285. #define USB2_GPTIMER1CTRL		(IMXRT_USB2.offset08C)

  8286. #define USB2_SBUSCFG			(IMXRT_USB2.offset090)

  8287. #define USB2_HCIVERSION			(IMXRT_USB2.offset100)

  8288. #define USB2_HCSPARAMS			(IMXRT_USB2.offset104)

  8289. #define USB2_HCCPARAMS			(IMXRT_USB2.offset108)

  8290. #define USB2_DCIVERSION			(IMXRT_USB2.offset120)

  8291. #define USB2_DCCPARAMS			(IMXRT_USB2.offset124)

  8292. #define USB2_USBCMD			(IMXRT_USB2.offset140)

  8293. #define USB2_USBSTS			(IMXRT_USB2.offset144)

  8294. #define USB2_USBINTR			(IMXRT_USB2.offset148)

  8295. #define USB2_FRINDEX			(IMXRT_USB2.offset14C)

  8296. #define USB2_PERIODICLISTBASE		(IMXRT_USB2.offset154)

  8297. #define USB2_DEVICEADDR			(IMXRT_USB2.offset154)

  8298. #define USB2_ASYNCLISTADDR		(IMXRT_USB2.offset158)

  8299. #define USB2_ENDPOINTLISTADDR		(IMXRT_USB2.offset158)

  8300. #define USB2_BURSTSIZE			(IMXRT_USB2.offset160)

  8301. #define USB2_TXFILLTUNING		(IMXRT_USB2.offset164)

  8302. #define USB2_ENDPTNAK			(IMXRT_USB2.offset178)

  8303. #define USB2_ENDPTNAKEN			(IMXRT_USB2.offset17C)

  8304. #define USB2_CONFIGFLAG			(IMXRT_USB2.offset180)

  8305. #define USB2_PORTSC1			(IMXRT_USB2.offset184)

  8306. #define USB2_OTGSC			(IMXRT_USB2.offset1A4)

  8307. #define USB2_USBMODE			(IMXRT_USB2.offset1A8)

  8308. #define USB2_ENDPTSETUPSTAT		(IMXRT_USB2.offset1AC)

  8309. #define USB2_ENDPTPRIME			(IMXRT_USB2.offset1B0)

  8310. #define USB2_ENDPTFLUSH			(IMXRT_USB2.offset1B4)

  8311. #define USB2_ENDPTSTATUS		(IMXRT_USB2.offset1B8)

  8312. #define USB2_ENDPTCOMPLETE		(IMXRT_USB2.offset1BC)

  8313. #define USB2_ENDPTCTRL0			(IMXRT_USB2.offset1C0)

  8314. #define USB2_ENDPTCTRL1			(IMXRT_USB2.offset1C4)

  8315. #define USB2_ENDPTCTRL2			(IMXRT_USB2.offset1C8)

  8316. #define USB2_ENDPTCTRL3			(IMXRT_USB2.offset1CC)

  8317. #define USB2_ENDPTCTRL4			(IMXRT_USB2.offset1D0)

  8318. #define USB2_ENDPTCTRL5			(IMXRT_USB2.offset1D4)

  8319. #define USB2_ENDPTCTRL6			(IMXRT_USB2.offset1D8)

  8320. #define USB2_ENDPTCTRL7			(IMXRT_USB2.offset1DC)

  8321. #define USB_USBCMD_ITC(n)			((uint32_t)(((n) & 0xFF) << 16))

  8322. #define USB_USBCMD_FS_2				((uint32_t)(1<<15))

  8323. #define USB_USBCMD_ATDTW			((uint32_t)(1<<14))

  8324. #define USB_USBCMD_SUTW				((uint32_t)(1<<13))

  8325. #define USB_USBCMD_ASPE				((uint32_t)(1<<11))

  8326. #define USB_USBCMD_ASP(n)			((uint32_t)(((n) & 0x03) << 8))

  8327. #define USB_USBCMD_IAA				((uint32_t)(1<<6))

  8328. #define USB_USBCMD_ASE				((uint32_t)(1<<5))

  8329. #define USB_USBCMD_PSE				((uint32_t)(1<<4))

  8330. #define USB_USBCMD_FS_1(n)			((uint32_t)(((n) & 0x03) << 2))

  8331. #define USB_USBCMD_RST				((uint32_t)(1<<1))

  8332. #define USB_USBCMD_RS				((uint32_t)(1<<0))

  8333. #define USB_USBSTS_TI1				((uint32_t)(1<<25))

  8334. #define USB_USBSTS_TI0				((uint32_t)(1<<24))

  8335. #define USB_USBSTS_NAKI				((uint32_t)(1<<16))

  8336. #define USB_USBSTS_AS				((uint32_t)(1<<15))

  8337. #define USB_USBSTS_PS				((uint32_t)(1<<14))

  8338. #define USB_USBSTS_RCL				((uint32_t)(1<<13))

  8339. #define USB_USBSTS_HCH				((uint32_t)(1<<12))

  8340. #define USB_USBSTS_ULPII			((uint32_t)(1<<10))

  8341. #define USB_USBSTS_SLI				((uint32_t)(1<<8))

  8342. #define USB_USBSTS_SRI				((uint32_t)(1<<7))

  8343. #define USB_USBSTS_URI				((uint32_t)(1<<6))

  8344. #define USB_USBSTS_AAI				((uint32_t)(1<<5))

  8345. #define USB_USBSTS_SEI				((uint32_t)(1<<4))

  8346. #define USB_USBSTS_FRI				((uint32_t)(1<<3))

  8347. #define USB_USBSTS_PCI				((uint32_t)(1<<2))

  8348. #define USB_USBSTS_UEI				((uint32_t)(1<<1))

  8349. #define USB_USBSTS_UI				((uint32_t)(1<<0))

  8350. #define USB_USBINTR_TIE1			((uint32_t)(1<<25))

  8351. #define USB_USBINTR_TIE0			((uint32_t)(1<<24))

  8352. #define USB_USBINTR_UPIE			((uint32_t)(1<<19))

  8353. #define USB_USBINTR_UAIE			((uint32_t)(1<<18))

  8354. #define USB_USBINTR_NAKE			((uint32_t)(1<<16))

  8355. #define USB_USBINTR_ULPIE			((uint32_t)(1<<10))

  8356. #define USB_USBINTR_SLE				((uint32_t)(1<<8))

  8357. #define USB_USBINTR_SRE				((uint32_t)(1<<7))

  8358. #define USB_USBINTR_URE				((uint32_t)(1<<6))

  8359. #define USB_USBINTR_AAE				((uint32_t)(1<<5))

  8360. #define USB_USBINTR_SEE				((uint32_t)(1<<4))

  8361. #define USB_USBINTR_FRE				((uint32_t)(1<<3))

  8362. #define USB_USBINTR_PCE				((uint32_t)(1<<2))

  8363. #define USB_USBINTR_UEE				((uint32_t)(1<<1))

  8364. #define USB_USBINTR_UE				((uint32_t)(1<<0))

  8365. #define USB_DEVICEADDR_USBADR(n)		((uint32_t)(((n) & 0x7F) << 25))

  8366. #define USB_DEVICEADDR_USBADRA			((uint32_t)(1<<24))

  8367. #define USB_PORTSC1_PTS_1(n)			((uint32_t)(((n) & 0x03) << 30))

  8368. #define USB_PORTSC1_STS				((uint32_t)(1<<29))

  8369. #define USB_PORTSC1_PTW				((uint32_t)(1<<28))

  8370. #define USB_PORTSC1_PSPD(n)			((uint32_t)(((n) & 0x03) << 26))

  8371. #define USB_PORTSC1_PTS_2			((uint32_t)(1<<25))

  8372. #define USB_PORTSC1_PFSC			((uint32_t)(1<<24))

  8373. #define USB_PORTSC1_PHCD			((uint32_t)(1<<23))

  8374. #define USB_PORTSC1_WKOC			((uint32_t)(1<<22))

  8375. #define USB_PORTSC1_WKDC			((uint32_t)(1<<21))

  8376. #define USB_PORTSC1_WKCN			((uint32_t)(1<<20))

  8377. #define USB_PORTSC1_PTC(n)			((uint32_t)(((n) & 0x0F) << 16))

  8378. #define USB_PORTSC1_PIC(n)			((uint32_t)(((n) & 0x03) << 14))

  8379. #define USB_PORTSC1_PO				((uint32_t)(1<<13))

  8380. #define USB_PORTSC1_PP				((uint32_t)(1<<12))

  8381. #define USB_PORTSC1_LS(n)			((uint32_t)(((n) & 0x03) << 10))

  8382. #define USB_PORTSC1_HSP				((uint32_t)(1<<9))

  8383. #define USB_PORTSC1_PR				((uint32_t)(1<<8))

  8384. #define USB_PORTSC1_SUSP			((uint32_t)(1<<7))

  8385. #define USB_PORTSC1_FPR				((uint32_t)(1<<6))

  8386. #define USB_PORTSC1_OCC				((uint32_t)(1<<5))

  8387. #define USB_PORTSC1_OCA				((uint32_t)(1<<4))

  8388. #define USB_PORTSC1_PEC				((uint32_t)(1<<3))

  8389. #define USB_PORTSC1_PE				((uint32_t)(1<<2))

  8390. #define USB_PORTSC1_CSC				((uint32_t)(1<<1))

  8391. #define USB_PORTSC1_CCS				((uint32_t)(1<<0))

  8392. #define USB_USBMODE_SDIS			((uint32_t)(1<<4))

  8393. #define USB_USBMODE_SLOM			((uint32_t)(1<<3))

  8394. #define USB_USBMODE_ES				((uint32_t)(1<<2))

  8395. #define USB_USBMODE_CM(n)			((uint32_t)(((n) & 0x03) << 0))

  8396. #define USB_USBMODE_CM_MASK			USB_USBMODE_CM(3)

  8397. #define USB_ENDPTCTRL_TXE			((uint32_t)(1<<23))

  8398. #define USB_ENDPTCTRL_TXR			((uint32_t)(1<<22))

  8399. #define USB_ENDPTCTRL_TXI			((uint32_t)(1<<21))

  8400. #define USB_ENDPTCTRL_TXT(n)			((uint32_t)(((n) & 0x03) << 18))

  8401. #define USB_ENDPTCTRL_TXD			((uint32_t)(1<<17))

  8402. #define USB_ENDPTCTRL_TXS			((uint32_t)(1<<16))

  8403. #define USB_ENDPTCTRL_RXE			((uint32_t)(1<<7))

  8404. #define USB_ENDPTCTRL_RXR			((uint32_t)(1<<6))

  8405. #define USB_ENDPTCTRL_RXI			((uint32_t)(1<<5))

  8406. #define USB_ENDPTCTRL_RXT(n)			((uint32_t)(((n) & 0x03) << 2))

  8407. #define USB_ENDPTCTRL_RXD			((uint32_t)(1<<1))

  8408. #define USB_ENDPTCTRL_RXS			((uint32_t)(1<<0))

  8409. #define USB_GPTIMERCTRL_GPTRUN			((uint32_t)(1<<31))

  8410. #define USB_GPTIMERCTRL_GPTRST			((uint32_t)(1<<30))

  8411. #define USB_GPTIMERCTRL_GPTMODE			((uint32_t)(1<<24))

  8412. #define USB_GPTIMERCTRL_GPTCNT(n)		((uint32_t)(((n) & 0xFFFFFF) << 0))

  8413. 

  8414. // 43.3: page 2474

  8415. #define IMXRT_USBPHY1		(*(IMXRT_REGISTER32_t *)0x400D9000)

  8416. #define USBPHY1_PWD			(IMXRT_USBPHY1.offset000)

  8417. #define USBPHY1_PWD_SET			(IMXRT_USBPHY1.offset004)

  8418. #define USBPHY1_PWD_CLR			(IMXRT_USBPHY1.offset008)

  8419. #define USBPHY1_PWD_TOG			(IMXRT_USBPHY1.offset00C)

  8420. #define USBPHY1_TX			(IMXRT_USBPHY1.offset010)

  8421. #define USBPHY1_TX_SET			(IMXRT_USBPHY1.offset014)

  8422. #define USBPHY1_TX_CLR			(IMXRT_USBPHY1.offset018)

  8423. #define USBPHY1_TX_TOG			(IMXRT_USBPHY1.offset01C)

  8424. #define USBPHY1_RX			(IMXRT_USBPHY1.offset020)

  8425. #define USBPHY1_RX_SET			(IMXRT_USBPHY1.offset024)

  8426. #define USBPHY1_RX_CLR			(IMXRT_USBPHY1.offset028)

  8427. #define USBPHY1_RX_TOG			(IMXRT_USBPHY1.offset02C)

  8428. #define USBPHY1_CTRL			(IMXRT_USBPHY1.offset030)

  8429. #define USBPHY1_CTRL_SET		(IMXRT_USBPHY1.offset034)

  8430. #define USBPHY1_CTRL_CLR		(IMXRT_USBPHY1.offset038)

  8431. #define USBPHY1_CTRL_TOG		(IMXRT_USBPHY1.offset03C)

  8432. #define USBPHY1_STATUS			(IMXRT_USBPHY1.offset040)

  8433. #define USBPHY1_DEBUG			(IMXRT_USBPHY1.offset050)

  8434. #define USBPHY1_DEBUG_SET		(IMXRT_USBPHY1.offset054)

  8435. #define USBPHY1_DEBUG_CLR		(IMXRT_USBPHY1.offset058)

  8436. #define USBPHY1_DEBUG_TOG		(IMXRT_USBPHY1.offset05C)

  8437. #define USBPHY1_DEBUG0_STATUS		(IMXRT_USBPHY1.offset060)

  8438. #define USBPHY1_DEBUG1			(IMXRT_USBPHY1.offset070)

  8439. #define USBPHY1_DEBUG1_SET		(IMXRT_USBPHY1.offset074)

  8440. #define USBPHY1_DEBUG1_CLR		(IMXRT_USBPHY1.offset078)

  8441. #define USBPHY1_DEBUG1_TOG		(IMXRT_USBPHY1.offset07C)

  8442. #define USBPHY1_VERSION			(IMXRT_USBPHY1.offset080)

  8443. #define IMXRT_USBPHY2		(*(IMXRT_REGISTER32_t *)0x400DA000)

  8444. #define USBPHY2_PWD			(IMXRT_USBPHY2.offset000)

  8445. #define USBPHY2_PWD_SET			(IMXRT_USBPHY2.offset004)

  8446. #define USBPHY2_PWD_CLR			(IMXRT_USBPHY2.offset008)

  8447. #define USBPHY2_PWD_TOG			(IMXRT_USBPHY2.offset00C)

  8448. #define USBPHY2_TX			(IMXRT_USBPHY2.offset010)

  8449. #define USBPHY2_TX_SET			(IMXRT_USBPHY2.offset014)

  8450. #define USBPHY2_TX_CLR			(IMXRT_USBPHY2.offset018)

  8451. #define USBPHY2_TX_TOG			(IMXRT_USBPHY2.offset01C)

  8452. #define USBPHY2_RX			(IMXRT_USBPHY2.offset020)

  8453. #define USBPHY2_RX_SET			(IMXRT_USBPHY2.offset024)

  8454. #define USBPHY2_RX_CLR			(IMXRT_USBPHY2.offset028)

  8455. #define USBPHY2_RX_TOG			(IMXRT_USBPHY2.offset02C)

  8456. #define USBPHY2_CTRL			(IMXRT_USBPHY2.offset030)

  8457. #define USBPHY2_CTRL_SET		(IMXRT_USBPHY2.offset034)

  8458. #define USBPHY2_CTRL_CLR		(IMXRT_USBPHY2.offset038)

  8459. #define USBPHY2_CTRL_TOG		(IMXRT_USBPHY2.offset03C)

  8460. #define USBPHY2_STATUS			(IMXRT_USBPHY2.offset040)

  8461. #define USBPHY2_DEBUG			(IMXRT_USBPHY2.offset050)

  8462. #define USBPHY2_DEBUG_SET		(IMXRT_USBPHY2.offset054)

  8463. #define USBPHY2_DEBUG_CLR		(IMXRT_USBPHY2.offset058)

  8464. #define USBPHY2_DEBUG_TOG		(IMXRT_USBPHY2.offset05C)

  8465. #define USBPHY2_DEBUG0_STATUS		(IMXRT_USBPHY2.offset060)

  8466. #define USBPHY2_DEBUG1			(IMXRT_USBPHY2.offset070)

  8467. #define USBPHY2_DEBUG1_SET		(IMXRT_USBPHY2.offset074)

  8468. #define USBPHY2_DEBUG1_CLR		(IMXRT_USBPHY2.offset078)

  8469. #define USBPHY2_DEBUG1_TOG		(IMXRT_USBPHY2.offset07C)

  8470. #define USBPHY2_VERSION			(IMXRT_USBPHY2.offset080)

  8471. #define USBPHY_PWD_RXPWDRX			((uint32_t)(1<<20))

  8472. #define USBPHY_PWD_RXPWDDIFF			((uint32_t)(1<<19))

  8473. #define USBPHY_PWD_RXPWD1PT1			((uint32_t)(1<<18))

  8474. #define USBPHY_PWD_RXPWDENV			((uint32_t)(1<<17))

  8475. #define USBPHY_PWD_TXPWDV2I			((uint32_t)(1<<12))

  8476. #define USBPHY_PWD_TXPWDIBIAS			((uint32_t)(1<<11))

  8477. #define USBPHY_PWD_TXPWDFS			((uint32_t)(1<<10))

  8478. #define USBPHY_TX_USBPHY_TX_EDGECTRL(n)		((uint32_t)(((n) & 0x07) << 26))

  8479. #define USBPHY_TX_TXCAL45DP(n)			((uint32_t)(((n) & 0x0F) << 16))

  8480. #define USBPHY_TX_TXCAL45DN(n)			((uint32_t)(((n) & 0x0F) << 8))

  8481. #define USBPHY_TX_D_CAL(n)			((uint32_t)(((n) & 0x0F) << 0))

  8482. #define USBPHY_RX_RXDBYPASS			((uint32_t)(1<<22))

  8483. #define USBPHY_RX_DISCONADJ(n)			((uint32_t)(((n) & 0x07) << 4))

  8484. #define USBPHY_RX_ENVADJ(n)			((uint32_t)(((n) & 0x07) << 0))

  8485. #define USBPHY_CTRL_SFTRST			((uint32_t)(1<<31))

  8486. #define USBPHY_CTRL_CLKGATE			((uint32_t)(1<<30))

  8487. #define USBPHY_CTRL_UTMI_SUSPENDM		((uint32_t)(1<<29))

  8488. #define USBPHY_CTRL_HOST_FORCE_LS_SE0		((uint32_t)(1<<28))

  8489. #define USBPHY_CTRL_OTG_ID_VALUE		((uint32_t)(1<<27))

  8490. #define USBPHY_CTRL_FSDLL_RST_EN		((uint32_t)(1<<24))

  8491. #define USBPHY_CTRL_ENVBUSCHG_WKUP		((uint32_t)(1<<23))

  8492. #define USBPHY_CTRL_ENIDCHG_WKUP		((uint32_t)(1<<22))

  8493. #define USBPHY_CTRL_ENDPDMCHG_WKUP		((uint32_t)(1<<21))

  8494. #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD		((uint32_t)(1<<20))

  8495. #define USBPHY_CTRL_ENAUTOCLR_CLKGATE		((uint32_t)(1<<19))

  8496. #define USBPHY_CTRL_ENAUTO_PWRON_PLL		((uint32_t)(1<<18))

  8497. #define USBPHY_CTRL_WAKEUP_IRQ			((uint32_t)(1<<17))

  8498. #define USBPHY_CTRL_ENIRQWAKEUP			((uint32_t)(1<<16))

  8499. #define USBPHY_CTRL_ENUTMILEVEL3		((uint32_t)(1<<15))

  8500. #define USBPHY_CTRL_ENUTMILEVEL2		((uint32_t)(1<<14))

  8501. #define USBPHY_CTRL_DATA_ON_LRADC		((uint32_t)(1<<13))

  8502. #define USBPHY_CTRL_DEVPLUGIN_IRQ		((uint32_t)(1<<12))

  8503. #define USBPHY_CTRL_ENIRQDEVPLUGIN		((uint32_t)(1<<11))

  8504. #define USBPHY_CTRL_RESUME_IRQ			((uint32_t)(1<<10))

  8505. #define USBPHY_CTRL_ENIRQRESUMEDETECT		((uint32_t)(1<<9))

  8506. #define USBPHY_CTRL_RESUMEIRQSTICKY		((uint32_t)(1<<8))

  8507. #define USBPHY_CTRL_ENOTGIDDETECT		((uint32_t)(1<<7))

  8508. #define USBPHY_CTRL_OTG_ID_CHG_IRQ		((uint32_t)(1<<6))

  8509. #define USBPHY_CTRL_DEVPLUGIN_POLARITY		((uint32_t)(1<<5))

  8510. #define USBPHY_CTRL_ENDEVPLUGINDETECT		((uint32_t)(1<<4))

  8511. #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ	((uint32_t)(1<<3))

  8512. #define USBPHY_CTRL_ENIRQHOSTDISCON		((uint32_t)(1<<2))

  8513. #define USBPHY_CTRL_ENHOSTDISCONDETECT		((uint32_t)(1<<1))

  8514. #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ		((uint32_t)(1<<0))

  8515. 

  8516. // 26.9.1.1: page 1553

  8517. #define IMXRT_USDHC1		(*(IMXRT_REGISTER32_t *)0x402C0000)

  8518. #define USDHC1_DS_ADDR			(IMXRT_USDHC1.offset000)

  8519. #define USDHC1_BLK_ATT			(IMXRT_USDHC1.offset004)

  8520. #define USDHC1_CMD_ARG			(IMXRT_USDHC1.offset008)

  8521. #define USDHC1_CMD_XFR_TYP		(IMXRT_USDHC1.offset00C)

  8522. #define USDHC1_CMD_RSP0			(IMXRT_USDHC1.offset010)

  8523. #define USDHC1_CMD_RSP1			(IMXRT_USDHC1.offset014)

  8524. #define USDHC1_CMD_RSP2			(IMXRT_USDHC1.offset018)

  8525. #define USDHC1_CMD_RSP3			(IMXRT_USDHC1.offset01C)

  8526. #define USDHC1_DATA_BUFF_ACC_PORT	(IMXRT_USDHC1.offset020)

  8527. #define USDHC1_PRES_STATE		(IMXRT_USDHC1.offset024)

  8528. #define USDHC1_PROT_CTRL		(IMXRT_USDHC1.offset028)

  8529. #define USDHC1_SYS_CTRL			(IMXRT_USDHC1.offset02C)

  8530. #define USDHC1_INT_STATUS		(IMXRT_USDHC1.offset030)

  8531. #define USDHC1_INT_STATUS_EN		(IMXRT_USDHC1.offset034)

  8532. #define USDHC1_INT_SIGNAL_EN		(IMXRT_USDHC1.offset038)

  8533. #define USDHC1_AUTOCMD12_ERR_STATUS	(IMXRT_USDHC1.offset03C)

  8534. #define USDHC1_HOST_CTRL_CAP		(IMXRT_USDHC1.offset040)

  8535. #define USDHC1_WTMK_LVL			(IMXRT_USDHC1.offset044)

  8536. #define USDHC1_MIX_CTRL			(IMXRT_USDHC1.offset048)

  8537. #define USDHC1_FORCE_EVENT		(IMXRT_USDHC1.offset050)

  8538. #define USDHC1_ADMA_ERR_STATUS		(IMXRT_USDHC1.offset054)

  8539. #define USDHC1_ADMA_SYS_ADDR		(IMXRT_USDHC1.offset058)

  8540. #define USDHC1_DLL_CTRL			(IMXRT_USDHC1.offset060)

  8541. #define USDHC1_DLL_STATUS		(IMXRT_USDHC1.offset064)

  8542. #define USDHC1_CLK_TUNE_CTRL_STATUS	(IMXRT_USDHC1.offset068)

  8543. #define USDHC1_VEND_SPEC		(IMXRT_USDHC1.offset0C0)

  8544. #define USDHC1_MMC_BOOT			(IMXRT_USDHC1.offset0C4)

  8545. #define USDHC1_VEND_SPEC2		(IMXRT_USDHC1.offset0C8)

  8546. #define USDHC1_TUNING_CTRL		(IMXRT_USDHC1.offset0CC)

  8547. #define IMXRT_USDHC2		(*(IMXRT_REGISTER32_t *)0x402C4000)

  8548. #define USDHC2_DS_ADDR			(IMXRT_USDHC2.offset000)

  8549. #define USDHC2_BLK_ATT			(IMXRT_USDHC2.offset004)

  8550. #define USDHC2_CMD_ARG			(IMXRT_USDHC2.offset008)

  8551. #define USDHC2_CMD_XFR_TYP		(IMXRT_USDHC2.offset00C)

  8552. #define USDHC2_CMD_RSP0			(IMXRT_USDHC2.offset010)

  8553. #define USDHC2_CMD_RSP1			(IMXRT_USDHC2.offset014)

  8554. #define USDHC2_CMD_RSP2			(IMXRT_USDHC2.offset018)

  8555. #define USDHC2_CMD_RSP3			(IMXRT_USDHC2.offset01C)

  8556. #define USDHC2_DATA_BUFF_ACC_PORT	(IMXRT_USDHC2.offset020)

  8557. #define USDHC2_PRES_STATE		(IMXRT_USDHC2.offset024)

  8558. #define USDHC2_PROT_CTRL		(IMXRT_USDHC2.offset028)

  8559. #define USDHC2_SYS_CTRL			(IMXRT_USDHC2.offset02C)

  8560. #define USDHC2_INT_STATUS		(IMXRT_USDHC2.offset030)

  8561. #define USDHC2_INT_STATUS_EN		(IMXRT_USDHC2.offset034)

  8562. #define USDHC2_INT_SIGNAL_EN		(IMXRT_USDHC2.offset038)

  8563. #define USDHC2_AUTOCMD12_ERR_STATUS	(IMXRT_USDHC2.offset03C)

  8564. #define USDHC2_HOST_CTRL_CAP		(IMXRT_USDHC2.offset040)

  8565. #define USDHC2_WTMK_LVL			(IMXRT_USDHC2.offset044)

  8566. #define USDHC2_MIX_CTRL			(IMXRT_USDHC2.offset048)

  8567. #define USDHC2_FORCE_EVENT		(IMXRT_USDHC2.offset050)

  8568. #define USDHC2_ADMA_ERR_STATUS		(IMXRT_USDHC2.offset054)

  8569. #define USDHC2_ADMA_SYS_ADDR		(IMXRT_USDHC2.offset058)

  8570. #define USDHC2_DLL_CTRL			(IMXRT_USDHC2.offset060)

  8571. #define USDHC2_DLL_STATUS		(IMXRT_USDHC2.offset064)

  8572. #define USDHC2_CLK_TUNE_CTRL_STATUS	(IMXRT_USDHC2.offset068)

  8573. #define USDHC2_VEND_SPEC		(IMXRT_USDHC2.offset0C0)

  8574. #define USDHC2_MMC_BOOT			(IMXRT_USDHC2.offset0C4)

  8575. #define USDHC2_VEND_SPEC2		(IMXRT_USDHC2.offset0C8)

  8576. #define USDHC2_TUNING_CTRL		(IMXRT_USDHC2.offset0CC)

  8577. 

  8578. // 57.8.1.1: page 3187

  8579. #define IMXRT_WDOG1		(*(IMXRT_REGISTER16_t *)0x400B8000)

  8580. #define WDOG1_WCR			(IMXRT_WDOG1.offset000)

  8581. #define WDOG1_WSR			(IMXRT_WDOG1.offset002)

  8582. #define WDOG1_WRSR			(IMXRT_WDOG1.offset004)

  8583. #define WDOG1_WICR			(IMXRT_WDOG1.offset006)

  8584. #define WDOG1_WMCR			(IMXRT_WDOG1.offset008)

  8585. #define IMXRT_WDOG2		(*(IMXRT_REGISTER16_t *)0x400D0000)

  8586. #define WDOG2_WCR			(IMXRT_WDOG2.offset000)

  8587. #define WDOG2_WSR			(IMXRT_WDOG2.offset002)

  8588. #define WDOG2_WRSR			(IMXRT_WDOG2.offset004)

  8589. #define WDOG2_WICR			(IMXRT_WDOG2.offset006)

  8590. #define WDOG2_WMCR			(IMXRT_WDOG2.offset008)

  8591. #define WDOG_WCR_WDZST				((uint16_t)(1<<0))

  8592. #define WDOG_WCR_WDBG				((uint16_t)(1<<1))

  8593. #define WDOG_WCR_WDE				((uint16_t)(1<<2))

  8594. #define WDOG_WCR_WDT				((uint16_t)(1<<3))

  8595. #define WDOG_WCR_SRS				((uint16_t)(1<<4))

  8596. #define WDOG_WCR_WDA				((uint16_t)(1<<5))

  8597. #define WDOG_WCR_SRE				((uint16_t)(1<<6))

  8598. #define WDOG_WCR_WDW				((uint16_t)(1<<7))

  8599. #define WDOG_WCR_WT(n)				((uint16_t)(((n) & 0xFF) << 8))

  8600. #define WDOG_WRSR_SFTW				((uint16_t)(1<<0))

  8601. #define WDOG_WRSR_TOUT				((uint16_t)(1<<1))

  8602. #define WDOG_WRSR_POR				((uint16_t)(1<<4))

  8603. 

  8604. // 58.5.1.1: page 3205

  8605. #define IMXRT_WDOG3		(*(IMXRT_REGISTER32_t *)0x400BC000)

  8606. #define WDOG3_CS			(IMXRT_WDOG3.offset000)

  8607. #define WDOG3_CNT			(IMXRT_WDOG3.offset004)

  8608. #define WDOG3_TOVAL			(IMXRT_WDOG3.offset008)

  8609. #define WDOG3_WIN			(IMXRT_WDOG3.offset00C)

  8610. #define WDOG_CS_STOP				((uint16_t)(1<<0))

  8611. #define WDOG_CS_WAIT				((uint16_t)(1<<1))

  8612. #define WDOG_CS_DBG				((uint16_t)(1<<2))

  8613. #define WDOG_CS_TST(n)				((uint16_t)(((n) & 0x03) << 3))

  8614. #define WDOG_CS_UPDATE				((uint16_t)(1<<5))

  8615. #define WDOG_CS_INT				((uint16_t)(1<<6))

  8616. #define WDOG_CS_EN				((uint16_t)(1<<7))

  8617. #define WDOG_CS_CLK(n)				((uint16_t)(((n) & 0x03) << 8))

  8618. #define WDOG_CS_RCS				((uint16_t)(1<<10))

  8619. #define WDOG_CS_ULK				((uint16_t)(1<<11))

  8620. #define WDOG_CS_PRES				((uint16_t)(1<<12))

  8621. #define WDOG_CS_CMD32EN				((uint16_t)(1<<13))

  8622. #define WDOG_CS_FLG				((uint16_t)(1<<14))

  8623. #define WDOG_CS_WIN				((uint16_t)(1<<15))

  8624. 

  8625. // 61.4: page 3235

  8626. #define IMXRT_XBARA1		(*(IMXRT_REGISTER16_t *)0x403BC000)

  8627. #define XBARA1_SEL0			(IMXRT_XBARA1.offset000)

  8628. #define XBARA1_SEL1			(IMXRT_XBARA1.offset002)

  8629. #define XBARA1_SEL2			(IMXRT_XBARA1.offset004)

  8630. #define XBARA1_SEL3			(IMXRT_XBARA1.offset006)

  8631. #define XBARA1_SEL4			(IMXRT_XBARA1.offset008)

  8632. #define XBARA1_SEL5			(IMXRT_XBARA1.offset00A)

  8633. #define XBARA1_SEL6			(IMXRT_XBARA1.offset00C)

  8634. #define XBARA1_SEL7			(IMXRT_XBARA1.offset00E)

  8635. #define XBARA1_SEL8			(IMXRT_XBARA1.offset010)

  8636. #define XBARA1_SEL9			(IMXRT_XBARA1.offset012)

  8637. #define XBARA1_SEL10			(IMXRT_XBARA1.offset014)

  8638. #define XBARA1_SEL11			(IMXRT_XBARA1.offset016)

  8639. #define XBARA1_SEL12			(IMXRT_XBARA1.offset018)

  8640. #define XBARA1_SEL13			(IMXRT_XBARA1.offset01A)

  8641. #define XBARA1_SEL14			(IMXRT_XBARA1.offset01C)

  8642. #define XBARA1_SEL15			(IMXRT_XBARA1.offset01E)

  8643. #define XBARA1_SEL16			(IMXRT_XBARA1.offset020)

  8644. #define XBARA1_SEL17			(IMXRT_XBARA1.offset022)

  8645. #define XBARA1_SEL18			(IMXRT_XBARA1.offset024)

  8646. #define XBARA1_SEL19			(IMXRT_XBARA1.offset026)

  8647. #define XBARA1_SEL20			(IMXRT_XBARA1.offset028)

  8648. #define XBARA1_SEL21			(IMXRT_XBARA1.offset02A)

  8649. #define XBARA1_SEL22			(IMXRT_XBARA1.offset02C)

  8650. #define XBARA1_SEL23			(IMXRT_XBARA1.offset02E)

  8651. #define XBARA1_SEL24			(IMXRT_XBARA1.offset030)

  8652. #define XBARA1_SEL25			(IMXRT_XBARA1.offset032)

  8653. #define XBARA1_SEL26			(IMXRT_XBARA1.offset034)

  8654. #define XBARA1_SEL27			(IMXRT_XBARA1.offset036)

  8655. #define XBARA1_SEL28			(IMXRT_XBARA1.offset038)

  8656. #define XBARA1_SEL29			(IMXRT_XBARA1.offset03A)

  8657. #define XBARA1_SEL30			(IMXRT_XBARA1.offset03C)

  8658. #define XBARA1_SEL31			(IMXRT_XBARA1.offset03E)

  8659. #define XBARA1_SEL32			(IMXRT_XBARA1.offset040)

  8660. #define XBARA1_SEL33			(IMXRT_XBARA1.offset042)

  8661. #define XBARA1_SEL34			(IMXRT_XBARA1.offset044)

  8662. #define XBARA1_SEL35			(IMXRT_XBARA1.offset046)

  8663. #define XBARA1_SEL36			(IMXRT_XBARA1.offset048)

  8664. #define XBARA1_SEL37			(IMXRT_XBARA1.offset04A)

  8665. #define XBARA1_SEL38			(IMXRT_XBARA1.offset04C)

  8666. #define XBARA1_SEL39			(IMXRT_XBARA1.offset04E)

  8667. #define XBARA1_SEL40			(IMXRT_XBARA1.offset050)

  8668. #define XBARA1_SEL41			(IMXRT_XBARA1.offset052)

  8669. #define XBARA1_SEL42			(IMXRT_XBARA1.offset054)

  8670. #define XBARA1_SEL43			(IMXRT_XBARA1.offset056)

  8671. #define XBARA1_SEL44			(IMXRT_XBARA1.offset058)

  8672. #define XBARA1_SEL45			(IMXRT_XBARA1.offset05A)

  8673. #define XBARA1_SEL46			(IMXRT_XBARA1.offset05C)

  8674. #define XBARA1_SEL47			(IMXRT_XBARA1.offset05E)

  8675. #define XBARA1_SEL48			(IMXRT_XBARA1.offset060)

  8676. #define XBARA1_SEL49			(IMXRT_XBARA1.offset062)

  8677. #define XBARA1_SEL50			(IMXRT_XBARA1.offset064)

  8678. #define XBARA1_SEL51			(IMXRT_XBARA1.offset066)

  8679. #define XBARA1_SEL52			(IMXRT_XBARA1.offset068)

  8680. #define XBARA1_SEL53			(IMXRT_XBARA1.offset06A)

  8681. #define XBARA1_SEL54			(IMXRT_XBARA1.offset06C)

  8682. #define XBARA1_SEL55			(IMXRT_XBARA1.offset06E)

  8683. #define XBARA1_SEL56			(IMXRT_XBARA1.offset070)

  8684. #define XBARA1_SEL57			(IMXRT_XBARA1.offset072)

  8685. #define XBARA1_SEL58			(IMXRT_XBARA1.offset074)

  8686. #define XBARA1_SEL59			(IMXRT_XBARA1.offset076)

  8687. #define XBARA1_SEL60			(IMXRT_XBARA1.offset078)

  8688. #define XBARA1_SEL61			(IMXRT_XBARA1.offset07A)

  8689. #define XBARA1_SEL62			(IMXRT_XBARA1.offset07C)

  8690. #define XBARA1_SEL63			(IMXRT_XBARA1.offset07E)

  8691. #define XBARA1_SEL64			(IMXRT_XBARA1.offset080)

  8692. #define XBARA1_SEL65			(IMXRT_XBARA1.offset082)

  8693. #define XBARA1_CTRL0			(IMXRT_XBARA1.offset084)

  8694. #define XBARA1_CTRL1			(IMXRT_XBARA1.offset086)

  8695. #define XBARA_CTRL_STS1				((uint16_t)(1<<12))

  8696. #define XBARA_CTRL_EDGE1(n)			((uint16_t)(((n) & 0x03) << 10))

  8697. #define XBARA_CTRL_IEN1				((uint16_t)(1<<9))

  8698. #define XBARA_CTRL_DEN1				((uint16_t)(1<<8))

  8699. #define XBARA_CTRL_STS0				((uint16_t)(1<<4))

  8700. #define XBARA_CTRL_EDGE0(n)			((uint16_t)(((n) & 0x03) << 2))

  8701. #define XBARA_CTRL_IEN0				((uint16_t)(1<<1))

  8702. #define XBARA_CTRL_DEN0				((uint16_t)(1<<0))

  8703. 

  8704. // 62.3: page 3278

  8705. #define IMXRT_XBARB2		(*(IMXRT_REGISTER16_t *)0x403C0000)

  8706. #define XBARB2_SEL0			(IMXRT_XBARB2.offset000)

  8707. #define XBARB2_SEL1			(IMXRT_XBARB2.offset002)

  8708. #define XBARB2_SEL2			(IMXRT_XBARB2.offset004)

  8709. #define XBARB2_SEL3			(IMXRT_XBARB2.offset006)

  8710. #define XBARB2_SEL4			(IMXRT_XBARB2.offset008)

  8711. #define XBARB2_SEL5			(IMXRT_XBARB2.offset00A)

  8712. #define XBARB2_SEL6			(IMXRT_XBARB2.offset00C)

  8713. #define XBARB2_SEL7			(IMXRT_XBARB2.offset00E)

  8714. #define IMXRT_XBARB3		(*(IMXRT_REGISTER16_t *)0x403C4000)

  8715. #define XBARB3_SEL0			(IMXRT_XBARB3.offset000)

  8716. #define XBARB3_SEL1			(IMXRT_XBARB3.offset002)

  8717. #define XBARB3_SEL2			(IMXRT_XBARB3.offset004)

  8718. #define XBARB3_SEL3			(IMXRT_XBARB3.offset006)

  8719. #define XBARB3_SEL4			(IMXRT_XBARB3.offset008)

  8720. #define XBARB3_SEL5			(IMXRT_XBARB3.offset00A)

  8721. #define XBARB3_SEL6			(IMXRT_XBARB3.offset00C)

  8722. #define XBARB3_SEL7			(IMXRT_XBARB3.offset00E)

  8723. 

  8724. // XBAR1 Inputs and Outputs Table 3-4 Starting Page 62

  8725. #define XBARA1_IN_LOGIC_LOW 0

  8726. #define XBARA1_IN_LOGIC_HIGH 1

  8727. #define XBARA1_IN_IOMUX_XBAR_IN02 2

  8728. #define XBARA1_IN_IOMUX_XBAR_IN03 3

  8729. #define XBARA1_IN_IOMUX_XBAR_INOUT04 4

  8730. #define XBARA1_IN_IOMUX_XBAR_INOUT05 5

  8731. #define XBARA1_IN_IOMUX_XBAR_INOUT06 6

  8732. #define XBARA1_IN_IOMUX_XBAR_INOUT07 7

  8733. #define XBARA1_IN_IOMUX_XBAR_INOUT08 8

  8734. #define XBARA1_IN_IOMUX_XBAR_INOUT09 9

  8735. #define XBARA1_IN_IOMUX_XBAR_INOUT10 10

  8736. #define XBARA1_IN_IOMUX_XBAR_INOUT11 11

  8737. #define XBARA1_IN_IOMUX_XBAR_INOUT12 12

  8738. #define XBARA1_IN_IOMUX_XBAR_INOUT13 13

  8739. #define XBARA1_IN_IOMUX_XBAR_INOUT14 14

  8740. #define XBARA1_IN_IOMUX_XBAR_INOUT15 15

  8741. #define XBARA1_IN_IOMUX_XBAR_INOUT16 16

  8742. #define XBARA1_IN_IOMUX_XBAR_INOUT17 17

  8743. #define XBARA1_IN_IOMUX_XBAR_INOUT18 18

  8744. #define XBARA1_IN_IOMUX_XBAR_INOUT19 19

  8745. #define XBARA1_IN_IOMUX_XBAR_IN20 20

  8746. #define XBARA1_IN_IOMUX_XBAR_IN21 21

  8747. #define XBARA1_IN_IOMUX_XBAR_IN22 22

  8748. #define XBARA1_IN_IOMUX_XBAR_IN23 23

  8749. #define XBARA1_IN_IOMUX_XBAR_IN24 24

  8750. #define XBARA1_IN_IOMUX_XBAR_IN25 25

  8751. #define XBARA1_IN_ACMP1_OUT 26

  8752. #define XBARA1_IN_ACMP2_OUT 27

  8753. #define XBARA1_IN_ACMP3_OUT 28

  8754. #define XBARA1_IN_ACMP4_OUT 29

  8755. //#define XBARA1_IN_Reserved 30

  8756. //#define XBARA1_IN_Reserved 31

  8757. #define XBARA1_IN_QTIMER3_TIMER0 32

  8758. #define XBARA1_IN_QTIMER3_TIMER1 33

  8759. #define XBARA1_IN_QTIMER3_TIMER2 34

  8760. #define XBARA1_IN_QTIMER3_TIMER3 35

  8761. #define XBARA1_IN_QTIMER4_TIMER0 36

  8762. #define XBARA1_IN_QTIMER4_TIMER1 37

  8763. #define XBARA1_IN_QTIMER4_TIMER2 38

  8764. #define XBARA1_IN_QTIMER4_TIMER3 39

  8765. #define XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG0 40

  8766. #define XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG1 40

  8767. #define XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG0 41

  8768. #define XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG1 41

  8769. #define XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG0 42

  8770. #define XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG1 42

  8771. #define XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG0 43

  8772. #define XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG1 43

  8773. #define XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG0 44

  8774. #define XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG1 44

  8775. #define XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG0 45

  8776. #define XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG1 45

  8777. #define XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG0 46

  8778. #define XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG1 46

  8779. #define XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG0 47

  8780. #define XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG1 47

  8781. #define XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG0 48

  8782. #define XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG1 48

  8783. #define XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG0 49

  8784. #define XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG1 49

  8785. #define XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG0 50

  8786. #define XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG1 50

  8787. #define XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG0 51

  8788. #define XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG1 51

  8789. #define XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG0 52

  8790. #define XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG1 52

  8791. #define XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG0 53

  8792. #define XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG1 53

  8793. #define XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG0 54

  8794. #define XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG1 54

  8795. #define XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG0 55

  8796. #define XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG1 55

  8797. #define XBARA1_IN_PIT_TRIGGER0 56

  8798. #define XBARA1_IN_PIT_TRIGGER1 57

  8799. #define XBARA1_IN_PIT_TRIGGER2 58

  8800. #define XBARA1_IN_PIT_TRIGGER3 59

  8801. #define XBARA1_IN_ENC1_POS_MATCH 60

  8802. #define XBARA1_IN_ENC2_POS_MATCH 61

  8803. #define XBARA1_IN_ENC3_POS_MATCH 62

  8804. #define XBARA1_IN_ENC4_POS_MATCH 63

  8805. #define XBARA1_IN_DMA_DONE0 64

  8806. #define XBARA1_IN_DMA_DONE1 65

  8807. #define XBARA1_IN_DMA_DONE2 66

  8808. #define XBARA1_IN_DMA_DONE3 67

  8809. #define XBARA1_IN_DMA_DONE4 68

  8810. #define XBARA1_IN_DMA_DONE5 69

  8811. #define XBARA1_IN_DMA_DONE6 70

  8812. #define XBARA1_IN_DMA_DONE7 71

  8813. #define XBARA1_IN_AOI1_OUT0 72

  8814. #define XBARA1_IN_AOI1_OUT1 73

  8815. #define XBARA1_IN_AOI1_OUT2 74

  8816. #define XBARA1_IN_AOI1_OUT3 75

  8817. #define XBARA1_IN_AOI2_OUT0 76

  8818. #define XBARA1_IN_AOI2_OUT1 77

  8819. #define XBARA1_IN_AOI2_OUT2 78

  8820. #define XBARA1_IN_AOI2_OUT3 79

  8821. #define XBARA1_IN_ADC_ETC0_COCO0 80

  8822. #define XBARA1_IN_ADC_ETC0_COCO1 81

  8823. #define XBARA1_IN_ADC_ETC0_COCO2 82

  8824. #define XBARA1_IN_ADC_ETC0_COCO3 83

  8825. #define XBARA1_IN_ADC_ETC1_COCO0 84

  8826. #define XBARA1_IN_ADC_ETC1_COCO1 85

  8827. #define XBARA1_IN_ADC_ETC1_COCO2 86

  8828. #define XBARA1_IN_ADC_ETC1_COCO3 87

  8829. 

  8830. #define XBARA1_OUT_DMA_CH_MUX_REQ30 0

  8831. #define XBARA1_OUT_DMA_CH_MUX_REQ31 1

  8832. #define XBARA1_OUT_DMA_CH_MUX_REQ94 2

  8833. #define XBARA1_OUT_DMA_CH_MUX_REQ95 3

  8834. #define XBARA1_OUT_IOMUX_XBAR_INOUT04 4

  8835. #define XBARA1_OUT_IOMUX_XBAR_INOUT05 5

  8836. #define XBARA1_OUT_IOMUX_XBAR_INOUT06 6

  8837. #define XBARA1_OUT_IOMUX_XBAR_INOUT07 7

  8838. #define XBARA1_OUT_IOMUX_XBAR_INOUT08 8

  8839. #define XBARA1_OUT_IOMUX_XBAR_INOUT09 9

  8840. #define XBARA1_OUT_IOMUX_XBAR_INOUT10 10

  8841. #define XBARA1_OUT_IOMUX_XBAR_INOUT11 11

  8842. #define XBARA1_OUT_IOMUX_XBAR_INOUT12 12

  8843. #define XBARA1_OUT_IOMUX_XBAR_INOUT13 13

  8844. #define XBARA1_OUT_IOMUX_XBAR_INOUT14 14

  8845. #define XBARA1_OUT_IOMUX_XBAR_INOUT15 15

  8846. #define XBARA1_OUT_IOMUX_XBAR_INOUT16 16

  8847. #define XBARA1_OUT_IOMUX_XBAR_INOUT17 17

  8848. #define XBARA1_OUT_IOMUX_XBAR_INOUT18 18

  8849. #define XBARA1_OUT_IOMUX_XBAR_INOUT19 19

  8850. #define XBARA1_OUT_ACMP1_SAMPLE 20

  8851. #define XBARA1_OUT_ACMP2_SAMPLE 21

  8852. #define XBARA1_OUT_ACMP3_SAMPLE 22

  8853. #define XBARA1_OUT_ACMP4_SAMPLE 23

  8854. //#define XBARA1_OUT_Reserved 24

  8855. //#define XBARA1_OUT_Reserved 25

  8856. #define XBARA1_OUT_FLEXPWM1_PWM0_EXTA 26

  8857. #define XBARA1_OUT_FLEXPWM1_PWM1_EXTA 27

  8858. #define XBARA1_OUT_FLEXPWM1_PWM2_EXTA 28

  8859. #define XBARA1_OUT_FLEXPWM1_PWM3_EXTA 29

  8860. #define XBARA1_OUT_FLEXPWM1_PWM0_EXT_SYNC 30

  8861. #define XBARA1_OUT_FLEXPWM1_PWM1_EXT_SYNC 31

  8862. #define XBARA1_OUT_FLEXPWM1_PWM2_EXT_SYNC 32

  8863. #define XBARA1_OUT_FLEXPWM1_PWM3_EXT_SYNC 33

  8864. #define XBARA1_OUT_FLEXPWM1_EXT_CLK 34

  8865. #define XBARA1_OUT_FLEXPWM1_FAULT0 35

  8866. #define XBARA1_OUT_FLEXPWM1_FAULT1 36

  8867. #define XBARA1_OUT_FLEXPWM1_FAULT2 37

  8868. #define XBARA1_OUT_FLEXPWM2_FAULT2 37

  8869. #define XBARA1_OUT_FLEXPWM3_FAULT2 37

  8870. #define XBARA1_OUT_FLEXPWM4_FAULT2 37

  8871. #define XBARA1_OUT_FLEXPWM1_FAULT3 38

  8872. #define XBARA1_OUT_FLEXPWM2_FAULT3 38

  8873. #define XBARA1_OUT_FLEXPWM3_FAULT3 38

  8874. #define XBARA1_OUT_FLEXPWM4_FAULT3 38

  8875. #define XBARA1_OUT_FLEXPWM1_EXT_FORCE 39

  8876. #define XBARA1_OUT_FLEXPWM2_PWM0_EXTA 40

  8877. #define XBARA1_OUT_FLEXPWM3_PWM0_EXTA 40

  8878. #define XBARA1_OUT_FLEXPWM4_PWM0_EXTA 40

  8879. #define XBARA1_OUT_FLEXPWM2_PWM1_EXTA 41

  8880. #define XBARA1_OUT_FLEXPWM3_PWM1_EXTA 41

  8881. #define XBARA1_OUT_FLEXPWM4_PWM1_EXTA 41

  8882. #define XBARA1_OUT_FLEXPWM2_PWM2_EXTA 42

  8883. #define XBARA1_OUT_FLEXPWM3_PWM2_EXTA 42

  8884. #define XBARA1_OUT_FLEXPWM4_PWM2_EXTA 42

  8885. #define XBARA1_OUT_FLEXPWM2_PWM3_EXTA 43

  8886. #define XBARA1_OUT_FLEXPWM3_PWM3_EXTA 43

  8887. #define XBARA1_OUT_FLEXPWM4_PWM3_EXTA 43

  8888. #define XBARA1_OUT_FLEXPWM2_PWM0_EXT_SYNC 44

  8889. #define XBARA1_OUT_FLEXPWM2_PWM1_EXT_SYNC 45

  8890. #define XBARA1_OUT_FLEXPWM2_PWM2_EXT_SYNC 46

  8891. #define XBARA1_OUT_FLEXPWM2_PWM3_EXT_SYNC 47

  8892. #define XBARA1_OUT_FLEXPWM2_EXT_CLK 48

  8893. #define XBARA1_OUT_FLEXPWM3_EXT_CLK 48

  8894. #define XBARA1_OUT_FLEXPWM4_EXT_CLK 48

  8895. #define XBARA1_OUT_FLEXPWM2_FAULT0 49

  8896. #define XBARA1_OUT_FLEXPWM2_FAULT1 50

  8897. #define XBARA1_OUT_FLEXPWM2_EXT_FORCE 51

  8898. #define XBARA1_OUT_FLEXPWM3_EXT_SYNC0 52

  8899. #define XBARA1_OUT_FLEXPWM3_EXT_SYNC1 53

  8900. #define XBARA1_OUT_FLEXPWM3_EXT_SYNC2 54

  8901. #define XBARA1_OUT_FLEXPWM3_EXT_SYNC3 55

  8902. #define XBARA1_OUT_FLEXPWM3_FAULT0 56

  8903. #define XBARA1_OUT_FLEXPWM3_FAULT1 57

  8904. #define XBARA1_OUT_FLEXPWM3_EXT_FORCE 58

  8905. #define XBARA1_OUT_FLEXPWM4_EXT_SYNC0 59

  8906. #define XBARA1_OUT_FLEXPWM4_EXT_SYNC1 60

  8907. #define XBARA1_OUT_FLEXPWM4_EXT_SYNC2 61

  8908. #define XBARA1_OUT_FLEXPWM4_EXT_SYNC3 62

  8909. #define XBARA1_OUT_FLEXPWM4_FAULT0 63

  8910. #define XBARA1_OUT_FLEXPWM4_FAULT1 64

  8911. #define XBARA1_OUT_FLEXPWM4_EXT_FORCE 65

  8912. #define XBARA1_OUT_ENC1_PHASEA_INPUT 66

  8913. #define XBARA1_OUT_ENC1_PHASEB_INPUT 67

  8914. #define XBARA1_OUT_ENC1_INDEX 68

  8915. #define XBARA1_OUT_ENC1_HOME 69

  8916. #define XBARA1_OUT_ENC1_TRIGGER 70

  8917. #define XBARA1_OUT_ENC2_PHASEA_INPUT 71

  8918. #define XBARA1_OUT_ENC2_PHASEB_INPUT 72

  8919. #define XBARA1_OUT_ENC2_INDEX 73

  8920. #define XBARA1_OUT_ENC2_HOME 74

  8921. #define XBARA1_OUT_ENC2_TRIGGER 75

  8922. #define XBARA1_OUT_ENC3_PHASEA_INPUT 76

  8923. #define XBARA1_OUT_ENC3_PHASEB_INPUT 77

  8924. #define XBARA1_OUT_ENC3_INDEX 78

  8925. #define XBARA1_OUT_ENC3_HOME 79

  8926. #define XBARA1_OUT_ENC3_TRIGGER 80

  8927. #define XBARA1_OUT_ENC4_PHASEA_INPUT 81

  8928. #define XBARA1_OUT_ENC4_PHASEB_INPUT 82

  8929. #define XBARA1_OUT_ENC4_INDEX 83

  8930. #define XBARA1_OUT_ENC4_HOME 84

  8931. #define XBARA1_OUT_ENC4_TRIGGER 85

  8932. #define XBARA1_OUT_QTIMER1_TIMER0 86

  8933. #define XBARA1_OUT_QTIMER1_TIMER1 87

  8934. #define XBARA1_OUT_QTIMER1_TIMER2 88

  8935. #define XBARA1_OUT_QTIMER1_TIMER3 89

  8936. #define XBARA1_OUT_QTIMER2_TIMER0 90

  8937. #define XBARA1_OUT_QTIMER2_TIMER1 91

  8938. #define XBARA1_OUT_QTIMER2_TIMER2 92

  8939. #define XBARA1_OUT_QTIMER2_TIMER3 93

  8940. #define XBARA1_OUT_QTIMER3_TIMER0 94

  8941. #define XBARA1_OUT_QTIMER3_TIMER1 95

  8942. #define XBARA1_OUT_QTIMER3_TIMER2 96

  8943. #define XBARA1_OUT_QTIMER3_TIMER3 97

  8944. #define XBARA1_OUT_QTIMER4_TIMER0 98

  8945. #define XBARA1_OUT_QTIMER4_TIMER1 99

  8946. #define XBARA1_OUT_QTIMER4_TIMER2 100

  8947. #define XBARA1_OUT_QTIMER4_TIMER3 101

  8948. #define XBARA1_OUT_EWM_EWM_IN 102

  8949. #define XBARA1_OUT_ADC_ETC_TRIG00 103

  8950. #define XBARA1_OUT_ADC_ETC_TRIG01 104

  8951. #define XBARA1_OUT_ADC_ETC_TRIG02 105

  8952. #define XBARA1_OUT_ADC_ETC_TRIG03 106

  8953. #define XBARA1_OUT_ADC_ETC_TRIG10 107

  8954. #define XBARA1_OUT_ADC_ETC_TRIG11 108

  8955. #define XBARA1_OUT_ADC_ETC_TRIG12 109

  8956. #define XBARA1_OUT_ADC_ETC_TRIG13 110

  8957. #define XBARA1_OUT_LPI2C1_TRG_INPUT 111

  8958. #define XBARA1_OUT_LPI2C2_TRG_INPUT 112

  8959. #define XBARA1_OUT_LPI2C3_TRG_INPUT 113

  8960. #define XBARA1_OUT_LPI2C4_TRG_INPUT 114

  8961. #define XBARA1_OUT_LPSPI1_TRG_INPUT 115

  8962. #define XBARA1_OUT_LPSPI2_TRG_INPUT 116

  8963. #define XBARA1_OUT_LPSPI3_TRG_INPUT 117

  8964. #define XBARA1_OUT_LPSPI4_TRG_INPUT 118

  8965. #define XBARA1_OUT_LPUART1_TRG_INPUT 119

  8966. #define XBARA1_OUT_LPUART2_TRG_INPUT 120

  8967. #define XBARA1_OUT_LPUART3_TRG_INPUT 121

  8968. #define XBARA1_OUT_LPUART4_TRG_INPUT 122

  8969. #define XBARA1_OUT_LPUART5_TRG_INPUT 123

  8970. #define XBARA1_OUT_LPUART6_TRG_INPUT 124

  8971. #define XBARA1_OUT_LPUART7_TRG_INPUT 125

  8972. #define XBARA1_OUT_LPUART8_TRG_INPUT 126

  8973. #define XBARA1_OUT_FLEXIO1_TRIGGER_IN0 127

  8974. #define XBARA1_OUT_FLEXIO1_TRIGGER_IN1 128

  8975. #define XBARA1_OUT_FLEXIO2_TRIGGER_IN0 129

  8976. #define XBARA1_OUT_FLEXIO2_TRIGGER_IN1 130

  8977. //#define XBARA1_OUT_Reserved 131

  8978. 

  8979. // XBAR2 Inputs and Outputs Table 3-5 P63

  8980. #define XBARB2_IN_LOGIC_LOW 0

  8981. #define XBARB2_IN_LOGIC_HIGH 1

  8982. //#define XBARB2_IN_Reserved 2

  8983. //#define XBARB2_IN_Reserved 3

  8984. //#define XBARB2_IN_Reserved 4

  8985. //#define XBARB2_IN_Reserved 5

  8986. #define XBARB2_IN_ACMP1_OUT 6

  8987. #define XBARB2_IN_ACMP2_OUT 7

  8988. #define XBARB2_IN_ACMP3_OUT 8

  8989. #define XBARB2_IN_ACMP4_OUT 9

  8990. //#define XBARB2_IN_Reserved 10

  8991. //#define XBARB2_IN_Reserved 11

  8992. #define XBARB2_IN_QTIMER3_TIMER0 12

  8993. #define XBARB2_IN_QTIMER3_TIMER1 13

  8994. #define XBARB2_IN_QTIMER3_TIMER2 14

  8995. #define XBARB2_IN_QTIMER3_TIMER3 15

  8996. #define XBARB2_IN_QTIMER4_TIMER0 16

  8997. #define XBARB2_IN_QTIMER4_TIMER1 17

  8998. #define XBARB2_IN_QTIMER4_TIMER2 18

  8999. #define XBARB2_IN_QTIMER4_TIMER3 19

  9000. #define XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG0 20

  9001. #define XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG1 20

  9002. #define XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG0 21

  9003. #define XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG1 21

  9004. #define XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG0 22

  9005. #define XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG1 22

  9006. #define XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG0 23

  9007. #define XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG1 23

  9008. #define XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG0 24

  9009. #define XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG1 24

  9010. #define XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG0 25

  9011. #define XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG1 25

  9012. #define XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG0 26

  9013. #define XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG1 26

  9014. #define XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG0 27

  9015. #define XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG1 27

  9016. #define XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG0 28

  9017. #define XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG1 28

  9018. #define XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG0 29

  9019. #define XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG1 29

  9020. #define XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG0 30

  9021. #define XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG1 30

  9022. #define XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG0 31

  9023. #define XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG1 31

  9024. #define XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG0 32

  9025. #define XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG1 32

  9026. #define XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG0 33

  9027. #define XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG1 33

  9028. #define XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG0 34

  9029. #define XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG1 34

  9030. #define XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG0 35

  9031. #define XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG1 35

  9032. #define XBARB2_IN_PIT_TRIGGER0 36

  9033. #define XBARB2_IN_PIT_TRIGGER1 37

  9034. #define XBARB2_IN_ADC_ETC0_COCO0 38

  9035. #define XBARB2_IN_ADC_ETC0_COCO1 39

  9036. #define XBARB2_IN_ADC_ETC0_COCO2 40

  9037. #define XBARB2_IN_ADC_ETC0_COCO3 41

  9038. #define XBARB2_IN_ADC_ETC1_COCO0 42

  9039. #define XBARB2_IN_ADC_ETC1_COCO1 43

  9040. #define XBARB2_IN_ADC_ETC1_COCO2 44

  9041. #define XBARB2_IN_ADC_ETC1_COCO3 45

  9042. #define XBARB2_IN_ENC1_POS_MATCH 46

  9043. #define XBARB2_IN_ENC2_POS_MATCH 47

  9044. #define XBARB2_IN_ENC3_POS_MATCH 48

  9045. #define XBARB2_IN_ENC4_POS_MATCH 49

  9046. #define XBARB2_IN_DMA_DONE0 50

  9047. #define XBARB2_IN_DMA_DONE1 51

  9048. #define XBARB2_IN_DMA_DONE2 52

  9049. #define XBARB2_IN_DMA_DONE3 53

  9050. #define XBARB2_IN_DMA_DONE4 54

  9051. #define XBARB2_IN_DMA_DONE5 55

  9052. #define XBARB2_IN_DMA_DONE6 56

  9053. #define XBARB2_IN_DMA_DONE7 57

  9054. 

  9055. #define XBARB2_OUT_AOI1_IN00 0

  9056. #define XBARB2_OUT_AOI1_IN01 1

  9057. #define XBARB2_OUT_AOI1_IN02 2

  9058. #define XBARB2_OUT_AOI1_IN03 3

  9059. #define XBARB2_OUT_AOI1_IN04 4

  9060. #define XBARB2_OUT_AOI1_IN05 5

  9061. #define XBARB2_OUT_AOI1_IN06 6

  9062. #define XBARB2_OUT_AOI1_IN07 7

  9063. #define XBARB2_OUT_AOI1_IN08 8

  9064. #define XBARB2_OUT_AOI1_IN09 9

  9065. #define XBARB2_OUT_AOI1_IN10 10

  9066. #define XBARB2_OUT_AOI1_IN11 11

  9067. #define XBARB2_OUT_AOI1_IN12 12

  9068. #define XBARB2_OUT_AOI1_IN13 13

  9069. #define XBARB2_OUT_AOI1_IN14 14

  9070. 

  9071. // XBAR3 Inputs and Outputs Table 3-6 Page 63

  9072. #define XBARB3_IN_LOGIC_LOW 0

  9073. #define XBARB3_IN_LOGIC_HIGH 1

  9074. //#define XBARB3_IN_Reserved 2

  9075. //#define XBARB3_IN_Reserved 3

  9076. //#define XBARB3_IN_Reserved 4

  9077. //#define XBARB3_IN_Reserved 5

  9078. #define XBARB3_IN_ACMP1_OUT 6

  9079. #define XBARB3_IN_ACMP2_OUT 7

  9080. #define XBARB3_IN_ACMP3_OUT 8

  9081. #define XBARB3_IN_ACMP4_OUT 9

  9082. //#define XBARB3_IN_Reserved 10

  9083. //#define XBARB3_IN_Reserved 11

  9084. #define XBARB3_IN_QTIMER3_TIMER0 12

  9085. #define XBARB3_IN_QTIMER3_TIMER1 13

  9086. #define XBARB3_IN_QTIMER3_TIMER2 14

  9087. #define XBARB3_IN_QTIMER3_TIMER3 15

  9088. #define XBARB3_IN_QTIMER4_TIMER0 16

  9089. #define XBARB3_IN_QTIMER4_TIMER1 17

  9090. #define XBARB3_IN_QTIMER4_TIMER2 18

  9091. #define XBARB3_IN_QTIMER4_TIMER3 19

  9092. #define XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG0 20

  9093. #define XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG0 21

  9094. #define XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG0 22

  9095. #define XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG0 23

  9096. #define XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG0 24

  9097. #define XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG0 25

  9098. #define XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG0 26

  9099. #define XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG0 27

  9100. #define XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG0 28

  9101. #define XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG0 29

  9102. #define XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG0 30

  9103. #define XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG0 31

  9104. #define XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG0 32

  9105. #define XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG0 33

  9106. #define XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG0 34

  9107. #define XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG0 35

  9108. #define XBARB3_IN_PIT_TRIGGER0 36

  9109. #define XBARB3_IN_PIT_TRIGGER1 37

  9110. #define XBARB3_IN_ADC_ETC0_COCO0 38

  9111. #define XBARB3_IN_ADC_ETC0_COCO1 39

  9112. #define XBARB3_IN_ADC_ETC0_COCO2 40

  9113. #define XBARB3_IN_ADC_ETC0_COCO3 41

  9114. #define XBARB3_IN_ADC_ETC1_COCO0 42

  9115. #define XBARB3_IN_ADC_ETC1_COCO1 43

  9116. #define XBARB3_IN_ADC_ETC1_COCO2 44

  9117. #define XBARB3_IN_ADC_ETC1_COCO3 45

  9118. #define XBARB3_IN_ENC1_POS_MATCH 46

  9119. #define XBARB3_IN_ENC2_POS_MATCH 47

  9120. #define XBARB3_IN_ENC3_POS_MATCH 48

  9121. #define XBARB3_IN_ENC4_POS_MATCH 49

  9122. #define XBARB3_IN_DMA_DONE0 50

  9123. #define XBARB3_IN_DMA_DONE1 51

  9124. #define XBARB3_IN_DMA_DONE2 52

  9125. #define XBARB3_IN_DMA_DONE3 53

  9126. #define XBARB3_IN_DMA_DONE4 54

  9127. #define XBARB3_IN_DMA_DONE5 55

  9128. #define XBARB3_IN_DMA_DONE6 56

  9129. #define XBARB3_IN_DMA_DONE7 57

  9130. 

  9131. #define XBARB3_OUT_AOI2_IN00 0

  9132. #define XBARB3_OUT_AOI2_IN01 1

  9133. #define XBARB3_OUT_AOI2_IN02 2

  9134. #define XBARB3_OUT_AOI2_IN03 3

  9135. #define XBARB3_OUT_AOI2_IN04 4

  9136. #define XBARB3_OUT_AOI2_IN05 5

  9137. #define XBARB3_OUT_AOI2_IN06 6

  9138. #define XBARB3_OUT_AOI2_IN07 7

  9139. #define XBARB3_OUT_AOI2_IN08 8

  9140. #define XBARB3_OUT_AOI2_IN09 9

  9141. #define XBARB3_OUT_AOI2_IN10 10

  9142. #define XBARB3_OUT_AOI2_IN11 11

  9143. #define XBARB3_OUT_AOI2_IN12 12

  9144. #define XBARB3_OUT_AOI2_IN13 13

  9145. #define XBARB3_OUT_AOI2_IN14 14

  9146. #define XBARB3_OUT_AOI2_IN15 15

  9147. 

  9148. 

  9149. // 15.6: page 1142

  9150. #define IMXRT_XTALOSC24M	(*(IMXRT_REGISTER32_t *)0x400D8000)

  9151. #define XTALOSC24M_MISC0		(IMXRT_XTALOSC24M.offset150)

  9152. #define XTALOSC24M_LOWPWR_CTRL		(IMXRT_XTALOSC24M.offset270)

  9153. #define XTALOSC24M_LOWPWR_CTRL_SET	(IMXRT_XTALOSC24M.offset274)

  9154. #define XTALOSC24M_LOWPWR_CTRL_CLR	(IMXRT_XTALOSC24M.offset278)

  9155. #define XTALOSC24M_LOWPWR_CTRL_TOG	(IMXRT_XTALOSC24M.offset27C)

  9156. #define XTALOSC24M_OSC_CONFIG0		(IMXRT_XTALOSC24M.offset2A0)

  9157. #define XTALOSC24M_OSC_CONFIG0_SET	(IMXRT_XTALOSC24M.offset2A4)

  9158. #define XTALOSC24M_OSC_CONFIG0_CLR	(IMXRT_XTALOSC24M.offset2A8)

  9159. #define XTALOSC24M_OSC_CONFIG0_TOG	(IMXRT_XTALOSC24M.offset2AC)

  9160. #define XTALOSC24M_OSC_CONFIG1		(IMXRT_XTALOSC24M.offset2B0)

  9161. #define XTALOSC24M_OSC_CONFIG1_SET	(IMXRT_XTALOSC24M.offset2B4)

  9162. #define XTALOSC24M_OSC_CONFIG1_CLR	(IMXRT_XTALOSC24M.offset2B8)

  9163. #define XTALOSC24M_OSC_CONFIG1_TOG	(IMXRT_XTALOSC24M.offset2BC)

  9164. #define XTALOSC24M_OSC_CONFIG2		(IMXRT_XTALOSC24M.offset2C0)

  9165. #define XTALOSC24M_OSC_CONFIG2_SET	(IMXRT_XTALOSC24M.offset2C4)

  9166. #define XTALOSC24M_OSC_CONFIG2_CLR	(IMXRT_XTALOSC24M.offset2C8)

  9167. #define XTALOSC24M_OSC_CONFIG2_TOG	(IMXRT_XTALOSC24M.offset2CC)

  9168. 

  9169. 

  9170. // 0 = highest priority

  9171. // Cortex-M7: 0,16,32,48,64,80,96,112,128,144,160,176,192,208,224,240

  9172. #define NVIC_SET_PRIORITY(irqnum, priority)  (*((volatile uint8_t *)0xE000E400 + (irqnum)) = (uint8_t)(priority))

  9173. #define NVIC_GET_PRIORITY(irqnum) (*((uint8_t *)0xE000E400 + (irqnum)))

  9174. 

  9175. 

  9176. #define __disable_irq() __asm__ volatile("CPSID i":::"memory");

  9177. #define __enable_irq()  __asm__ volatile("CPSIE i":::"memory");

  9178. 

  9179. 

  9180. // System Control Space (SCS), ARMv7 ref manual, B3.2, page 708

  9181. #define SCB_CPUID               (*(const    uint32_t *)0xE000ED00) // CPUID Base Register

  9182. #define SCB_ICSR                (*(volatile uint32_t *)0xE000ED04) // Interrupt Control and State

  9183. #define SCB_ICSR_NMIPENDSET             ((uint32_t)(1<<31))

  9184. #define SCB_ICSR_PENDSVSET              ((uint32_t)(1<<28))

  9185. #define SCB_ICSR_PENDSVCLR              ((uint32_t)(1<<27))

  9186. #define SCB_ICSR_PENDSTSET              ((uint32_t)(1<<26))

  9187. #define SCB_ICSR_PENDSTCLR              ((uint32_t)(1<<25))

  9188. #define SCB_ICSR_ISRPREEMPT             ((uint32_t)(1<<23))

  9189. #define SCB_ICSR_ISRPENDING             ((uint32_t)(1<<22))

  9190. #define SCB_ICSR_RETTOBASE              ((uint32_t)(1<<11))

  9191. #define SCB_VTOR                (*(volatile uint32_t *)0xE000ED08) // Vector Table Offset

  9192. #define SCB_AIRCR               (*(volatile uint32_t *)0xE000ED0C) // Application Interrupt & Reset

  9193. #define SCB_SCR                 (*(volatile uint32_t *)0xE000ED10) // System Control Register

  9194. #define SCB_SCR_SEVONPEND   ((uint8_t)0x10)        // Send Event on Pending bit

  9195. #define SCB_SCR_SLEEPDEEP   ((uint8_t)0x04)        // Sleep or Deep Sleep

  9196. #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02)        // Sleep-on-exit

  9197. #define SCB_CCR                 (*(volatile uint32_t *)0xE000ED14) // Configuration and Control

  9198. #define SCB_CCR_BP			((uint32_t)(1<<18))	// Branch prediction enable

  9199. #define SCB_CCR_IC			((uint32_t)(1<<17))	// Instruction caches enable

  9200. #define SCB_CCR_DC			((uint32_t)(1<<16))

  9201. #define SCB_CCR_STKALIGN		((uint32_t)(1<<9))

  9202. #define SCB_CCR_BFHFNMIGN		((uint32_t)(1<<8))

  9203. #define SCB_CCR_DIV_0_TRP		((uint32_t)(1<<4))

  9204. #define SCB_CCR_UNALIGN_TRP		((uint32_t)(1<<3))

  9205. #define SCB_CCR_USERSETMPEND		((uint32_t)(1<<1))

  9206. #define SCB_CCR_NONBASETHRDENA		((uint32_t)(1<<0))

  9207. #define SCB_SHPR1               (*(volatile uint32_t *)0xE000ED18) // System Handler Priority 1

  9208. #define SCB_SHPR2               (*(volatile uint32_t *)0xE000ED1C) // System Handler Priority 2

  9209. #define SCB_SHPR3               (*(volatile uint32_t *)0xE000ED20) // System Handler Priority 3

  9210. #define SCB_SHCSR               (*(volatile uint32_t *)0xE000ED24) // System Handler Control & State

  9211. #define SCB_CFSR                (*(volatile uint32_t *)0xE000ED28) // Configurable Fault Status

  9212. #define SCB_HFSR                (*(volatile uint32_t *)0xE000ED2C) // HardFault Status

  9213. #define SCB_DFSR                (*(volatile uint32_t *)0xE000ED30) // Debug Fault Status

  9214. #define SCB_MMFAR               (*(volatile uint32_t *)0xE000ED34) // MemManage Fault Address

  9215. #define SCB_BFAR                (*(volatile uint32_t *)0xE000ED38) // Bus Fault Address

  9216. #define SCB_AFAR                (*(volatile uint32_t *)0xE000ED3C) // Aux Fault Address

  9217. #define SCB_ID_PFR0		(*(const    uint32_t *)0xE000ED40) // Processor Feature 0

  9218. #define SCB_ID_PFR1		(*(const    uint32_t *)0xE000ED44) // Processor Feature 1

  9219. #define SCB_ID_DFR0		(*(const    uint32_t *)0xE000ED48) // Debug Feature 0

  9220. #define SCB_ID_AFR0		(*(const    uint32_t *)0xE000ED4C) // Auxiliary Feature 0

  9221. #define SCB_ID_MMFR0		(*(const    uint32_t *)0xE000ED50) // Memory Model Feature 0

  9222. #define SCB_ID_MMFR1		(*(const    uint32_t *)0xE000ED54) // Memory Model Feature 1

  9223. #define SCB_ID_MMFR2		(*(const    uint32_t *)0xE000ED58) // Memory Model Feature 2

  9224. #define SCB_ID_MMFR3		(*(const    uint32_t *)0xE000ED5C) // Memory Model Feature 3

  9225. #define SCB_ID_ISAR0		(*(const    uint32_t *)0xE000ED60) // Instruction Set Attribute 0

  9226. #define SCB_ID_ISAR1		(*(const    uint32_t *)0xE000ED64) // Instruction Set Attribute 1

  9227. #define SCB_ID_ISAR2 		(*(const    uint32_t *)0xE000ED68) // Instruction Set Attribute 2

  9228. #define SCB_ID_ISAR3 		(*(const    uint32_t *)0xE000ED6C) // Instruction Set Attribute 3

  9229. #define SCB_ID_ISAR4 		(*(const    uint32_t *)0xE000ED70) // Instruction Set Attribute 4

  9230. #define SCB_ID_CLIDR		(*(const    uint32_t *)0xE000ED78) // Cache Level ID

  9231. #define SCB_ID_CTR		(*(const    uint32_t *)0xE000ED7C) // Cache Type

  9232. #define SCB_ID_CCSIDR		(*(const    uint32_t *)0xE000ED80) // Cache Size ID

  9233. #define SCB_ID_CSSELR		(*(volatile uint32_t *)0xE000ED84) // Cache Size Selection

  9234. #define SCB_CPACR               (*(volatile uint32_t *)0xE000ED88) // Coprocessor Access Control

  9235. #define SCB_FPCCR               (*(volatile uint32_t *)0xE000EF34) // FP Context Control

  9236. #define SCB_FPCAR               (*(volatile uint32_t *)0xE000EF38) // FP Context Address

  9237. #define SCB_FPDSCR              (*(volatile uint32_t *)0xE000EF3C) // FP Default Status Control

  9238. #define SCB_MVFR0               (*(volatile uint32_t *)0xE000EF40) // Media & FP Feature 0

  9239. #define SCB_MVFR1               (*(volatile uint32_t *)0xE000EF44) // Media & FP Feature 1

  9240. #define SCB_MVFR2               (*(volatile uint32_t *)0xE000EF48) // Media & FP Feature 2

  9241. 

  9242. #define SYST_CSR                (*(volatile uint32_t *)0xE000E010) // SysTick Control and Status

  9243. #define SYST_CSR_COUNTFLAG              ((uint32_t)(1<<16))

  9244. #define SYST_CSR_CLKSOURCE              ((uint32_t)(1<<2))

  9245. #define SYST_CSR_TICKINT                ((uint32_t)(1<<1))

  9246. #define SYST_CSR_ENABLE                 ((uint32_t)(1<<0))

  9247. #define SYST_RVR                (*(volatile uint32_t *)0xE000E014) // SysTick Reload Value Register

  9248. #define SYST_CVR                (*(volatile uint32_t *)0xE000E018) // SysTick Current Value Register

  9249. #define SYST_CALIB              (*(const    uint32_t *)0xE000E01C) // SysTick Calibration Value

  9250. 

  9251. // Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)

  9252. #define NVIC_ISER0              (*(volatile uint32_t *)0xE000E100)

  9253. #define NVIC_ISER1              (*(volatile uint32_t *)0xE000E104)

  9254. #define NVIC_ISER2              (*(volatile uint32_t *)0xE000E108)

  9255. #define NVIC_ISER3              (*(volatile uint32_t *)0xE000E10C)

  9256. #define NVIC_ISER4              (*(volatile uint32_t *)0xE000E110)

  9257. #define NVIC_ICER0              (*(volatile uint32_t *)0xE000E180)

  9258. #define NVIC_ICER1              (*(volatile uint32_t *)0xE000E184)

  9259. #define NVIC_ICER2              (*(volatile uint32_t *)0xE000E188)

  9260. #define NVIC_ICER3              (*(volatile uint32_t *)0xE000E18C)

  9261. #define NVIC_ICER4              (*(volatile uint32_t *)0xE000E190)

  9262. #define NVIC_STIR		(*(volatile uint32_t *)0xE000EF00)

  9263. #define NVIC_ENABLE_IRQ(n)      (*(&NVIC_ISER0 + ((n) >> 5)) = (1 << ((n) & 31)))

  9264. #define NVIC_DISABLE_IRQ(n)     (*(&NVIC_ICER0 + ((n) >> 5)) = (1 << ((n) & 31)))

  9265. #define NVIC_SET_PENDING(n)     (*((volatile uint32_t *)0xE000E200 + ((n) >> 5)) = (1 << ((n) & 31)))

  9266. #define NVIC_CLEAR_PENDING(n)   (*((volatile uint32_t *)0xE000E280 + ((n) >> 5)) = (1 << ((n) & 31)))

  9267. #define NVIC_IS_ENABLED(n)      (*(&NVIC_ISER0 + ((n) >> 5)) & (1 << ((n) & 31)))

  9268. #define NVIC_IS_PENDING(n)      (*((volatile uint32_t *)0xE000E200 + ((n) >> 5)) & (1 << ((n) & 31)))

  9269. #define NVIC_IS_ACTIVE(n)       (*((volatile uint32_t *)0xE000E300 + ((n) >> 5)) & (1 << ((n) & 31)))

  9270. #define NVIC_TRIGGER_IRQ(n)     NVIC_STIR=(n)

  9271. 

  9272. #define ARM_DEMCR               (*(volatile uint32_t *)0xE000EDFC) // Debug Exception and Monitor Control

  9273. #define ARM_DEMCR_TRCENA                (1 << 24)        // Enable debugging & monitoring blocks

  9274. #define ARM_DWT_CTRL            (*(volatile uint32_t *)0xE0001000) // DWT control register

  9275. #define ARM_DWT_CTRL_CYCCNTENA          (1 << 0)                // Enable cycle count

  9276. #define ARM_DWT_CYCCNT          (*(volatile uint32_t *)0xE0001004) // Cycle count register

  9277. 

  9278. #define SCB_MPU_TYPE		(*(volatile uint32_t *)0xE000ED90) // 

  9279. #define SCB_MPU_CTRL		(*(volatile uint32_t *)0xE000ED94) // 

  9280. #define SCB_MPU_CTRL_PRIVDEFENA		((uint32_t)(1<<2)) // Enables default memory map

  9281. #define SCB_MPU_CTRL_HFNMIENA		((uint32_t)(1<<1)) // Use MPU for HardFault & NMI

  9282. #define SCB_MPU_CTRL_ENABLE		((uint32_t)(1<<0)) // Enables MPU

  9283. #define SCB_MPU_RNR		(*(volatile uint32_t *)0xE000ED98) // 

  9284. #define SCB_MPU_RBAR		(*(volatile uint32_t *)0xE000ED9C) // 

  9285. #define SCB_MPU_RBAR_ADDR_MASK		((uint32_t)(0xFFFFFFE0))

  9286. #define SCB_MPU_RBAR_VALID		((uint32_t)(1<<4))

  9287. #define SCB_MPU_RBAR_REGION(n)		((uint32_t)((n) & 15))

  9288. #define SCB_MPU_RASR		(*(volatile uint32_t *)0xE000EDA0) // ARM DDI0403E, pg 696

  9289. #define SCB_MPU_RASR_XN			((uint32_t)(1<<28))

  9290. #define SCB_MPU_RASR_AP(n)		((uint32_t)(((n) & 7) << 24))

  9291. #define SCB_MPU_RASR_TEX(n)		((uint32_t)(((n) & 7) << 19))

  9292. #define SCB_MPU_RASR_S			((uint32_t)(1<<18))

  9293. #define SCB_MPU_RASR_C			((uint32_t)(1<<17))

  9294. #define SCB_MPU_RASR_B			((uint32_t)(1<<16))

  9295. #define SCB_MPU_RASR_SRD(n)		((uint32_t)(((n) & 255) << 8))

  9296. #define SCB_MPU_RASR_SIZE(n)		((uint32_t)(((n) & 31) << 1))

  9297. #define SCB_MPU_RASR_ENABLE		((uint32_t)(1<<0))

  9298. #define SCB_MPU_RBAR_A1		(*(volatile uint32_t *)0xE000EDA4) // 

  9299. #define SCB_MPU_RASR_A1		(*(volatile uint32_t *)0xE000EDA8) // 

  9300. #define SCB_MPU_RBAR_A2		(*(volatile uint32_t *)0xE000EDAC) // 

  9301. #define SCB_MPU_RASR_A2		(*(volatile uint32_t *)0xE000EDB0) // 

  9302. #define SCB_MPU_RBAR_A3		(*(volatile uint32_t *)0xE000EDB4) // 

  9303. #define SCB_MPU_RASR_A3		(*(volatile uint32_t *)0xE000EDB8) // 

  9304. 

  9305. #define SCB_CACHE_ICIALLU	(*(volatile uint32_t *)0xE000EF50)

  9306. #define SCB_CACHE_ICIMVAU	(*(volatile uint32_t *)0xE000EF58)

  9307. #define SCB_CACHE_DCIMVAC	(*(volatile uint32_t *)0xE000EF5C)

  9308. #define SCB_CACHE_DCISW		(*(volatile uint32_t *)0xE000EF60)

  9309. #define SCB_CACHE_DCCMVAU	(*(volatile uint32_t *)0xE000EF64)

  9310. #define SCB_CACHE_DCCMVAC	(*(volatile uint32_t *)0xE000EF68)

  9311. #define SCB_CACHE_DCCSW		(*(volatile uint32_t *)0xE000EF6C)

  9312. #define SCB_CACHE_DCCIMVAC	(*(volatile uint32_t *)0xE000EF70)

  9313. #define SCB_CACHE_DCCISW	(*(volatile uint32_t *)0xE000EF74)

  9314. #define SCB_CACHE_BPIALL	(*(volatile uint32_t *)0xE000EF78)

  9315. 

  9316. // Flush data from cache to memory

  9317. //

  9318. // Normally arm_dcache_flush() is used when metadata written to memory

  9319. // will be used by a DMA or a bus-master peripheral.  Any data in the

  9320. // cache is written to memory.  A copy remains in the cache, so this is

  9321. // typically used with special fields you will want to quickly access

  9322. // in the future.  For data transmission, use arm_dcache_flush_delete().

  9323. __attribute__((always_inline, unused))

  9324. static inline void arm_dcache_flush(void *addr, uint32_t size)

  9325. {

  9326. 	uint32_t location = (uint32_t)addr & 0xFFFFFFE0;

  9327. 	uint32_t end_addr = (uint32_t)addr + size;

  9328. 	asm volatile("": : :"memory");

  9329. 	asm("dsb");

  9330. 	do {

  9331. 		SCB_CACHE_DCCMVAC = location;

  9332. 		location += 32;

  9333. 	} while (location < end_addr);

  9334. 	asm("dsb");

  9335. 	asm("isb");

  9336. }

  9337. 

  9338. // Delete data from the cache, without touching memory

  9339. //

  9340. // Normally arm_dcache_delete() is used before receiving data via

  9341. // DMA or from bus-master peripherals which write to memory.  You

  9342. // want to delete anything the cache may have stored, so your next

  9343. // read is certain to access the physical memory.

  9344. __attribute__((always_inline, unused))

  9345. static inline void arm_dcache_delete(void *addr, uint32_t size)

  9346. {

  9347. 	uint32_t location = (uint32_t)addr & 0xFFFFFFE0;

  9348. 	uint32_t end_addr = (uint32_t)addr + size;

  9349. 	asm volatile("": : :"memory");

  9350. 	asm("dsb");

  9351. 	do {

  9352. 		SCB_CACHE_DCIMVAC = location;

  9353. 		location += 32;

  9354. 	} while (location < end_addr);

  9355. 	asm("dsb");

  9356. 	asm("isb");

  9357. }

  9358. 

  9359. // Flush data from cache to memory, and delete it from the cache

  9360. //

  9361. // Normally arm_dcache_flush_delete() is used when transmitting data

  9362. // via DMA or bus-master peripherals which read from memory.  You want

  9363. // any cached data written to memory, and then removed from the cache,

  9364. // because you no longer need to access the data after transmission.

  9365. __attribute__((always_inline, unused))

  9366. static inline void arm_dcache_flush_delete(void *addr, uint32_t size)

  9367. {

  9368. 	uint32_t location = (uint32_t)addr & 0xFFFFFFE0;

  9369. 	uint32_t end_addr = (uint32_t)addr + size;

  9370. 	asm volatile("": : :"memory");

  9371. 	asm("dsb");

  9372. 	do {

  9373. 		SCB_CACHE_DCCIMVAC = location;

  9374. 		location += 32;

  9375. 	} while (location < end_addr);

  9376. 	asm("dsb");

  9377. 	asm("isb");

  9378. }