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teensy-sd/utility/NXP_SDHC.cpp

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  1. // adapted for Arduino SD library by Paul Stoffregen

  2. // following code is modified by Walter Zimmer from

  3. // from version provided by

  4. // Petr Gargulak (NXP Employee)

  5. //https://community.nxp.com/servlet/JiveServlet/download/339474-1-263510/SDHC_K60_Baremetal.ZIP

  6. //see also

  7. //https://community.nxp.com/thread/99202

  8. 

  9. #if defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(__IMXRT1052__)

  10. 

  11. #include "core_pins.h"  // include calls to kinetis.h or imxrt.h

  12. #include "usb_serial.h" // for Serial

  13. 

  14. #include "NXP_SDHC.h"

  15. 

  16. // Missing in Teensyduino 1.30

  17. #ifndef MPU_CESR_VLD_MASK

  18. #define MPU_CESR_VLD_MASK         0x1u

  19. #endif

  20. 

  21. /******************************************************************************

  22.   Constants

  23. ******************************************************************************/

  24. 

  25. enum {

  26.   SDHC_RESULT_OK = 0,             /* 0: Successful */

  27.   SDHC_RESULT_ERROR,              /* 1: R/W Error */

  28.   SDHC_RESULT_WRPRT,              /* 2: Write Protected */

  29.   SDHC_RESULT_NOT_READY,          /* 3: Not Ready */

  30.   SDHC_RESULT_PARERR,             /* 4: Invalid Parameter */

  31.   SDHC_RESULT_NO_RESPONSE         /* 5: No Response */ // from old diskio.h

  32. };

  33. 

  34. /*void print_result(int n)

  35.   {

  36.         switch (n) {

  37.         case SDHC_RESULT_OK: serial_print("OK\n"); break;

  38.         case SDHC_RESULT_ERROR: serial_print("R/W Error\n"); break;

  39.         case SDHC_RESULT_WRPRT: serial_print("Write Protect\n"); break;

  40.         case SDHC_RESULT_NOT_READY: serial_print("Not Ready\n"); break;

  41.         case SDHC_RESULT_PARERR: serial_print("Invalid Param\n"); break;

  42.         case SDHC_RESULT_NO_RESPONSE: serial_print("No Response\n"); break;

  43.         default: serial_print("Unknown result\n");

  44.         }

  45.   }*/

  46. 

  47. 

  48. #define IO_SDHC_ATTRIBS (IO_DEV_ATTR_READ | IO_DEV_ATTR_REMOVE | IO_DEV_ATTR_SEEK | IO_DEV_ATTR_WRITE | IO_DEV_ATTR_BLOCK_MODE)

  49. 

  50. #define SDHC_XFERTYP_RSPTYP_NO              (0x00)

  51. #define SDHC_XFERTYP_RSPTYP_136             (0x01)

  52. #define SDHC_XFERTYP_RSPTYP_48              (0x02)

  53. #define SDHC_XFERTYP_RSPTYP_48BUSY          (0x03)

  54. 

  55. #define SDHC_XFERTYP_CMDTYP_ABORT           (0x03)

  56. 

  57. #define SDHC_PROCTL_EMODE_INVARIANT         (0x02)

  58. 

  59. #define SDHC_PROCTL_DTW_1BIT                (0x00)

  60. #define SDHC_PROCTL_DTW_4BIT                (0x01)

  61. #define SDHC_PROCTL_DTW_8BIT                (0x10)

  62. 

  63. #define SDHC_INITIALIZATION_MAX_CNT 100000

  64. 

  65. /* SDHC commands */

  66. #define SDHC_CMD0                           (0)

  67. #define SDHC_CMD1                           (1)

  68. #define SDHC_CMD2                           (2)

  69. #define SDHC_CMD3                           (3)

  70. #define SDHC_CMD4                           (4)

  71. #define SDHC_CMD5                           (5)

  72. #define SDHC_CMD6                           (6)

  73. #define SDHC_CMD7                           (7)

  74. #define SDHC_CMD8                           (8)

  75. #define SDHC_CMD9                           (9)

  76. #define SDHC_CMD10                          (10)

  77. #define SDHC_CMD11                          (11)

  78. #define SDHC_CMD12                          (12)

  79. #define SDHC_CMD13                          (13)

  80. #define SDHC_CMD15                          (15)

  81. #define SDHC_CMD16                          (16)

  82. #define SDHC_CMD17                          (17)

  83. #define SDHC_CMD18                          (18)

  84. #define SDHC_CMD20                          (20)

  85. #define SDHC_CMD24                          (24)

  86. #define SDHC_CMD25                          (25)

  87. #define SDHC_CMD26                          (26)

  88. #define SDHC_CMD27                          (27)

  89. #define SDHC_CMD28                          (28)

  90. #define SDHC_CMD29                          (29)

  91. #define SDHC_CMD30                          (30)

  92. #define SDHC_CMD32                          (32)

  93. #define SDHC_CMD33                          (33)

  94. #define SDHC_CMD34                          (34)

  95. #define SDHC_CMD35                          (35)

  96. #define SDHC_CMD36                          (36)

  97. #define SDHC_CMD37                          (37)

  98. #define SDHC_CMD38                          (38)

  99. #define SDHC_CMD39                          (39)

  100. #define SDHC_CMD40                          (40)

  101. #define SDHC_CMD42                          (42)

  102. #define SDHC_CMD52                          (52)

  103. #define SDHC_CMD53                          (53)

  104. #define SDHC_CMD55                          (55)

  105. #define SDHC_CMD56                          (56)

  106. #define SDHC_CMD59                          (59)

  107. #define SDHC_CMD60                          (60)

  108. #define SDHC_CMD61                          (61)

  109. #define SDHC_ACMD6                          (0x40 + 6)

  110. #define SDHC_ACMD13                         (0x40 + 13)

  111. #define SDHC_ACMD22                         (0x40 + 22)

  112. #define SDHC_ACMD23                         (0x40 + 23)

  113. #define SDHC_ACMD41                         (0x40 + 41)

  114. #define SDHC_ACMD42                         (0x40 + 42)

  115. #define SDHC_ACMD51                         (0x40 + 51)

  116. 

  117. #define SDHC_FIFO_BUFFER_SIZE               16

  118. #define SDHC_BLOCK_SIZE                     512

  119. 

  120. #if defined(__IMXRT1052__)

  121. #define MAKE_REG_MASK(m,s) (((uint32_t)(((uint32_t)(m) << s))))

  122. #define MAKE_REG_GET(x,m,s) (((uint32_t)(((uint32_t)(x)>>s) & m)))

  123. #define MAKE_REG_SET(x,m,s) (((uint32_t)(((uint32_t)(x) & m) << s)))

  124. 

  125. #define SDHC_BLKATTR_BLKSIZE_MASK MAKE_REG_MASK(0x1FFF,0) //uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size Mask

  126. #define SDHC_BLKATTR_BLKSIZE(n)   MAKE_REG_SET(n,0x1FFF,0) //uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size

  127. #define SDHC_BLKATTR_BLKCNT_MASK  MAKE_REG_MASK(0x1FFF,16) //((uint32_t)0x1FFF<<16)

  128. #define SDHC_BLKATTR_BLKCNT(n)    MAKE_REG_SET(n,0x1FFF,16) //(uint32_t)(((n) & 0x1FFF)<<16) // Blocks Count For Current Transfer

  129. 

  130. #define SDHC_XFERTYP_CMDINX(n)  MAKE_REG_SET(n,0x3F,24) //(uint32_t)(((n) & 0x3F)<<24)// Command Index

  131. #define SDHC_XFERTYP_CMDTYP(n)  MAKE_REG_SET(n,0x3,22) //(uint32_t)(((n) & 0x3)<<22)  // Command Type

  132. #define SDHC_XFERTYP_DPSEL    MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data Present Select

  133. #define SDHC_XFERTYP_CICEN    MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Command Index Check Enable

  134. #define SDHC_XFERTYP_CCCEN    MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command CRC Check Enable

  135. #define SDHC_XFERTYP_RSPTYP(n)  MAKE_REG_SET(n,0x3,16) //(uint32_t)(((n) & 0x3)<<16)  // Response Type Select

  136. #define SDHC_XFERTYP_MSBSEL   MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // Multi/Single Block Select

  137. #define SDHC_XFERTYP_DTDSEL   MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Data Transfer Direction Select

  138. #define SDHC_XFERTYP_AC12EN   MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Auto CMD12 Enable

  139. #define SDHC_XFERTYP_BCEN   MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Block Count Enable

  140. #define SDHC_XFERTYP_DMAEN    MAKE_REG_MASK(0x3,0) //((uint32_t)0x00000001)   // DMA Enable

  141. 

  142. #define SDHC_PRSSTAT_DLSL_MASK    MAKE_REG_MASK(0xFF,24)  //((uint32_t)0xFF000000)    // DAT Line Signal Level

  143. #define SDHC_PRSSTAT_CLSL     MAKE_REG_MASK(0x1,23) //((uint32_t)0x00800000)    // CMD Line Signal Level

  144. #define SDHC_PRSSTAT_WPSPL      MAKE_REG_MASK(0x1,19) //

  145. #define SDHC_PRSSTAT_CDPL     MAKE_REG_MASK(0x1,18) //

  146. #define SDHC_PRSSTAT_CINS     MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Card Inserted

  147. #define SDHC_PRSSTAT_TSCD     MAKE_REG_MASK(0x1,15)

  148. #define SDHC_PRSSTAT_RTR      MAKE_REG_MASK(0x1,12)

  149. #define SDHC_PRSSTAT_BREN     MAKE_REG_MASK(0x1,11) //((uint32_t)0x00000800)    // Buffer Read Enable

  150. #define SDHC_PRSSTAT_BWEN     MAKE_REG_MASK(0x1,10) //((uint32_t)0x00000400)    // Buffer Write Enable

  151. #define SDHC_PRSSTAT_RTA      MAKE_REG_MASK(0x1,9) //((uint32_t)0x00000200)   // Read Transfer Active

  152. #define SDHC_PRSSTAT_WTA      MAKE_REG_MASK(0x1,8) //((uint32_t)0x00000100)   // Write Transfer Active

  153. #define SDHC_PRSSTAT_SDOFF      MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // SD Clock Gated Off Internally

  154. #define SDHC_PRSSTAT_PEROFF     MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // SDHC clock Gated Off Internally

  155. #define SDHC_PRSSTAT_HCKOFF     MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // System Clock Gated Off Internally

  156. #define SDHC_PRSSTAT_IPGOFF     MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Bus Clock Gated Off Internally

  157. #define SDHC_PRSSTAT_SDSTB      MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // SD Clock Stable

  158. #define SDHC_PRSSTAT_DLA      MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Data Line Active

  159. #define SDHC_PRSSTAT_CDIHB      MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Command Inhibit (DAT)

  160. #define SDHC_PRSSTAT_CIHB     MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // Command Inhibit (CMD)

  161. 

  162. #define SDHC_PROTCT_NONEXACT_BLKRD  MAKE_REG_MASK(0x1,30) //

  163. #define SDHC_PROTCT_BURST_LENEN(n)  MAKE_REG_SET(n,0x7,12) //

  164. #define SDHC_PROCTL_WECRM     MAKE_REG_MASK(0x1,26) //((uint32_t)0x04000000)    // Wakeup Event Enable On SD Card Removal

  165. #define SDHC_PROCTL_WECINS      MAKE_REG_MASK(0x1,25) //((uint32_t)0x02000000)    // Wakeup Event Enable On SD Card Insertion

  166. #define SDHC_PROCTL_WECINT      MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Wakeup Event Enable On Card Interrupt

  167. #define SDHC_PROCTL_RD_DONE_NOBLK MAKE_REG_MASK(0x1,20) //

  168. #define SDHC_PROCTL_IABG      MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Interrupt At Block Gap

  169. #define SDHC_PROCTL_RWCTL     MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Read Wait Control

  170. #define SDHC_PROCTL_CREQ      MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Continue Request

  171. #define SDHC_PROCTL_SABGREQ     MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Stop At Block Gap Request

  172. #define SDHC_PROCTL_DMAS(n)     MAKE_REG_SET(n,0x3,8) //(uint32_t)(((n) & 0x3)<<8)  // DMA Select

  173. #define SDHC_PROCTL_CDSS      MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // Card Detect Signal Selection

  174. #define SDHC_PROCTL_CDTL      MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // Card Detect Test Level

  175. #define SDHC_PROCTL_EMODE(n)    MAKE_REG_SET(n,0x3,4) //(uint32_t)(((n) & 0x3)<<4)  // Endian Mode

  176. #define SDHC_PROCTL_EMODE_MASK  MAKE_REG_MASK(0x3,4) //(uint32_t)((0x3)<<4) // Endian Mode

  177. #define SDHC_PROCTL_D3CD      MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // DAT3 As Card Detection Pin

  178. #define SDHC_PROCTL_DTW(n)      MAKE_REG_SET(n,0x3,1) //(uint32_t)(((n) & 0x3)<<1)  // Data Transfer Width, 0=1bit, 1=4bit, 2=8bit

  179. #define SDHC_PROCTL_DTW_MASK    MAKE_REG_MASK(0x3,1) //((uint32_t)0x00000006)

  180. #define SDHC_PROCTL_LCTL      MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // LED Control

  181. 

  182. #define SDHC_SYSCTL_RSTT      MAKE_REG_MASK(0x1,28) //

  183. #define SDHC_SYSCTL_INITA     MAKE_REG_MASK(0x1,27) //((uint32_t)0x08000000)    // Initialization Active

  184. #define SDHC_SYSCTL_RSTD      MAKE_REG_MASK(0x1,26) //((uint32_t)0x04000000)    // Software Reset For DAT Line

  185. #define SDHC_SYSCTL_RSTC      MAKE_REG_MASK(0x1,25) //((uint32_t)0x02000000)    // Software Reset For CMD Line

  186. #define SDHC_SYSCTL_RSTA      MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Software Reset For ALL

  187. #define SDHC_SYSCTL_DTOCV(n)  MAKE_REG_SET(n,0xF,16) //(uint32_t)(((n) & 0xF)<<16)  // Data Timeout Counter Value

  188. #define SDHC_SYSCTL_DTOCV_MASK    MAKE_REG_MASK(0xF,16) //((uint32_t)0x000F0000)

  189. #define SDHC_SYSCTL_SDCLKFS(n)    MAKE_REG_SET(n,0xFF,8) //(uint32_t)(((n) & 0xFF)<<8)  // SDCLK Frequency Select

  190. #define SDHC_SYSCTL_SDCLKFS_MASK  MAKE_REG_MASK(0xFF,8) //((uint32_t)0x0000FF00)

  191. #define SDHC_SYSCTL_DVS(n)      MAKE_REG_SET(n,0xF,4) //(uint32_t)(((n) & 0xF)<<4)  // Divisor

  192. #define SDHC_SYSCTL_DVS_MASK    MAKE_REG_MASK(0xF,4)  //((uint32_t)0x000000F0)

  193. 

  194. #define SDHC_SYSCTL_SDCLKEN   ((uint32_t)0x00000008)    // SD Clock Enable

  195. #define SDHC_SYSCTL_PEREN     ((uint32_t)0x00000004)    // Peripheral Clock Enable

  196. #define SDHC_SYSCTL_HCKEN     ((uint32_t)0x00000002)    // System Clock Enable

  197. #define SDHC_SYSCTL_IPGEN     ((uint32_t)0x00000001)    // IPG Clock Enable

  198. 

  199. #define SDHC_IRQSTAT_DMAE     MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // DMA Error

  200. #define SDHC_IRQSTAT_TNE      MAKE_REG_MASK(0x1,26) //

  201. #define SDHC_IRQSTAT_AC12E    MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Auto CMD12 Error

  202. #define SDHC_IRQSTAT_DEBE     MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Data End Bit Error

  203. #define SDHC_IRQSTAT_DCE      MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data CRC Error

  204. #define SDHC_IRQSTAT_DTOE     MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Data Timeout Error

  205. #define SDHC_IRQSTAT_CIE      MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command Index Error

  206. #define SDHC_IRQSTAT_CEBE     MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Command End Bit Error

  207. #define SDHC_IRQSTAT_CCE      MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Command CRC Error

  208. #define SDHC_IRQSTAT_CTOE     MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Command Timeout Error

  209. #define SDHC_IRQSTAT_TP       MAKE_REG_MASK(0x1,14) //

  210. #define SDHC_IRQSTAT_RTE      MAKE_REG_MASK(0x1,12) //

  211. #define SDHC_IRQSTAT_CINT     MAKE_REG_MASK(0x1,8) //((uint32_t)0x00000100)   // Card Interrupt

  212. #define SDHC_IRQSTAT_CRM      MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // Card Removal

  213. #define SDHC_IRQSTAT_CINS     MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // Card Insertion

  214. #define SDHC_IRQSTAT_BRR      MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // Buffer Read Ready

  215. #define SDHC_IRQSTAT_BWR      MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Buffer Write Ready

  216. #define SDHC_IRQSTAT_DINT     MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // DMA Interrupt

  217. #define SDHC_IRQSTAT_BGE      MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Block Gap Event

  218. #define SDHC_IRQSTAT_TC       MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Transfer Complete

  219. #define SDHC_IRQSTAT_CC       MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // Command Complete

  220. 

  221. #define SDHC_IRQSTATEN_DMAESEN    MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // DMA Error Status Enable

  222. #define SDHC_IRQSTATEN_TNESEN   MAKE_REG_MASK(0x1,26) //

  223. #define SDHC_IRQSTATEN_AC12ESEN   MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Auto CMD12 Error Status Enable

  224. #define SDHC_IRQSTATEN_DEBESEN    MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Data End Bit Error Status Enable

  225. #define SDHC_IRQSTATEN_DCESEN   MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data CRC Error Status Enable

  226. #define SDHC_IRQSTATEN_DTOESEN    MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Data Timeout Error Status Enable

  227. #define SDHC_IRQSTATEN_CIESEN   MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command Index Error Status Enable

  228. #define SDHC_IRQSTATEN_CEBESEN    MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Command End Bit Error Status Enable

  229. #define SDHC_IRQSTATEN_CCESEN   MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Command CRC Error Status Enable

  230. #define SDHC_IRQSTATEN_CTOESEN    MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Command Timeout Error Status Enable

  231. #define SDHC_IRQSTATEN_TPSEN    MAKE_REG_MASK(0x1,14) //

  232. #define SDHC_IRQSTATEN_RTESEN   MAKE_REG_MASK(0x1,12) //

  233. #define SDHC_IRQSTATEN_CINTSEN    MAKE_REG_MASK(0x1,8) //((uint32_t)0x00000100)   // Card Interrupt Status Enable

  234. #define SDHC_IRQSTATEN_CRMSEN   MAKE_REG_MASK(0x1,7) //((uint32_t)0x00000080)   // Card Removal Status Enable

  235. #define SDHC_IRQSTATEN_CINSEN   MAKE_REG_MASK(0x1,6) //((uint32_t)0x00000040)   // Card Insertion Status Enable

  236. #define SDHC_IRQSTATEN_BRRSEN   MAKE_REG_MASK(0x1,5) //((uint32_t)0x00000020)   // Buffer Read Ready Status Enable

  237. #define SDHC_IRQSTATEN_BWRSEN   MAKE_REG_MASK(0x1,4) //((uint32_t)0x00000010)   // Buffer Write Ready Status Enable

  238. #define SDHC_IRQSTATEN_DINTSEN    MAKE_REG_MASK(0x1,3) //((uint32_t)0x00000008)   // DMA Interrupt Status Enable

  239. #define SDHC_IRQSTATEN_BGESEN   MAKE_REG_MASK(0x1,2) //((uint32_t)0x00000004)   // Block Gap Event Status Enable

  240. #define SDHC_IRQSTATEN_TCSEN    MAKE_REG_MASK(0x1,1) //((uint32_t)0x00000002)   // Transfer Complete Status Enable

  241. #define SDHC_IRQSTATEN_CCSEN    MAKE_REG_MASK(0x1,0) //((uint32_t)0x00000001)   // Command Complete Status Enable

  242. 

  243. #define SDHC_IRQSIGEN_DMAEIEN   MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // DMA Error Interrupt Enable

  244. #define SDHC_IRQSIGEN_TNEIEN    MAKE_REG_MASK(0x1,26) //

  245. #define SDHC_IRQSIGEN_AC12EIEN    MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Auto CMD12 Error Interrupt Enable

  246. #define SDHC_IRQSIGEN_DEBEIEN   MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Data End Bit Error Interrupt Enable

  247. #define SDHC_IRQSIGEN_DCEIEN    MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Data CRC Error Interrupt Enable

  248. #define SDHC_IRQSIGEN_DTOEIEN   MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Data Timeout Error Interrupt Enable

  249. #define SDHC_IRQSIGEN_CIEIEN    MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Command Index Error Interrupt Enable

  250. #define SDHC_IRQSIGEN_CEBEIEN   MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Command End Bit Error Interrupt Enable

  251. #define SDHC_IRQSIGEN_CCEIEN    MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Command CRC Error Interrupt Enable

  252. #define SDHC_IRQSIGEN_CTOEIEN   MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Command Timeout Error Interrupt Enable

  253. #define SDHC_IRQSIGEN_TPIEN     MAKE_REG_MASK(0x1,14) //

  254. #define SDHC_IRQSIGEN_RTEIEN    MAKE_REG_MASK(0x1,12) //

  255. #define SDHC_IRQSIGEN_CINTIEN   MAKE_REG_MASK(0x1,8)  //((uint32_t)0x00000100)    // Card Interrupt Interrupt Enable

  256. #define SDHC_IRQSIGEN_CRMIEN    MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // Card Removal Interrupt Enable

  257. #define SDHC_IRQSIGEN_CINSIEN   MAKE_REG_MASK(0x1,6)  //((uint32_t)0x00000040)    // Card Insertion Interrupt Enable

  258. #define SDHC_IRQSIGEN_BRRIEN    MAKE_REG_MASK(0x1,5)  //((uint32_t)0x00000020)    // Buffer Read Ready Interrupt Enable

  259. #define SDHC_IRQSIGEN_BWRIEN    MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Buffer Write Ready Interrupt Enable

  260. #define SDHC_IRQSIGEN_DINTIEN   MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)    // DMA Interrupt Interrupt Enable

  261. #define SDHC_IRQSIGEN_BGEIEN    MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)    // Block Gap Event Interrupt Enable

  262. #define SDHC_IRQSIGEN_TCIEN     MAKE_REG_MASK(0x1,1)  //((uint32_t)0x00000002)    // Transfer Complete Interrupt Enable

  263. #define SDHC_IRQSIGEN_CCIEN     MAKE_REG_MASK(0x1,0)  //((uint32_t)0x00000001)    // Command Complete Interrupt Enable

  264. 

  265. #define SDHC_AC12ERR_SMPLCLK_SEL  MAKE_REG_MASK(0x1,23) //

  266. #define SDHC_AC12ERR_EXEC_TUNING  MAKE_REG_MASK(0x1,22) //

  267. #define SDHC_AC12ERR_CNIBAC12E    MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // Command Not Issued By Auto CMD12 Error

  268. #define SDHC_AC12ERR_AC12IE     MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Auto CMD12 Index Error

  269. #define SDHC_AC12ERR_AC12CE     MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)    // Auto CMD12 CRC Error

  270. #define SDHC_AC12ERR_AC12EBE    MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)    // Auto CMD12 End Bit Error

  271. #define SDHC_AC12ERR_AC12TOE    MAKE_REG_MASK(0x1,1)  //((uint32_t)0x00000002)    // Auto CMD12 Timeout Error

  272. #define SDHC_AC12ERR_AC12NE     MAKE_REG_MASK(0x1,0)  //((uint32_t)0x00000001)    // Auto CMD12 Not Executed

  273. 

  274. #define SDHC_HTCAPBLT_VS18      MAKE_REG_MASK(0x1,26) //

  275. #define SDHC_HTCAPBLT_VS30      MAKE_REG_MASK(0x1,25) //

  276. #define SDHC_HTCAPBLT_VS33      MAKE_REG_MASK(0x1,24) //

  277. #define SDHC_HTCAPBLT_SRS     MAKE_REG_MASK(0x1,23) //

  278. #define SDHC_HTCAPBLT_DMAS      MAKE_REG_MASK(0x1,22) //

  279. #define SDHC_HTCAPBLT_HSS     MAKE_REG_MASK(0x1,21) //

  280. #define SDHC_HTCAPBLT_ADMAS     MAKE_REG_MASK(0x1,20) //

  281. #define SDHC_HTCAPBLT_MBL_VAL   MAKE_REG_GET((USDHC1_HOST_CTRL_CAP),0x7,16) //

  282. #define SDHC_HTCAPBLT_RETUN_MODE  MAKE_REG_GET((USDHC1_HOST_CTRL_CAP),0x3,14) //

  283. #define SDHC_HTCAPBLT_TUNE_SDR50  MAKE_REG_MASK(0x1,13) //

  284. #define SDHC_HTCAPBLT_TIME_RETUN(n) MAKE_REG_SET(n,0xF,8) //

  285. 

  286. #define SDHC_WML_WR_BRSTLEN_MASK    MAKE_REG_MASK(0x1F,24)  //

  287. #define SDHC_WML_RD_BRSTLEN_MASK    MAKE_REG_MASK(0x1F,8)   //

  288. #define SDHC_WML_WR_WML_MASK      MAKE_REG_MASK(0xFF,16)  //

  289. #define SDHC_WML_RD_WML_MASK      MAKE_REG_MASK(0xFF,0)   //

  290. #define SDHC_WML_WR_BRSTLEN(n)    MAKE_REG_SET(n,0x1F,24) //(uint32_t)(((n) & 0x7F)<<16)  // Write Burst Len

  291. #define SDHC_WML_RD_BRSTLEN(n)    MAKE_REG_SET(n,0x1F,8)  //(uint32_t)(((n) & 0x7F)<<0)   // Read Burst Len

  292. #define SDHC_WML_WR_WML(n)      MAKE_REG_SET(n,0xFF,16) //(uint32_t)(((n) & 0x7F)<<16)  // Write Watermark Level

  293. #define SDHC_WML_RD_WML(n)      MAKE_REG_SET(n,0xFF,0)  //(uint32_t)(((n) & 0x7F)<<0)   // Read Watermark Level

  294. #define SDHC_WML_WRWML(n)     MAKE_REG_SET(n,0xFF,16) //(uint32_t)(((n) & 0x7F)<<16)  // Write Watermark Level

  295. #define SDHC_WML_RDWML(n)     MAKE_REG_SET(n,0xFF,0)  //(uint32_t)(((n) & 0x7F)<<0)   // Read Watermark Level

  296. 

  297. #define SDHC_MIX_CTRL_DMAEN     MAKE_REG_MASK(0x1,0)  //

  298. #define SDHC_MIX_CTRL_BCEN      MAKE_REG_MASK(0x1,1)  //

  299. #define SDHC_MIX_CTRL_AC12EN    MAKE_REG_MASK(0x1,2)  //

  300. #define SDHC_MIX_CTRL_DDR_EN    MAKE_REG_MASK(0x1,3)  //

  301. #define SDHC_MIX_CTRL_DTDSEL    MAKE_REG_MASK(0x1,4)  //

  302. #define SDHC_MIX_CTRL_MSBSEL    MAKE_REG_MASK(0x1,5)  //

  303. #define SDHC_MIX_CTRL_NIBBLE_POS  MAKE_REG_MASK(0x1,6)  //

  304. #define SDHC_MIX_CTRL_AC23EN    MAKE_REG_MASK(0x1,7)  //

  305. 

  306. #define SDHC_FEVT_CINT        MAKE_REG_MASK(0x1,31) //((uint32_t)0x80000000)    // Force Event Card Interrupt

  307. #define SDHC_FEVT_DMAE        MAKE_REG_MASK(0x1,28) //((uint32_t)0x10000000)    // Force Event DMA Error

  308. #define SDHC_FEVT_AC12E       MAKE_REG_MASK(0x1,24) //((uint32_t)0x01000000)    // Force Event Auto CMD12 Error

  309. #define SDHC_FEVT_DEBE        MAKE_REG_MASK(0x1,22) //((uint32_t)0x00400000)    // Force Event Data End Bit Error

  310. #define SDHC_FEVT_DCE       MAKE_REG_MASK(0x1,21) //((uint32_t)0x00200000)    // Force Event Data CRC Error

  311. #define SDHC_FEVT_DTOE        MAKE_REG_MASK(0x1,20) //((uint32_t)0x00100000)    // Force Event Data Timeout Error

  312. #define SDHC_FEVT_CIE       MAKE_REG_MASK(0x1,19) //((uint32_t)0x00080000)    // Force Event Command Index Error

  313. #define SDHC_FEVT_CEBE        MAKE_REG_MASK(0x1,18) //((uint32_t)0x00040000)    // Force Event Command End Bit Error

  314. #define SDHC_FEVT_CCE       MAKE_REG_MASK(0x1,17) //((uint32_t)0x00020000)    // Force Event Command CRC Error

  315. #define SDHC_FEVT_CTOE        MAKE_REG_MASK(0x1,16) //((uint32_t)0x00010000)    // Force Event Command Timeout Error

  316. #define SDHC_FEVT_CNIBAC12E     MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // Force Event Command Not Executed By Auto Command 12 Error

  317. #define SDHC_FEVT_AC12IE      MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Force Event Auto Command 12 Index Error

  318. #define SDHC_FEVT_AC12EBE     MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)    // Force Event Auto Command 12 End Bit Error

  319. #define SDHC_FEVT_AC12CE      MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)    // Force Event Auto Command 12 CRC Error

  320. #define SDHC_FEVT_AC12TOE     MAKE_REG_MASK(0x1,1)  //((uint32_t)0x00000002)    // Force Event Auto Command 12 Time Out Error

  321. #define SDHC_FEVT_AC12NE      MAKE_REG_MASK(0x1,0)  //((uint32_t)0x00000001)    // Force Event Auto Command 12 Not Executed

  322. 

  323. #define SDHC_ADMAES_ADMADCE     MAKE_REG_MASK(0x1,3)  //((uint32_t)0x00000008)

  324. #define SDHC_ADMAES_ADMALME     MAKE_REG_MASK(0x1,2)  //((uint32_t)0x00000004)

  325. #define SDHC_ADMAES_ADMAES_MASK   MAKE_REG_MASK(0x3,0)  //((uint32_t)0x00000003)

  326. 

  327. #define SDHC_MMCBOOT_BOOTBLKCNT(n)  MAKE_REG_MASK(0xFF,16)  //(uint32_t)(((n) & 0xFFF)<<16) // stop at block gap value of automatic mode

  328. #define SDHC_MMCBOOT_AUTOSABGEN   MAKE_REG_MASK(0x1,7)  //((uint32_t)0x00000080)    // enable auto stop at block gap function

  329. #define SDHC_MMCBOOT_BOOTEN     MAKE_REG_MASK(0x1,6)  //((uint32_t)0x00000040)    // Boot Mode Enable

  330. #define SDHC_MMCBOOT_BOOTMODE   MAKE_REG_MASK(0x1,5)  //((uint32_t)0x00000020)    // Boot Mode Select

  331. #define SDHC_MMCBOOT_BOOTACK    MAKE_REG_MASK(0x1,4)  //((uint32_t)0x00000010)    // Boot Ack Mode Select

  332. #define SDHC_MMCBOOT_DTOCVACK(n)  MAKE_REG_MASK(0xF,0)  //(uint32_t)(((n) & 0xF)<<0)  // Boot ACK Time Out Counter Value

  333. //#define SDHC_HOSTVER    (*(volatile uint32_t *)0x400B10FC) // Host Controller Version

  334. 

  335. #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK 0x3f

  336. #define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((n) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)

  337. #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f<<8)

  338. #define CCM_ANALOG_PFD_528_PFD1_FRAC(n) (((n)<<8) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)

  339. #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f<<16)

  340. #define CCM_ANALOG_PFD_528_PFD2_FRAC(n) (((n)<<16) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)

  341. #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK ((0x3f<<24)

  342. #define CCM_ANALOG_PFD_528_PFD3_FRAC(n) (((n)<<24) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)

  343. 

  344. #define SDHC_DSADDR       (USDHC1_DS_ADDR ) // DMA System Address register

  345. #define SDHC_BLKATTR      (USDHC1_BLK_ATT) // Block Attributes register

  346. #define SDHC_CMDARG       (USDHC1_CMD_ARG) // Command Argument register

  347. #define SDHC_XFERTYP      (USDHC1_CMD_XFR_TYP) // Transfer Type register

  348. #define SDHC_CMDRSP0      (USDHC1_CMD_RSP0) // Command Response 0

  349. #define SDHC_CMDRSP1      (USDHC1_CMD_RSP1) // Command Response 1

  350. #define SDHC_CMDRSP2      (USDHC1_CMD_RSP2) // Command Response 2

  351. #define SDHC_CMDRSP3      (USDHC1_CMD_RSP3) // Command Response 3

  352. #define SDHC_DATPORT      (USDHC1_DATA_BUFF_ACC_PORT) // Buffer Data Port register

  353. #define SDHC_PRSSTAT      (USDHC1_PRES_STATE) // Present State register

  354. #define SDHC_PROCTL       (USDHC1_PROT_CTRL) // Protocol Control register

  355. #define SDHC_SYSCTL       (USDHC1_SYS_CTRL) // System Control register

  356. #define SDHC_IRQSTAT      (USDHC1_INT_STATUS) // Interrupt Status register

  357. #define SDHC_IRQSTATEN      (USDHC1_INT_STATUS_EN) // Interrupt Status Enable register

  358. #define SDHC_IRQSIGEN     (USDHC1_INT_SIGNAL_EN) // Interrupt Signal Enable register

  359. #define SDHC_AC12ERR      (USDHC1_AUTOCMD12_ERR_STATUS) // Auto CMD12 Error Status Register

  360. #define SDHC_HTCAPBLT     (USDHC1_HOST_CTRL_CAP) // Host Controller Capabilities

  361. #define SDHC_WML        (USDHC1_WTMK_LVL) // Watermark Level Register

  362. #define SDHC_MIX_CTRL     (USDHC1_MIX_CTRL) // Mixer Control

  363. #define SDHC_FEVT       (USDHC1_FORCE_EVENT) // Force Event register

  364. #define SDHC_ADMAES       (USDHC1_ADMA_ERR_STATUS) // ADMA Error Status register

  365. #define SDHC_ADSADDR      (USDHC1_ADMA_SYS_ADDR) // ADMA System Addressregister

  366. #define SDHC_VENDOR       (USDHC1_VEND_SPEC) // Vendor Specific register

  367. #define SDHC_MMCBOOT      (USDHC1_MMC_BOOT) // MMC Boot register

  368. #define SDHC_VENDOR2    (USDHC2_VEND_SPEC2) // Vendor Specific2 register

  369. //

  370. #define IRQ_SDHC    IRQ_SDHC1

  371. 

  372. #define SDHC_MAX_DVS (0xF + 1U)

  373. #define SDHC_MAX_CLKFS (0xFF + 1U)

  374. #define SDHC_PREV_DVS(x) ((x) -= 1U)

  375. #define SDHC_PREV_CLKFS(x, y) ((x) >>= (y))

  376. 

  377. #define CCM_CSCDR1_USDHC1_CLK_PODF_MASK (0x7<<11)

  378. #define CCM_CSCDR1_USDHC1_CLK_PODF(n) (((n)&0x7)<<11)

  379. 

  380. #define IOMUXC_SW_PAD_CTL_PAD_SRE     ((0x1<)<0)

  381. #define IOMUXC_SW_PAD_CTL_PAD_PKE     ((0x1)<<12)

  382. #define IOMUXC_SW_PAD_CTL_PAD_PUE       ((0x1)<<13)

  383. #define IOMUXC_SW_PAD_CTL_PAD_HYS       ((0x1)<<16)

  384. #define IOMUXC_SW_PAD_CTL_PAD_SPEED(n)  (((n)&0x3)<<6)

  385. #define IOMUXC_SW_PAD_CTL_PAD_PUS(n)    (((n)&0x3)<<14)

  386. #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK  ((0x3)<<14)

  387. #define IOMUXC_SW_PAD_CTL_PAD_DSE(n)    (((n)&0x7)<<3)

  388. #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK  ((0x7)<<3)

  389. 

  390. #endif

  391. 

  392. #define SDHC_IRQSIGEN_DMA_MASK (SDHC_IRQSIGEN_TCIEN | SDHC_IRQSIGEN_DINTIEN | SDHC_IRQSIGEN_DMAEIEN)

  393. #define CARD_STATUS_READY_FOR_DATA  (1UL << 8)

  394. 

  395. /******************************************************************************

  396.   Types

  397. ******************************************************************************/

  398. typedef struct {

  399.   uint8_t  status;

  400.   uint8_t  highCapacity;

  401.   uint8_t  version2;

  402.   uint8_t  tranSpeed;

  403.   uint32_t address;

  404.   uint32_t numBlocks;

  405.   uint32_t lastCardStatus;

  406. } SD_CARD_DESCRIPTOR;

  407. 

  408. /******************************************************************************

  409.   Global functions

  410. ******************************************************************************/

  411. 

  412. /******************************************************************************

  413.   Private variables

  414. ******************************************************************************/

  415. 

  416. static SD_CARD_DESCRIPTOR sdCardDesc;

  417. static volatile uint32_t dmaDone=0;

  418. //

  419. 

  420. /******************************************************************************

  421.   Forward declaration of private functions

  422. ******************************************************************************/

  423. static void sdhc_setSdclk(uint32_t kHzMax);

  424. 

  425. static uint8_t SDHC_Init(void);

  426. static void SDHC_InitGPIO(void);

  427. static void SDHC_ReleaseGPIO(void);

  428. static void SDHC_SetClock(uint32_t sysctl);

  429. static uint32_t SDHC_WaitStatus(uint32_t mask);

  430. static int SDHC_ReadBlock(uint32_t* pData);

  431. static int SDHC_WriteBlock(const uint32_t* pData);

  432. static int SDHC_CMD_Do(uint32_t xfertyp);

  433. static int SDHC_CMD0_GoToIdle(void);

  434. static int SDHC_CMD2_Identify(void);

  435. static int SDHC_CMD3_GetAddress(void);

  436. static int SDHC_ACMD6_SetBusWidth(uint32_t address, uint32_t width);

  437. static int SDHC_CMD7_SelectCard(uint32_t address);

  438. static int SDHC_CMD8_SetInterface(uint32_t cond);

  439. static int SDHC_CMD9_GetParameters(uint32_t address);

  440. static int SDHC_CMD12_StopTransfer(void);

  441. static int SDHC_CMD12_StopTransferWaitForBusy(void);

  442. static int SDHC_CMD16_SetBlockSize(uint32_t block_size);

  443. static int SDHC_CMD17_ReadBlock(uint32_t sector);

  444. static int SDHC_CMD24_WriteBlock(uint32_t sector);

  445. static int SDHC_ACMD41_SendOperationCond(uint32_t cond);

  446. 

  447. /******************************************************************************

  448. 

  449.     Public functions

  450. 

  451. ******************************************************************************/

  452. uint8_t SDHC_CardGetType(void)

  453. {

  454.   if (sdCardDesc.status) return 0;

  455.   if (sdCardDesc.version2 == 0) return 1; // SD_CARD_TYPE_SD1

  456.   if (sdCardDesc.highCapacity == 0) return 2; // SD_CARD_TYPE_SD2

  457.   return 3; // SD_CARD_TYPE_SDHC

  458. }

  459. 

  460. //-----------------------------------------------------------------------------

  461. // initialize the SDHC Controller and SD Card

  462. // returns status of initialization(OK, nonInit, noCard, CardProtected)

  463. uint8_t SDHC_CardInit(void)

  464. {

  465.   uint8_t resS;

  466.   int resR;

  467. 

  468.   resS = SDHC_Init();

  469. 

  470.   sdCardDesc.status = resS;

  471.   sdCardDesc.address = 0;

  472.   sdCardDesc.highCapacity = 0;

  473.   sdCardDesc.version2 = 0;

  474.   sdCardDesc.numBlocks = 0;

  475. 

  476.   if (resS)  return resS;

  477.   SDHC_IRQSIGEN = 0;

  478. 

  479.   resR = SDHC_CMD0_GoToIdle();

  480.   if (resR) { return sdCardDesc.status = SDHC_STATUS_NOINIT;}

  481.   

  482.   resR = SDHC_CMD8_SetInterface(0x000001AA); // 3.3V and AA check pattern

  483.   if (resR == SDHC_RESULT_OK) 

  484.   { if (SDHC_CMDRSP0 != 0x000001AA) return sdCardDesc.status = SDHC_STATUS_NOINIT;

  485.     sdCardDesc.highCapacity = 1;

  486.   } 

  487.   else if (resR == SDHC_RESULT_NO_RESPONSE) 

  488.   { // version 1 cards do not respond to CMD8

  489.   } 

  490.   else return sdCardDesc.status = SDHC_STATUS_NOINIT;

  491. 

  492.   if (SDHC_ACMD41_SendOperationCond(0))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  493. 

  494.   if (SDHC_CMDRSP0 & 0x300000) {

  495.     uint32_t condition = 0x00300000;

  496.     if (sdCardDesc.highCapacity) condition |= 0x40000000;

  497.     //

  498.     uint32_t ii = 0;

  499.     do {

  500.       ii++;

  501.       if (SDHC_ACMD41_SendOperationCond(condition)) {

  502.         resS = SDHC_STATUS_NOINIT;

  503.         break;

  504.       }

  505.     } while ((!(SDHC_CMDRSP0 & 0x80000000)) && (ii < SDHC_INITIALIZATION_MAX_CNT));

  506. 

  507.     if (resS) return resS;

  508. 

  509.     if ((ii >= SDHC_INITIALIZATION_MAX_CNT) || (!(SDHC_CMDRSP0 & 0x40000000)))

  510.       sdCardDesc.highCapacity = 0;

  511.   }

  512. 

  513.   // Card identify

  514.   if (SDHC_CMD2_Identify())  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  515.   

  516.   // Get card address

  517.   if (SDHC_CMD3_GetAddress())  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  518. 

  519.   sdCardDesc.address = SDHC_CMDRSP0 & 0xFFFF0000;

  520. 

  521.   // Get card parameters

  522.   if (SDHC_CMD9_GetParameters(sdCardDesc.address))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  523. 

  524.   if (!(SDHC_CMDRSP3 & 0x00C00000)) {

  525.     uint32_t read_bl_len, c_size, c_size_mult;

  526. 

  527.     read_bl_len = (SDHC_CMDRSP2 >> 8) & 0x0F;

  528.     c_size = SDHC_CMDRSP2 & 0x03;

  529.     c_size = (c_size << 10) | (SDHC_CMDRSP1 >> 22);

  530.     c_size_mult = (SDHC_CMDRSP1 >> 7) & 0x07;

  531.     sdCardDesc.numBlocks = (c_size + 1) * (1 << (c_size_mult + 2)) * (1 << (read_bl_len - 9));

  532.   } else {

  533.     uint32_t c_size;

  534.     sdCardDesc.version2 = 1;

  535.     c_size = (SDHC_CMDRSP1 >> 8) & 0x003FFFFF;

  536.     sdCardDesc.numBlocks = (c_size + 1) << 10;

  537.   }

  538. 

  539.   // Select card

  540.   if (SDHC_CMD7_SelectCard(sdCardDesc.address)) return sdCardDesc.status = SDHC_STATUS_NOINIT;

  541. 

  542.   // Set Block Size to 512

  543.   // Block Size in SDHC Controller is already set to 512 by SDHC_Init();

  544.   // Set 512 Block size in SD card

  545.   if (SDHC_CMD16_SetBlockSize(SDHC_BLOCK_SIZE))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  546. 

  547.   // Set 4 bit data bus width

  548.   if (SDHC_ACMD6_SetBusWidth(sdCardDesc.address, 2))  return sdCardDesc.status = SDHC_STATUS_NOINIT;

  549. 

  550.   // Set Data bus width also in SDHC controller

  551.   SDHC_PROCTL &= ~SDHC_PROCTL_DTW_MASK;

  552.   SDHC_PROCTL |= SDHC_PROCTL_DTW(SDHC_PROCTL_DTW_4BIT);

  553.   

  554.   // De-Init GPIO

  555.   SDHC_ReleaseGPIO();

  556. 

  557.   // Set the SDHC default baud rate

  558.   sdhc_setSdclk(25000);

  559.   // SDHC_SetClock(SDHC_SYSCTL_25MHZ);

  560.   // TODO: use CMD6 and CMD9 to detect if card supports 50 MHz

  561.   // then use CMD4 to configure card to high speed mode,

  562.   // and SDHC_SetClock() for 50 MHz config

  563. 

  564.   // Init GPIO

  565.   SDHC_InitGPIO();

  566. 

  567.   return sdCardDesc.status;

  568. }

  569. 

  570. //-----------------------------------------------------------------------------

  571. // FUNCTION:    SDHC_CardReadBlock (disk_read)

  572. // SCOPE:       SDHC public related function

  573. // DESCRIPTION: Function read block to disk

  574. //

  575. // PARAMETERS:  buff - pointer on buffer where read data should be stored

  576. //              sector - index of sector

  577. //

  578. // RETURNS:     result of operation

  579. //-----------------------------------------------------------------------------

  580. int SDHC_CardReadBlock(void * buff, uint32_t sector)

  581. {

  582.   int result=0;

  583.   uint32_t* pData = (uint32_t*)buff;

  584.   /* check alignment for DMA */

  585.   if (reinterpret_cast<uintptr_t>(static_cast<const void*>(buff)) % 4) {

  586.     return -1;

  587.   }

  588. //  Serial.print("Sector: "); Serial.println(sector); Serial.flush();

  589.   // Check if this is ready

  590.   if (sdCardDesc.status != 0) return SDHC_RESULT_NOT_READY;

  591. 

  592.   while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB));

  593. 

  594.   // Convert LBA to BYTE address if needed

  595.   if (!sdCardDesc.highCapacity)  sector *= 512;

  596. 

  597.   // clear status

  598.   SDHC_IRQSTAT = SDHC_IRQSTAT;

  599.   

  600.   // use dma: disabling polling

  601.   uint32_t irqstat = SDHC_IRQSTATEN;

  602.   irqstat &= ~(SDHC_IRQSTATEN_BRRSEN | SDHC_IRQSTATEN_BWRSEN | SDHC_IRQSTATEN_CCSEN) ;

  603.   irqstat &= ~(SDHC_IRQSTATEN_DCESEN | SDHC_IRQSTATEN_CCESEN) ;

  604.   // enable status

  605.   irqstat |= SDHC_IRQSTATEN_DMAESEN | SDHC_IRQSTATEN_DINTSEN | SDHC_IRQSTATEN_TCSEN ;

  606.   SDHC_IRQSTATEN = irqstat;

  607.   

  608.   uint32_t sigen = SDHC_IRQSIGEN;

  609.   sigen |= SDHC_IRQSIGEN_DMA_MASK ;

  610.   

  611.   SDHC_SYSCTL |= SDHC_SYSCTL_HCKEN;

  612.   #if defined(__IMXRT1052__)

  613.     SDHC_MIX_CTRL |= SDHC_MIX_CTRL_DTDSEL ; // read

  614.     SDHC_MIX_CTRL |=  SDHC_MIX_CTRL_DMAEN ; // DMA

  615.   #endif

  616. 

  617.   uint32_t xfertyp = SDHC_XFERTYP_CMDINX(SDHC_CMD17) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) | SDHC_XFERTYP_DPSEL

  618.                      | SDHC_XFERTYP_DTDSEL | SDHC_XFERTYP_DMAEN;

  619. 

  620.   dmaDone=0;

  621.   SDHC_DSADDR  = (uint32_t)buff;

  622.   SDHC_CMDARG = sector;

  623.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | SDHC_BLKATTR_BLKSIZE(512);

  624.   SDHC_IRQSIGEN = sigen;

  625.   SDHC_XFERTYP = xfertyp;

  626.   //

  627.   while(!dmaDone);

  628.   SDHC_IRQSTAT &= (SDHC_IRQSTAT_CC | SDHC_IRQSTAT_TC);

  629. 

  630.   return result;

  631. }

  632. 

  633. //-----------------------------------------------------------------------------

  634. // FUNCTION:    SDHC_CardWriteBlock (disk_write)

  635. // SCOPE:       SDHC public related function

  636. // DESCRIPTION: Function write block to disk

  637. //

  638. // PARAMETERS:  buff - pointer on buffer where is stored data

  639. //              sector - index of sector

  640. //

  641. // RETURNS:     result of operation

  642. //-----------------------------------------------------------------------------

  643. int SDHC_CardWriteBlock(const void * buff, uint32_t sector)

  644. {

  645.   int result=0;

  646.   const uint32_t *pData = (const uint32_t *)buff;

  647.   /* check alignment for DMA */

  648.   if (reinterpret_cast<uintptr_t>(static_cast<const void*>(buff)) % 4) {

  649.     return -1;

  650.   }

  651. 

  652.   // Check if this is ready

  653.   if (sdCardDesc.status != 0) return SDHC_RESULT_NOT_READY;

  654. 

  655.   while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB)) ;

  656. 

  657.   // Convert LBA to uint8_t address if needed

  658.   if (!sdCardDesc.highCapacity) sector *= 512;

  659. 

  660.   // clear status

  661.   SDHC_IRQSTAT = SDHC_IRQSTAT;

  662. 

  663.   uint32_t irqstat = SDHC_IRQSTATEN;

  664.   // use dma: disabling polling

  665.   irqstat &= ~(SDHC_IRQSTATEN_BRRSEN | SDHC_IRQSTATEN_BWRSEN | SDHC_IRQSTATEN_CCSEN) ;

  666.   irqstat &= ~(SDHC_IRQSTATEN_DCESEN | SDHC_IRQSTATEN_CCESEN) ;

  667.   // enable status

  668.   irqstat |= /*SDHC_IRQSTATEN_DCESEN | SDHC_IRQSTATEN_CCESEN | */SDHC_IRQSTATEN_DMAESEN ; 

  669.   irqstat |= SDHC_IRQSTATEN_DINTSEN | SDHC_IRQSTATEN_TCSEN ; 

  670.   SDHC_IRQSTATEN = irqstat;

  671.   

  672.   uint32_t sigen = SDHC_IRQSIGEN;

  673.   sigen |= SDHC_IRQSIGEN_DMA_MASK ;

  674.   

  675.   SDHC_SYSCTL |= SDHC_SYSCTL_HCKEN;

  676.   

  677.   #if defined(__IMXRT1052__)

  678.     SDHC_MIX_CTRL &= ~ SDHC_MIX_CTRL_DTDSEL;  // write

  679.     SDHC_MIX_CTRL |=  SDHC_MIX_CTRL_DMAEN ;   //DMA

  680.   #endif

  681. 

  682.   uint32_t xfertyp = SDHC_XFERTYP_CMDINX(SDHC_CMD24) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) | SDHC_XFERTYP_DPSEL

  683.                      | SDHC_XFERTYP_DMAEN;

  684. 

  685.   dmaDone=0;

  686.   SDHC_DSADDR  = (uint32_t)buff;

  687.   SDHC_CMDARG = sector;

  688.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | SDHC_BLKATTR_BLKSIZE(512);

  689.   SDHC_IRQSIGEN = sigen;

  690.   SDHC_XFERTYP = xfertyp;

  691.   //

  692.   while(!dmaDone);

  693.   SDHC_IRQSTAT &= (SDHC_IRQSTAT_CC | SDHC_IRQSTAT_TC);

  694. 

  695.   while(SDHC_PRSSTAT & SDHC_PRSSTAT_DLA);

  696. 

  697.   //check for uSD status

  698.   do

  699.   { while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB)) ;

  700.     SDHC_IRQSTATEN |= SDHC_IRQSTATEN_CCSEN;

  701.     SDHC_IRQSTAT=SDHC_IRQSTAT;

  702.     // CMD13 to check uSD status

  703.     xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD13) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  704.     //

  705.     SDHC_CMDARG = sdCardDesc.address;

  706.     SDHC_XFERTYP = xfertyp;

  707.     while(!(SDHC_IRQSTAT & SDHC_IRQSTAT_CC)); SDHC_IRQSTAT &= SDHC_IRQSTAT_CC;

  708.   } while(SDHC_CMDRSP0 & 0x200); // while data?

  709. //  } while(!(SDHC_CMDRSP0 & CARD_STATUS_READY_FOR_DATA ));

  710. 

  711.   return result;

  712. }

  713. 

  714. /******************************************************************************

  715. 

  716.     Private functions

  717. 

  718. ******************************************************************************/

  719. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  720.   // initialize the SDHC Controller signals

  721.   static void SDHC_InitGPIO(void)

  722.   {

  723.     PORTE_PCR0 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D1  */

  724.     PORTE_PCR1 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D0  */

  725.     PORTE_PCR2 = PORT_PCR_MUX(4) | PORT_PCR_DSE;                             /* SDHC.CLK */

  726.     PORTE_PCR3 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.CMD */

  727.     PORTE_PCR4 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D3  */

  728.     PORTE_PCR5 = PORT_PCR_MUX(4) | PORT_PCR_PS | PORT_PCR_PE | PORT_PCR_DSE; /* SDHC.D2  */

  729.   }

  730.   

  731.   // release the SDHC Controller signals

  732.   static void SDHC_ReleaseGPIO(void)

  733.   {

  734.     PORTE_PCR0 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.D1  */

  735.     PORTE_PCR1 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.D0  */

  736.     PORTE_PCR2 = 0;           /* SDHC.CLK */

  737.     PORTE_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.CMD */

  738.     PORTE_PCR4 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS; /* PULLUP SDHC.D3  */

  739.     PORTE_PCR5 = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;   /* PULLUP SDHC.D2  */

  740.   }

  741.   

  742.   void initClock()

  743.   {

  744.   #ifdef HAS_KINETIS_MPU

  745.     // Allow SDHC Bus Master access.

  746.     MPU_RGDAAC0 |= 0x0C000000;

  747.   #endif

  748.     // Enable SDHC clock.

  749.     SIM_SCGC3 |= SIM_SCGC3_SDHC;

  750.   }

  751.   

  752.   uint32_t sdhcClock()

  753.   { return F_CPU;

  754.   }

  755. 

  756. #else

  757. 

  758.   static void SDHC_InitGPIO(void)

  759.   {

  760.     { 											//T4                      

  761.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 0; //DAT2  

  762.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 0; //DAT3  

  763.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 0; //CMD   

  764.       //3.3V                                           

  765.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 0; //CLK   

  766.       //GND                                           

  767.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 0; //DAT0 

  768.       IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 0; //DAT1 

  769.   

  770.       const uint32_t CLOCK_MASK = IOMUXC_SW_PAD_CTL_PAD_PKE |

  771.                                   IOMUXC_SW_PAD_CTL_PAD_DSE(1) |

  772.                                   IOMUXC_SW_PAD_CTL_PAD_SPEED(2);

  773.   

  774.       const uint32_t DATA_MASK = CLOCK_MASK |

  775.                                  (IOMUXC_SW_PAD_CTL_PAD_PUE | IOMUXC_SW_PAD_CTL_PAD_PUS(1));

  776.   

  777.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = DATA_MASK;

  778.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = DATA_MASK;

  779.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = DATA_MASK;

  780.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = CLOCK_MASK;

  781.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = DATA_MASK;

  782.       IOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = DATA_MASK;

  783.     }

  784.   }

  785.   

  786.   static void SDHC_ReleaseGPIO(void)

  787.   {

  788.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 5; //GPIO3_IO16

  789.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 5; //GPIO3_IO17

  790.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 5; //GPIO3_IO12

  791.     //3.3V

  792.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 5; //GPIO3_IO13

  793.     //GND

  794.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 5; //GPIO3_IO14

  795.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 5; //GPIO3_IO15

  796.   }

  797.   

  798.   void initClock()

  799.   {

  800.     /* set PDF_528 PLL2PFD0 */

  801.     CCM_ANALOG_PFD_528 |= (1 << 7);

  802.     CCM_ANALOG_PFD_528 &= ~(0x3F << 0);

  803.     CCM_ANALOG_PFD_528 |= ((24) & 0x3F << 0); // 12 - 35

  804.     CCM_ANALOG_PFD_528 &= ~(1 << 7);

  805.   

  806.     /* Enable USDHC clock. */

  807.     CCM_CCGR6 |= CCM_CCGR6_USDHC1(CCM_CCGR_ON);

  808.     CCM_CSCDR1 &= ~(CCM_CSCDR1_USDHC1_CLK_PODF_MASK);

  809.     //

  810.     //  CCM_CSCMR1 &= ~(CCM_CSCMR1_USDHC1_CLK_SEL);     // PLL2PFD2

  811.     CCM_CSCMR1 |= CCM_CSCMR1_USDHC1_CLK_SEL;          // PLL2PFD0

  812.     CCM_CSCDR1 |= CCM_CSCDR1_USDHC1_CLK_PODF((7)); // &0x7

  813.   

  814.     // for testing

  815.     CCM_CCOSR = CCM_CCOSR_CLKO1_EN | CCM_CCOSR_CLKO1_DIV(7) | CCM_CCOSR_CLKO1_SEL(1); //(1: SYS_PLL/2)

  816.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 6; //CCM_CLKO1 (0 is USDHC1_DAT2)

  817.     // for testing

  818.     CCM_CCOSR |= (CCM_CCOSR_CLKO2_EN | CCM_CCOSR_CLKO2_DIV(7) | CCM_CCOSR_CLKO2_SEL(3)); //(3: usdhc1_clk_root))

  819.     IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 6; //CCM_CLKO2 (0 is USDHC1_DAT3)

  820.   }

  821.   

  822.   uint32_t sdhcClock()

  823.   {

  824.     uint32_t divider = ((CCM_CSCDR1 >> 11) & 0x7) + 1;

  825.     uint32_t PLL2PFD0 = (528000000U * 3) / ((CCM_ANALOG_PFD_528 & 0x3F) / 6) / divider;

  826.     return PLL2PFD0;

  827.   }

  828. 

  829. #endif

  830. /* //may be useful for debugging

  831. static void printRegs()

  832. {

  833. // Serial.print("DS_ADDR: "); Serial.println(SDHC_DSADDR,HEX);        // DMA System Address register

  834.  Serial.print("BLK_ATT:       "); Serial.println(SDHC_BLKATTR,HEX);       // Block Attributes register

  835. // Serial.print("CMD_ARG: "); Serial.println(SDHC_CMDARG,HEX);        // Command Argument register

  836. // Serial.print("CMD_XFR_TYP: "); Serial.println(SDHC_XFERTYP,HEX);    // Transfer Type register

  837. // Serial.print("CMD_RSP0: "); Serial.println(SDHC_CMDRSP0,HEX);       // Command Response 0

  838. // Serial.print("CMD_RSP1: "); Serial.println(SDHC_CMDRSP1,HEX);       // Command Response 1

  839. // Serial.print("CMD_RSP2: "); Serial.println(SDHC_CMDRSP2,HEX);       // Command Response 2

  840. // Serial.print("CMD_RSP3: "); Serial.println(SDHC_CMDRSP3,HEX);       // Command Response 3

  841. // Serial.print("DATA_BUFF_ACC_POR: "); Serial.println(SDHC_DATPORT,HEX); // Buffer Data Port register

  842.  Serial.print("PRES_STATE:    "); Serial.println(SDHC_PRSSTAT,HEX);     // Present State register

  843.  Serial.print("PROT_CTRL:     "); Serial.println(SDHC_PROCTL,HEX);      // Protocol Control register

  844.  Serial.print("SYS_CTRL:      "); Serial.println(SDHC_SYSCTL,HEX);        // System Control register

  845.  Serial.print("INT_STATUS:    "); Serial.println(SDHC_IRQSTAT,HEX);      // Interrupt Status register

  846.  Serial.print("INT_STATUS_EN: "); Serial.println(SDHC_IRQSTATEN,HEX);    // Interrupt Status Enable register

  847.  Serial.print("INT_SIGNAL_EN: "); Serial.println(SDHC_IRQSIGEN,HEX);      // Interrupt Signal Enable register

  848. // Serial.print("AUTOCMD12_ERR_STATUS: "); Serial.println(SDHC_AC12ERR,HEX); // Auto CMD12 Error Status Register

  849.  Serial.print("HOST_CTRL_CAP: "); Serial.println(SDHC_HTCAPBLT,HEX);  // Host Controller Capabilities

  850.  Serial.print("WTMK_LVL:      "); Serial.println(SDHC_WML,HEX);        // Watermark Level Register

  851.  #if defined(__IMXRT1052__)

  852.  Serial.print("MIX_CTRL:      "); Serial.println(SDHC_MIX_CTRL,HEX);     // Mixer Control

  853.  #endif

  854. // Serial.print("FORCE_EVENT:   "); Serial.println(SDHC_FEVT,HEX);      // Force Event register

  855. // Serial.print("ADMA_ERR_STATUS: "); Serial.println(SDHC_ADMAES,HEX); // ADMA Error Status register

  856. // Serial.print("ADMA_SYS_ADDR: "); Serial.println(SDHC_ADSADDR,HEX);  // ADMA System Addressregister

  857.  Serial.print("VEND_SPEC:     "); Serial.println(SDHC_VENDOR,HEX);       // Vendor Specific register

  858. // Serial.print("MMC_BOOT:      "); Serial.println(SDHC_MMCBOOT,HEX);      // MMC Boot register

  859.  #if defined(__IMXRT1052__)

  860.  Serial.print("VEND_SPEC2:    "); Serial.println(SDHC_VENDOR2,HEX);    // Vendor Specific2 register

  861.  #endif

  862. }

  863. */

  864. 

  865. static void sdhc_setSdclk(uint32_t kHzMax) {

  866.   const uint32_t DVS_LIMIT = 0X10;

  867.   const uint32_t SDCLKFS_LIMIT = 0X100;

  868.   uint32_t dvs = 1;

  869.   uint32_t sdclkfs = 1;

  870.   uint32_t maxSdclk = 1000 * kHzMax;

  871. 

  872.   //  uint32_t f_pll = F_CPU;

  873.   uint32_t f_pll = sdhcClock();

  874. 

  875.   while ((f_pll / (sdclkfs * DVS_LIMIT) > maxSdclk) && (sdclkfs < SDCLKFS_LIMIT)) {

  876.     sdclkfs <<= 1;

  877.   }

  878.   while ((f_pll / (sdclkfs * dvs) > maxSdclk) && (dvs < DVS_LIMIT)) {

  879.     dvs++;

  880.   }

  881.   uint32_t m_sdClkKhz = f_pll / (1000 * sdclkfs * dvs);

  882. 

  883.   sdclkfs >>= 1;

  884.   dvs--;

  885. 

  886. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  887.   // Disable SDHC clock.

  888.   SDHC_SYSCTL &= ~SDHC_SYSCTL_SDCLKEN;

  889. #endif

  890. 

  891.   // Change dividers.

  892.   uint32_t sysctl = SDHC_SYSCTL & ~(SDHC_SYSCTL_DTOCV_MASK

  893.                                     | SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK);

  894. 

  895.   SDHC_SYSCTL = sysctl | SDHC_SYSCTL_DTOCV(0x0E) | SDHC_SYSCTL_DVS(dvs)

  896.                 | SDHC_SYSCTL_SDCLKFS(sdclkfs);

  897. 

  898.   // Wait until the SDHC clock is stable.

  899.   while (!(SDHC_PRSSTAT & SDHC_PRSSTAT_SDSTB)) { }

  900. 

  901. #if defined(__MK64FX512__) || defined(__MK66FX1M0__)

  902.   // Enable the SDHC clock.

  903.   SDHC_SYSCTL |= SDHC_SYSCTL_SDCLKEN;

  904. #endif

  905. 

  906. //  Serial.printf("setSdclk: %d %d : %x %x\n\r", f_pll, m_sdClkKhz, sdclkfs, dvs);

  907. }

  908. 

  909. 

  910. void sdhc_isr(void)

  911. { SDHC_IRQSIGEN &= ~SDHC_IRQSIGEN_DMA_MASK;

  912.   //

  913. //  Serial.print("IRQ1: "); Serial.println(SDHC_IRQSTAT,HEX);

  914.   while(!(SDHC_IRQSTAT & SDHC_IRQSTAT_TC));//  SDHC_IRQSTAT &= ~SDHC_IRQSTAT_TC;

  915. 

  916.   #if defined(__IMXRT1052__)

  917.     SDHC_MIX_CTRL &= ~(SDHC_MIX_CTRL_AC23EN | SDHC_MIX_CTRL_DMAEN) ;  

  918.   #endif

  919.   // for T3.6, seems not to hurt for T4  

  920.   if(SDHC_SYSCTL & SDHC_SYSCTL_HCKEN) SDHC_SYSCTL &=  ~SDHC_SYSCTL_HCKEN;

  921.   SDHC_PROCTL &= ~SDHC_PROCTL_D3CD; SDHC_PROCTL |=  SDHC_PROCTL_D3CD;

  922. 

  923.   dmaDone=1;

  924. }

  925. 

  926. // initialize the SDHC Controller

  927. // returns status of initialization(OK, nonInit, noCard, CardProtected)

  928. static uint8_t SDHC_Init(void)

  929. {

  930.   initClock();

  931.   

  932.   // De-init GPIO - to prevent unwanted clocks on bus

  933.   SDHC_ReleaseGPIO();

  934. 

  935.   #if defined (__IMXRT1052__)

  936.     SDHC_SYSCTL   |= 0xF;

  937.     SDHC_MIX_CTRL |= 0x80000000;

  938.   #endif  

  939. 

  940.   /* Reset SDHC */

  941.   SDHC_SYSCTL |= SDHC_SYSCTL_RSTA | SDHC_SYSCTL_SDCLKFS(0x80);

  942.   while (SDHC_SYSCTL & SDHC_SYSCTL_RSTA) ; // wait

  943. 

  944.   /* Set the SDHC initial baud rate divider and start */

  945.   sdhc_setSdclk(400);

  946. 

  947.   /* Poll inhibit bits */

  948.   while (SDHC_PRSSTAT & (SDHC_PRSSTAT_CIHB | SDHC_PRSSTAT_CDIHB)) ;

  949. 

  950.   /* Init GPIO again */

  951.   SDHC_InitGPIO();

  952. 

  953.   /* Initial values */ // to do - Check values

  954.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | SDHC_BLKATTR_BLKSIZE(512);

  955.   SDHC_PROCTL &= ~SDHC_PROCTL_DMAS(3); // clear ADMA

  956. 

  957.   SDHC_PROCTL |=  SDHC_PROCTL_D3CD;

  958.   // SDHC_PROCTL = SDHC_PROCTL_EMODE(SDHC_PROCTL_EMODE_INVARIANT) | SDHC_PROCTL_D3CD;

  959.   // SDHC_WML |= SDHC_WML_RDWML(SDHC_FIFO_BUFFER_SIZE) | SDHC_WML_WRWML(SDHC_FIFO_BUFFER_SIZE);

  960. 

  961.   #if defined(__IMXRT1052__)

  962.     SDHC_VENDOR = 0x2000F801; // (1<<29 | 0x1F<<11 | 1);

  963.     SDHC_VENDOR2 &= ~(1<<12); //switch off ACMD23 sharing SDMA

  964.   #endif

  965.   

  966.   /* Enable requests */

  967.   // clear interrupt status

  968.   SDHC_IRQSTAT = SDHC_IRQSTAT;

  969. 

  970.   SDHC_IRQSTATEN =  //SDHC_IRQSTAT_CRM | SDHC_IRQSTATEN_CIESEN | 

  971.                     SDHC_IRQSTATEN_TCSEN | SDHC_IRQSTATEN_CCSEN;

  972. 

  973.   attachInterruptVector(IRQ_SDHC, sdhc_isr);

  974.   NVIC_SET_PRIORITY(IRQ_SDHC, 6 * 16);

  975.   NVIC_ENABLE_IRQ(IRQ_SDHC);

  976. 

  977.   // initial clocks... SD spec says only 74 clocks are needed, but if Teensy rebooted

  978.   // while the card was in middle of an operation, thousands of clock cycles can be

  979.   // needed to get the card to complete a prior command and return to a usable state.

  980.   for (int ii = 0; ii < 500; ii++) {

  981.     SDHC_SYSCTL |= SDHC_SYSCTL_INITA;

  982.     while (SDHC_SYSCTL & SDHC_SYSCTL_INITA) ;

  983.   }

  984. 

  985.   // to do - check if this needed

  986.   SDHC_IRQSTAT |= SDHC_IRQSTAT_CRM;

  987.   // Check card

  988.   if (SDHC_PRSSTAT & SDHC_PRSSTAT_CINS) {

  989.     return 0;

  990.   } else {

  991.     return SDHC_STATUS_NODISK;

  992.   }

  993. }

  994. 

  995. /******************************************************************************

  996. 

  997.     Private SD Card functions

  998. 

  999. ******************************************************************************/

  1000. 

  1001. // waits for status bits sets

  1002. static uint32_t SDHC_WaitStatus(uint32_t mask)

  1003. {

  1004.   uint32_t             result;

  1005.   uint32_t             timeout = 1 << 24;

  1006.   do

  1007.   { result = SDHC_IRQSTAT & mask;

  1008.     timeout--;

  1009.   } while (!result && (timeout));

  1010.   if (timeout) return result;

  1011.   return 0;

  1012. }

  1013. 

  1014. //-----------------------------------------------------------------------------------

  1015. // sends the command to SDcard

  1016. static int SDHC_CMD_Do(uint32_t xfertyp)

  1017. {

  1018.   // Card removal check preparation

  1019.   SDHC_IRQSTAT |= SDHC_IRQSTAT_CRM;

  1020. 

  1021.   // Wait for cmd line idle // to do timeout PRSSTAT[CDIHB] and the PRSSTAT[CIHB]

  1022.   while ((SDHC_PRSSTAT & SDHC_PRSSTAT_CIHB) || (SDHC_PRSSTAT & SDHC_PRSSTAT_CDIHB)) { };

  1023.   SDHC_XFERTYP = xfertyp;

  1024. 

  1025.   /* Wait for response */

  1026.   const uint32_t mask = SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE | SDHC_IRQSTAT_CC;

  1027.   if (SDHC_WaitStatus(mask) != SDHC_IRQSTAT_CC)

  1028.   { SDHC_IRQSTAT |= mask;

  1029.     return SDHC_RESULT_ERROR;

  1030.   }

  1031.   /* Check card removal */

  1032.   if (SDHC_IRQSTAT & SDHC_IRQSTAT_CRM) {

  1033.       SDHC_IRQSTAT |= SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;

  1034.       return SDHC_RESULT_NOT_READY;

  1035.   }

  1036.   

  1037.   /* Get response, if available */

  1038.   if (SDHC_IRQSTAT & SDHC_IRQSTAT_CTOE)

  1039.   { SDHC_IRQSTAT |= SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;

  1040.     return SDHC_RESULT_NO_RESPONSE;

  1041.   }

  1042.   SDHC_IRQSTAT |= SDHC_IRQSTAT_CC;

  1043. 

  1044.   return SDHC_RESULT_OK;

  1045. }

  1046. 

  1047. // sends CMD0 to put SDCARD to idle

  1048. static int SDHC_CMD0_GoToIdle(void)

  1049. {

  1050.   uint32_t xfertyp;

  1051.   int result;

  1052. 

  1053.   SDHC_CMDARG = 0;

  1054. 

  1055.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD0) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_NO));

  1056. 

  1057.   result = SDHC_CMD_Do(xfertyp);

  1058. 

  1059.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1060.   return result;

  1061. }

  1062. 

  1063. // sends CMD2 to identify card

  1064. static int SDHC_CMD2_Identify(void)

  1065. {

  1066.   uint32_t xfertyp;

  1067.   int result;

  1068. 

  1069.   SDHC_CMDARG = 0;

  1070. 

  1071.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD2) | SDHC_XFERTYP_CCCEN 

  1072.             | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_136));

  1073. 

  1074.   result = SDHC_CMD_Do(xfertyp);

  1075. 

  1076.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1077. 

  1078.   return result;

  1079. }

  1080. 

  1081. // sends CMD 3 to get address

  1082. static int SDHC_CMD3_GetAddress(void)

  1083. {

  1084.   uint32_t xfertyp;

  1085.   int result;

  1086. 

  1087.   SDHC_CMDARG = 0;

  1088. 

  1089.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD3) | SDHC_XFERTYP_CICEN |

  1090.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1091. 

  1092.   result = SDHC_CMD_Do(xfertyp);

  1093. 

  1094.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1095.   return result;

  1096. }

  1097. 

  1098. // sends ACMD6 to set bus width

  1099. static int SDHC_ACMD6_SetBusWidth(uint32_t address, uint32_t width)

  1100. {

  1101.   uint32_t xfertyp;

  1102.   int result;

  1103. 

  1104.   SDHC_CMDARG = address;

  1105.   // first send CMD 55 Application specific command

  1106.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD55) | SDHC_XFERTYP_CICEN |

  1107.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1108. 

  1109.   result = SDHC_CMD_Do(xfertyp);

  1110.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0;} else { return result; }

  1111.   SDHC_CMDARG = width;

  1112. 

  1113.   // Send CMD6

  1114.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD6) | SDHC_XFERTYP_CICEN |

  1115.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1116. 

  1117.   result = SDHC_CMD_Do(xfertyp);

  1118. 

  1119.   if (result == SDHC_RESULT_OK) {  (void)SDHC_CMDRSP0; }

  1120.   return result;

  1121. }

  1122. 

  1123. 

  1124. // sends CMD 7 to select card

  1125. static int SDHC_CMD7_SelectCard(uint32_t address)

  1126. {

  1127.   uint32_t xfertyp;

  1128.   int result;

  1129. 

  1130.   SDHC_CMDARG = address;

  1131. 

  1132.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD7) | SDHC_XFERTYP_CICEN |

  1133.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48BUSY));

  1134. 

  1135.   result = SDHC_CMD_Do(xfertyp);

  1136. 

  1137.   if (result == SDHC_RESULT_OK) {(void)SDHC_CMDRSP0; }

  1138.   return result;

  1139. }

  1140. 

  1141. // CMD8 to send interface condition

  1142. static int SDHC_CMD8_SetInterface(uint32_t cond)

  1143. {

  1144.   uint32_t xfertyp;

  1145.   int result;

  1146. 

  1147.   SDHC_CMDARG = cond;

  1148. 

  1149.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD8) | SDHC_XFERTYP_CICEN |

  1150.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1151. 

  1152.   result = SDHC_CMD_Do(xfertyp);

  1153. 

  1154.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1155.   return result;

  1156. }

  1157. 

  1158. // sends CMD 9 to get interface condition

  1159. static int SDHC_CMD9_GetParameters(uint32_t address)

  1160. {

  1161.   uint32_t xfertyp;

  1162.   int result;

  1163. 

  1164.   SDHC_CMDARG = address;

  1165. 

  1166.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD9) | SDHC_XFERTYP_CCCEN |

  1167.              SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_136));

  1168. 

  1169.   result = SDHC_CMD_Do(xfertyp);

  1170. 

  1171.   if (result == SDHC_RESULT_OK) {

  1172.     //(void)SDHC_CMDRSP0;

  1173.     sdCardDesc.tranSpeed = SDHC_CMDRSP2 >> 24;

  1174.   }

  1175. 

  1176.   return result;

  1177. }

  1178. 

  1179. // sends CMD12 to stop transfer

  1180. static int SDHC_CMD12_StopTransfer(void)

  1181. {

  1182.   uint32_t xfertyp;

  1183.   int result;

  1184. 

  1185.   SDHC_CMDARG = 0;

  1186.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD12) | SDHC_XFERTYP_CMDTYP(SDHC_XFERTYP_CMDTYP_ABORT) |

  1187.              SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48BUSY));

  1188. 

  1189.   result = SDHC_CMD_Do(xfertyp);

  1190. 

  1191.   if (result == SDHC_RESULT_OK) { }

  1192.   return result;

  1193. }

  1194. 

  1195. // sends CMD12 to stop transfer and first waits to ready SDCArd

  1196. static int SDHC_CMD12_StopTransferWaitForBusy(void)

  1197. {

  1198.   uint32_t timeOut = 1000;

  1199.   int result;

  1200.   do {

  1201.     result = SDHC_CMD12_StopTransfer();

  1202.     timeOut--;

  1203.   } while (timeOut && (SDHC_PRSSTAT & SDHC_PRSSTAT_DLA) && result == SDHC_RESULT_OK);

  1204.   

  1205.   if (result != SDHC_RESULT_OK)  return result;

  1206.   if (!timeOut)  return SDHC_RESULT_NO_RESPONSE;

  1207. 

  1208.   return SDHC_RESULT_OK;

  1209. }

  1210. 

  1211. // sends CMD16 to set block size

  1212. static int SDHC_CMD16_SetBlockSize(uint32_t block_size)

  1213. {

  1214.   uint32_t xfertyp;

  1215.   int result;

  1216. 

  1217.   SDHC_CMDARG = block_size;

  1218. 

  1219.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD16) | SDHC_XFERTYP_CICEN |

  1220.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1221. 

  1222.   result = SDHC_CMD_Do(xfertyp);

  1223. 

  1224.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1225. 

  1226.   return result;

  1227. }

  1228. 

  1229. // sends CMD17 to read one block

  1230. static int SDHC_CMD17_ReadBlock(uint32_t sector)

  1231. {

  1232.   uint32_t xfertyp;

  1233.   int result;

  1234. 

  1235.   SDHC_CMDARG = sector;

  1236. 

  1237.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | 512;

  1238. 

  1239.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD17) | SDHC_XFERTYP_CICEN |

  1240.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) |

  1241.              SDHC_XFERTYP_DTDSEL | SDHC_XFERTYP_DPSEL);

  1242. 

  1243.   result = SDHC_CMD_Do(xfertyp);

  1244.   if (result == SDHC_RESULT_OK) { ( void)SDHC_CMDRSP0; }

  1245. 

  1246.   return result;

  1247. }

  1248. 

  1249. // sends CMD24 to write one block

  1250. static int SDHC_CMD24_WriteBlock(uint32_t sector)

  1251. {

  1252.   uint32_t xfertyp;

  1253.   int result;

  1254. 

  1255.   SDHC_CMDARG = sector;

  1256.   SDHC_BLKATTR = SDHC_BLKATTR_BLKCNT(1) | 512;

  1257. 

  1258.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD24) | SDHC_XFERTYP_CICEN |

  1259.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48) |

  1260.              SDHC_XFERTYP_DPSEL);

  1261. 

  1262.   result = SDHC_CMD_Do(xfertyp);

  1263.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1264. 

  1265.   return result;

  1266. }

  1267. 

  1268. // ACMD 41 to send operation condition

  1269. static int SDHC_ACMD41_SendOperationCond(uint32_t cond)

  1270. {

  1271.   uint32_t xfertyp;

  1272.   int result;

  1273. 

  1274.   SDHC_CMDARG = 0;

  1275.   // first send CMD 55 Application specific command

  1276.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_CMD55) | SDHC_XFERTYP_CICEN |

  1277.              SDHC_XFERTYP_CCCEN | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1278. 

  1279.   result = SDHC_CMD_Do(xfertyp);

  1280. 

  1281.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; } else { return result; }

  1282. 

  1283.   SDHC_CMDARG = cond;

  1284. 

  1285.   // Send 41CMD

  1286.   xfertyp = (SDHC_XFERTYP_CMDINX(SDHC_ACMD41) | SDHC_XFERTYP_RSPTYP(SDHC_XFERTYP_RSPTYP_48));

  1287.   result = SDHC_CMD_Do(xfertyp);

  1288. 

  1289.   if (result == SDHC_RESULT_OK) { (void)SDHC_CMDRSP0; }

  1290. 

  1291.   return result;

  1292. }

  1293. #endif // __MK64FX512__ or __MK66FX1M0__ or __IMXRT1052__