T4 - Add some support for LSB/MSB and MODE

Added - the code to set them as part of the Transaction Setttings.

Also put in implementations for,
SPI.setBitOrder and SPI.setDataMode.
Note the setDatMode like the T3.x does not appear to do anything yet.

SPI.cpp

@@ -1372,6 +1372,23 @@ void SPIClass::setSCK(uint8_t pin)
 }
 
 
+void SPIClass::setBitOrder(uint8_t bitOrder)
+{
+	hardware->clock_gate_register |= hardware->clock_gate_mask;
+
+	if (bitOrder == LSBFIRST) {
+		port->TCR |= LPSPI_TCR_LSBF;
+	} else {
+		port->TCR &= ~LPSPI_TCR_LSBF;
+	}
+}
+
+void SPIClass::setDataMode(uint8_t dataMode)
+{
+	hardware->clock_gate_register |= hardware->clock_gate_mask;
+	//SPCR = (SPCR & ~SPI_MODE_MASK) | dataMode;
+}
+
 const SPIClass::SPI_Hardware_t spiclass_lpspi4_hardware = {
 	CCM_CCGR1, CCM_CCGR1_LPSPI4(CCM_CCGR_ON),
 	12, 

SPI.h

@@ -1051,7 +1051,7 @@ private:
 	}
 	void init_AlwaysInline(uint32_t clock, uint8_t bitOrder, uint8_t dataMode)
 	  __attribute__((__always_inline__)) {
-		// TODO: make these implement settings - for now, just fixed config
+		// TODO: Need to check timings as related to chip selects?
 
 		uint32_t d, div, clkhz = 528000000/7;  // LPSPI peripheral clock
 		if (clock == 0) clock =1;
@@ -1065,6 +1065,16 @@ private:
 		}
 		ccr = LPSPI_CCR_SCKDIV(div) | LPSPI_CCR_DBT(div/2);
 		tcr = LPSPI_TCR_FRAMESZ(7);    // TCR has polarity and bit order too
+
+		// handle LSB setup 
+		if (bitOrder == LSBFIRST) tcr |= LPSPI_TCR_LSBF;
+
+		// Handle Data Mode
+		if (dataMode & 0x08) tcr |= LPSPI_TCR_CPOL;
+
+		// Note: On T3.2 when we set CPHA it also updated the timing.  It moved the 
+		// PCS to SCK Delay Prescaler into the After SCK Delay Prescaler	
+		if (dataMode & 0x04) tcr |= LPSPI_TCR_CPHA; 
 	}
 	uint32_t ccr; // clock config, pg 2660 (RT1050 ref, rev 2)
 	uint32_t tcr; // transmit command, pg 2664 (RT1050 ref, rev 2)