T4 - DMA transfer > 32K did not flush or delete whole dcache range.

Ran into issues where large buffer, were not fully outputting the right data.
Was seeing it on RA8876 on pages from DMAMEM and at times EXTRAM.

Turns out where I did the arm_dcache_flush (or delete) I had already decreased the count to be the max size I could output in any one DMA operation without chain... So now do it before we check for MAX size...

Appears to fix the display issue I was seeing

SPI.cpp

 		event_responder.triggerEvent();
 		return true;
 	}
+	// lets clear cache before we update sizes...
+	if ((uint32_t)buf >= 0x20200000u)  arm_dcache_flush((uint8_t *)buf, count);
+	if ((uint32_t)retbuf >= 0x20200000u)  arm_dcache_delete(retbuf, count);
 
 	// Now handle the cases where the count > then how many we can output in one DMA request
 	if (count > MAX_DMA_COUNT) {
 	if (buf) {
 		_dmaTX->sourceBuffer((uint8_t*)write_data, count);  
 		_dmaTX->TCD->SLAST = 0;	// Finish with it pointing to next location
-		if ((uint32_t)write_data >= 0x20200000u)  arm_dcache_flush(write_data, count);
 	} else {
 		_dmaTX->source((uint8_t&)_transferWriteFill);   // maybe have setable value
 		DMAChanneltransferCount(_dmaTX, count);
 		_dmaRX->TCD->ATTR_SRC = 0;		//Make sure set for 8 bit mode...
 		_dmaRX->destinationBuffer((uint8_t*)retbuf, count);
 		_dmaRX->TCD->DLASTSGA = 0;		// At end point after our bufffer
-		if ((uint32_t)retbuf >= 0x20200000u)  arm_dcache_delete(retbuf, count);
 	} else {
 			// Write  only mode
 		_dmaRX->TCD->ATTR_SRC = 0;		//Make sure set for 8 bit mode...