Browse Source

T4 - Require setting Input MUX values

Some of the SPI pins for SPI1 and SPI2 require
changing the Input chain mux registers.  So those register pointers and values are not stored in the SPI object and are updated as part of the begin
main
Kurt Eckhardt 5 years ago
parent
commit
e4d94d492a
2 changed files with 23 additions and 0 deletions
  1. +14
    -0
      SPI.cpp
  2. +9
    -0
      SPI.h

+ 14
- 0
SPI.cpp View File

*(portConfigRegister(hardware().mosi_pin [mosi_pin_index])) = hardware().mosi_mux[mosi_pin_index]; *(portConfigRegister(hardware().mosi_pin [mosi_pin_index])) = hardware().mosi_mux[mosi_pin_index];
*(portConfigRegister(hardware().sck_pin [sck_pin_index])) = hardware().sck_mux[sck_pin_index]; *(portConfigRegister(hardware().sck_pin [sck_pin_index])) = hardware().sck_mux[sck_pin_index];


// Set the Mux pins
//Serial.println("SPI: Set Input select registers");
hardware().sck_select_input_register = hardware().sck_select_val;
hardware().sdi_select_input_register = hardware().sdi_select_val;
hardware().sdo_select_input_register = hardware().sdo_select_val;

//digitalWriteFast(10, HIGH); //digitalWriteFast(10, HIGH);
//pinMode(10, OUTPUT); //pinMode(10, OUTPUT);
//digitalWriteFast(10, HIGH); //digitalWriteFast(10, HIGH);
3 | 0x10, 3 | 0x10,
10, 10,
3 | 0x10, 3 | 0x10,
IOMUXC_LPSPI4_SCK_SELECT_INPUT, IOMUXC_LPSPI4_SDI_SELECT_INPUT, IOMUXC_LPSPI4_SDO_SELECT_INPUT, IOMUXC_LPSPI4_PCS0_SELECT_INPUT,
0, 0, 0, 0
}; };


SPIClass SPI((uintptr_t)&IMXRT_LPSPI4_S, (uintptr_t)&SPIClass::spiclass_lpspi4_hardware); SPIClass SPI((uintptr_t)&IMXRT_LPSPI4_S, (uintptr_t)&SPIClass::spiclass_lpspi4_hardware);


#if defined(__IMXRT1062__) #if defined(__IMXRT1062__)
7 | 0x10, 7 | 0x10,
0, 0,
7 | 0x10, 7 | 0x10,
IOMUXC_LPSPI3_SCK_SELECT_INPUT, IOMUXC_LPSPI3_SDI_SELECT_INPUT, IOMUXC_LPSPI3_SDO_SELECT_INPUT, IOMUXC_LPSPI3_PCS0_SELECT_INPUT,
1, 1, 0, 0
}; };
SPIClass SPI1((uintptr_t)&IMXRT_LPSPI3_S, (uintptr_t)&SPIClass::spiclass_lpspi3_hardware); SPIClass SPI1((uintptr_t)&IMXRT_LPSPI3_S, (uintptr_t)&SPIClass::spiclass_lpspi3_hardware);


4 | 0x10, 4 | 0x10,
36, 36,
4 | 0x10, 4 | 0x10,
IOMUXC_LPSPI1_SCK_SELECT_INPUT, IOMUXC_LPSPI1_SDI_SELECT_INPUT, IOMUXC_LPSPI1_SDO_SELECT_INPUT, IOMUXC_LPSPI1_PCS0_SELECT_INPUT,
1, 1, 1, 0
}; };
SPIClass SPI2((uintptr_t)&IMXRT_LPSPI1_S, (uintptr_t)&SPIClass::spiclass_lpspi1_hardware); SPIClass SPI2((uintptr_t)&IMXRT_LPSPI1_S, (uintptr_t)&SPIClass::spiclass_lpspi1_hardware);
#endif #endif

+ 9
- 0
SPI.h View File

const uint32_t sck_mux[CNT_SCK_PINS]; const uint32_t sck_mux[CNT_SCK_PINS];
const uint8_t cs_pin[CNT_CS_PINS]; const uint8_t cs_pin[CNT_CS_PINS];
const uint32_t cs_mux[CNT_CS_PINS]; const uint32_t cs_mux[CNT_CS_PINS];

volatile uint32_t &sck_select_input_register;
volatile uint32_t &sdi_select_input_register;
volatile uint32_t &sdo_select_input_register;
volatile uint32_t &pcs0_select_input_register;
const uint8_t sck_select_val;
const uint8_t sdi_select_val;
const uint8_t sdo_select_val;
const uint8_t pcs0_select_val;
} SPI_Hardware_t; } SPI_Hardware_t;
static const SPI_Hardware_t spiclass_lpspi4_hardware; static const SPI_Hardware_t spiclass_lpspi4_hardware;
#if defined(__IMXRT1062__) #if defined(__IMXRT1062__)

Loading…
Cancel
Save