T4 - Use new SPI structure and Hardware data

Warning this change uses the updates I did in core library to define a
SPI structure for the T4...

The code now uses this structure as wlll as pointer to it passed in to constructor to talk to the SPI registers.

Also Miso, Mosi and SCK pins are defined in Hardware structure which again is passed in to constructor... Still a few more things to cleanup in ::begin to make it  completely independant of the hardware such that I can define SPI1 as well...

SPI.cpp

@@ -1266,7 +1266,7 @@ bool SPIClass::transfer(const void *buf, void *retbuf, size_t count, EventRespon
 
 #elif defined(__arm__) && defined(TEENSYDUINO) && (defined(__IMXRT1052__) || defined(__IMXRT1062__))
 
-#include "debug/printf.h"
+//#include "debug/printf.h"
 
 void SPIClass::begin()
 {
@@ -1274,25 +1274,29 @@ void SPIClass::begin()
 	// CBCMR[LPSPI_CLK_SEL] - PLL2 = 528 MHz
 	// CBCMR[LPSPI_PODF] - div4 = 132 MHz
 
-	CCM_CCGR1 &= ~CCM_CCGR1_LPSPI4(CCM_CCGR_ON);
+
+	hardware->clock_gate_register &= ~hardware->clock_gate_mask;
 
 	CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_LPSPI_PODF_MASK | CCM_CBCMR_LPSPI_CLK_SEL_MASK)) |
 		CCM_CBCMR_LPSPI_PODF(6) | CCM_CBCMR_LPSPI_CLK_SEL(2); // pg 714
+
 	uint32_t fastio = IOMUXC_PAD_SRE | IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
 	//uint32_t fastio = IOMUXC_PAD_DSE(3) | IOMUXC_PAD_SPEED(3);
-	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = fastio;
-	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = fastio;
-	IOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = fastio;
+	Serial.printf("SPI MISO: %d MOSI: %d, SCK: %d\n", hardware->miso_pin[miso_pin_index], hardware->mosi_pin[mosi_pin_index], hardware->sck_pin[sck_pin_index]);
+	*(portControlRegister(hardware->miso_pin[miso_pin_index])) = fastio;
+	*(portControlRegister(hardware->mosi_pin[mosi_pin_index])) = fastio;
+	*(portControlRegister(hardware->sck_pin[sck_pin_index])) = fastio;
 
 	//printf("CBCMR = %08lX\n", CCM_CBCMR);
-	CCM_CCGR1 |= CCM_CCGR1_LPSPI4(CCM_CCGR_ON);
-	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 3 | 0x10; // SDI
-	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 3 | 0x10; // SDO
-	IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 3 | 0x10; // SCK
+	hardware->clock_gate_register |= hardware->clock_gate_mask;
+	*(portConfigRegister(hardware->miso_pin[miso_pin_index])) = hardware->miso_mux[miso_pin_index];
+	*(portConfigRegister(hardware->mosi_pin [mosi_pin_index])) = hardware->mosi_mux[mosi_pin_index];
+	*(portConfigRegister(hardware->sck_pin [sck_pin_index])) = hardware->sck_mux[sck_pin_index];
+
 	//digitalWriteFast(10, HIGH);
 	//pinMode(10, OUTPUT);
 	//digitalWriteFast(10, HIGH);
-	LPSPI4_CR = LPSPI_CR_RST;
+	port->CR = LPSPI_CR_RST;
 }
 
 uint8_t SPIClass::pinIsChipSelect(uint8_t pin)
@@ -1312,24 +1316,24 @@ bool SPIClass::pinIsChipSelect(uint8_t pin1, uint8_t pin2)
 
 bool SPIClass::pinIsMOSI(uint8_t pin)
 {
-	for (unsigned int i = 0; i < sizeof(hardware().mosi_pin); i++) {
-		if (pin == hardware().mosi_pin[i]) return true;
+	for (unsigned int i = 0; i < sizeof(hardware->mosi_pin); i++) {
+		if (pin == hardware->mosi_pin[i]) return true;
 	}
 	return false;
 }
 
 bool SPIClass::pinIsMISO(uint8_t pin)
 {
-	for (unsigned int i = 0; i < sizeof(hardware().miso_pin); i++) {
-		if (pin == hardware().miso_pin[i]) return true;
+	for (unsigned int i = 0; i < sizeof(hardware->miso_pin); i++) {
+		if (pin == hardware->miso_pin[i]) return true;
 	}
 	return false;
 }
 
 bool SPIClass::pinIsSCK(uint8_t pin)
 {
-	for (unsigned int i = 0; i < sizeof(hardware().sck_pin); i++) {
-		if (pin == hardware().sck_pin[i]) return true;
+	for (unsigned int i = 0; i < sizeof(hardware->sck_pin); i++) {
+		if (pin == hardware->sck_pin[i]) return true;
 	}
 	return false;
 }
@@ -1338,11 +1342,11 @@ bool SPIClass::pinIsSCK(uint8_t pin)
 uint8_t SPIClass::setCS(uint8_t pin)
 {
 	/*
-	for (unsigned int i = 0; i < sizeof(hardware().cs_pin); i++) {
-		if (pin == hardware().cs_pin[i]) {
+	for (unsigned int i = 0; i < sizeof(hardware->cs_pin); i++) {
+		if (pin == hardware->cs_pin[i]) {
 			volatile uint32_t *reg = portConfigRegister(pin);
-			*reg = hardware().cs_mux[i];
-			return hardware().cs_mask[i];
+			*reg = hardware->cs_mux[i];
+			return hardware->cs_mask[i];
 		}
 	} */
 	return 0;
@@ -1364,10 +1368,8 @@ void SPIClass::setSCK(uint8_t pin)
 }
 
 
-
-
-const SPIClass::SPI_Hardware_t SPIClass::lpspi4_hardware = {
-	CCM_CCGR1,
+const SPIClass::SPI_Hardware_t spiclass_lpspi4_hardware = {
+	CCM_CCGR1, CCM_CCGR1_LPSPI4(CCM_CCGR_ON),
 	12, 
 	3 | 0x10,
 	11,
@@ -1377,7 +1379,7 @@ const SPIClass::SPI_Hardware_t SPIClass::lpspi4_hardware = {
 	10,
 	3 | 0x10,
 };
-SPIClass SPI(0, (uintptr_t)&SPIClass::lpspi4_hardware);
+SPIClass SPI(&IMXRT_LPSPI4_S, &spiclass_lpspi4_hardware);
 
 
 void SPIClass::transfer(const void * buf, void * retbuf, size_t count)

SPI.h

@@ -1079,21 +1079,20 @@ public:
 	static const uint8_t CNT_CS_PINS = 1;
 	typedef struct {
 		volatile uint32_t &clock_gate_register;
-		uint32_t clock_gate_mask;
-		uint8_t  miso_pin[CNT_MISO_PINS];
-		uint32_t  miso_mux[CNT_MISO_PINS];
-		uint8_t  mosi_pin[CNT_MOSI_PINS];
-		uint32_t  mosi_mux[CNT_MOSI_PINS];
-		uint8_t  sck_pin[CNT_SCK_PINS];
-		uint32_t  sck_mux[CNT_SCK_PINS];
-		uint8_t  cs_pin[CNT_CS_PINS];
-		uint32_t  cs_mux[CNT_CS_PINS];
+		const uint32_t clock_gate_mask;
+		const uint8_t  miso_pin[CNT_MISO_PINS];
+		const uint32_t  miso_mux[CNT_MISO_PINS];
+		const uint8_t  mosi_pin[CNT_MOSI_PINS];
+		const uint32_t  mosi_mux[CNT_MOSI_PINS];
+		const uint8_t  sck_pin[CNT_SCK_PINS];
+		const uint32_t  sck_mux[CNT_SCK_PINS];
+		const uint8_t  cs_pin[CNT_CS_PINS];
+		const uint32_t  cs_mux[CNT_CS_PINS];
 	} SPI_Hardware_t;
-	static const SPI_Hardware_t lpspi4_hardware;
 
 public:
-	constexpr SPIClass(uintptr_t myport, uintptr_t myhardware)
-		: port_addr(myport), hardware_addr(myhardware) {
+	constexpr SPIClass(IMXRT_LPSPI_t *myport, const SPI_Hardware_t *myhardware)
+		: port(myport), hardware(myhardware) {
 	}
 	// Initialize the SPI library
 	void begin();
@@ -1157,22 +1156,22 @@ public:
 		#endif
 
 		//printf("trans\n");
-		LPSPI4_CR = 0;
-		LPSPI4_CFGR1 = LPSPI_CFGR1_MASTER | LPSPI_CFGR1_SAMPLE;
-		LPSPI4_CCR = settings.ccr;
-		LPSPI4_TCR = settings.tcr;
-		//LPSPI4_CCR = LPSPI_CCR_SCKDIV(4);
-		//LPSPI4_TCR = LPSPI_TCR_FRAMESZ(7);
-		LPSPI4_CR = LPSPI_CR_MEN;
+		port->CR = 0;
+		port->CFGR1 = LPSPI_CFGR1_MASTER | LPSPI_CFGR1_SAMPLE;
+		port->CCR = settings.ccr;
+		port->TCR = settings.tcr;
+		//port->CCR = LPSPI_CCR_SCKDIV(4);
+		//port->TCR = LPSPI_TCR_FRAMESZ(7);
+		port->CR = LPSPI_CR_MEN;
 	}
 
 	// Write to the SPI bus (MOSI pin) and also receive (MISO pin)
 	uint8_t transfer(uint8_t data) {
 		// TODO: check for space in fifo?
-		LPSPI4_TDR = data;
+		port->TDR = data;
 		while (1) {
-			uint32_t fifo = (LPSPI4_FSR >> 16) & 0x1F;
-			if (fifo > 0) return LPSPI4_RDR;
+			uint32_t fifo = (port->FSR >> 16) & 0x1F;
+			if (fifo > 0) return port->RDR;
 		}
 		//port().SR = SPI_SR_TCF;
 		//port().PUSHR = data;
@@ -1281,10 +1280,10 @@ public:
 
 private:
 	//KINETISK_SPI_t & port() { return *(KINETISK_SPI_t *)port_addr; }
-	const SPI_Hardware_t & hardware() { return *(const SPI_Hardware_t *)hardware_addr; }
+	IMXRT_LPSPI_t * const port;
+	const SPI_Hardware_t * const hardware;
+
 	void updateCTAR(uint32_t ctar);
-	uintptr_t port_addr;
-	uintptr_t hardware_addr;
 	uint8_t miso_pin_index = 0;
 	uint8_t mosi_pin_index = 0;
 	uint8_t sck_pin_index = 0;