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Merge pull request #27 from KurtE/ENABLE_PCR_DSE-on-enable-pins 

Enable Pins - can set more options
main
Paul Stoffregen 7 years ago
parent
3f5108d197 52812c04cd
commit
f1bbde289c
2 changed files with 40 additions and 40 deletions
Unified View Show Diff Stats
  1. +32
    -32
      SPI.cpp
  2. +8
    -8
      SPI.h

+ 32
- 32
SPI.cpp View File

32767, DMAMUX_SOURCE_SPI0_TX, DMAMUX_SOURCE_SPI0_RX, 32767, DMAMUX_SOURCE_SPI0_TX, DMAMUX_SOURCE_SPI0_RX,
_spi_dma_rxISR0, _spi_dma_rxISR0,
12, 8, 12, 8,
2, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(2),
11, 7, 11, 7,
2, 2,
PORT_PCR_DSE | PORT_PCR_MUX(2), PORT_PCR_MUX(2),
13, 14, 13, 14,
2, 2,
PORT_PCR_DSE | PORT_PCR_MUX(2), PORT_PCR_MUX(2),
10, 2, 9, 6, 20, 23, 21, 22, 15, 10, 2, 9, 6, 20, 23, 21, 22, 15,
2, 2, 2, 2, 2, 2, 2, 2, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2),
0x1, 0x1, 0x2, 0x2, 0x4, 0x4, 0x8, 0x8, 0x10 0x1, 0x1, 0x2, 0x2, 0x4, 0x4, 0x8, 0x8, 0x10
}; };
SPIClass SPI((uintptr_t)&KINETISK_SPI0, (uintptr_t)&SPIClass::spi0_hardware); SPIClass SPI((uintptr_t)&KINETISK_SPI0, (uintptr_t)&SPIClass::spi0_hardware);
32767, DMAMUX_SOURCE_SPI0_TX, DMAMUX_SOURCE_SPI0_RX, 32767, DMAMUX_SOURCE_SPI0_TX, DMAMUX_SOURCE_SPI0_RX,
_spi_dma_rxISR0, _spi_dma_rxISR0,
12, 8, 39, 255, 12, 8, 39, 255,
2, 2, 2, 0,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), 0,
11, 7, 28, 255, 11, 7, 28, 255,
2, 2, 2, 0,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), 0,
13, 14, 27, 13, 14, 27,
2, 2, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2),
10, 2, 9, 6, 20, 23, 21, 22, 15, 26, 45, 10, 2, 9, 6, 20, 23, 21, 22, 15, 26, 45,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(3),
0x1, 0x1, 0x2, 0x2, 0x4, 0x4, 0x8, 0x8, 0x10, 0x1, 0x20 0x1, 0x1, 0x2, 0x2, 0x4, 0x4, 0x8, 0x8, 0x10, 0x1, 0x20
}; };
const SPIClass::SPI_Hardware_t SPIClass::spi1_hardware = { const SPIClass::SPI_Hardware_t SPIClass::spi1_hardware = {
#endif #endif
_spi_dma_rxISR1, _spi_dma_rxISR1,
1, 5, 61, 59, 1, 5, 61, 59,
2, 7, 2, 7,
PORT_PCR_MUX(2), PORT_PCR_MUX(7), PORT_PCR_MUX(2), PORT_PCR_MUX(7),
0, 21, 61, 59, 0, 21, 61, 59,
2, 7, 7, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(7), PORT_PCR_MUX(7), PORT_PCR_MUX(2),
32, 20, 60, 32, 20, 60,
2, 7, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(7), PORT_PCR_MUX(2),
6, 31, 58, 62, 63, 255, 255, 255, 255, 255, 255, 6, 31, 58, 62, 63, 255, 255, 255, 255, 255, 255,
7, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0,
PORT_PCR_MUX(7), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), 0, 0, 0, 0, 0, 0,
0x1, 0x1, 0x2, 0x1, 0x4, 0, 0, 0, 0, 0, 0 0x1, 0x1, 0x2, 0x1, 0x4, 0, 0, 0, 0, 0, 0
}; };
const SPIClass::SPI_Hardware_t SPIClass::spi2_hardware = { const SPIClass::SPI_Hardware_t SPIClass::spi2_hardware = {
#endif #endif
_spi_dma_rxISR2, _spi_dma_rxISR2,
45, 51, 255, 255, 45, 51, 255, 255,
2, 2, 0, 0,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), 0, 0,
44, 52, 255, 255, 44, 52, 255, 255,
2, 2, 0, 0,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), 0, 0,
46, 53, 255, 46, 53, 255,
2, 2, 0,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), 0,
43, 54, 55, 255, 255, 255, 255, 255, 255, 255, 255, 43, 54, 55, 255, 255, 255, 255, 255, 255, 255, 255,
2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0,
PORT_PCR_MUX(2), PORT_PCR_MUX(2), PORT_PCR_MUX(2), 0, 0, 0, 0, 0, 0, 0, 0,
0x1, 0x2, 0x1, 0, 0, 0, 0, 0, 0, 0, 0 0x1, 0x2, 0x1, 0, 0, 0, 0, 0, 0, 0, 0
}; };
SPIClass SPI((uintptr_t)&KINETISK_SPI0, (uintptr_t)&SPIClass::spi0_hardware); SPIClass SPI((uintptr_t)&KINETISK_SPI0, (uintptr_t)&SPIClass::spi0_hardware);
port().CTAR1 = SPI_CTAR_FMSZ(15) | SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1); port().CTAR1 = SPI_CTAR_FMSZ(15) | SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);
port().MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F); port().MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F);
reg = portConfigRegister(hardware().mosi_pin[mosi_pin_index]); reg = portConfigRegister(hardware().mosi_pin[mosi_pin_index]);
*reg = PORT_PCR_MUX(hardware().mosi_mux[mosi_pin_index]);
*reg = hardware().mosi_mux[mosi_pin_index];
reg = portConfigRegister(hardware().miso_pin[miso_pin_index]); reg = portConfigRegister(hardware().miso_pin[miso_pin_index]);
*reg= PORT_PCR_MUX(hardware().miso_mux[miso_pin_index]);
*reg= hardware().miso_mux[miso_pin_index];
reg = portConfigRegister(hardware().sck_pin[sck_pin_index]); reg = portConfigRegister(hardware().sck_pin[sck_pin_index]);
*reg = PORT_PCR_MUX(hardware().sck_mux[sck_pin_index]);
*reg = hardware().sck_mux[sck_pin_index];
} }


void SPIClass::end() void SPIClass::end()
for (unsigned int i = 0; i < sizeof(hardware().cs_pin); i++) { for (unsigned int i = 0; i < sizeof(hardware().cs_pin); i++) {
if (pin == hardware().cs_pin[i]) { if (pin == hardware().cs_pin[i]) {
volatile uint32_t *reg = portConfigRegister(pin); volatile uint32_t *reg = portConfigRegister(pin);
*reg = PORT_PCR_MUX(hardware().cs_mux[i]);
*reg = hardware().cs_mux[i];
return hardware().cs_mask[i]; return hardware().cs_mask[i];
} }
} }
0, // BR index 0 0, // BR index 0
DMAMUX_SOURCE_SPI0_TX, DMAMUX_SOURCE_SPI0_RX, _spi_dma_rxISR0, DMAMUX_SOURCE_SPI0_TX, DMAMUX_SOURCE_SPI0_RX, _spi_dma_rxISR0,
12, 8, 12, 8,
2, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(2),
11, 7, 11, 7,
2, 2,
PORT_PCR_DSE | PORT_PCR_MUX(2), PORT_PCR_MUX(2),
13, 14, 13, 14,
2, 2,
PORT_PCR_DSE | PORT_PCR_MUX(2), PORT_PCR_MUX(2),
10, 2, 10, 2,
2, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(2),
0x1, 0x1 0x1, 0x1
}; };
SPIClass SPI((uintptr_t)&KINETISL_SPI0, (uintptr_t)&SPIClass::spi0_hardware); SPIClass SPI((uintptr_t)&KINETISL_SPI0, (uintptr_t)&SPIClass::spi0_hardware);
1, // BR index 1 in SPI Settings 1, // BR index 1 in SPI Settings
DMAMUX_SOURCE_SPI1_TX, DMAMUX_SOURCE_SPI1_RX, _spi_dma_rxISR1, DMAMUX_SOURCE_SPI1_TX, DMAMUX_SOURCE_SPI1_RX, _spi_dma_rxISR1,
1, 5, 1, 5,
2, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(2),
0, 21, 0, 21,
2, 2,
PORT_PCR_MUX(2), PORT_PCR_MUX(2),
20, 255, 20, 255,
2, 0,
PORT_PCR_MUX(2), 0,
6, 255, 6, 255,
2, 0,
PORT_PCR_MUX(2), 0,
0x1, 0 0x1, 0
}; };
SPIClass SPI1((uintptr_t)&KINETISL_SPI1, (uintptr_t)&SPIClass::spi1_hardware); SPIClass SPI1((uintptr_t)&KINETISL_SPI1, (uintptr_t)&SPIClass::spi1_hardware);
port().C2 = 0; port().C2 = 0;
uint8_t tmp __attribute__((unused)) = port().S; uint8_t tmp __attribute__((unused)) = port().S;
reg = portConfigRegister(hardware().mosi_pin[mosi_pin_index]); reg = portConfigRegister(hardware().mosi_pin[mosi_pin_index]);
*reg = PORT_PCR_MUX(hardware().mosi_mux[mosi_pin_index]);
*reg = hardware().mosi_mux[mosi_pin_index];
reg = portConfigRegister(hardware().miso_pin[miso_pin_index]); reg = portConfigRegister(hardware().miso_pin[miso_pin_index]);
*reg = PORT_PCR_MUX(hardware().miso_mux[miso_pin_index]);
*reg = hardware().miso_mux[miso_pin_index];
reg = portConfigRegister(hardware().sck_pin[sck_pin_index]); reg = portConfigRegister(hardware().sck_pin[sck_pin_index]);
*reg = PORT_PCR_MUX(hardware().sck_mux[sck_pin_index]);
*reg = hardware().sck_mux[sck_pin_index];
} }


void SPIClass::end() { void SPIClass::end() {
for (unsigned int i = 0; i < sizeof(hardware().cs_pin); i++) { for (unsigned int i = 0; i < sizeof(hardware().cs_pin); i++) {
if (pin == hardware().cs_pin[i]) { if (pin == hardware().cs_pin[i]) {
volatile uint32_t *reg = portConfigRegister(pin); volatile uint32_t *reg = portConfigRegister(pin);
*reg = PORT_PCR_MUX(hardware().cs_mux[i]);
*reg = hardware().cs_mux[i];
return hardware().cs_mask[i]; return hardware().cs_mask[i];
} }
} }

+ 8
- 8
SPI.h View File

uint8_t rx_dma_channel; uint8_t rx_dma_channel;
void (*dma_rxisr)(); void (*dma_rxisr)();
uint8_t miso_pin[CNT_MISO_PINS]; uint8_t miso_pin[CNT_MISO_PINS];
uint8_t miso_mux[CNT_MISO_PINS];
uint32_t miso_mux[CNT_MISO_PINS];
uint8_t mosi_pin[CNT_MOSI_PINS]; uint8_t mosi_pin[CNT_MOSI_PINS];
uint8_t mosi_mux[CNT_MOSI_PINS];
uint32_t mosi_mux[CNT_MOSI_PINS];
uint8_t sck_pin[CNT_SCK_PINS]; uint8_t sck_pin[CNT_SCK_PINS];
uint8_t sck_mux[CNT_SCK_PINS];
uint32_t sck_mux[CNT_SCK_PINS];
uint8_t cs_pin[CNT_CS_PINS]; uint8_t cs_pin[CNT_CS_PINS];
uint8_t cs_mux[CNT_CS_PINS];
uint32_t cs_mux[CNT_CS_PINS];
uint8_t cs_mask[CNT_CS_PINS]; uint8_t cs_mask[CNT_CS_PINS];
} SPI_Hardware_t; } SPI_Hardware_t;
static const SPI_Hardware_t spi0_hardware; static const SPI_Hardware_t spi0_hardware;
uint8_t rx_dma_channel; uint8_t rx_dma_channel;
void (*dma_isr)(); void (*dma_isr)();
uint8_t miso_pin[CNT_MISO_PINS]; uint8_t miso_pin[CNT_MISO_PINS];
uint8_t miso_mux[CNT_MISO_PINS];
uint32_t miso_mux[CNT_MISO_PINS];
uint8_t mosi_pin[CNT_MMOSI_PINS]; uint8_t mosi_pin[CNT_MMOSI_PINS];
uint8_t mosi_mux[CNT_MMOSI_PINS];
uint32_t mosi_mux[CNT_MMOSI_PINS];
uint8_t sck_pin[CNT_SCK_PINS]; uint8_t sck_pin[CNT_SCK_PINS];
uint8_t sck_mux[CNT_SCK_PINS];
uint32_t sck_mux[CNT_SCK_PINS];
uint8_t cs_pin[CNT_CS_PINS]; uint8_t cs_pin[CNT_CS_PINS];
uint8_t cs_mux[CNT_CS_PINS];
uint32_t cs_mux[CNT_CS_PINS];
uint8_t cs_mask[CNT_CS_PINS]; uint8_t cs_mask[CNT_CS_PINS];
} SPI_Hardware_t; } SPI_Hardware_t;
static const SPI_Hardware_t spi0_hardware; static const SPI_Hardware_t spi0_hardware;

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