Ran into issues where large buffer, were not fully outputting the right data.
Was seeing it on RA8876 on pages from DMAMEM and at times EXTRAM.
Turns out where I did the arm_dcache_flush (or delete) I had already decreased the count to be the max size I could output in any one DMA operation without chain... So now do it before we check for MAX size...
Appears to fix the display issue I was seeing
The CS pins on T4.x are not like 3.x in that is you select one by index, not one or more by mask. So changed returned values to be index (1 based)
Also while testing I pulled in Frank's change for adding delay after CS pin is logically selected.
Double checked the pin definitions and forgot to update that
there is MISO1 on pin 39, likewise CS1-0 on pin 38
Also SPI0 has two additional CS pins on 37 and 36.
I changed the Clock that was used and settings.
So I think maximum speed changed from about 37+mhz to 60mhz
I was haing issues at 60mhz with simple test so also changed the IO ins Speed and DSE values which appeared to work.
I tried running our ILI9488_t3 library at 60mhz and it appears to work :D
The code would fail if the user did an SPI.transfer without calling SPI.beginTransaction.
So begin now calls beginTransaction with default parameters.
Also put in an implemention for SPI.setClockDivider as well as SPI.setDataMode
They appear to work OK... Tried to do with out changing any of the current functionality other than to call begin/end transaction in begin to get to a stable state.
There have been some issues with SCK pins and the like not appearing to work as well as on T3.x...
We have been experiementing with changing the DSE and SPEED value and this has helped in some cases.
Some of the SPI pins for SPI1 and SPI2 require
changing the Input chain mux registers. So those register pointers and values are not stored in the SPI object and are updated as part of the begin
If a buffer is up in the high memory, that is either in the area marked DMARAM or created by malloc and you try to do a SPI transfer using DMA, the code detects the addresses >= 0x20200000 and then calls the system functions to either flush the cache or delete the cache on the read...
Still testing and running into memory usage issues, but I think some of the basics are working. Still need to do more testing, including verifying on larger buffers.
Added - the code to set them as part of the Transaction Setttings.
Also put in implementations for,
SPI.setBitOrder and SPI.setDataMode.
Note the setDatMode like the T3.x does not appear to do anything yet.
The buffer transfer now uses FIFO queues,
Currently it only outputs the 8 bits per entry, unlike the T3.x version which packed the bytes into words in order to speed up some more.
Warning this change uses the updates I did in core library to define a
SPI structure for the T4...
The code now uses this structure as wlll as pointer to it passed in to constructor to talk to the SPI registers.
Also Miso, Mosi and SCK pins are defined in Hardware structure which again is passed in to constructor... Still a few more things to cleanup in ::begin to make it completely independant of the hardware such that I can define SPI1 as well...
Some libraries actually call this. So define the Hardware data for the one pin for each of the MISO, MOSI, SCK and CS...
So far setting does nothing.
Enough to get Sparkfun Teensyview to build, other than example uses String class which is not included in link phase.
Made the SPI code work like the old stuff where you could set the miso/mosi/sck pins after the begin.
Some people actually used this for changing SPI on the fly to use multiple sets of pins
The current table code was setup that when we choose a specific pin for MOSI or Miso or SCK (or CS), that the only thing set at the time was the MUX value.
Well the old enable_pins that was called off of the enumlated register was setting the PORT_PCR_DSE option on pins 11 and 13...
So to fix it, I have the table, allow you to fully set the options for each pin.
Still have most all of them just setting the MUX, but do have pins 11 and 13 setting the PCR_DSE option to be compatible with old code.
Experiment with making the whole transfer of the buffer act like it is
to logically hold the CS pins for that whole transfer. This removes
gaps between each 16 bit transfer.
Update SPI.transfer(buf, cnt) to use the FIFO queue to speed things up.
It also speeds things up to pack the data into 16 bit transfers instead
of 8 bits.
As this code is more complicated, no longer makes sense to inline it,
so functions moved from .h to .cpp files.
SPI1 and SPI2 transfer functions were updated as well for T3.5 and T3.6
John Robinson
Tino Hernandez
Kurt Eckhardt
Mike S
xxxajk
PaulStoffregen
max mc costa