There have been some issues with SCK pins and the like not appearing to work as well as on T3.x...
We have been experiementing with changing the DSE and SPEED value and this has helped in some cases.
With the T4 transaction code settings being dependent on which clock is choosen to be used in SPI. All of the work had to be done at run time.
As such the statically defined ones may not work as you have no idea which clock may be actually used...
So moved the work to comput CCR into the SPI.beginTransaction code, which is only called if something like the clock speed is different than the previous call to beginTransaction
We can still convert the bit Order and Data Mode parameters into the TCR
register value as part of the SPISettings constructor code as these do
not depend on external run time settings.
Some of the SPI pins for SPI1 and SPI2 require
changing the Input chain mux registers. So those register pointers and values are not stored in the SPI object and are updated as part of the begin
If a buffer is up in the high memory, that is either in the area marked DMARAM or created by malloc and you try to do a SPI transfer using DMA, the code detects the addresses >= 0x20200000 and then calls the system functions to either flush the cache or delete the cache on the read...
Still testing and running into memory usage issues, but I think some of the basics are working. Still need to do more testing, including verifying on larger buffers.
Added - the code to set them as part of the Transaction Setttings.
Also put in implementations for,
SPI.setBitOrder and SPI.setDataMode.
Note the setDatMode like the T3.x does not appear to do anything yet.
The buffer transfer now uses FIFO queues,
Currently it only outputs the 8 bits per entry, unlike the T3.x version which packed the bytes into words in order to speed up some more.
Warning this change uses the updates I did in core library to define a
SPI structure for the T4...
The code now uses this structure as wlll as pointer to it passed in to constructor to talk to the SPI registers.
Also Miso, Mosi and SCK pins are defined in Hardware structure which again is passed in to constructor... Still a few more things to cleanup in ::begin to make it completely independant of the hardware such that I can define SPI1 as well...
Some libraries actually call this. So define the Hardware data for the one pin for each of the MISO, MOSI, SCK and CS...
So far setting does nothing.
Enough to get Sparkfun Teensyview to build, other than example uses String class which is not included in link phase.
but it is CS5 which encodes to 0x20 and our
macros only handled up to 0x1f... so changed
to 0x3f.
Tested on my ILI9341_t3n test now works with DC on 45... Needs change in Core as well
Made the SPI code work like the old stuff where you could set the miso/mosi/sck pins after the begin.
Some people actually used this for changing SPI on the fly to use multiple sets of pins
The current table code was setup that when we choose a specific pin for MOSI or Miso or SCK (or CS), that the only thing set at the time was the MUX value.
Well the old enable_pins that was called off of the enumlated register was setting the PORT_PCR_DSE option on pins 11 and 13...
So to fix it, I have the table, allow you to fully set the options for each pin.
Still have most all of them just setting the MUX, but do have pins 11 and 13 setting the PCR_DSE option to be compatible with old code.
Paul Stoffregen
Kurt Eckhardt
Mike S
Frank
xxxajk