T4 async support

If a buffer is up in the high memory, that is either in the area marked DMARAM or created by malloc and you try to do a SPI transfer using DMA, the code detects the addresses >= 0x20200000 and then calls the system functions to either flush the cache or delete the cache on the read...

Still testing and running into memory usage issues, but I think some of the basics are working.  Still need to do more testing, including verifying on larger buffers.

Added dummy end() function to SPI.ccp

Use PFD setting to prevent wrong calculation (needed for high SPI-Clo…

T4- Switch to port() and hardware() like T3.x

T4 Fixes plus macros

Implemented these two functions to use the hardware table

Appears to fix issue associated with SerialFlash

Use CCM_CBCMR instead "/7"

T4 - put inital calls for check pins and set pins...

Added - the code to set them as part of the Transaction Setttings.

Also put in implementations for,
SPI.setBitOrder and SPI.setDataMode.
Note the setDatMode like the T3.x does not appear to do anything yet.

Implemented using 16 bit writes

The buffer transfer now uses FIFO queues,

Currently it only outputs the 8 bits per entry, unlike the T3.x version which packed the bytes into words in order to speed up some more.

Warning this change uses the updates I did in core library to define a
SPI structure for the T4...

The code now uses this structure as wlll as pointer to it passed in to constructor to talk to the SPI registers.

Also Miso, Mosi and SCK pins are defined in Hardware structure which again is passed in to constructor... Still a few more things to cleanup in ::begin to make it  completely independant of the hardware such that I can define SPI1 as well...

Some libraries actually call this.  So define the Hardware data for the one pin for each of the MISO, MOSI, SCK and CS...

So far setting does nothing.

Enough to get Sparkfun Teensyview to build, other than example uses String class which is not included in link phase.

T3.5/6 Pin 45 is valid CS

but it is CS5 which encodes to 0x20 and our
macros only handled up to 0x1f... so changed
to 0x3f.

Tested on my ILI9341_t3n test now works with DC on 45... Needs change in Core as well

Example setup code bug

The code was doing:
pinMode(slaveSelectPin, OUTPUT);
pinMode(slaveSelectPin, HIGH);

Second pinMode should be digitalWrite

Add SPI Buffer functions

A define was under a #ifdef that it should not have been

Merged in the SPI.transfer(buf, retbuf, cnt)  version.

Also merged in the SPI.transfer(buf, retbuf, cnt, event_responder) version that does DMA access.

Allow setMISO/setMOSI/setSCK - after begin

Made the SPI code work like the old stuff where you could set the miso/mosi/sck pins after the begin.

Some people actually used this for changing SPI on the fly to use multiple sets of pins

Enable Pins - can set more options

The current table code was setup that when we choose a specific pin for MOSI or Miso or SCK (or CS), that the only thing set at the time was the MUX value.

Well the old enable_pins that was called off of the enumlated register was setting the PORT_PCR_DSE option on pins 11 and 13...

So to fix it, I have the table, allow you to fully set the options for each pin.
Still have most all of them just setting the MUX, but do have pins 11 and 13 setting the PCR_DSE option to be compatible with old code.

SPI Transfer(buf, cnt) use FIFO 16 bit

Experiment with making the whole transfer of the buffer act like it is
to logically hold the CS pins for that whole transfer.  This removes
gaps between each 16 bit transfer.

Update SPI.transfer(buf, cnt) to use the FIFO queue to speed things up.
It also speeds things up to pack the data into 16 bit transfers instead
of 8 bits.

As this code is more complicated,  no longer makes sense to inline it,
so functions moved from .h to .cpp files.

SPI1 and SPI2 transfer functions were updated as well for T3.5 and T3.6

Pin 45 is valid CS for SPI0 on new boards