Kurt Eckhardt 4cb57636b4 T4 - DMA transfer > 32K did not flush or delete whole dcache range. Ran into issues where large buffer, were not fully outputting the right data. Was seeing it on RA8876 on pages from DMAMEM and at times EXTRAM. Turns out where I did the arm_dcache_flush (or delete) I had already decreased the count to be the max size I could output in any one DMA operation without chain... So now do it before we check for MAX size... Appears to fix the display issue I was seeing		4 anni fa
examples	Example setup code bug	7 anni fa
README.md	Update readme	10 anni fa
SPI.cpp	T4 - DMA transfer > 32K did not flush or delete whole dcache range.	4 anni fa
SPI.h	T4.1 make SPI CS pins be index not mask, plus Franks change to timing	4 anni fa
keywords.txt	Add SPI Buffer functions	7 anni fa
library.properties	Add library.properties	8 anni fa

SPI Library for Teensy