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<a name="ARC_002dRegs"></a>
<div class="header">
<p>
Previous: <a href="ARC_002dChars.html#ARC_002dChars" accesskey="p" rel="prev">ARC-Chars</a>, Up: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="u" rel="up">ARC Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="Register-Names-2"></a>
<h4 class="subsubsection">9.3.2.2 Register Names</h4>

<a name="index-ARC-register-names"></a>
<a name="index-register-names_002c-ARC"></a>
<p>The ARC assembler uses the following register names for its core
registers:
</p>
<dl compact="compact">
<dt><code>r0-r31</code></dt>
<dd><a name="index-core-general-registers_002c-ARC"></a>
<a name="index-ARC-core-general-registers"></a>
<p>The core general registers.  Registers <code>r26</code> through <code>r31</code>
have special functions, and are usually referred to by those synonyms.
</p>
</dd>
<dt><code>gp</code></dt>
<dd><a name="index-global-pointer_002c-ARC"></a>
<a name="index-ARC-global-pointer"></a>
<p>The global pointer and a synonym for <code>r26</code>.
</p>
</dd>
<dt><code>fp</code></dt>
<dd><a name="index-frame-pointer_002c-ARC"></a>
<a name="index-ARC-frame-pointer"></a>
<p>The frame pointer and a synonym for <code>r27</code>.
</p>
</dd>
<dt><code>sp</code></dt>
<dd><a name="index-stack-pointer_002c-ARC"></a>
<a name="index-ARC-stack-pointer"></a>
<p>The stack pointer and a synonym for <code>r28</code>.
</p>
</dd>
<dt><code>ilink1</code></dt>
<dd><a name="index-level-1-interrupt-link-register_002c-ARC"></a>
<a name="index-ARC-level-1-interrupt-link-register"></a>
<p>For ARC 600 and ARC 700, the level 1 interrupt link register and a
synonym for <code>r29</code>.  Not supported for ARCv2.
</p>
</dd>
<dt><code>ilink</code></dt>
<dd><a name="index-interrupt-link-register_002c-ARC"></a>
<a name="index-ARC-interrupt-link-register"></a>
<p>For ARCv2, the interrupt link register and a synonym for <code>r29</code>.
Not supported for ARC 600 and ARC 700.
</p>
</dd>
<dt><code>ilink2</code></dt>
<dd><a name="index-level-2-interrupt-link-register_002c-ARC"></a>
<a name="index-ARC-level-2-interrupt-link-register"></a>
<p>For ARC 600 and ARC 700, the level 2 interrupt link register and a
synonym for <code>r30</code>.  Not supported for ARC v2.
</p>
</dd>
<dt><code>blink</code></dt>
<dd><a name="index-link-register_002c-ARC"></a>
<a name="index-ARC-link-register"></a>
<p>The link register and a synonym for <code>r31</code>.
</p>
</dd>
<dt><code>r32-r59</code></dt>
<dd><a name="index-extension-core-registers_002c-ARC"></a>
<a name="index-ARC-extension-core-registers"></a>
<p>The extension core registers.
</p>
</dd>
<dt><code>lp_count</code></dt>
<dd><a name="index-loop-counter_002c-ARC"></a>
<a name="index-ARC-loop-counter"></a>
<p>The loop count register.
</p>
</dd>
<dt><code>pcl</code></dt>
<dd><a name="index-word-aligned-program-counter_002c-ARC"></a>
<a name="index-ARC-word-aligned-program-counter"></a>
<p>The word aligned program counter.
</p>
</dd>
</dl>

<p>In addition the ARC processor has a large number of <em>auxiliary
registers</em>.  The precise set depends on the extensions being
supported, but the following baseline set are always defined:
</p>
<dl compact="compact">
<dt><code>identity</code></dt>
<dd><a name="index-Processor-Identification-register_002c-ARC"></a>
<a name="index-ARC-Processor-Identification-register"></a>
<p>Processor Identification register.  Auxiliary register address 0x4.
</p>
</dd>
<dt><code>pc</code></dt>
<dd><a name="index-Program-Counter_002c-ARC"></a>
<a name="index-ARC-Program-Counter"></a>
<p>Program Counter.  Auxiliary register address 0x6.
</p>
</dd>
<dt><code>status32</code></dt>
<dd><a name="index-Status-register_002c-ARC"></a>
<a name="index-ARC-Status-register"></a>
<p>Status register.  Auxiliary register address 0x0a.
</p>
</dd>
<dt><code>bta</code></dt>
<dd><a name="index-Branch-Target-Address_002c-ARC"></a>
<a name="index-ARC-Branch-Target-Address"></a>
<p>Branch Target Address.  Auxiliary register address 0x412.
</p>
</dd>
<dt><code>ecr</code></dt>
<dd><a name="index-Exception-Cause-Register_002c-ARC"></a>
<a name="index-ARC-Exception-Cause-Register"></a>
<p>Exception Cause Register.  Auxiliary register address 0x403.
</p>
</dd>
<dt><code>int_vector_base</code></dt>
<dd><a name="index-Interrupt-Vector-Base-address_002c-ARC"></a>
<a name="index-ARC-Interrupt-Vector-Base-address"></a>
<p>Interrupt Vector Base address.  Auxiliary register address 0x25.
</p>
</dd>
<dt><code>status32_p0</code></dt>
<dd><a name="index-Stored-STATUS32-register-on-entry-to-level-P0-interrupts_002c-ARC"></a>
<a name="index-ARC-Stored-STATUS32-register-on-entry-to-level-P0-interrupts"></a>
<p>Stored STATUS32 register on entry to level P0 interrupts.  Auxiliary
register address 0xb.
</p>
</dd>
<dt><code>aux_user_sp</code></dt>
<dd><a name="index-Saved-User-Stack-Pointer_002c-ARC"></a>
<a name="index-ARC-Saved-User-Stack-Pointer"></a>
<p>Saved User Stack Pointer.  Auxiliary register address 0xd.
</p>
</dd>
<dt><code>eret</code></dt>
<dd><a name="index-Exception-Return-Address_002c-ARC"></a>
<a name="index-ARC-Exception-Return-Address"></a>
<p>Exception Return Address.  Auxiliary register address 0x400.
</p>
</dd>
<dt><code>erbta</code></dt>
<dd><a name="index-BTA-saved-on-exception-entry_002c-ARC"></a>
<a name="index-ARC-BTA-saved-on-exception-entry"></a>
<p>BTA saved on exception entry.  Auxiliary register address 0x401.
</p>
</dd>
<dt><code>erstatus</code></dt>
<dd><a name="index-STATUS32-saved-on-exception_002c-ARC"></a>
<a name="index-ARC-STATUS32-saved-on-exception"></a>
<p>STATUS32 saved on exception.  Auxiliary register address 0x402.
</p>
</dd>
<dt><code>bcr_ver</code></dt>
<dd><a name="index-Build-Configuration-Registers-Version_002c-ARC"></a>
<a name="index-ARC-Build-Configuration-Registers-Version"></a>
<p>Build Configuration Registers Version.  Auxiliary register address 0x60.
</p>
</dd>
<dt><code>bta_link_build</code></dt>
<dd><a name="index-Build-configuration-for_003a-BTA-Registers_002c-ARC"></a>
<a name="index-ARC-Build-configuration-for_003a-BTA-Registers"></a>
<p>Build configuration for: BTA Registers.  Auxiliary register address 0x63.
</p>
</dd>
<dt><code>vecbase_ac_build</code></dt>
<dd><a name="index-Build-configuration-for_003a-Interrupts_002c-ARC"></a>
<a name="index-ARC-Build-configuration-for_003a-Interrupts"></a>
<p>Build configuration for: Interrupts.  Auxiliary register address 0x68.
</p>
</dd>
<dt><code>rf_build</code></dt>
<dd><a name="index-Build-configuration-for_003a-Core-Registers_002c-ARC"></a>
<a name="index-ARC-Build-configuration-for_003a-Core-Registers"></a>
<p>Build configuration for: Core Registers.  Auxiliary register address 0x6e.
</p>
</dd>
<dt><code>dccm_build</code></dt>
<dd><a name="index-DCCM-RAM-Configuration-Register_002c-ARC"></a>
<a name="index-ARC-DCCM-RAM-Configuration-Register"></a>
<p>DCCM RAM Configuration Register.  Auxiliary register address 0xc1.
</p>
</dd>
</dl>

<p>Additional auxiliary register names are defined according to the
processor architecture version and extensions selected by the options.
</p>
<hr>
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<p>
Previous: <a href="ARC_002dChars.html#ARC_002dChars" accesskey="p" rel="prev">ARC-Chars</a>, Up: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="u" rel="up">ARC Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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