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<title>RISC-V Features (Debugging with GDB)</title>

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<a name="RISC_002dV-Features"></a>
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Next: <a href="RX-Features.html#RX-Features" accesskey="n" rel="next">RX Features</a>, Previous: <a href="PowerPC-Features.html#PowerPC-Features" accesskey="p" rel="prev">PowerPC Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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<a name="RISC_002dV-Features-1"></a>
<h4 class="subsection">G.5.12 RISC-V Features</h4>
<a name="index-target-descriptions_002c-RISC_002dV-Features"></a>

<p>The &lsquo;<samp>org.gnu.gdb.riscv.cpu</samp>&rsquo; feature is required for RISC-V
targets.  It should contain the registers &lsquo;<samp>x0</samp>&rsquo; through
&lsquo;<samp>x31</samp>&rsquo;, and &lsquo;<samp>pc</samp>&rsquo;.  Either the architectural names (&lsquo;<samp>x0</samp>&rsquo;,
&lsquo;<samp>x1</samp>&rsquo;, etc) can be used, or the ABI names (&lsquo;<samp>zero</samp>&rsquo;, &lsquo;<samp>ra</samp>&rsquo;,
etc).
</p>
<p>The &lsquo;<samp>org.gnu.gdb.riscv.fpu</samp>&rsquo; feature is optional.  If present, it
should contain registers &lsquo;<samp>f0</samp>&rsquo; through &lsquo;<samp>f31</samp>&rsquo;, &lsquo;<samp>fflags</samp>&rsquo;,
&lsquo;<samp>frm</samp>&rsquo;, and &lsquo;<samp>fcsr</samp>&rsquo;.  As with the cpu feature, either the
architectural register names, or the ABI names can be used.
</p>
<p>The &lsquo;<samp>org.gnu.gdb.riscv.virtual</samp>&rsquo; feature is optional.  If present,
it should contain registers that are not backed by real registers on
the target, but are instead virtual, where the register value is
derived from other target state.  In many ways these are like
<small>GDB</small>s pseudo-registers, except implemented by the target.
Currently the only register expected in this set is the one byte
&lsquo;<samp>priv</samp>&rsquo; register that contains the target&rsquo;s privilege level in the
least significant two bits.
</p>
<p>The &lsquo;<samp>org.gnu.gdb.riscv.csr</samp>&rsquo; feature is optional.  If present, it
should contain all of the target&rsquo;s standard CSRs.  Standard CSRs are
those defined in the RISC-V specification documents.  There is some
overlap between this feature and the fpu feature; the &lsquo;<samp>fflags</samp>&rsquo;,
&lsquo;<samp>frm</samp>&rsquo;, and &lsquo;<samp>fcsr</samp>&rsquo; registers could be in either feature.  The
expectation is that these registers will be in the fpu feature if the
target has floating point hardware, but can be moved into the csr
feature if the target has the floating point control registers, but no
other floating point hardware.
</p>


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