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<a name="AArch64-Extensions"></a>
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<p>
Next: <a href="AArch64-Syntax.html#AArch64-Syntax" accesskey="n" rel="next">AArch64 Syntax</a>, Previous: <a href="AArch64-Options.html#AArch64-Options" accesskey="p" rel="prev">AArch64 Options</a>, Up: <a href="AArch64_002dDependent.html#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
<a name="Architecture-Extensions"></a>
<h4 class="subsection">9.1.2 Architecture Extensions</h4>

<p>The table below lists the permitted architecture extensions that are
supported by the assembler and the conditions under which they are
automatically enabled.
</p>
<p>Multiple extensions may be specified, separated by a <code>+</code>.
Extension mnemonics may also be removed from those the assembler
accepts.  This is done by prepending <code>no</code> to the option that adds
the extension.  Extensions that are removed must be listed after all
extensions that have been added.
</p>
<p>Enabling an extension that requires other extensions will
automatically cause those extensions to be enabled.  Similarly,
disabling an extension that is required by other extensions will
automatically cause those extensions to be disabled.
</p>
<table>
<thead><tr><th width="12%">Extension</th><th width="17%">Minimum Architecture</th><th width="17%">Enabled by default</th><th width="54%">Description</th></tr></thead>
<tr><td width="12%"><code>i8mm</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.6-A or later</td><td width="54%">Enable Int8 Matrix Multiply extension.</td></tr>
<tr><td width="12%"><code>f32mm</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable F32 Matrix Multiply extension.</td></tr>
<tr><td width="12%"><code>f64mm</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable F64 Matrix Multiply extension.</td></tr>
<tr><td width="12%"><code>bf16</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.6-A or later</td><td width="54%">Enable BFloat16 extension.</td></tr>
<tr><td width="12%"><code>compnum</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.3-A or later</td><td width="54%">Enable the complex number SIMD extensions.  This implies
 <code>fp16</code> and <code>simd</code>.</td></tr>
<tr><td width="12%"><code>crc</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable CRC instructions.</td></tr>
<tr><td width="12%"><code>crypto</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable cryptographic extensions.  This implies <code>fp</code>, <code>simd</code>, <code>aes</code> and <code>sha2</code>.</td></tr>
<tr><td width="12%"><code>aes</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable the AES cryptographic extensions. This implies <code>fp</code> and <code>simd</code>.</td></tr>
<tr><td width="12%"><code>sha2</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable the SHA2 cryptographic extensions. This implies <code>fp</code> and <code>simd</code>.</td></tr>
<tr><td width="12%"><code>sha3</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies <code>fp</code>, <code>simd</code> and <code>sha2</code>.</td></tr>
<tr><td width="12%"><code>sm4</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies <code>fp</code> and <code>simd</code>.</td></tr>
<tr><td width="12%"><code>fp</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8-A or later</td><td width="54%">Enable floating-point extensions.</td></tr>
<tr><td width="12%"><code>fp16</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.2-A or later</td><td width="54%">Enable ARMv8.2 16-bit floating-point support.  This implies
 <code>fp</code>.</td></tr>
<tr><td width="12%"><code>lor</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable Limited Ordering Regions extensions.</td></tr>
<tr><td width="12%"><code>lse</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable Large System extensions.</td></tr>
<tr><td width="12%"><code>pan</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable Privileged Access Never support.</td></tr>
<tr><td width="12%"><code>profile</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable statistical profiling extensions.</td></tr>
<tr><td width="12%"><code>ras</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.2-A or later</td><td width="54%">Enable the Reliability, Availability and Serviceability
 extension.</td></tr>
<tr><td width="12%"><code>rcpc</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.3-A or later</td><td width="54%">Enable the weak release consistency extension.</td></tr>
<tr><td width="12%"><code>rdma</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.1-A or later</td><td width="54%">Enable ARMv8.1 Advanced SIMD extensions.  This implies <code>simd</code>.</td></tr>
<tr><td width="12%"><code>simd</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8-A or later</td><td width="54%">Enable Advanced SIMD extensions.  This implies <code>fp</code>.</td></tr>
<tr><td width="12%"><code>sve</code></td><td width="17%">ARMv8.2-A</td><td width="17%">No</td><td width="54%">Enable the Scalable Vector Extensions.  This implies <code>fp16</code>,
 <code>simd</code> and <code>compnum</code>.</td></tr>
<tr><td width="12%"><code>dotprod</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.4-A or later</td><td width="54%">Enable the Dot Product extension.  This implies <code>simd</code>.</td></tr>
<tr><td width="12%"><code>fp16fml</code></td><td width="17%">ARMv8.2-A</td><td width="17%">ARMv8.4-A or later</td><td width="54%">Enable ARMv8.2 16-bit floating-point multiplication variant support.
 This implies <code>fp16</code>.</td></tr>
<tr><td width="12%"><code>sb</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.5-A or later</td><td width="54%">Enable the speculation barrier instruction sb.</td></tr>
<tr><td width="12%"><code>predres</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.5-A or later</td><td width="54%">Enable the Execution and Data and Prediction instructions.</td></tr>
<tr><td width="12%"><code>rng</code></td><td width="17%">ARMv8.5-A</td><td width="17%">No</td><td width="54%">Enable ARMv8.5-A random number instructions.</td></tr>
<tr><td width="12%"><code>ssbs</code></td><td width="17%">ARMv8-A</td><td width="17%">ARMv8.5-A or later</td><td width="54%">Enable Speculative Store Bypassing Safe state read and write.</td></tr>
<tr><td width="12%"><code>memtag</code></td><td width="17%">ARMv8.5-A</td><td width="17%">No</td><td width="54%">Enable ARMv8.5-A Memory Tagging Extensions.</td></tr>
<tr><td width="12%"><code>tme</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable Transactional Memory Extensions.</td></tr>
<tr><td width="12%"><code>sve2</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable the SVE2 Extension.</td></tr>
<tr><td width="12%"><code>sve2-bitperm</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 BITPERM Extension.</td></tr>
<tr><td width="12%"><code>sve2-sm4</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 SM4 Extension.</td></tr>
<tr><td width="12%"><code>sve2-aes</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 AES Extension.  This also enables the .Q-&gt;.B form of the
 <code>pmullt</code> and <code>pmullb</code> instructions.</td></tr>
<tr><td width="12%"><code>sve2-sha3</code></td><td width="17%">ARMv8-A</td><td width="17%">No</td><td width="54%">Enable SVE2 SHA3 Extension.</td></tr>
</table>

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