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  56. <a name="MSP430-Options"></a>
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  58. <p>
  59. Next: <a href="MSP430-Syntax.html#MSP430-Syntax" accesskey="n" rel="next">MSP430 Syntax</a>, Up: <a href="MSP430_002dDependent.html#MSP430_002dDependent" accesskey="u" rel="up">MSP430-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
  60. </div>
  61. <hr>
  62. <a name="Options-15"></a>
  63. <h4 class="subsection">9.29.1 Options</h4>
  64. <a name="index-MSP-430-options-_0028none_0029"></a>
  65. <a name="index-options-for-MSP430-_0028none_0029"></a>
  66. <dl compact="compact">
  67. <dt><code>-mmcu</code></dt>
  68. <dd><p>selects the mcu architecture. If the architecture is 430Xv2 then this
  69. also enables NOP generation unless the <samp>-mN</samp> is also specified.
  70. </p>
  71. </dd>
  72. <dt><code>-mcpu</code></dt>
  73. <dd><p>selects the cpu architecture. If the architecture is 430Xv2 then this
  74. also enables NOP generation unless the <samp>-mN</samp> is also specified.
  75. </p>
  76. </dd>
  77. <dt><code>-msilicon-errata=<var>name</var>[,<var>name</var>&hellip;]</code></dt>
  78. <dd><p>Implements a fixup for named silicon errata. Multiple silicon errata
  79. can be specified by multiple uses of the <samp>-msilicon-errata</samp>
  80. option and/or by including the errata names, separated by commas, on
  81. an individual <samp>-msilicon-errata</samp> option. Errata names
  82. currently recognised by the assembler are:
  83. </p>
  84. <dl compact="compact">
  85. <dt><code>cpu4</code></dt>
  86. <dd><p><code>PUSH #4</code> and <samp>PUSH #8</samp> need longer encodings on the
  87. MSP430. This option is enabled by default, and cannot be disabled.
  88. </p></dd>
  89. <dt><code>cpu8</code></dt>
  90. <dd><p>Do not set the <code>SP</code> to an odd value.
  91. </p></dd>
  92. <dt><code>cpu11</code></dt>
  93. <dd><p>Do not update the <code>SR</code> and the <code>PC</code> in the same instruction.
  94. </p></dd>
  95. <dt><code>cpu12</code></dt>
  96. <dd><p>Do not use the <code>PC</code> in a <code>CMP</code> or <code>BIT</code> instruction.
  97. </p></dd>
  98. <dt><code>cpu13</code></dt>
  99. <dd><p>Do not use an arithmetic instruction to modify the <code>SR</code>.
  100. </p></dd>
  101. <dt><code>cpu19</code></dt>
  102. <dd><p>Insert <code>NOP</code> after <code>CPUOFF</code>.
  103. </p></dd>
  104. </dl>
  105. </dd>
  106. <dt><code>-msilicon-errata-warn=<var>name</var>[,<var>name</var>&hellip;]</code></dt>
  107. <dd><p>Like the <samp>-msilicon-errata</samp> option except that instead of
  108. fixing the specified errata, a warning message is issued instead.
  109. This option can be used alongside <samp>-msilicon-errata</samp> to
  110. generate messages whenever a problem is fixed, or on its own in order
  111. to inspect code for potential problems.
  112. </p>
  113. </dd>
  114. <dt><code>-mP</code></dt>
  115. <dd><p>enables polymorph instructions handler.
  116. </p>
  117. </dd>
  118. <dt><code>-mQ</code></dt>
  119. <dd><p>enables relaxation at assembly time. DANGEROUS!
  120. </p>
  121. </dd>
  122. <dt><code>-ml</code></dt>
  123. <dd><p>indicates that the input uses the large code model.
  124. </p>
  125. </dd>
  126. <dt><code>-mn</code></dt>
  127. <dd><p>enables the generation of a NOP instruction following any instruction
  128. that might change the interrupts enabled/disabled state. The
  129. pipelined nature of the MSP430 core means that any instruction that
  130. changes the interrupt state (<code>EINT</code>, <code>DINT</code>, <code>BIC #8,
  131. SR</code>, <code>BIS #8, SR</code> or <code>MOV.W &lt;&gt;, SR</code>) must be
  132. followed by a NOP instruction in order to ensure the correct
  133. processing of interrupts. By default it is up to the programmer to
  134. supply these NOP instructions, but this command-line option enables
  135. the automatic insertion by the assembler, if they are missing.
  136. </p>
  137. </dd>
  138. <dt><code>-mN</code></dt>
  139. <dd><p>disables the generation of a NOP instruction following any instruction
  140. that might change the interrupts enabled/disabled state. This is the
  141. default behaviour.
  142. </p>
  143. </dd>
  144. <dt><code>-my</code></dt>
  145. <dd><p>tells the assembler to generate a warning message if a NOP does not
  146. immediately follow an instruction that enables or disables
  147. interrupts. This is the default.
  148. </p>
  149. <p>Note that this option can be stacked with the <samp>-mn</samp> option so
  150. that the assembler will both warn about missing NOP instructions and
  151. then insert them automatically.
  152. </p>
  153. </dd>
  154. <dt><code>-mY</code></dt>
  155. <dd><p>disables warnings about missing NOP instructions.
  156. </p>
  157. </dd>
  158. <dt><code>-md</code></dt>
  159. <dd><p>mark the object file as one that requires data to copied from ROM to
  160. RAM at execution startup. Disabled by default.
  161. </p>
  162. </dd>
  163. <dt><code>-mdata-region=<var>region</var></code></dt>
  164. <dd><p>Select the region data will be placed in.
  165. Region placement is performed by the compiler and linker. The only effect this
  166. option will have on the assembler is that if <var>upper</var> or <var>either</var> is
  167. selected, then the symbols to initialise high data and bss will be defined.
  168. Valid <var>region</var> values are:
  169. </p><dl compact="compact">
  170. <dt><code>none</code></dt>
  171. <dt><code>lower</code></dt>
  172. <dt><code>upper</code></dt>
  173. <dt><code>either</code></dt>
  174. </dl>
  175. </dd>
  176. </dl>
  177. <hr>
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  179. <p>
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