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SH-Opcodes.html 3.9KB

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  15. <title>SH Opcodes (Using as)</title>
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  56. <a name="SH-Opcodes"></a>
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  58. <p>
  59. Previous: <a href="SH-Directives.html#SH-Directives" accesskey="p" rel="prev">SH Directives</a>, Up: <a href="SH_002dDependent.html#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
  60. </div>
  61. <hr>
  62. <a name="Opcodes-18"></a>
  63. <h4 class="subsection">9.43.5 Opcodes</h4>
  64. <a name="index-SH-opcode-summary"></a>
  65. <a name="index-opcode-summary_002c-SH"></a>
  66. <a name="index-mnemonics_002c-SH"></a>
  67. <a name="index-instruction-summary_002c-SH"></a>
  68. <p>For detailed information on the SH machine instruction set, see
  69. <cite>SH-Microcomputer User&rsquo;s Manual</cite> (Renesas) or
  70. <cite>SH-4 32-bit CPU Core Architecture</cite> (SuperH) and
  71. <cite>SuperH (SH) 64-Bit RISC Series</cite> (SuperH).
  72. </p>
  73. <p><code>as</code> implements all the standard SH opcodes. No additional
  74. pseudo-instructions are needed on this family. Note, however, that
  75. because <code>as</code> supports a simpler form of PC-relative
  76. addressing, you may simply write (for example)
  77. </p>
  78. <div class="example">
  79. <pre class="example">mov.l bar,r0
  80. </pre></div>
  81. <p>where other assemblers might require an explicit displacement to
  82. <code>bar</code> from the program counter:
  83. </p>
  84. <div class="example">
  85. <pre class="example">mov.l @(<var>disp</var>, PC)
  86. </pre></div>
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