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<a name="Z80-Opcodes"></a>
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<p>
Previous: <a href="Z80-Directives.html#Z80-Directives" accesskey="p" rel="prev">Z80 Directives</a>, Up: <a href="Z80_002dDependent.html#Z80_002dDependent" accesskey="u" rel="up">Z80-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
<a name="Opcodes-22"></a>
<h4 class="subsection">9.56.5 Opcodes</h4>
<p>In line with common practice, Z80 mnemonics are used for the Z80,
Z80N, Z180, eZ80, Ascii R800 and the GameBoy Z80.
</p>
<p>In many instructions it is possible to use one of the half index
registers (&lsquo;<samp>ixl</samp>&rsquo;,&lsquo;<samp>ixh</samp>&rsquo;,&lsquo;<samp>iyl</samp>&rsquo;,&lsquo;<samp>iyh</samp>&rsquo;) in stead of an
8-bit general purpose register. This yields instructions that are
documented on the eZ80 and the R800, undocumented on the Z80 and
unsupported on the Z180.
Similarly <code>in f,(c)</code> is documented on the R800, undocumented on
the Z80 and unsupported on the Z180 and the eZ80.
</p>
<p>The assembler also supports the following undocumented Z80-instructions,
that have not been adopted in any other instruction set:
</p><dl compact="compact">
<dt><code>out (c),0</code></dt>
<dd><p>Sends zero to the port pointed to by register <code>C</code>.
</p>
</dd>
<dt><code>sli <var>m</var></code></dt>
<dd><p>Equivalent to <code><var>m</var> = (<var>m</var>&lt;&lt;1)+1</code>, the operand <var>m</var> can
be any operand that is valid for &lsquo;<samp>sla</samp>&rsquo;. One can use &lsquo;<samp>sll</samp>&rsquo; as a
synonym for &lsquo;<samp>sli</samp>&rsquo;.
</p>
</dd>
<dt><code><var>op</var> (ix+<var>d</var>), <var>r</var></code></dt>
<dd><p>This is equivalent to
</p>
<div class="example">
<pre class="example">ld <var>r</var>, (ix+<var>d</var>)
<var>op</var> <var>r</var>
ld (ix+<var>d</var>), <var>r</var>
</pre></div>

<p>The operation &lsquo;<samp><var>op</var></samp>&rsquo; may be any of &lsquo;<samp>res <var>b</var>,</samp>&rsquo;,
&lsquo;<samp>set <var>b</var>,</samp>&rsquo;, &lsquo;<samp>rl</samp>&rsquo;, &lsquo;<samp>rlc</samp>&rsquo;, &lsquo;<samp>rr</samp>&rsquo;, &lsquo;<samp>rrc</samp>&rsquo;,
&lsquo;<samp>sla</samp>&rsquo;, &lsquo;<samp>sli</samp>&rsquo;, &lsquo;<samp>sra</samp>&rsquo; and &lsquo;<samp>srl</samp>&rsquo;, and the register
&lsquo;<samp><var>r</var></samp>&rsquo; may be any of &lsquo;<samp>a</samp>&rsquo;, &lsquo;<samp>b</samp>&rsquo;, &lsquo;<samp>c</samp>&rsquo;, &lsquo;<samp>d</samp>&rsquo;,
&lsquo;<samp>e</samp>&rsquo;, &lsquo;<samp>h</samp>&rsquo; and &lsquo;<samp>l</samp>&rsquo;.
</p>
</dd>
<dt><code><var>op</var> (iy+<var>d</var>), <var>r</var></code></dt>
<dd><p>As above, but with &lsquo;<samp>iy</samp>&rsquo; instead of &lsquo;<samp>ix</samp>&rsquo;.
</p></dd>
</dl>

<p>The web site at <a href="http://www.z80.info">http://www.z80.info</a> is a good starting place to
find more information on programming the Z80.
</p>
<p>You may enable or disable any of these instructions for any target CPU
even this instruction is not supported by any real CPU of this type.
Useful for custom CPU cores.
</p>
<hr>
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<p>
Previous: <a href="Z80-Directives.html#Z80-Directives" accesskey="p" rel="prev">Z80 Directives</a>, Up: <a href="Z80_002dDependent.html#Z80_002dDependent" accesskey="u" rel="up">Z80-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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