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i386_002dDependent.html 7.1KB

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  15. <title>i386-Dependent (Using as)</title>
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  24. <link href="Machine-Dependencies.html#Machine-Dependencies" rel="up" title="Machine Dependencies">
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  56. <a name="i386_002dDependent"></a>
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  58. <p>
  59. Next: <a href="IA_002d64_002dDependent.html#IA_002d64_002dDependent" accesskey="n" rel="next">IA-64-Dependent</a>, Previous: <a href="HPPA_002dDependent.html#HPPA_002dDependent" accesskey="p" rel="prev">HPPA-Dependent</a>, Up: <a href="Machine-Dependencies.html#Machine-Dependencies" accesskey="u" rel="up">Machine Dependencies</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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  61. <hr>
  62. <a name="g_t80386-Dependent-Features"></a>
  63. <h3 class="section">9.16 80386 Dependent Features</h3>
  64. <a name="index-i386-support"></a>
  65. <a name="index-i80386-support"></a>
  66. <a name="index-x86_002d64-support"></a>
  67. <p>The i386 version <code>as</code> supports both the original Intel 386
  68. architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
  69. extending the Intel architecture to 64-bits.
  70. </p>
  71. <table class="menu" border="0" cellspacing="0">
  72. <tr><td align="left" valign="top">&bull; <a href="i386_002dOptions.html#i386_002dOptions" accesskey="1">i386-Options</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Options
  73. </td></tr>
  74. <tr><td align="left" valign="top">&bull; <a href="i386_002dDirectives.html#i386_002dDirectives" accesskey="2">i386-Directives</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">X86 specific directives
  75. </td></tr>
  76. <tr><td align="left" valign="top">&bull; <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="3">i386-Syntax</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Syntactical considerations
  77. </td></tr>
  78. <tr><td align="left" valign="top">&bull; <a href="i386_002dMnemonics.html#i386_002dMnemonics" accesskey="4">i386-Mnemonics</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Instruction Naming
  79. </td></tr>
  80. <tr><td align="left" valign="top">&bull; <a href="i386_002dRegs.html#i386_002dRegs" accesskey="5">i386-Regs</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Register Naming
  81. </td></tr>
  82. <tr><td align="left" valign="top">&bull; <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="6">i386-Prefixes</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Instruction Prefixes
  83. </td></tr>
  84. <tr><td align="left" valign="top">&bull; <a href="i386_002dMemory.html#i386_002dMemory" accesskey="7">i386-Memory</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Memory References
  85. </td></tr>
  86. <tr><td align="left" valign="top">&bull; <a href="i386_002dJumps.html#i386_002dJumps" accesskey="8">i386-Jumps</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Handling of Jump Instructions
  87. </td></tr>
  88. <tr><td align="left" valign="top">&bull; <a href="i386_002dFloat.html#i386_002dFloat" accesskey="9">i386-Float</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Floating Point
  89. </td></tr>
  90. <tr><td align="left" valign="top">&bull; <a href="i386_002dSIMD.html#i386_002dSIMD">i386-SIMD</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Intel&rsquo;s MMX and AMD&rsquo;s 3DNow! SIMD Operations
  91. </td></tr>
  92. <tr><td align="left" valign="top">&bull; <a href="i386_002dLWP.html#i386_002dLWP">i386-LWP</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">AMD&rsquo;s Lightweight Profiling Instructions
  93. </td></tr>
  94. <tr><td align="left" valign="top">&bull; <a href="i386_002dBMI.html#i386_002dBMI">i386-BMI</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Bit Manipulation Instruction
  95. </td></tr>
  96. <tr><td align="left" valign="top">&bull; <a href="i386_002dTBM.html#i386_002dTBM">i386-TBM</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">AMD&rsquo;s Trailing Bit Manipulation Instructions
  97. </td></tr>
  98. <tr><td align="left" valign="top">&bull; <a href="i386_002d16bit.html#i386_002d16bit">i386-16bit</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Writing 16-bit Code
  99. </td></tr>
  100. <tr><td align="left" valign="top">&bull; <a href="i386_002dArch.html#i386_002dArch">i386-Arch</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Specifying an x86 CPU architecture
  101. </td></tr>
  102. <tr><td align="left" valign="top">&bull; <a href="i386_002dISA.html#i386_002dISA">i386-ISA</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">AMD64 ISA vs. Intel64 ISA
  103. </td></tr>
  104. <tr><td align="left" valign="top">&bull; <a href="i386_002dBugs.html#i386_002dBugs">i386-Bugs</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">AT&amp;T Syntax bugs
  105. </td></tr>
  106. <tr><td align="left" valign="top">&bull; <a href="i386_002dNotes.html#i386_002dNotes">i386-Notes</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Notes
  107. </td></tr>
  108. </table>
  109. </body>
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