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These ‘-m’ options are defined for the ARM port:
-mabi=nameGenerate code for the specified ABI. Permissible values are: ‘apcs-gnu’, ‘atpcs’, ‘aapcs’, ‘aapcs-linux’ and ‘iwmmxt’.
-mapcs-frameGenerate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if this is not strictly necessary for correct execution of the code. Specifying -fomit-frame-pointer with this option causes the stack frames not to be generated for leaf functions. The default is -mno-apcs-frame. This option is deprecated.
-mapcsThis is a synonym for -mapcs-frame and is deprecated.
-mthumb-interworkGenerate code that supports calling between the ARM and Thumb instruction sets. Without this option, on pre-v5 architectures, the two instruction sets cannot be reliably used inside one program. The default is -mno-thumb-interwork, since slightly larger code is generated when -mthumb-interwork is specified. In AAPCS configurations this option is meaningless.
-mno-sched-prologPrevent the reordering of instructions in the function prologue, or the merging of those instruction with the instructions in the function’s body. This means that all functions start with a recognizable set of instructions (or in fact one of a choice from a small set of different function prologues), and this information can be used to locate the start of functions inside an executable piece of code. The default is -msched-prolog.
-mfloat-abi=nameSpecifies which floating-point ABI to use. Permissible values are: ‘soft’, ‘softfp’ and ‘hard’.
Specifying ‘soft’ causes GCC to generate output containing library calls for floating-point operations. ‘softfp’ allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions. ‘hard’ allows generation of floating-point instructions and uses FPU-specific calling conventions.
The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.
-mgeneral-regs-onlyGenerate code which uses only the general-purpose registers. This will prevent the compiler from using floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler.
-mlittle-endianGenerate code for a processor running in little-endian mode. This is the default for all standard configurations.
-mbig-endianGenerate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor.
-mbe8-mbe32When linking a big-endian image select between BE8 and BE32 formats. The option has no effect for little-endian images and is ignored. The default is dependent on the selected target architecture. For ARMv6 and later architectures the default is BE8, for older architectures the default is BE32. BE32 format has been deprecated by ARM.
-march=name[+extension…]This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the -mcpu= option.
Permissible names are: ‘armv4t’, ‘armv5t’, ‘armv5te’, ‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6kz’, ‘armv6t2’, ‘armv6z’, ‘armv6zk’, ‘armv7’, ‘armv7-a’, ‘armv7ve’, ‘armv8-a’, ‘armv8.1-a’, ‘armv8.2-a’, ‘armv8.3-a’, ‘armv8.4-a’, ‘armv8.5-a’, ‘armv8.6-a’, ‘armv7-r’, ‘armv8-r’, ‘armv6-m’, ‘armv6s-m’, ‘armv7-m’, ‘armv7e-m’, ‘armv8-m.base’, ‘armv8-m.main’, ‘armv8.1-m.main’, ‘iwmmxt’ and ‘iwmmxt2’.
Additionally, the following architectures, which lack support for the Thumb execution state, are recognized but support is deprecated: ‘armv4’.
Many of the architectures support extensions. These can be added by appending ‘+extension’ to the architecture name. Extension options are processed in order and capabilities accumulate. An extension will also enable any necessary base extensions upon which it depends. For example, the ‘+crypto’ extension will always enable the ‘+simd’ extension. The exception to the additive construction is for extensions that are prefixed with ‘+no…’: these extensions disable the specified option and any other extensions that may depend on the presence of that extension.
For example, ‘-march=armv7-a+simd+nofp+vfpv4’ is equivalent to writing ‘-march=armv7-a+vfpv4’ since the ‘+simd’ option is entirely disabled by the ‘+nofp’ option that follows it.
Most extension names are generically named, but have an effect that is dependent upon the architecture to which it is applied. For example, the ‘+simd’ option can be applied to both ‘armv7-a’ and ‘armv8-a’ architectures, but will enable the original ARMv7-A Advanced SIMD (Neon) extensions for ‘armv7-a’ and the ARMv8-A variant for ‘armv8-a’.
The table below lists the supported extensions for each architecture. Architectures not mentioned do not support any extensions.
The VFPv2 floating-point instructions. The extension ‘+vfpv2’ can be used as an alias for this extension.
Disable the floating-point instructions.
The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures.
The VFPv3 floating-point instructions, with 16 double-precision registers. The extension ‘+vfpv3-d16’ can be used as an alias for this extension. Note that floating-point is not supported by the base ARMv7-M architecture, but is compatible with both the ARMv7-A and ARMv7-R architectures.
Disable the floating-point instructions.
The multiprocessing extension.
The security extension.
The VFPv3 floating-point instructions, with 16 double-precision registers. The extension ‘+vfpv3-d16’ can be used as an alias for this extension.
The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extensions ‘+neon’ and ‘+neon-vfpv3’ can be used as aliases for this extension.
The VFPv3 floating-point instructions, with 32 double-precision registers.
The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision floating-point conversion operations.
The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision floating-point conversion operations.
The VFPv4 floating-point instructions, with 16 double-precision registers.
The VFPv4 floating-point instructions, with 32 double-precision registers.
The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision floating-point conversion operations.
The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions.
Disable the Advanced SIMD instructions (does not disable floating point).
Disable the floating-point and Advanced SIMD instructions.
The extended version of the ARMv7-A architecture with support for virtualization.
The VFPv4 floating-point instructions, with 16 double-precision registers. The extension ‘+vfpv4-d16’ can be used as an alias for this extension.
The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. The extension ‘+neon-vfpv4’ can be used as an alias for this extension.
The VFPv3 floating-point instructions, with 16 double-precision registers.
The VFPv3 floating-point instructions, with 32 double-precision registers.
The VFPv3 floating-point instructions, with 16 double-precision registers and the half-precision floating-point conversion operations.
The VFPv3 floating-point instructions, with 32 double-precision registers and the half-precision floating-point conversion operations.
The VFPv4 floating-point instructions, with 16 double-precision registers.
The VFPv4 floating-point instructions, with 32 double-precision registers.
The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. The extension ‘+neon-vfpv3’ can be used as an alias for this extension.
The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with the half-precision floating-point conversion operations.
Disable the Advanced SIMD instructions (does not disable floating point).
Disable the floating-point and Advanced SIMD instructions.
The Cyclic Redundancy Check (CRC) instructions.
The ARMv8-A Advanced SIMD and floating-point instructions.
The cryptographic instructions.
Disable the cryptographic instructions.
Disable the floating-point, Advanced SIMD and cryptographic instructions.
Speculation Barrier Instruction.
Execution and Data Prediction Restriction Instructions.
The ARMv8.1-A Advanced SIMD and floating-point instructions.
The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions.
Disable the cryptographic instructions.
Disable the floating-point, Advanced SIMD and cryptographic instructions.
Speculation Barrier Instruction.
Execution and Data Prediction Restriction Instructions.
The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions.
The half-precision floating-point fmla extension. This also enables the half-precision floating-point extension and Advanced SIMD and floating-point instructions.
The ARMv8.1-A Advanced SIMD and floating-point instructions.
The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions.
Enable the Dot Product extension. This also enables Advanced SIMD instructions.
Disable the cryptographic extension.
Disable the floating-point, Advanced SIMD and cryptographic instructions.
Speculation Barrier Instruction.
Execution and Data Prediction Restriction Instructions.
8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions.
Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions.
The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension.
The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension.
The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension.
Disable the cryptographic extension.
Disable the floating-point, Advanced SIMD and cryptographic instructions.
Speculation Barrier Instruction.
Execution and Data Prediction Restriction Instructions.
8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions.
Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions.
The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension.
The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension.
The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension.
Disable the cryptographic extension.
Disable the floating-point, Advanced SIMD and cryptographic instructions.
8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions.
Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions.
The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension and the half-precision floating-point fmla extension.
The ARMv8.3-A Advanced SIMD and floating-point instructions as well as the Dot Product extension.
The cryptographic instructions. This also enables the Advanced SIMD and floating-point instructions as well as the Dot Product extension.
Disable the cryptographic extension.
Disable the floating-point, Advanced SIMD and cryptographic instructions.
8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point instructions.
Brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-point instructions.
The single-precision VFPv3 floating-point instructions. The extension ‘+vfpv3xd’ can be used as an alias for this extension.
The VFPv3 floating-point instructions with 16 double-precision registers. The extension +vfpv3-d16 can be used as an alias for this extension.
The single-precision VFPv3 floating-point instructions with 16 double-precision registers and the half-precision floating-point conversion operations.
The VFPv3 floating-point instructions with 16 double-precision registers and the half-precision floating-point conversion operations.
Disable the floating-point extension.
The ARM-state integer division instructions.
Disable the ARM-state integer division extension.
The single-precision VFPv4 floating-point instructions.
The single-precision FPv5 floating-point instructions.
The single- and double-precision FPv5 floating-point instructions.
Disable the floating-point extensions.
The DSP instructions.
The M-Profile Vector Extension (MVE) integer instructions.
The M-Profile Vector Extension (MVE) integer and single precision floating-point instructions.
The single-precision floating-point instructions.
The single- and double-precision floating-point instructions.
Disable the floating-point extension.
Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7.
The DSP instructions.
Disable the DSP extension.
The single-precision floating-point instructions.
The single- and double-precision floating-point instructions.
Disable the floating-point extension.
Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7.
The Cyclic Redundancy Check (CRC) instructions.
The single-precision FPv5 floating-point instructions.
The ARMv8-A Advanced SIMD and floating-point instructions.
The cryptographic instructions.
Disable the cryptographic instructions.
Disable the floating-point, Advanced SIMD and cryptographic instructions.
-march=native causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-mtune=nameThis option specifies the name of the target ARM processor for which GCC should tune the performance of the code. For some ARM implementations better performance can be obtained by using this option. Permissible names are: ‘arm7tdmi’, ‘arm7tdmi-s’, ‘arm710t’, ‘arm720t’, ‘arm740t’, ‘strongarm’, ‘strongarm110’, ‘strongarm1100’, 0‘strongarm1110’, ‘arm8’, ‘arm810’, ‘arm9’, ‘arm9e’, ‘arm920’, ‘arm920t’, ‘arm922t’, ‘arm946e-s’, ‘arm966e-s’, ‘arm968e-s’, ‘arm926ej-s’, ‘arm940t’, ‘arm9tdmi’, ‘arm10tdmi’, ‘arm1020t’, ‘arm1026ej-s’, ‘arm10e’, ‘arm1020e’, ‘arm1022e’, ‘arm1136j-s’, ‘arm1136jf-s’, ‘mpcore’, ‘mpcorenovfp’, ‘arm1156t2-s’, ‘arm1156t2f-s’, ‘arm1176jz-s’, ‘arm1176jzf-s’, ‘generic-armv7-a’, ‘cortex-a5’, ‘cortex-a7’, ‘cortex-a8’, ‘cortex-a9’, ‘cortex-a12’, ‘cortex-a15’, ‘cortex-a17’, ‘cortex-a32’, ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a55’, ‘cortex-a57’, ‘cortex-a72’, ‘cortex-a73’, ‘cortex-a75’, ‘cortex-a76’, ‘cortex-a76ae’, ‘cortex-a77’, ‘ares’, ‘cortex-r4’, ‘cortex-r4f’, ‘cortex-r5’, ‘cortex-r7’, ‘cortex-r8’, ‘cortex-r52’, ‘cortex-m0’, ‘cortex-m0plus’, ‘cortex-m1’, ‘cortex-m3’, ‘cortex-m4’, ‘cortex-m7’, ‘cortex-m23’, ‘cortex-m33’, ‘cortex-m35p’, ‘cortex-m55’, ‘cortex-m1.small-multiply’, ‘cortex-m0.small-multiply’, ‘cortex-m0plus.small-multiply’, ‘exynos-m1’, ‘marvell-pj4’, ‘neoverse-n1’, ‘neoverse-n2’, ‘neoverse-v1’, ‘xscale’, ‘iwmmxt’, ‘iwmmxt2’, ‘ep9312’, ‘fa526’, ‘fa626’, ‘fa606te’, ‘fa626te’, ‘fmp626’, ‘fa726te’, ‘xgene1’.
Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: ‘cortex-a15.cortex-a7’, ‘cortex-a17.cortex-a7’, ‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’, ‘cortex-a72.cortex-a35’, ‘cortex-a73.cortex-a53’, ‘cortex-a75.cortex-a55’, ‘cortex-a76.cortex-a55’.
-mtune=generic-arch specifies that GCC should tune the performance for a blend of processors within architecture arch. The aim is to generate code that run well on the current most popular processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go.
-mtune permits the same extension options as -mcpu, but the extension options do not affect the tuning of the generated code.
-mtune=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-mcpu=name[+extension…]This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified by -march) and the ARM processor type for which to tune for performance (as if specified by -mtune). Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option.
Many of the supported CPUs implement optional architectural extensions. Where this is so the architectural extensions are normally enabled by default. If implementations that lack the extension exist, then the extension syntax can be used to disable those extensions that have been omitted. For floating-point and Advanced SIMD (Neon) instructions, the settings of the options -mfloat-abi and -mfpu must also be considered: floating-point and Advanced SIMD instructions will only be used if -mfloat-abi is not set to ‘soft’; and any setting of -mfpu other than ‘auto’ will override the available floating-point and SIMD extension instructions.
For example, ‘cortex-a9’ can be found in three major configurations: integer only, with just a floating-point unit or with floating-point and Advanced SIMD. The default is to enable all the instructions, but the extensions ‘+nosimd’ and ‘+nofp’ can be used to disable just the SIMD or both the SIMD and floating-point instructions respectively.
Permissible names for this option are the same as those for -mtune.
The following extension options are common to the listed CPUs:
Disable the DSP instructions on ‘cortex-m33’, ‘cortex-m35p’.
Disables the floating-point instructions on ‘arm9e’, ‘arm946e-s’, ‘arm966e-s’, ‘arm968e-s’, ‘arm10e’, ‘arm1020e’, ‘arm1022e’, ‘arm926ej-s’, ‘arm1026ej-s’, ‘cortex-r5’, ‘cortex-r7’, ‘cortex-r8’, ‘cortex-m4’, ‘cortex-m7’, ‘cortex-m33’ and ‘cortex-m35p’. Disables the floating-point and SIMD instructions on ‘generic-armv7-a’, ‘cortex-a5’, ‘cortex-a7’, ‘cortex-a8’, ‘cortex-a9’, ‘cortex-a12’, ‘cortex-a15’, ‘cortex-a17’, ‘cortex-a15.cortex-a7’, ‘cortex-a17.cortex-a7’, ‘cortex-a32’, ‘cortex-a35’, ‘cortex-a53’ and ‘cortex-a55’.
Disables the double-precision component of the floating-point instructions on ‘cortex-r5’, ‘cortex-r7’, ‘cortex-r8’, ‘cortex-r52’ and ‘cortex-m7’.
Disables the SIMD (but not floating-point) instructions on ‘generic-armv7-a’, ‘cortex-a5’, ‘cortex-a7’ and ‘cortex-a9’.
Enables the cryptographic instructions on ‘cortex-a32’, ‘cortex-a35’, ‘cortex-a53’, ‘cortex-a55’, ‘cortex-a57’, ‘cortex-a72’, ‘cortex-a73’, ‘cortex-a75’, ‘exynos-m1’, ‘xgene1’, ‘cortex-a57.cortex-a53’, ‘cortex-a72.cortex-a53’, ‘cortex-a73.cortex-a35’, ‘cortex-a73.cortex-a53’ and ‘cortex-a75.cortex-a55’.
Additionally the ‘generic-armv7-a’ pseudo target defaults to VFPv3 with 16 double-precision registers. It supports the following extension options: ‘mp’, ‘sec’, ‘vfpv3-d16’, ‘vfpv3’, ‘vfpv3-d16-fp16’, ‘vfpv3-fp16’, ‘vfpv4-d16’, ‘vfpv4’, ‘neon’, ‘neon-vfpv3’, ‘neon-fp16’, ‘neon-vfpv4’. The meanings are the same as for the extensions to -march=armv7-a.
-mcpu=generic-arch is also permissible, and is equivalent to -march=arch -mtune=generic-arch. See -mtune for more information.
-mcpu=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-mfpu=nameThis specifies what floating-point hardware (or hardware emulation) is available on the target. Permissible names are: ‘auto’, ‘vfpv2’, ‘vfpv3’, ‘vfpv3-fp16’, ‘vfpv3-d16’, ‘vfpv3-d16-fp16’, ‘vfpv3xd’, ‘vfpv3xd-fp16’, ‘neon-vfpv3’, ‘neon-fp16’, ‘vfpv4’, ‘vfpv4-d16’, ‘fpv4-sp-d16’, ‘neon-vfpv4’, ‘fpv5-d16’, ‘fpv5-sp-d16’, ‘fp-armv8’, ‘neon-fp-armv8’ and ‘crypto-neon-fp-armv8’. Note that ‘neon’ is an alias for ‘neon-vfpv3’ and ‘vfp’ is an alias for ‘vfpv2’.
The setting ‘auto’ is the default and is special. It causes the compiler to select the floating-point and Advanced SIMD instructions based on the settings of -mcpu and -march.
If the selected floating-point hardware includes the NEON extension (e.g. -mfpu=neon), note that floating-point operations are not generated by GCC’s auto-vectorization pass unless -funsafe-math-optimizations is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision.
You can also set the fpu name at function level by using the target("fpu=") function attributes (see ARM Function Attributes) or pragmas (see Function Specific Option Pragmas).
-mfp16-format=nameSpecify the format of the __fp16 half-precision floating-point type.
Permissible names are ‘none’, ‘ieee’, and ‘alternative’;
the default is ‘none’, in which case the __fp16 type is not
defined. See Half-Precision, for more information.
-mstructure-size-boundary=nThe sizes of all structures and unions are rounded up to a multiple of the number of bits set by this option. Permissible values are 8, 32 and 64. The default value varies for different toolchains. For the COFF targeted toolchain the default value is 8. A value of 64 is only allowed if the underlying ABI supports it.
Specifying a larger number can produce faster, more efficient code, but can also increase the size of the program. Different values are potentially incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions.
This option is deprecated.
-mabort-on-noreturnGenerate a call to the function abort at the end of a
noreturn function. It is executed if the function tries to
return.
-mlong-calls-mno-long-callsTells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 64-megabyte addressing range of the offset-based version of subroutine call instruction.
Even if this switch is enabled, not all function calls are turned
into long calls. The heuristic is that static functions, functions
that have the short_call attribute, functions that are inside
the scope of a #pragma no_long_calls directive, and functions whose
definitions have already been compiled within the current compilation
unit are not turned into long calls. The exceptions to this rule are
that weak function definitions, functions with the long_call
attribute or the section attribute, and functions that are within
the scope of a #pragma long_calls directive are always
turned into long calls.
This feature is not enabled by default. Specifying
-mno-long-calls restores the default behavior, as does
placing the function calls within the scope of a #pragma
long_calls_off directive. Note these switches have no effect on how
the compiler generates code to handle function calls via function
pointers.
-msingle-pic-baseTreat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins.
-mpic-register=regSpecify the register to be used for PIC addressing. For standard PIC base case, the default is any suitable register determined by compiler. For single PIC base case, the default is ‘R9’ if target is EABI based or stack-checking is enabled, otherwise the default is ‘R10’.
-mpic-data-is-text-relativeAssume that the displacement between the text and data segments is fixed at static link time. This permits using PC-relative addressing operations to access data known to be in the data segment. For non-VxWorks RTP targets, this option is enabled by default. When disabled on such targets, it will enable -msingle-pic-base by default.
-mpoke-function-nameWrite the name of each function into the text section, directly preceding the function prologue. The generated code is similar to this:
t0
.ascii "arm_poke_function_name", 0
.align
t1
.word 0xff000000 + (t1 - t0)
arm_poke_function_name
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
When performing a stack backtrace, code can inspect the value of
pc stored at fp + 0. If the trace function then looks at
location pc - 12 and the top 8 bits are set, then we know that
there is a function name embedded immediately preceding this location
and has length ((pc[-3]) & 0xff000000).
-mthumb-marmSelect between generating code that executes in ARM and Thumb states. The default for most configurations is to generate code that executes in ARM state, but the default can be changed by configuring GCC with the --with-mode=state configure option.
You can also override the ARM and Thumb mode for each function
by using the target("thumb") and target("arm") function attributes
(see ARM Function Attributes) or pragmas (see Function Specific Option Pragmas).
-mflip-thumbSwitch ARM/Thumb modes on alternating functions. This option is provided for regression testing of mixed Thumb/ARM code generation, and is not intended for ordinary use in compiling code.
-mtpcs-frameGenerate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions. (A leaf function is one that does not call any other functions.) The default is -mno-tpcs-frame.
-mtpcs-leaf-frameGenerate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions. (A leaf function is one that does not call any other functions.) The default is -mno-apcs-leaf-frame.
-mcallee-super-interworkingGives all externally visible functions in the file being compiled an ARM instruction set header which switches to Thumb mode before executing the rest of the function. This allows these functions to be called from non-interworking code. This option is not valid in AAPCS configurations because interworking is enabled by default.
-mcaller-super-interworkingAllows calls via function pointers (including virtual functions) to execute correctly regardless of whether the target code has been compiled for interworking or not. There is a small overhead in the cost of executing a function pointer if this option is enabled. This option is not valid in AAPCS configurations because interworking is enabled by default.
-mtp=nameSpecify the access model for the thread local storage pointer. The valid
models are ‘soft’, which generates calls to __aeabi_read_tp,
‘cp15’, which fetches the thread pointer from cp15 directly
(supported in the arm6k architecture), and ‘auto’, which uses the
best available method for the selected processor. The default setting is
‘auto’.
-mtls-dialect=dialectSpecify the dialect to use for accessing thread local storage. Two dialects are supported—‘gnu’ and ‘gnu2’. The ‘gnu’ dialect selects the original GNU scheme for supporting local and global dynamic TLS models. The ‘gnu2’ dialect selects the GNU descriptor scheme, which provides better performance for shared libraries. The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker and library support. Initial and local exec TLS models are unaffected by this option and always use the original scheme.
-mword-relocationsOnly generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). This is enabled by default on targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when -fpic or -fPIC is specified. This option conflicts with -mslow-flash-data.
-mfix-cortex-m3-ldrdSome Cortex-M3 cores can cause data corruption when ldrd instructions
with overlapping destination and base registers are used. This option avoids
generating these instructions. This option is enabled by default when
-mcpu=cortex-m3 is specified.
-munaligned-access-mno-unaligned-accessEnables (or disables) reading and writing of 16- and 32- bit values from addresses that are not 16- or 32- bit aligned. By default unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for ARMv8-M Baseline architectures, and enabled for all other architectures. If unaligned access is not enabled then words in packed data structures are accessed a byte at a time.
The ARM attribute Tag_CPU_unaligned_access is set in the
generated object file to either true or false, depending upon the
setting of this option. If unaligned access is enabled then the
preprocessor symbol __ARM_FEATURE_UNALIGNED is also
defined.
-mneon-for-64bitsThis option is deprecated and has no effect.
-mslow-flash-dataAssume loading data from flash is slower than fetching instruction. Therefore literal load is minimized for better performance. This option is only supported when compiling for ARMv7 M-profile and off by default. It conflicts with -mword-relocations.
-masm-syntax-unifiedAssume inline assembler is using unified asm syntax. The default is currently off which implies divided syntax. This option has no impact on Thumb2. However, this may change in future releases of GCC. Divided syntax should be considered deprecated.
-mrestrict-itRestricts generation of IT blocks to conform to the rules of ARMv8-A. IT blocks can only contain a single 16-bit instruction from a select set of instructions. This option is on by default for ARMv8-A Thumb mode.
-mprint-tune-infoPrint CPU tuning information as comment in assembler file. This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code. This option is disabled by default.
-mverbose-cost-dumpEnable verbose cost model dumping in the debug dump files. This option is provided for use in debugging the compiler.
-mpure-codeDo not allow constant data to be placed in code sections.
Additionally, when compiling for ELF object format give all text sections the
ELF processor-specific section attribute SHF_ARM_PURECODE. This option
is only available when generating non-pic code for M-profile targets.
-mcmseGenerate secure code as per the "ARMv8-M Security Extensions: Requirements on Development Tools Engineering Specification", which can be found on https://developer.arm.com/documentation/ecm0359818/latest/.
-mfdpic-mno-fdpicSelect the FDPIC ABI, which uses 64-bit function descriptors to
represent pointers to functions. When the compiler is configured for
arm-*-uclinuxfdpiceabi targets, this option is on by default
and implies -fPIE if none of the PIC/PIE-related options is
provided. On other targets, it only enables the FDPIC-specific code
generation features, and the user should explicitly provide the
PIC/PIE-related options as needed.
Note that static linking is not supported because it would still involve the dynamic linker when the program self-relocates. If such behavior is acceptable, use -static and -Wl,-dynamic-linker options.
The opposite -mno-fdpic option is useful (and required) to
build the Linux kernel using the same (arm-*-uclinuxfdpiceabi)
toolchain as the one used to build the userland programs.
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