9.16.4 i386-Mnemonics

9.16.4.1 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters ‘b’, ‘w’, ‘l’ and ‘q’ specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, ‘mov %ax, %bx’ is equivalent to ‘movw %ax, %bx’; also, ‘mov $1, %bx’ is equivalent to ‘movw $1, bx’. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

When there is no sizing suffix and no (suitable) register operands to deduce the size of memory operands, with a few exceptions and where long operand size is possible in the first place, operand size will default to long in 32- and 64-bit modes. Similarly it will default to short in 16-bit mode. Noteworthy exceptions are

• Instructions with an implicit on-stack operand as well as branches, which default to quad in 64-bit mode.
• Sign- and zero-extending moves, which default to byte size source operands.
• Floating point insns with integer operands, which default to short (for perhaps historical reasons).
• CRC32 with a 64-bit destination, which defaults to a quad source operand.

Different encoding options can be specified via pseudo prefixes:

• ‘{disp8}’ – prefer 8-bit displacement.
• ‘{disp32}’ – prefer 32-bit displacement.
• ‘{disp16}’ – prefer 16-bit displacement.
• ‘{load}’ – prefer load-form instruction.
• ‘{store}’ – prefer store-form instruction.
• ‘{vex}’ – encode with VEX prefix.
• ‘{vex3}’ – encode with 3-byte VEX prefix.
• ‘{evex}’ – encode with EVEX prefix.
• ‘{rex}’ – prefer REX prefix for integer and legacy vector instructions (x86-64 only). Note that this differs from the ‘rex’ prefix which generates REX prefix unconditionally.
• ‘{nooptimize}’ – disable instruction size optimization.

The Intel-syntax conversion instructions

• ‘cbw’ — sign-extend byte in ‘%al’ to word in ‘%ax’,
• ‘cwde’ — sign-extend word in ‘%ax’ to long in ‘%eax’,
• ‘cwd’ — sign-extend word in ‘%ax’ to long in ‘%dx:%ax’,
• ‘cdq’ — sign-extend dword in ‘%eax’ to quad in ‘%edx:%eax’,
• ‘cdqe’ — sign-extend dword in ‘%eax’ to quad in ‘%rax’ (x86-64 only),
• ‘cqo’ — sign-extend quad in ‘%rax’ to octuple in ‘%rdx:%rax’ (x86-64 only),

are called ‘cbtw’, ‘cwtl’, ‘cwtd’, ‘cltd’, ‘cltq’, and ‘cqto’ in AT&T naming. as accepts either naming for these instructions.

The Intel-syntax extension instructions

• ‘movsx’ — sign-extend ‘reg8/mem8’ to ‘reg16’.
• ‘movsx’ — sign-extend ‘reg8/mem8’ to ‘reg32’.
• ‘movsx’ — sign-extend ‘reg8/mem8’ to ‘reg64’ (x86-64 only).
• ‘movsx’ — sign-extend ‘reg16/mem16’ to ‘reg32’
• ‘movsx’ — sign-extend ‘reg16/mem16’ to ‘reg64’ (x86-64 only).
• ‘movsxd’ — sign-extend ‘reg32/mem32’ to ‘reg64’ (x86-64 only).
• ‘movzx’ — zero-extend ‘reg8/mem8’ to ‘reg16’.
• ‘movzx’ — zero-extend ‘reg8/mem8’ to ‘reg32’.
• ‘movzx’ — zero-extend ‘reg8/mem8’ to ‘reg64’ (x86-64 only).
• ‘movzx’ — zero-extend ‘reg16/mem16’ to ‘reg32’
• ‘movzx’ — zero-extend ‘reg16/mem16’ to ‘reg64’ (x86-64 only).

are called ‘movsbw/movsxb/movsx’, ‘movsbl/movsxb/movsx’, ‘movsbq/movsb/movsx’, ‘movswl/movsxw’, ‘movswq/movsxw’, ‘movslq/movsxl’, ‘movzbw/movzxb/movzx’, ‘movzbl/movzxb/movzx’, ‘movzbq/movzxb/movzx’, ‘movzwl/movzxw’ and ‘movzwq/movzxw’ in AT&T syntax.

Far call/jump instructions are ‘lcall’ and ‘ljmp’ in AT&T syntax, but are ‘call far’ and ‘jump far’ in Intel convention.

9.16.4.2 AT&T Mnemonic versus Intel Mnemonic

as supports assembly using Intel mnemonic. .intel_mnemonic selects Intel mnemonic with Intel syntax, and .att_mnemonic switches back to the usual AT&T mnemonic with AT&T syntax for compatibility with the output of gcc. Several x87 instructions, ‘fadd’, ‘fdiv’, ‘fdivp’, ‘fdivr’, ‘fdivrp’, ‘fmul’, ‘fsub’, ‘fsubp’, ‘fsubr’ and ‘fsubrp’, are implemented in AT&T System V/386 assembler with different mnemonics from those in Intel IA32 specification. gcc generates those instructions with AT&T mnemonic.

• ‘movslq’ with AT&T mnemonic only accepts 64-bit destination register. ‘movsxd’ should be used to encode 16-bit or 32-bit destination register with both AT&T and Intel mnemonics.