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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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  3. <!-- This file documents the GNU Assembler "as".
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  15. <title>SH Floating Point (Using as)</title>
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  23. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
  24. <link href="SH_002dDependent.html#SH_002dDependent" rel="up" title="SH-Dependent">
  25. <link href="SH-Directives.html#SH-Directives" rel="next" title="SH Directives">
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  56. <a name="SH-Floating-Point"></a>
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  58. <p>
  59. Next: <a href="SH-Directives.html#SH-Directives" accesskey="n" rel="next">SH Directives</a>, Previous: <a href="SH-Syntax.html#SH-Syntax" accesskey="p" rel="prev">SH Syntax</a>, Up: <a href="SH_002dDependent.html#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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  61. <hr>
  62. <a name="Floating-Point-14"></a>
  63. <h4 class="subsection">9.43.3 Floating Point</h4>
  64. <a name="index-floating-point_002c-SH-_0028IEEE_0029"></a>
  65. <a name="index-SH-floating-point-_0028IEEE_0029"></a>
  66. <p>SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
  67. SH groups can use <code>.float</code> directive to generate <small>IEEE</small>
  68. floating-point numbers.
  69. </p>
  70. <p>SH2E and SH3E support single-precision floating point calculations as
  71. well as entirely PCAPI compatible emulation of double-precision
  72. floating point calculations. SH2E and SH3E instructions are a subset of
  73. the floating point calculations conforming to the IEEE754 standard.
  74. </p>
  75. <p>In addition to single-precision and double-precision floating-point
  76. operation capability, the on-chip FPU of SH4 has a 128-bit graphic
  77. engine that enables 32-bit floating-point data to be processed 128
  78. bits at a time. It also supports 4 * 4 array operations and inner
  79. product operations. Also, a superscalar architecture is employed that
  80. enables simultaneous execution of two instructions (including FPU
  81. instructions), providing performance of up to twice that of
  82. conventional architectures at the same frequency.
  83. </p>
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