visus
/
toolchain-gcc-arm-embedded
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
2 Commits
1 Branch
Branch: main
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'main'
${ noResults }
toolchain-gcc-arm-embedded/share/doc/gcc-arm-none-eabi/html/gcc/AArch64-Options.html

625 lines
32KB
Raw Permalink Blame History 

  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

  2. <html>

  3. <!-- Copyright (C) 1988-2020 Free Software Foundation, Inc.

  4. 

  5. Permission is granted to copy, distribute and/or modify this document

  6. under the terms of the GNU Free Documentation License, Version 1.3 or

  7. any later version published by the Free Software Foundation; with the

  8. Invariant Sections being "Funding Free Software", the Front-Cover

  9. Texts being (a) (see below), and with the Back-Cover Texts being (b)

  10. (see below).  A copy of the license is included in the section entitled

  11. "GNU Free Documentation License".

  12. 

  13. (a) The FSF's Front-Cover Text is:

  14. 

  15. A GNU Manual

  16. 

  17. (b) The FSF's Back-Cover Text is:

  18. 

  19. You have freedom to copy and modify this GNU Manual, like GNU

  20.      software.  Copies published by the Free Software Foundation raise

  21.      funds for GNU development. -->

  22. <!-- Created by GNU Texinfo 6.5, http://www.gnu.org/software/texinfo/ -->

  23. <head>

  24. <meta http-equiv="Content-Type" content="text/html; charset=utf-8">

  25. <title>AArch64 Options (Using the GNU Compiler Collection (GCC))</title>

  26. 

  27. <meta name="description" content="AArch64 Options (Using the GNU Compiler Collection (GCC))">

  28. <meta name="keywords" content="AArch64 Options (Using the GNU Compiler Collection (GCC))">

  29. <meta name="resource-type" content="document">

  30. <meta name="distribution" content="global">

  31. <meta name="Generator" content="makeinfo">

  32. <link href="index.html#Top" rel="start" title="Top">

  33. <link href="Option-Index.html#Option-Index" rel="index" title="Option Index">

  34. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  35. <link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">

  36. <link href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" rel="next" title="Adapteva Epiphany Options">

  37. <link href="Submodel-Options.html#Submodel-Options" rel="prev" title="Submodel Options">

  38. <style type="text/css">

  39. <!--

  40. a.summary-letter {text-decoration: none}

  41. blockquote.indentedblock {margin-right: 0em}

  42. blockquote.smallindentedblock {margin-right: 0em; font-size: smaller}

  43. blockquote.smallquotation {font-size: smaller}

  44. div.display {margin-left: 3.2em}

  45. div.example {margin-left: 3.2em}

  46. div.lisp {margin-left: 3.2em}

  47. div.smalldisplay {margin-left: 3.2em}

  48. div.smallexample {margin-left: 3.2em}

  49. div.smalllisp {margin-left: 3.2em}

  50. kbd {font-style: oblique}

  51. pre.display {font-family: inherit}

  52. pre.format {font-family: inherit}

  53. pre.menu-comment {font-family: serif}

  54. pre.menu-preformatted {font-family: serif}

  55. pre.smalldisplay {font-family: inherit; font-size: smaller}

  56. pre.smallexample {font-size: smaller}

  57. pre.smallformat {font-family: inherit; font-size: smaller}

  58. pre.smalllisp {font-size: smaller}

  59. span.nolinebreak {white-space: nowrap}

  60. span.roman {font-family: initial; font-weight: normal}

  61. span.sansserif {font-family: sans-serif; font-weight: normal}

  62. ul.no-bullet {list-style: none}

  63. -->

  64. </style>

  65. 

  66. 

  67. </head>

  68. 

  69. <body lang="en">

  70. <a name="AArch64-Options"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" accesskey="n" rel="next">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="AArch64-Options-1"></a>

  77. <h4 class="subsection">3.19.1 AArch64 Options</h4>

  78. <a name="index-AArch64-Options"></a>

  79. 

  80. <p>These options are defined for AArch64 implementations:

  81. </p>

  82. <dl compact="compact">

  83. <dt><code>-mabi=<var>name</var></code></dt>

  84. <dd><a name="index-mabi"></a>

  85. <p>Generate code for the specified data model.  Permissible values

  86. are &lsquo;<samp>ilp32</samp>&rsquo; for SysV-like data model where int, long int and pointers

  87. are 32 bits, and &lsquo;<samp>lp64</samp>&rsquo; for SysV-like data model where int is 32 bits,

  88. but long int and pointers are 64 bits.

  89. </p>

  90. <p>The default depends on the specific target configuration.  Note that

  91. the LP64 and ILP32 ABIs are not link-compatible; you must compile your

  92. entire program with the same ABI, and link with a compatible set of libraries.

  93. </p>

  94. </dd>

  95. <dt><code>-mbig-endian</code></dt>

  96. <dd><a name="index-mbig_002dendian"></a>

  97. <p>Generate big-endian code.  This is the default when GCC is configured for an

  98. &lsquo;<samp>aarch64_be-*-*</samp>&rsquo; target.

  99. </p>

  100. </dd>

  101. <dt><code>-mgeneral-regs-only</code></dt>

  102. <dd><a name="index-mgeneral_002dregs_002donly"></a>

  103. <p>Generate code which uses only the general-purpose registers.  This will prevent

  104. the compiler from using floating-point and Advanced SIMD registers but will not

  105. impose any restrictions on the assembler.

  106. </p>

  107. </dd>

  108. <dt><code>-mlittle-endian</code></dt>

  109. <dd><a name="index-mlittle_002dendian"></a>

  110. <p>Generate little-endian code.  This is the default when GCC is configured for an

  111. &lsquo;<samp>aarch64-*-*</samp>&rsquo; but not an &lsquo;<samp>aarch64_be-*-*</samp>&rsquo; target.

  112. </p>

  113. </dd>

  114. <dt><code>-mcmodel=tiny</code></dt>

  115. <dd><a name="index-mcmodel_003dtiny"></a>

  116. <p>Generate code for the tiny code model.  The program and its statically defined

  117. symbols must be within 1MB of each other.  Programs can be statically or

  118. dynamically linked.

  119. </p>

  120. </dd>

  121. <dt><code>-mcmodel=small</code></dt>

  122. <dd><a name="index-mcmodel_003dsmall"></a>

  123. <p>Generate code for the small code model.  The program and its statically defined

  124. symbols must be within 4GB of each other.  Programs can be statically or

  125. dynamically linked.  This is the default code model.

  126. </p>

  127. </dd>

  128. <dt><code>-mcmodel=large</code></dt>

  129. <dd><a name="index-mcmodel_003dlarge"></a>

  130. <p>Generate code for the large code model.  This makes no assumptions about

  131. addresses and sizes of sections.  Programs can be statically linked only.  The

  132. <samp>-mcmodel=large</samp> option is incompatible with <samp>-mabi=ilp32</samp>,

  133. <samp>-fpic</samp> and <samp>-fPIC</samp>.

  134. </p>

  135. </dd>

  136. <dt><code>-mstrict-align</code></dt>

  137. <dt><code>-mno-strict-align</code></dt>

  138. <dd><a name="index-mstrict_002dalign"></a>

  139. <a name="index-mno_002dstrict_002dalign"></a>

  140. <p>Avoid or allow generating memory accesses that may not be aligned on a natural

  141. object boundary as described in the architecture specification.

  142. </p>

  143. </dd>

  144. <dt><code>-momit-leaf-frame-pointer</code></dt>

  145. <dt><code>-mno-omit-leaf-frame-pointer</code></dt>

  146. <dd><a name="index-momit_002dleaf_002dframe_002dpointer"></a>

  147. <a name="index-mno_002domit_002dleaf_002dframe_002dpointer"></a>

  148. <p>Omit or keep the frame pointer in leaf functions.  The former behavior is the

  149. default.

  150. </p>

  151. </dd>

  152. <dt><code>-mstack-protector-guard=<var>guard</var></code></dt>

  153. <dt><code>-mstack-protector-guard-reg=<var>reg</var></code></dt>

  154. <dt><code>-mstack-protector-guard-offset=<var>offset</var></code></dt>

  155. <dd><a name="index-mstack_002dprotector_002dguard"></a>

  156. <a name="index-mstack_002dprotector_002dguard_002dreg"></a>

  157. <a name="index-mstack_002dprotector_002dguard_002doffset"></a>

  158. <p>Generate stack protection code using canary at <var>guard</var>.  Supported

  159. locations are &lsquo;<samp>global</samp>&rsquo; for a global canary or &lsquo;<samp>sysreg</samp>&rsquo; for a

  160. canary in an appropriate system register.

  161. </p>

  162. <p>With the latter choice the options

  163. <samp>-mstack-protector-guard-reg=<var>reg</var></samp> and

  164. <samp>-mstack-protector-guard-offset=<var>offset</var></samp> furthermore specify

  165. which system register to use as base register for reading the canary,

  166. and from what offset from that base register. There is no default

  167. register or offset as this is entirely for use within the Linux

  168. kernel.

  169. </p>

  170. </dd>

  171. <dt><code>-mstack-protector-guard=<var>guard</var></code></dt>

  172. <dt><code>-mstack-protector-guard-reg=<var>reg</var></code></dt>

  173. <dt><code>-mstack-protector-guard-offset=<var>offset</var></code></dt>

  174. <dd><a name="index-mstack_002dprotector_002dguard-1"></a>

  175. <a name="index-mstack_002dprotector_002dguard_002dreg-1"></a>

  176. <a name="index-mstack_002dprotector_002dguard_002doffset-1"></a>

  177. <p>Generate stack protection code using canary at <var>guard</var>.  Supported

  178. locations are &lsquo;<samp>global</samp>&rsquo; for a global canary or &lsquo;<samp>sysreg</samp>&rsquo; for a

  179. canary in an appropriate system register.

  180. </p>

  181. <p>With the latter choice the options

  182. <samp>-mstack-protector-guard-reg=<var>reg</var></samp> and

  183. <samp>-mstack-protector-guard-offset=<var>offset</var></samp> furthermore specify

  184. which system register to use as base register for reading the canary,

  185. and from what offset from that base register. There is no default

  186. register or offset as this is entirely for use within the Linux

  187. kernel.

  188. </p>

  189. </dd>

  190. <dt><code>-mtls-dialect=desc</code></dt>

  191. <dd><a name="index-mtls_002ddialect_003ddesc"></a>

  192. <p>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses

  193. of TLS variables.  This is the default.

  194. </p>

  195. </dd>

  196. <dt><code>-mtls-dialect=traditional</code></dt>

  197. <dd><a name="index-mtls_002ddialect_003dtraditional"></a>

  198. <p>Use traditional TLS as the thread-local storage mechanism for dynamic accesses

  199. of TLS variables.

  200. </p>

  201. </dd>

  202. <dt><code>-mtls-size=<var>size</var></code></dt>

  203. <dd><a name="index-mtls_002dsize"></a>

  204. <p>Specify bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.

  205. This option requires binutils 2.26 or newer.

  206. </p>

  207. </dd>

  208. <dt><code>-mfix-cortex-a53-835769</code></dt>

  209. <dt><code>-mno-fix-cortex-a53-835769</code></dt>

  210. <dd><a name="index-mfix_002dcortex_002da53_002d835769"></a>

  211. <a name="index-mno_002dfix_002dcortex_002da53_002d835769"></a>

  212. <p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.

  213. This involves inserting a NOP instruction between memory instructions and

  214. 64-bit integer multiply-accumulate instructions.

  215. </p>

  216. </dd>

  217. <dt><code>-mfix-cortex-a53-843419</code></dt>

  218. <dt><code>-mno-fix-cortex-a53-843419</code></dt>

  219. <dd><a name="index-mfix_002dcortex_002da53_002d843419"></a>

  220. <a name="index-mno_002dfix_002dcortex_002da53_002d843419"></a>

  221. <p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.

  222. This erratum workaround is made at link time and this will only pass the

  223. corresponding flag to the linker.

  224. </p>

  225. </dd>

  226. <dt><code>-mlow-precision-recip-sqrt</code></dt>

  227. <dt><code>-mno-low-precision-recip-sqrt</code></dt>

  228. <dd><a name="index-mlow_002dprecision_002drecip_002dsqrt"></a>

  229. <a name="index-mno_002dlow_002dprecision_002drecip_002dsqrt"></a>

  230. <p>Enable or disable the reciprocal square root approximation.

  231. This option only has an effect if <samp>-ffast-math</samp> or

  232. <samp>-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces

  233. precision of reciprocal square root results to about 16 bits for

  234. single precision and to 32 bits for double precision.

  235. </p>

  236. </dd>

  237. <dt><code>-mlow-precision-sqrt</code></dt>

  238. <dt><code>-mno-low-precision-sqrt</code></dt>

  239. <dd><a name="index-mlow_002dprecision_002dsqrt"></a>

  240. <a name="index-mno_002dlow_002dprecision_002dsqrt"></a>

  241. <p>Enable or disable the square root approximation.

  242. This option only has an effect if <samp>-ffast-math</samp> or

  243. <samp>-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces

  244. precision of square root results to about 16 bits for

  245. single precision and to 32 bits for double precision.

  246. If enabled, it implies <samp>-mlow-precision-recip-sqrt</samp>.

  247. </p>

  248. </dd>

  249. <dt><code>-mlow-precision-div</code></dt>

  250. <dt><code>-mno-low-precision-div</code></dt>

  251. <dd><a name="index-mlow_002dprecision_002ddiv"></a>

  252. <a name="index-mno_002dlow_002dprecision_002ddiv"></a>

  253. <p>Enable or disable the division approximation.

  254. This option only has an effect if <samp>-ffast-math</samp> or

  255. <samp>-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces

  256. precision of division results to about 16 bits for

  257. single precision and to 32 bits for double precision.

  258. </p>

  259. </dd>

  260. <dt><code>-mtrack-speculation</code></dt>

  261. <dt><code>-mno-track-speculation</code></dt>

  262. <dd><p>Enable or disable generation of additional code to track speculative

  263. execution through conditional branches.  The tracking state can then

  264. be used by the compiler when expanding calls to

  265. <code>__builtin_speculation_safe_copy</code> to permit a more efficient code

  266. sequence to be generated.

  267. </p>

  268. </dd>

  269. <dt><code>-moutline-atomics</code></dt>

  270. <dt><code>-mno-outline-atomics</code></dt>

  271. <dd><p>Enable or disable calls to out-of-line helpers to implement atomic operations.

  272. These helpers will, at runtime, determine if the LSE instructions from

  273. ARMv8.1-A can be used; if not, they will use the load/store-exclusive

  274. instructions that are present in the base ARMv8.0 ISA.

  275. </p>

  276. <p>This option is only applicable when compiling for the base ARMv8.0

  277. instruction set.  If using a later revision, e.g. <samp>-march=armv8.1-a</samp>

  278. or <samp>-march=armv8-a+lse</samp>, the ARMv8.1-Atomics instructions will be

  279. used directly.  The same applies when using <samp>-mcpu=</samp> when the

  280. selected cpu supports the &lsquo;<samp>lse</samp>&rsquo; feature.

  281. This option is on by default.

  282. </p>

  283. </dd>

  284. <dt><code>-march=<var>name</var></code></dt>

  285. <dd><a name="index-march"></a>

  286. <p>Specify the name of the target architecture and, optionally, one or

  287. more feature modifiers.  This option has the form

  288. <samp>-march=<var>arch</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>.

  289. </p>

  290. <p>The table below summarizes the permissible values for <var>arch</var>

  291. and the features that they enable by default:

  292. </p>

  293. <table>

  294. <thead><tr><th width="20%"><var>arch</var> value</th><th width="20%">Architecture</th><th width="60%">Includes by default</th></tr></thead>

  295. <tr><td width="20%">&lsquo;<samp>armv8-a</samp>&rsquo;</td><td width="20%">Armv8-A</td><td width="60%">&lsquo;<samp>+fp</samp>&rsquo;, &lsquo;<samp>+simd</samp>&rsquo;</td></tr>

  296. <tr><td width="20%">&lsquo;<samp>armv8.1-a</samp>&rsquo;</td><td width="20%">Armv8.1-A</td><td width="60%">&lsquo;<samp>armv8-a</samp>&rsquo;, &lsquo;<samp>+crc</samp>&rsquo;, &lsquo;<samp>+lse</samp>&rsquo;, &lsquo;<samp>+rdma</samp>&rsquo;</td></tr>

  297. <tr><td width="20%">&lsquo;<samp>armv8.2-a</samp>&rsquo;</td><td width="20%">Armv8.2-A</td><td width="60%">&lsquo;<samp>armv8.1-a</samp>&rsquo;</td></tr>

  298. <tr><td width="20%">&lsquo;<samp>armv8.3-a</samp>&rsquo;</td><td width="20%">Armv8.3-A</td><td width="60%">&lsquo;<samp>armv8.2-a</samp>&rsquo;</td></tr>

  299. <tr><td width="20%">&lsquo;<samp>armv8.4-a</samp>&rsquo;</td><td width="20%">Armv8.4-A</td><td width="60%">&lsquo;<samp>armv8.3-a</samp>&rsquo;, &lsquo;<samp>+fp16fml</samp>&rsquo;, &lsquo;<samp>+dotprod</samp>&rsquo;</td></tr>

  300. <tr><td width="20%">&lsquo;<samp>armv8.5-a</samp>&rsquo;</td><td width="20%">Armv8.5-A</td><td width="60%">&lsquo;<samp>armv8.4-a</samp>&rsquo;, &lsquo;<samp>+sb</samp>&rsquo;, &lsquo;<samp>+ssbs</samp>&rsquo;, &lsquo;<samp>+predres</samp>&rsquo;</td></tr>

  301. <tr><td width="20%">&lsquo;<samp>armv8.6-a</samp>&rsquo;</td><td width="20%">Armv8.6-A</td><td width="60%">&lsquo;<samp>armv8.5-a</samp>&rsquo;, &lsquo;<samp>+bf16</samp>&rsquo;, &lsquo;<samp>+i8mm</samp>&rsquo;</td></tr>

  302. </table>

  303. 

  304. <p>The value &lsquo;<samp>native</samp>&rsquo; is available on native AArch64 GNU/Linux and

  305. causes the compiler to pick the architecture of the host system.  This

  306. option has no effect if the compiler is unable to recognize the

  307. architecture of the host system,

  308. </p>

  309. <p>The permissible values for <var>feature</var> are listed in the sub-section

  310. on <a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp>

  311. Feature Modifiers</a>.  Where conflicting feature modifiers are

  312. specified, the right-most feature is used.

  313. </p>

  314. <p>GCC uses <var>name</var> to determine what kind of instructions it can emit

  315. when generating assembly code.  If <samp>-march</samp> is specified

  316. without either of <samp>-mtune</samp> or <samp>-mcpu</samp> also being

  317. specified, the code is tuned to perform well across a range of target

  318. processors implementing the target architecture.

  319. </p>

  320. </dd>

  321. <dt><code>-mtune=<var>name</var></code></dt>

  322. <dd><a name="index-mtune"></a>

  323. <p>Specify the name of the target processor for which GCC should tune the

  324. performance of the code.  Permissible values for this option are:

  325. &lsquo;<samp>generic</samp>&rsquo;, &lsquo;<samp>cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a55</samp>&rsquo;,

  326. &lsquo;<samp>cortex-a57</samp>&rsquo;, &lsquo;<samp>cortex-a72</samp>&rsquo;, &lsquo;<samp>cortex-a73</samp>&rsquo;, &lsquo;<samp>cortex-a75</samp>&rsquo;,

  327. &lsquo;<samp>cortex-a76</samp>&rsquo;, &lsquo;<samp>cortex-a76ae</samp>&rsquo;, &lsquo;<samp>cortex-a77</samp>&rsquo;,

  328. &lsquo;<samp>cortex-a65</samp>&rsquo;, &lsquo;<samp>cortex-a65ae</samp>&rsquo;, &lsquo;<samp>cortex-a34</samp>&rsquo;,

  329. &lsquo;<samp>ares</samp>&rsquo;, &lsquo;<samp>exynos-m1</samp>&rsquo;, &lsquo;<samp>emag</samp>&rsquo;, &lsquo;<samp>falkor</samp>&rsquo;, &lsquo;<samp>neoverse-e1</samp>&rsquo;,

  330. &lsquo;<samp>neoverse-n1</samp>&rsquo;, &lsquo;<samp>neoverse-n2</samp>&rsquo;, &lsquo;<samp>neoverse-v1</samp>&rsquo;, &lsquo;<samp>qdf24xx</samp>&rsquo;,

  331. &lsquo;<samp>saphira</samp>&rsquo;, &lsquo;<samp>phecda</samp>&rsquo;, &lsquo;<samp>xgene1</samp>&rsquo;, &lsquo;<samp>vulcan</samp>&rsquo;, &lsquo;<samp>octeontx</samp>&rsquo;,

  332. &lsquo;<samp>octeontx81</samp>&rsquo;,  &lsquo;<samp>octeontx83</samp>&rsquo;,

  333. &lsquo;<samp>octeontx2</samp>&rsquo;, &lsquo;<samp>octeontx2t98</samp>&rsquo;, &lsquo;<samp>octeontx2t96</samp>&rsquo;

  334. &lsquo;<samp>octeontx2t93</samp>&rsquo;, &lsquo;<samp>octeontx2f95</samp>&rsquo;, &lsquo;<samp>octeontx2f95n</samp>&rsquo;,

  335. &lsquo;<samp>octeontx2f95mm</samp>&rsquo;,

  336. &lsquo;<samp>a64fx</samp>&rsquo;,

  337. &lsquo;<samp>thunderx</samp>&rsquo;, &lsquo;<samp>thunderxt88</samp>&rsquo;,

  338. &lsquo;<samp>thunderxt88p1</samp>&rsquo;, &lsquo;<samp>thunderxt81</samp>&rsquo;, &lsquo;<samp>tsv110</samp>&rsquo;,

  339. &lsquo;<samp>thunderxt83</samp>&rsquo;, &lsquo;<samp>thunderx2t99</samp>&rsquo;, &lsquo;<samp>thunderx3t110</samp>&rsquo;, &lsquo;<samp>zeus</samp>&rsquo;,

  340. &lsquo;<samp>cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a72.cortex-a53</samp>&rsquo;,

  341. &lsquo;<samp>cortex-a73.cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a73.cortex-a53</samp>&rsquo;,

  342. &lsquo;<samp>cortex-a75.cortex-a55</samp>&rsquo;, &lsquo;<samp>cortex-a76.cortex-a55</samp>&rsquo;

  343. &lsquo;<samp>native</samp>&rsquo;.

  344. </p>

  345. <p>The values &lsquo;<samp>cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a72.cortex-a53</samp>&rsquo;,

  346. &lsquo;<samp>cortex-a73.cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a73.cortex-a53</samp>&rsquo;,

  347. &lsquo;<samp>cortex-a75.cortex-a55</samp>&rsquo;, &lsquo;<samp>cortex-a76.cortex-a55</samp>&rsquo; specify that GCC

  348. should tune for a big.LITTLE system.

  349. </p>

  350. <p>Additionally on native AArch64 GNU/Linux systems the value

  351. &lsquo;<samp>native</samp>&rsquo; tunes performance to the host system.  This option has no effect

  352. if the compiler is unable to recognize the processor of the host system.

  353. </p>

  354. <p>Where none of <samp>-mtune=</samp>, <samp>-mcpu=</samp> or <samp>-march=</samp>

  355. are specified, the code is tuned to perform well across a range

  356. of target processors.

  357. </p>

  358. <p>This option cannot be suffixed by feature modifiers.

  359. </p>

  360. </dd>

  361. <dt><code>-mcpu=<var>name</var></code></dt>

  362. <dd><a name="index-mcpu"></a>

  363. <p>Specify the name of the target processor, optionally suffixed by one

  364. or more feature modifiers.  This option has the form

  365. <samp>-mcpu=<var>cpu</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>, where

  366. the permissible values for <var>cpu</var> are the same as those available

  367. for <samp>-mtune</samp>.  The permissible values for <var>feature</var> are

  368. documented in the sub-section on

  369. <a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp>

  370. Feature Modifiers</a>.  Where conflicting feature modifiers are

  371. specified, the right-most feature is used.

  372. </p>

  373. <p>GCC uses <var>name</var> to determine what kind of instructions it can emit when

  374. generating assembly code (as if by <samp>-march</samp>) and to determine

  375. the target processor for which to tune for performance (as if

  376. by <samp>-mtune</samp>).  Where this option is used in conjunction

  377. with <samp>-march</samp> or <samp>-mtune</samp>, those options take precedence

  378. over the appropriate part of this option.

  379. </p>

  380. </dd>

  381. <dt><code>-moverride=<var>string</var></code></dt>

  382. <dd><a name="index-moverride"></a>

  383. <p>Override tuning decisions made by the back-end in response to a

  384. <samp>-mtune=</samp> switch.  The syntax, semantics, and accepted values

  385. for <var>string</var> in this option are not guaranteed to be consistent

  386. across releases.

  387. </p>

  388. <p>This option is only intended to be useful when developing GCC.

  389. </p>

  390. </dd>

  391. <dt><code>-mverbose-cost-dump</code></dt>

  392. <dd><a name="index-mverbose_002dcost_002ddump"></a>

  393. <p>Enable verbose cost model dumping in the debug dump files.  This option is

  394. provided for use in debugging the compiler.

  395. </p>

  396. </dd>

  397. <dt><code>-mpc-relative-literal-loads</code></dt>

  398. <dt><code>-mno-pc-relative-literal-loads</code></dt>

  399. <dd><a name="index-mpc_002drelative_002dliteral_002dloads"></a>

  400. <a name="index-mno_002dpc_002drelative_002dliteral_002dloads"></a>

  401. <p>Enable or disable PC-relative literal loads.  With this option literal pools are

  402. accessed using a single instruction and emitted after each function.  This

  403. limits the maximum size of functions to 1MB.  This is enabled by default for

  404. <samp>-mcmodel=tiny</samp>.

  405. </p>

  406. </dd>

  407. <dt><code>-msign-return-address=<var>scope</var></code></dt>

  408. <dd><a name="index-msign_002dreturn_002daddress"></a>

  409. <p>Select the function scope on which return address signing will be applied.

  410. Permissible values are &lsquo;<samp>none</samp>&rsquo;, which disables return address signing,

  411. &lsquo;<samp>non-leaf</samp>&rsquo;, which enables pointer signing for functions which are not leaf

  412. functions, and &lsquo;<samp>all</samp>&rsquo;, which enables pointer signing for all functions.  The

  413. default value is &lsquo;<samp>none</samp>&rsquo;. This option has been deprecated by

  414. -mbranch-protection.

  415. </p>

  416. </dd>

  417. <dt><code>-mbranch-protection=<var>none</var>|<var>standard</var>|<var>pac-ret</var>[+<var>leaf</var>+<var>b-key</var>]|<var>bti</var></code></dt>

  418. <dd><a name="index-mbranch_002dprotection"></a>

  419. <p>Select the branch protection features to use.

  420. &lsquo;<samp>none</samp>&rsquo; is the default and turns off all types of branch protection.

  421. &lsquo;<samp>standard</samp>&rsquo; turns on all types of branch protection features.  If a feature

  422. has additional tuning options, then &lsquo;<samp>standard</samp>&rsquo; sets it to its standard

  423. level.

  424. &lsquo;<samp>pac-ret[+<var>leaf</var>]</samp>&rsquo; turns on return address signing to its standard

  425. level: signing functions that save the return address to memory (non-leaf

  426. functions will practically always do this) using the a-key.  The optional

  427. argument &lsquo;<samp>leaf</samp>&rsquo; can be used to extend the signing to include leaf

  428. functions.  The optional argument &lsquo;<samp>b-key</samp>&rsquo; can be used to sign the functions

  429. with the B-key instead of the A-key.

  430. &lsquo;<samp>bti</samp>&rsquo; turns on branch target identification mechanism.

  431. </p>

  432. </dd>

  433. <dt><code>-mharden-sls=<var>opts</var></code></dt>

  434. <dd><a name="index-mharden_002dsls"></a>

  435. <p>Enable compiler hardening against straight line speculation (SLS).

  436. <var>opts</var> is a comma-separated list of the following options:

  437. </p><dl compact="compact">

  438. <dt>&lsquo;<samp>retbr</samp>&rsquo;</dt>

  439. <dt>&lsquo;<samp>blr</samp>&rsquo;</dt>

  440. </dl>

  441. <p>In addition, &lsquo;<samp>-mharden-sls=all</samp>&rsquo; enables all SLS hardening while

  442. &lsquo;<samp>-mharden-sls=none</samp>&rsquo; disables all SLS hardening.

  443. </p>

  444. </dd>

  445. <dt><code>-msve-vector-bits=<var>bits</var></code></dt>

  446. <dd><a name="index-msve_002dvector_002dbits"></a>

  447. <p>Specify the number of bits in an SVE vector register.  This option only has

  448. an effect when SVE is enabled.

  449. </p>

  450. <p>GCC supports two forms of SVE code generation: &ldquo;vector-length

  451. agnostic&rdquo; output that works with any size of vector register and

  452. &ldquo;vector-length specific&rdquo; output that allows GCC to make assumptions

  453. about the vector length when it is useful for optimization reasons.

  454. The possible values of &lsquo;<samp>bits</samp>&rsquo; are: &lsquo;<samp>scalable</samp>&rsquo;, &lsquo;<samp>128</samp>&rsquo;,

  455. &lsquo;<samp>256</samp>&rsquo;, &lsquo;<samp>512</samp>&rsquo;, &lsquo;<samp>1024</samp>&rsquo; and &lsquo;<samp>2048</samp>&rsquo;.

  456. Specifying &lsquo;<samp>scalable</samp>&rsquo; selects vector-length agnostic

  457. output.  At present &lsquo;<samp>-msve-vector-bits=128</samp>&rsquo; also generates vector-length

  458. agnostic output for big-endian targets.  All other values generate

  459. vector-length specific code.  The behavior of these values may change

  460. in future releases and no value except &lsquo;<samp>scalable</samp>&rsquo; should be

  461. relied on for producing code that is portable across different

  462. hardware SVE vector lengths.

  463. </p>

  464. <p>The default is &lsquo;<samp>-msve-vector-bits=scalable</samp>&rsquo;, which produces

  465. vector-length agnostic code.

  466. </p></dd>

  467. </dl>

  468. 

  469. <a name="g_t_002dmarch-and-_002dmcpu-Feature-Modifiers"></a>

  470. <h4 class="subsubsection">3.19.1.1 <samp>-march</samp> and <samp>-mcpu</samp> Feature Modifiers</h4>

  471. <a name="aarch64_002dfeature_002dmodifiers"></a><a name="index-_002dmarch-feature-modifiers"></a>

  472. <a name="index-_002dmcpu-feature-modifiers"></a>

  473. <p>Feature modifiers used with <samp>-march</samp> and <samp>-mcpu</samp> can be any of

  474. the following and their inverses <samp>no<var>feature</var></samp>:

  475. </p>

  476. <dl compact="compact">

  477. <dt>&lsquo;<samp>crc</samp>&rsquo;</dt>

  478. <dd><p>Enable CRC extension.  This is on by default for

  479. <samp>-march=armv8.1-a</samp>.

  480. </p></dd>

  481. <dt>&lsquo;<samp>crypto</samp>&rsquo;</dt>

  482. <dd><p>Enable Crypto extension.  This also enables Advanced SIMD and floating-point

  483. instructions.

  484. </p></dd>

  485. <dt>&lsquo;<samp>fp</samp>&rsquo;</dt>

  486. <dd><p>Enable floating-point instructions.  This is on by default for all possible

  487. values for options <samp>-march</samp> and <samp>-mcpu</samp>.

  488. </p></dd>

  489. <dt>&lsquo;<samp>simd</samp>&rsquo;</dt>

  490. <dd><p>Enable Advanced SIMD instructions.  This also enables floating-point

  491. instructions.  This is on by default for all possible values for options

  492. <samp>-march</samp> and <samp>-mcpu</samp>.

  493. </p></dd>

  494. <dt>&lsquo;<samp>sve</samp>&rsquo;</dt>

  495. <dd><p>Enable Scalable Vector Extension instructions.  This also enables Advanced

  496. SIMD and floating-point instructions.

  497. </p></dd>

  498. <dt>&lsquo;<samp>lse</samp>&rsquo;</dt>

  499. <dd><p>Enable Large System Extension instructions.  This is on by default for

  500. <samp>-march=armv8.1-a</samp>.

  501. </p></dd>

  502. <dt>&lsquo;<samp>rdma</samp>&rsquo;</dt>

  503. <dd><p>Enable Round Double Multiply Accumulate instructions.  This is on by default

  504. for <samp>-march=armv8.1-a</samp>.

  505. </p></dd>

  506. <dt>&lsquo;<samp>fp16</samp>&rsquo;</dt>

  507. <dd><p>Enable FP16 extension.  This also enables floating-point instructions.

  508. </p></dd>

  509. <dt>&lsquo;<samp>fp16fml</samp>&rsquo;</dt>

  510. <dd><p>Enable FP16 fmla extension.  This also enables FP16 extensions and

  511. floating-point instructions. This option is enabled by default for <samp>-march=armv8.4-a</samp>. Use of this option with architectures prior to Armv8.2-A is not supported.

  512. </p>

  513. </dd>

  514. <dt>&lsquo;<samp>rcpc</samp>&rsquo;</dt>

  515. <dd><p>Enable the RcPc extension.  This does not change code generation from GCC,

  516. but is passed on to the assembler, enabling inline asm statements to use

  517. instructions from the RcPc extension.

  518. </p></dd>

  519. <dt>&lsquo;<samp>dotprod</samp>&rsquo;</dt>

  520. <dd><p>Enable the Dot Product extension.  This also enables Advanced SIMD instructions.

  521. </p></dd>

  522. <dt>&lsquo;<samp>aes</samp>&rsquo;</dt>

  523. <dd><p>Enable the Armv8-a aes and pmull crypto extension.  This also enables Advanced

  524. SIMD instructions.

  525. </p></dd>

  526. <dt>&lsquo;<samp>sha2</samp>&rsquo;</dt>

  527. <dd><p>Enable the Armv8-a sha2 crypto extension.  This also enables Advanced SIMD instructions.

  528. </p></dd>

  529. <dt>&lsquo;<samp>sha3</samp>&rsquo;</dt>

  530. <dd><p>Enable the sha512 and sha3 crypto extension.  This also enables Advanced SIMD

  531. instructions. Use of this option with architectures prior to Armv8.2-A is not supported.

  532. </p></dd>

  533. <dt>&lsquo;<samp>sm4</samp>&rsquo;</dt>

  534. <dd><p>Enable the sm3 and sm4 crypto extension.  This also enables Advanced SIMD instructions.

  535. Use of this option with architectures prior to Armv8.2-A is not supported.

  536. </p></dd>

  537. <dt>&lsquo;<samp>profile</samp>&rsquo;</dt>

  538. <dd><p>Enable the Statistical Profiling extension.  This option is only to enable the

  539. extension at the assembler level and does not affect code generation.

  540. </p></dd>

  541. <dt>&lsquo;<samp>rng</samp>&rsquo;</dt>

  542. <dd><p>Enable the Armv8.5-a Random Number instructions.  This option is only to

  543. enable the extension at the assembler level and does not affect code

  544. generation.

  545. </p></dd>

  546. <dt>&lsquo;<samp>memtag</samp>&rsquo;</dt>

  547. <dd><p>Enable the Armv8.5-a Memory Tagging Extensions.

  548. Use of this option with architectures prior to Armv8.5-A is not supported.

  549. </p></dd>

  550. <dt>&lsquo;<samp>sb</samp>&rsquo;</dt>

  551. <dd><p>Enable the Armv8-a Speculation Barrier instruction.  This option is only to

  552. enable the extension at the assembler level and does not affect code

  553. generation.  This option is enabled by default for <samp>-march=armv8.5-a</samp>.

  554. </p></dd>

  555. <dt>&lsquo;<samp>ssbs</samp>&rsquo;</dt>

  556. <dd><p>Enable the Armv8-a Speculative Store Bypass Safe instruction.  This option

  557. is only to enable the extension at the assembler level and does not affect code

  558. generation.  This option is enabled by default for <samp>-march=armv8.5-a</samp>.

  559. </p></dd>

  560. <dt>&lsquo;<samp>predres</samp>&rsquo;</dt>

  561. <dd><p>Enable the Armv8-a Execution and Data Prediction Restriction instructions.

  562. This option is only to enable the extension at the assembler level and does

  563. not affect code generation.  This option is enabled by default for

  564. <samp>-march=armv8.5-a</samp>.

  565. </p></dd>

  566. <dt>&lsquo;<samp>sve2</samp>&rsquo;</dt>

  567. <dd><p>Enable the Armv8-a Scalable Vector Extension 2.  This also enables SVE

  568. instructions.

  569. </p></dd>

  570. <dt>&lsquo;<samp>sve2-bitperm</samp>&rsquo;</dt>

  571. <dd><p>Enable SVE2 bitperm instructions.  This also enables SVE2 instructions.

  572. </p></dd>

  573. <dt>&lsquo;<samp>sve2-sm4</samp>&rsquo;</dt>

  574. <dd><p>Enable SVE2 sm4 instructions.  This also enables SVE2 instructions.

  575. </p></dd>

  576. <dt>&lsquo;<samp>sve2-aes</samp>&rsquo;</dt>

  577. <dd><p>Enable SVE2 aes instructions.  This also enables SVE2 instructions.

  578. </p></dd>

  579. <dt>&lsquo;<samp>sve2-sha3</samp>&rsquo;</dt>

  580. <dd><p>Enable SVE2 sha3 instructions.  This also enables SVE2 instructions.

  581. </p></dd>

  582. <dt>&lsquo;<samp>tme</samp>&rsquo;</dt>

  583. <dd><p>Enable the Transactional Memory Extension.

  584. </p></dd>

  585. <dt>&lsquo;<samp>i8mm</samp>&rsquo;</dt>

  586. <dd><p>Enable 8-bit Integer Matrix Multiply instructions.  This also enables

  587. Advanced SIMD and floating-point instructions.  This option is enabled by

  588. default for <samp>-march=armv8.6-a</samp>.  Use of this option with architectures

  589. prior to Armv8.2-A is not supported.

  590. </p></dd>

  591. <dt>&lsquo;<samp>f32mm</samp>&rsquo;</dt>

  592. <dd><p>Enable 32-bit Floating point Matrix Multiply instructions.  This also enables

  593. SVE instructions.  Use of this option with architectures prior to Armv8.2-A is

  594. not supported.

  595. </p></dd>

  596. <dt>&lsquo;<samp>f64mm</samp>&rsquo;</dt>

  597. <dd><p>Enable 64-bit Floating point Matrix Multiply instructions.  This also enables

  598. SVE instructions.  Use of this option with architectures prior to Armv8.2-A is

  599. not supported.

  600. </p></dd>

  601. <dt>&lsquo;<samp>bf16</samp>&rsquo;</dt>

  602. <dd><p>Enable brain half-precision floating-point instructions.  This also enables

  603. Advanced SIMD and floating-point instructions.  This option is enabled by

  604. default for <samp>-march=armv8.6-a</samp>.  Use of this option with architectures

  605. prior to Armv8.2-A is not supported.

  606. </p>

  607. </dd>

  608. </dl>

  609. 

  610. <p>Feature <samp>crypto</samp> implies <samp>aes</samp>, <samp>sha2</samp>, and <samp>simd</samp>,

  611. which implies <samp>fp</samp>.

  612. Conversely, <samp>nofp</samp> implies <samp>nosimd</samp>, which implies

  613. <samp>nocrypto</samp>, <samp>noaes</samp> and <samp>nosha2</samp>.

  614. </p>

  615. <hr>

  616. <div class="header">

  617. <p>

  618. Next: <a href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" accesskey="n" rel="next">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  619. </div>

  620. 

  621. 

  622. 

  623. </body>

  624. </html>