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  20. <title>OpenRISC Options (Using the GNU Compiler Collection (GCC))</title>
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  61. <a name="OpenRISC-Options"></a>
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  64. Next: <a href="PDP_002d11-Options.html#PDP_002d11-Options" accesskey="n" rel="next">PDP-11 Options</a>, Previous: <a href="Nvidia-PTX-Options.html#Nvidia-PTX-Options" accesskey="p" rel="prev">Nvidia PTX Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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  66. <hr>
  67. <a name="OpenRISC-Options-1"></a>
  68. <h4 class="subsection">3.19.37 OpenRISC Options</h4>
  69. <a name="index-OpenRISC-Options"></a>
  70. <p>These options are defined for OpenRISC:
  71. </p>
  72. <dl compact="compact">
  73. <dt><code>-mboard=<var>name</var></code></dt>
  74. <dd><a name="index-mboard"></a>
  75. <p>Configure a board specific runtime. This will be passed to the linker for
  76. newlib board library linking. The default is <code>or1ksim</code>.
  77. </p>
  78. </dd>
  79. <dt><code>-mnewlib</code></dt>
  80. <dd><a name="index-mnewlib"></a>
  81. <p>This option is ignored; it is for compatibility purposes only. This used to
  82. select linker and preprocessor options for use with newlib.
  83. </p>
  84. </dd>
  85. <dt><code>-msoft-div</code></dt>
  86. <dt><code>-mhard-div</code></dt>
  87. <dd><a name="index-msoft_002ddiv"></a>
  88. <a name="index-mhard_002ddiv"></a>
  89. <p>Select software or hardware divide (<code>l.div</code>, <code>l.divu</code>) instructions.
  90. This default is hardware divide.
  91. </p>
  92. </dd>
  93. <dt><code>-msoft-mul</code></dt>
  94. <dt><code>-mhard-mul</code></dt>
  95. <dd><a name="index-msoft_002dmul"></a>
  96. <a name="index-mhard_002dmul"></a>
  97. <p>Select software or hardware multiply (<code>l.mul</code>, <code>l.muli</code>) instructions.
  98. This default is hardware multiply.
  99. </p>
  100. </dd>
  101. <dt><code>-msoft-float</code></dt>
  102. <dt><code>-mhard-float</code></dt>
  103. <dd><a name="index-msoft_002dfloat-8"></a>
  104. <a name="index-mhard_002dfloat-5"></a>
  105. <p>Select software or hardware for floating point operations.
  106. The default is software.
  107. </p>
  108. </dd>
  109. <dt><code>-mdouble-float</code></dt>
  110. <dd><a name="index-mdouble_002dfloat-2"></a>
  111. <p>When <samp>-mhard-float</samp> is selected, enables generation of double-precision
  112. floating point instructions. By default functions from <samp>libgcc</samp> are used
  113. to perform double-precision floating point operations.
  114. </p>
  115. </dd>
  116. <dt><code>-munordered-float</code></dt>
  117. <dd><a name="index-munordered_002dfloat"></a>
  118. <p>When <samp>-mhard-float</samp> is selected, enables generation of unordered
  119. floating point compare and set flag (<code>lf.sfun*</code>) instructions. By default
  120. functions from <samp>libgcc</samp> are used to perform unordered floating point
  121. compare and set flag operations.
  122. </p>
  123. </dd>
  124. <dt><code>-mcmov</code></dt>
  125. <dd><a name="index-mcmov-1"></a>
  126. <p>Enable generation of conditional move (<code>l.cmov</code>) instructions. By
  127. default the equivalent will be generated using set and branch.
  128. </p>
  129. </dd>
  130. <dt><code>-mror</code></dt>
  131. <dd><a name="index-mror"></a>
  132. <p>Enable generation of rotate right (<code>l.ror</code>) instructions. By default
  133. functions from <samp>libgcc</samp> are used to perform rotate right operations.
  134. </p>
  135. </dd>
  136. <dt><code>-mrori</code></dt>
  137. <dd><a name="index-mrori"></a>
  138. <p>Enable generation of rotate right with immediate (<code>l.rori</code>) instructions.
  139. By default functions from <samp>libgcc</samp> are used to perform rotate right with
  140. immediate operations.
  141. </p>
  142. </dd>
  143. <dt><code>-msext</code></dt>
  144. <dd><a name="index-msext"></a>
  145. <p>Enable generation of sign extension (<code>l.ext*</code>) instructions. By default
  146. memory loads are used to perform sign extension.
  147. </p>
  148. </dd>
  149. <dt><code>-msfimm</code></dt>
  150. <dd><a name="index-msfimm"></a>
  151. <p>Enable generation of compare and set flag with immediate (<code>l.sf*i</code>)
  152. instructions. By default extra instructions will be generated to store the
  153. immediate to a register first.
  154. </p>
  155. </dd>
  156. <dt><code>-mshftimm</code></dt>
  157. <dd><a name="index-mshftimm"></a>
  158. <p>Enable generation of shift with immediate (<code>l.srai</code>, <code>l.srli</code>,
  159. <code>l.slli</code>) instructions. By default extra instructions will be generated
  160. to store the immediate to a register first.
  161. </p>
  162. </dd>
  163. </dl>
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