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  25. <title>SPARC Options (Using the GNU Compiler Collection (GCC))</title>

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  34. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  35. <link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">

  36. <link href="System-V-Options.html#System-V-Options" rel="next" title="System V Options">

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  68. 

  69. <body lang="en">

  70. <a name="SPARC-Options"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="System-V-Options.html#System-V-Options" accesskey="n" rel="next">System V Options</a>, Previous: <a href="Solaris-2-Options.html#Solaris-2-Options" accesskey="p" rel="prev">Solaris 2 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="SPARC-Options-1"></a>

  77. <h4 class="subsection">3.19.50 SPARC Options</h4>

  78. <a name="index-SPARC-options"></a>

  79. 

  80. <p>These &lsquo;<samp>-m</samp>&rsquo; options are supported on the SPARC:

  81. </p>

  82. <dl compact="compact">

  83. <dt><code>-mno-app-regs</code></dt>

  84. <dt><code>-mapp-regs</code></dt>

  85. <dd><a name="index-mno_002dapp_002dregs"></a>

  86. <a name="index-mapp_002dregs"></a>

  87. <p>Specify <samp>-mapp-regs</samp> to generate output using the global registers

  88. 2 through 4, which the SPARC SVR4 ABI reserves for applications.  Like the

  89. global register 1, each global register 2 through 4 is then treated as an

  90. allocable register that is clobbered by function calls.  This is the default.

  91. </p>

  92. <p>To be fully SVR4 ABI-compliant at the cost of some performance loss,

  93. specify <samp>-mno-app-regs</samp>.  You should compile libraries and system

  94. software with this option.

  95. </p>

  96. </dd>

  97. <dt><code>-mflat</code></dt>

  98. <dt><code>-mno-flat</code></dt>

  99. <dd><a name="index-mflat"></a>

  100. <a name="index-mno_002dflat"></a>

  101. <p>With <samp>-mflat</samp>, the compiler does not generate save/restore instructions

  102. and uses a &ldquo;flat&rdquo; or single register window model.  This model is compatible

  103. with the regular register window model.  The local registers and the input

  104. registers (0&ndash;5) are still treated as &ldquo;call-saved&rdquo; registers and are

  105. saved on the stack as needed.

  106. </p>

  107. <p>With <samp>-mno-flat</samp> (the default), the compiler generates save/restore

  108. instructions (except for leaf functions).  This is the normal operating mode.

  109. </p>

  110. </dd>

  111. <dt><code>-mfpu</code></dt>

  112. <dt><code>-mhard-float</code></dt>

  113. <dd><a name="index-mfpu-3"></a>

  114. <a name="index-mhard_002dfloat-8"></a>

  115. <p>Generate output containing floating-point instructions.  This is the

  116. default.

  117. </p>

  118. </dd>

  119. <dt><code>-mno-fpu</code></dt>

  120. <dt><code>-msoft-float</code></dt>

  121. <dd><a name="index-mno_002dfpu"></a>

  122. <a name="index-msoft_002dfloat-12"></a>

  123. <p>Generate output containing library calls for floating point.

  124. <strong>Warning:</strong> the requisite libraries are not available for all SPARC

  125. targets.  Normally the facilities of the machine&rsquo;s usual C compiler are

  126. used, but this cannot be done directly in cross-compilation.  You must make

  127. your own arrangements to provide suitable library functions for

  128. cross-compilation.  The embedded targets &lsquo;<samp>sparc-*-aout</samp>&rsquo; and

  129. &lsquo;<samp>sparclite-*-*</samp>&rsquo; do provide software floating-point support.

  130. </p>

  131. <p><samp>-msoft-float</samp> changes the calling convention in the output file;

  132. therefore, it is only useful if you compile <em>all</em> of a program with

  133. this option.  In particular, you need to compile <samp>libgcc.a</samp>, the

  134. library that comes with GCC, with <samp>-msoft-float</samp> in order for

  135. this to work.

  136. </p>

  137. </dd>

  138. <dt><code>-mhard-quad-float</code></dt>

  139. <dd><a name="index-mhard_002dquad_002dfloat"></a>

  140. <p>Generate output containing quad-word (long double) floating-point

  141. instructions.

  142. </p>

  143. </dd>

  144. <dt><code>-msoft-quad-float</code></dt>

  145. <dd><a name="index-msoft_002dquad_002dfloat"></a>

  146. <p>Generate output containing library calls for quad-word (long double)

  147. floating-point instructions.  The functions called are those specified

  148. in the SPARC ABI.  This is the default.

  149. </p>

  150. <p>As of this writing, there are no SPARC implementations that have hardware

  151. support for the quad-word floating-point instructions.  They all invoke

  152. a trap handler for one of these instructions, and then the trap handler

  153. emulates the effect of the instruction.  Because of the trap handler overhead,

  154. this is much slower than calling the ABI library routines.  Thus the

  155. <samp>-msoft-quad-float</samp> option is the default.

  156. </p>

  157. </dd>

  158. <dt><code>-mno-unaligned-doubles</code></dt>

  159. <dt><code>-munaligned-doubles</code></dt>

  160. <dd><a name="index-mno_002dunaligned_002ddoubles"></a>

  161. <a name="index-munaligned_002ddoubles"></a>

  162. <p>Assume that doubles have 8-byte alignment.  This is the default.

  163. </p>

  164. <p>With <samp>-munaligned-doubles</samp>, GCC assumes that doubles have 8-byte

  165. alignment only if they are contained in another type, or if they have an

  166. absolute address.  Otherwise, it assumes they have 4-byte alignment.

  167. Specifying this option avoids some rare compatibility problems with code

  168. generated by other compilers.  It is not the default because it results

  169. in a performance loss, especially for floating-point code.

  170. </p>

  171. </dd>

  172. <dt><code>-muser-mode</code></dt>

  173. <dt><code>-mno-user-mode</code></dt>

  174. <dd><a name="index-muser_002dmode"></a>

  175. <a name="index-mno_002duser_002dmode"></a>

  176. <p>Do not generate code that can only run in supervisor mode.  This is relevant

  177. only for the <code>casa</code> instruction emitted for the LEON3 processor.  This

  178. is the default.

  179. </p>

  180. </dd>

  181. <dt><code>-mfaster-structs</code></dt>

  182. <dt><code>-mno-faster-structs</code></dt>

  183. <dd><a name="index-mfaster_002dstructs"></a>

  184. <a name="index-mno_002dfaster_002dstructs"></a>

  185. <p>With <samp>-mfaster-structs</samp>, the compiler assumes that structures

  186. should have 8-byte alignment.  This enables the use of pairs of

  187. <code>ldd</code> and <code>std</code> instructions for copies in structure

  188. assignment, in place of twice as many <code>ld</code> and <code>st</code> pairs.

  189. However, the use of this changed alignment directly violates the SPARC

  190. ABI.  Thus, it&rsquo;s intended only for use on targets where the developer

  191. acknowledges that their resulting code is not directly in line with

  192. the rules of the ABI.

  193. </p>

  194. </dd>

  195. <dt><code>-mstd-struct-return</code></dt>

  196. <dt><code>-mno-std-struct-return</code></dt>

  197. <dd><a name="index-mstd_002dstruct_002dreturn"></a>

  198. <a name="index-mno_002dstd_002dstruct_002dreturn"></a>

  199. <p>With <samp>-mstd-struct-return</samp>, the compiler generates checking code

  200. in functions returning structures or unions to detect size mismatches

  201. between the two sides of function calls, as per the 32-bit ABI.

  202. </p>

  203. <p>The default is <samp>-mno-std-struct-return</samp>.  This option has no effect

  204. in 64-bit mode.

  205. </p>

  206. </dd>

  207. <dt><code>-mlra</code></dt>

  208. <dt><code>-mno-lra</code></dt>

  209. <dd><a name="index-mlra-3"></a>

  210. <a name="index-mno_002dlra"></a>

  211. <p>Enable Local Register Allocation.  This is the default for SPARC since GCC 7

  212. so <samp>-mno-lra</samp> needs to be passed to get old Reload.

  213. </p>

  214. </dd>

  215. <dt><code>-mcpu=<var>cpu_type</var></code></dt>

  216. <dd><a name="index-mcpu-11"></a>

  217. <p>Set the instruction set, register set, and instruction scheduling parameters

  218. for machine type <var>cpu_type</var>.  Supported values for <var>cpu_type</var> are

  219. &lsquo;<samp>v7</samp>&rsquo;, &lsquo;<samp>cypress</samp>&rsquo;, &lsquo;<samp>v8</samp>&rsquo;, &lsquo;<samp>supersparc</samp>&rsquo;, &lsquo;<samp>hypersparc</samp>&rsquo;,

  220. &lsquo;<samp>leon</samp>&rsquo;, &lsquo;<samp>leon3</samp>&rsquo;, &lsquo;<samp>leon3v7</samp>&rsquo;, &lsquo;<samp>sparclite</samp>&rsquo;, &lsquo;<samp>f930</samp>&rsquo;,

  221. &lsquo;<samp>f934</samp>&rsquo;, &lsquo;<samp>sparclite86x</samp>&rsquo;, &lsquo;<samp>sparclet</samp>&rsquo;, &lsquo;<samp>tsc701</samp>&rsquo;, &lsquo;<samp>v9</samp>&rsquo;,

  222. &lsquo;<samp>ultrasparc</samp>&rsquo;, &lsquo;<samp>ultrasparc3</samp>&rsquo;, &lsquo;<samp>niagara</samp>&rsquo;, &lsquo;<samp>niagara2</samp>&rsquo;,

  223. &lsquo;<samp>niagara3</samp>&rsquo;, &lsquo;<samp>niagara4</samp>&rsquo;, &lsquo;<samp>niagara7</samp>&rsquo; and &lsquo;<samp>m8</samp>&rsquo;.

  224. </p>

  225. <p>Native Solaris and GNU/Linux toolchains also support the value &lsquo;<samp>native</samp>&rsquo;,

  226. which selects the best architecture option for the host processor.

  227. <samp>-mcpu=native</samp> has no effect if GCC does not recognize

  228. the processor.

  229. </p>

  230. <p>Default instruction scheduling parameters are used for values that select

  231. an architecture and not an implementation.  These are &lsquo;<samp>v7</samp>&rsquo;, &lsquo;<samp>v8</samp>&rsquo;,

  232. &lsquo;<samp>sparclite</samp>&rsquo;, &lsquo;<samp>sparclet</samp>&rsquo;, &lsquo;<samp>v9</samp>&rsquo;.

  233. </p>

  234. <p>Here is a list of each supported architecture and their supported

  235. implementations.

  236. </p>

  237. <dl compact="compact">

  238. <dt>v7</dt>

  239. <dd><p>cypress, leon3v7

  240. </p>

  241. </dd>

  242. <dt>v8</dt>

  243. <dd><p>supersparc, hypersparc, leon, leon3

  244. </p>

  245. </dd>

  246. <dt>sparclite</dt>

  247. <dd><p>f930, f934, sparclite86x

  248. </p>

  249. </dd>

  250. <dt>sparclet</dt>

  251. <dd><p>tsc701

  252. </p>

  253. </dd>

  254. <dt>v9</dt>

  255. <dd><p>ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4,

  256. niagara7, m8

  257. </p></dd>

  258. </dl>

  259. 

  260. <p>By default (unless configured otherwise), GCC generates code for the V7

  261. variant of the SPARC architecture.  With <samp>-mcpu=cypress</samp>, the compiler

  262. additionally optimizes it for the Cypress CY7C602 chip, as used in the

  263. SPARCStation/SPARCServer 3xx series.  This is also appropriate for the older

  264. SPARCStation 1, 2, IPX etc.

  265. </p>

  266. <p>With <samp>-mcpu=v8</samp>, GCC generates code for the V8 variant of the SPARC

  267. architecture.  The only difference from V7 code is that the compiler emits

  268. the integer multiply and integer divide instructions which exist in SPARC-V8

  269. but not in SPARC-V7.  With <samp>-mcpu=supersparc</samp>, the compiler additionally

  270. optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and

  271. 2000 series.

  272. </p>

  273. <p>With <samp>-mcpu=sparclite</samp>, GCC generates code for the SPARClite variant of

  274. the SPARC architecture.  This adds the integer multiply, integer divide step

  275. and scan (<code>ffs</code>) instructions which exist in SPARClite but not in SPARC-V7.

  276. With <samp>-mcpu=f930</samp>, the compiler additionally optimizes it for the

  277. Fujitsu MB86930 chip, which is the original SPARClite, with no FPU.  With

  278. <samp>-mcpu=f934</samp>, the compiler additionally optimizes it for the Fujitsu

  279. MB86934 chip, which is the more recent SPARClite with FPU.

  280. </p>

  281. <p>With <samp>-mcpu=sparclet</samp>, GCC generates code for the SPARClet variant of

  282. the SPARC architecture.  This adds the integer multiply, multiply/accumulate,

  283. integer divide step and scan (<code>ffs</code>) instructions which exist in SPARClet

  284. but not in SPARC-V7.  With <samp>-mcpu=tsc701</samp>, the compiler additionally

  285. optimizes it for the TEMIC SPARClet chip.

  286. </p>

  287. <p>With <samp>-mcpu=v9</samp>, GCC generates code for the V9 variant of the SPARC

  288. architecture.  This adds 64-bit integer and floating-point move instructions,

  289. 3 additional floating-point condition code registers and conditional move

  290. instructions.  With <samp>-mcpu=ultrasparc</samp>, the compiler additionally

  291. optimizes it for the Sun UltraSPARC I/II/IIi chips.  With

  292. <samp>-mcpu=ultrasparc3</samp>, the compiler additionally optimizes it for the

  293. Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips.  With

  294. <samp>-mcpu=niagara</samp>, the compiler additionally optimizes it for

  295. Sun UltraSPARC T1 chips.  With <samp>-mcpu=niagara2</samp>, the compiler

  296. additionally optimizes it for Sun UltraSPARC T2 chips. With

  297. <samp>-mcpu=niagara3</samp>, the compiler additionally optimizes it for Sun

  298. UltraSPARC T3 chips.  With <samp>-mcpu=niagara4</samp>, the compiler

  299. additionally optimizes it for Sun UltraSPARC T4 chips.  With

  300. <samp>-mcpu=niagara7</samp>, the compiler additionally optimizes it for

  301. Oracle SPARC M7 chips.  With <samp>-mcpu=m8</samp>, the compiler

  302. additionally optimizes it for Oracle M8 chips.

  303. </p>

  304. </dd>

  305. <dt><code>-mtune=<var>cpu_type</var></code></dt>

  306. <dd><a name="index-mtune-14"></a>

  307. <p>Set the instruction scheduling parameters for machine type

  308. <var>cpu_type</var>, but do not set the instruction set or register set that the

  309. option <samp>-mcpu=<var>cpu_type</var></samp> does.

  310. </p>

  311. <p>The same values for <samp>-mcpu=<var>cpu_type</var></samp> can be used for

  312. <samp>-mtune=<var>cpu_type</var></samp>, but the only useful values are those

  313. that select a particular CPU implementation.  Those are

  314. &lsquo;<samp>cypress</samp>&rsquo;, &lsquo;<samp>supersparc</samp>&rsquo;, &lsquo;<samp>hypersparc</samp>&rsquo;, &lsquo;<samp>leon</samp>&rsquo;,

  315. &lsquo;<samp>leon3</samp>&rsquo;, &lsquo;<samp>leon3v7</samp>&rsquo;, &lsquo;<samp>f930</samp>&rsquo;, &lsquo;<samp>f934</samp>&rsquo;,

  316. &lsquo;<samp>sparclite86x</samp>&rsquo;, &lsquo;<samp>tsc701</samp>&rsquo;, &lsquo;<samp>ultrasparc</samp>&rsquo;,

  317. &lsquo;<samp>ultrasparc3</samp>&rsquo;, &lsquo;<samp>niagara</samp>&rsquo;, &lsquo;<samp>niagara2</samp>&rsquo;, &lsquo;<samp>niagara3</samp>&rsquo;,

  318. &lsquo;<samp>niagara4</samp>&rsquo;, &lsquo;<samp>niagara7</samp>&rsquo; and &lsquo;<samp>m8</samp>&rsquo;.  With native Solaris

  319. and GNU/Linux toolchains, &lsquo;<samp>native</samp>&rsquo; can also be used.

  320. </p>

  321. </dd>

  322. <dt><code>-mv8plus</code></dt>

  323. <dt><code>-mno-v8plus</code></dt>

  324. <dd><a name="index-mv8plus"></a>

  325. <a name="index-mno_002dv8plus"></a>

  326. <p>With <samp>-mv8plus</samp>, GCC generates code for the SPARC-V8+ ABI.  The

  327. difference from the V8 ABI is that the global and out registers are

  328. considered 64 bits wide.  This is enabled by default on Solaris in 32-bit

  329. mode for all SPARC-V9 processors.

  330. </p>

  331. </dd>

  332. <dt><code>-mvis</code></dt>

  333. <dt><code>-mno-vis</code></dt>

  334. <dd><a name="index-mvis"></a>

  335. <a name="index-mno_002dvis"></a>

  336. <p>With <samp>-mvis</samp>, GCC generates code that takes advantage of the UltraSPARC

  337. Visual Instruction Set extensions.  The default is <samp>-mno-vis</samp>.

  338. </p>

  339. </dd>

  340. <dt><code>-mvis2</code></dt>

  341. <dt><code>-mno-vis2</code></dt>

  342. <dd><a name="index-mvis2"></a>

  343. <a name="index-mno_002dvis2"></a>

  344. <p>With <samp>-mvis2</samp>, GCC generates code that takes advantage of

  345. version 2.0 of the UltraSPARC Visual Instruction Set extensions.  The

  346. default is <samp>-mvis2</samp> when targeting a cpu that supports such

  347. instructions, such as UltraSPARC-III and later.  Setting <samp>-mvis2</samp>

  348. also sets <samp>-mvis</samp>.

  349. </p>

  350. </dd>

  351. <dt><code>-mvis3</code></dt>

  352. <dt><code>-mno-vis3</code></dt>

  353. <dd><a name="index-mvis3"></a>

  354. <a name="index-mno_002dvis3"></a>

  355. <p>With <samp>-mvis3</samp>, GCC generates code that takes advantage of

  356. version 3.0 of the UltraSPARC Visual Instruction Set extensions.  The

  357. default is <samp>-mvis3</samp> when targeting a cpu that supports such

  358. instructions, such as niagara-3 and later.  Setting <samp>-mvis3</samp>

  359. also sets <samp>-mvis2</samp> and <samp>-mvis</samp>.

  360. </p>

  361. </dd>

  362. <dt><code>-mvis4</code></dt>

  363. <dt><code>-mno-vis4</code></dt>

  364. <dd><a name="index-mvis4"></a>

  365. <a name="index-mno_002dvis4"></a>

  366. <p>With <samp>-mvis4</samp>, GCC generates code that takes advantage of

  367. version 4.0 of the UltraSPARC Visual Instruction Set extensions.  The

  368. default is <samp>-mvis4</samp> when targeting a cpu that supports such

  369. instructions, such as niagara-7 and later.  Setting <samp>-mvis4</samp>

  370. also sets <samp>-mvis3</samp>, <samp>-mvis2</samp> and <samp>-mvis</samp>.

  371. </p>

  372. </dd>

  373. <dt><code>-mvis4b</code></dt>

  374. <dt><code>-mno-vis4b</code></dt>

  375. <dd><a name="index-mvis4b"></a>

  376. <a name="index-mno_002dvis4b"></a>

  377. <p>With <samp>-mvis4b</samp>, GCC generates code that takes advantage of

  378. version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus

  379. the additional VIS instructions introduced in the Oracle SPARC

  380. Architecture 2017.  The default is <samp>-mvis4b</samp> when targeting a

  381. cpu that supports such instructions, such as m8 and later.  Setting

  382. <samp>-mvis4b</samp> also sets <samp>-mvis4</samp>, <samp>-mvis3</samp>,

  383. <samp>-mvis2</samp> and <samp>-mvis</samp>.

  384. </p>

  385. </dd>

  386. <dt><code>-mcbcond</code></dt>

  387. <dt><code>-mno-cbcond</code></dt>

  388. <dd><a name="index-mcbcond"></a>

  389. <a name="index-mno_002dcbcond"></a>

  390. <p>With <samp>-mcbcond</samp>, GCC generates code that takes advantage of the UltraSPARC

  391. Compare-and-Branch-on-Condition instructions.  The default is <samp>-mcbcond</samp>

  392. when targeting a CPU that supports such instructions, such as Niagara-4 and

  393. later.

  394. </p>

  395. </dd>

  396. <dt><code>-mfmaf</code></dt>

  397. <dt><code>-mno-fmaf</code></dt>

  398. <dd><a name="index-mfmaf"></a>

  399. <a name="index-mno_002dfmaf"></a>

  400. <p>With <samp>-mfmaf</samp>, GCC generates code that takes advantage of the UltraSPARC

  401. Fused Multiply-Add Floating-point instructions.  The default is <samp>-mfmaf</samp>

  402. when targeting a CPU that supports such instructions, such as Niagara-3 and

  403. later.

  404. </p>

  405. </dd>

  406. <dt><code>-mfsmuld</code></dt>

  407. <dt><code>-mno-fsmuld</code></dt>

  408. <dd><a name="index-mfsmuld"></a>

  409. <a name="index-mno_002dfsmuld"></a>

  410. <p>With <samp>-mfsmuld</samp>, GCC generates code that takes advantage of the

  411. Floating-point Multiply Single to Double (FsMULd) instruction.  The default is

  412. <samp>-mfsmuld</samp> when targeting a CPU supporting the architecture versions V8

  413. or V9 with FPU except <samp>-mcpu=leon</samp>.

  414. </p>

  415. </dd>

  416. <dt><code>-mpopc</code></dt>

  417. <dt><code>-mno-popc</code></dt>

  418. <dd><a name="index-mpopc"></a>

  419. <a name="index-mno_002dpopc"></a>

  420. <p>With <samp>-mpopc</samp>, GCC generates code that takes advantage of the UltraSPARC

  421. Population Count instruction.  The default is <samp>-mpopc</samp>

  422. when targeting a CPU that supports such an instruction, such as Niagara-2 and

  423. later.

  424. </p>

  425. </dd>

  426. <dt><code>-msubxc</code></dt>

  427. <dt><code>-mno-subxc</code></dt>

  428. <dd><a name="index-msubxc"></a>

  429. <a name="index-mno_002dsubxc"></a>

  430. <p>With <samp>-msubxc</samp>, GCC generates code that takes advantage of the UltraSPARC

  431. Subtract-Extended-with-Carry instruction.  The default is <samp>-msubxc</samp>

  432. when targeting a CPU that supports such an instruction, such as Niagara-7 and

  433. later.

  434. </p>

  435. </dd>

  436. <dt><code>-mfix-at697f</code></dt>

  437. <dd><a name="index-mfix_002dat697f"></a>

  438. <p>Enable the documented workaround for the single erratum of the Atmel AT697F

  439. processor (which corresponds to erratum #13 of the AT697E processor).

  440. </p>

  441. </dd>

  442. <dt><code>-mfix-ut699</code></dt>

  443. <dd><a name="index-mfix_002dut699"></a>

  444. <p>Enable the documented workarounds for the floating-point errata and the data

  445. cache nullify errata of the UT699 processor.

  446. </p>

  447. </dd>

  448. <dt><code>-mfix-ut700</code></dt>

  449. <dd><a name="index-mfix_002dut700"></a>

  450. <p>Enable the documented workaround for the back-to-back store errata of

  451. the UT699E/UT700 processor.

  452. </p>

  453. </dd>

  454. <dt><code>-mfix-gr712rc</code></dt>

  455. <dd><a name="index-mfix_002dgr712rc"></a>

  456. <p>Enable the documented workaround for the back-to-back store errata of

  457. the GR712RC processor.

  458. </p></dd>

  459. </dl>

  460. 

  461. <p>These &lsquo;<samp>-m</samp>&rsquo; options are supported in addition to the above

  462. on SPARC-V9 processors in 64-bit environments:

  463. </p>

  464. <dl compact="compact">

  465. <dt><code>-m32</code></dt>

  466. <dt><code>-m64</code></dt>

  467. <dd><a name="index-m32-2"></a>

  468. <a name="index-m64-3"></a>

  469. <p>Generate code for a 32-bit or 64-bit environment.

  470. The 32-bit environment sets int, long and pointer to 32 bits.

  471. The 64-bit environment sets int to 32 bits and long and pointer

  472. to 64 bits.

  473. </p>

  474. </dd>

  475. <dt><code>-mcmodel=<var>which</var></code></dt>

  476. <dd><a name="index-mcmodel-1"></a>

  477. <p>Set the code model to one of

  478. </p>

  479. <dl compact="compact">

  480. <dt>&lsquo;<samp>medlow</samp>&rsquo;</dt>

  481. <dd><p>The Medium/Low code model: 64-bit addresses, programs

  482. must be linked in the low 32 bits of memory.  Programs can be statically

  483. or dynamically linked.

  484. </p>

  485. </dd>

  486. <dt>&lsquo;<samp>medmid</samp>&rsquo;</dt>

  487. <dd><p>The Medium/Middle code model: 64-bit addresses, programs

  488. must be linked in the low 44 bits of memory, the text and data segments must

  489. be less than 2GB in size and the data segment must be located within 2GB of

  490. the text segment.

  491. </p>

  492. </dd>

  493. <dt>&lsquo;<samp>medany</samp>&rsquo;</dt>

  494. <dd><p>The Medium/Anywhere code model: 64-bit addresses, programs

  495. may be linked anywhere in memory, the text and data segments must be less

  496. than 2GB in size and the data segment must be located within 2GB of the

  497. text segment.

  498. </p>

  499. </dd>

  500. <dt>&lsquo;<samp>embmedany</samp>&rsquo;</dt>

  501. <dd><p>The Medium/Anywhere code model for embedded systems:

  502. 64-bit addresses, the text and data segments must be less than 2GB in

  503. size, both starting anywhere in memory (determined at link time).  The

  504. global register %g4 points to the base of the data segment.  Programs

  505. are statically linked and PIC is not supported.

  506. </p></dd>

  507. </dl>

  508. 

  509. </dd>

  510. <dt><code>-mmemory-model=<var>mem-model</var></code></dt>

  511. <dd><a name="index-mmemory_002dmodel"></a>

  512. <p>Set the memory model in force on the processor to one of

  513. </p>

  514. <dl compact="compact">

  515. <dt>&lsquo;<samp>default</samp>&rsquo;</dt>

  516. <dd><p>The default memory model for the processor and operating system.

  517. </p>

  518. </dd>

  519. <dt>&lsquo;<samp>rmo</samp>&rsquo;</dt>

  520. <dd><p>Relaxed Memory Order

  521. </p>

  522. </dd>

  523. <dt>&lsquo;<samp>pso</samp>&rsquo;</dt>

  524. <dd><p>Partial Store Order

  525. </p>

  526. </dd>

  527. <dt>&lsquo;<samp>tso</samp>&rsquo;</dt>

  528. <dd><p>Total Store Order

  529. </p>

  530. </dd>

  531. <dt>&lsquo;<samp>sc</samp>&rsquo;</dt>

  532. <dd><p>Sequential Consistency

  533. </p></dd>

  534. </dl>

  535. 

  536. <p>These memory models are formally defined in Appendix D of the SPARC-V9

  537. architecture manual, as set in the processor&rsquo;s <code>PSTATE.MM</code> field.

  538. </p>

  539. </dd>

  540. <dt><code>-mstack-bias</code></dt>

  541. <dt><code>-mno-stack-bias</code></dt>

  542. <dd><a name="index-mstack_002dbias"></a>

  543. <a name="index-mno_002dstack_002dbias"></a>

  544. <p>With <samp>-mstack-bias</samp>, GCC assumes that the stack pointer, and

  545. frame pointer if present, are offset by -2047 which must be added back

  546. when making stack frame references.  This is the default in 64-bit mode.

  547. Otherwise, assume no such offset is present.

  548. </p></dd>

  549. </dl>

  550. 

  551. <hr>

  552. <div class="header">

  553. <p>

  554. Next: <a href="System-V-Options.html#System-V-Options" accesskey="n" rel="next">System V Options</a>, Previous: <a href="Solaris-2-Options.html#Solaris-2-Options" accesskey="p" rel="prev">Solaris 2 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  555. </div>

  556. 

  557. 

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