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toolchain-gcc-arm-embedded/share/doc/gcc-arm-none-eabi/html/gcc/x86-Options.html

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  35. <link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">

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  70. <a name="x86-Options"></a>

  71. <div class="header">

  72. <p>

  73. Next: <a href="x86-Windows-Options.html#x86-Windows-Options" accesskey="n" rel="next">x86 Windows Options</a>, Previous: <a href="VxWorks-Options.html#VxWorks-Options" accesskey="p" rel="prev">VxWorks Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="x86-Options-1"></a>

  77. <h4 class="subsection">3.19.59 x86 Options</h4>

  78. <a name="index-x86-Options"></a>

  79. 

  80. <p>These &lsquo;<samp>-m</samp>&rsquo; options are defined for the x86 family of computers.

  81. </p>

  82. <dl compact="compact">

  83. <dt><code>-march=<var>cpu-type</var></code></dt>

  84. <dd><a name="index-march-14"></a>

  85. <p>Generate instructions for the machine type <var>cpu-type</var>.  In contrast to

  86. <samp>-mtune=<var>cpu-type</var></samp>, which merely tunes the generated code 

  87. for the specified <var>cpu-type</var>, <samp>-march=<var>cpu-type</var></samp> allows GCC

  88. to generate code that may not run at all on processors other than the one

  89. indicated.  Specifying <samp>-march=<var>cpu-type</var></samp> implies 

  90. <samp>-mtune=<var>cpu-type</var></samp>.

  91. </p>

  92. <p>The choices for <var>cpu-type</var> are:

  93. </p>

  94. <dl compact="compact">

  95. <dt>&lsquo;<samp>native</samp>&rsquo;</dt>

  96. <dd><p>This selects the CPU to generate code for at compilation time by determining

  97. the processor type of the compiling machine.  Using <samp>-march=native</samp>

  98. enables all instruction subsets supported by the local machine (hence

  99. the result might not run on different machines).  Using <samp>-mtune=native</samp>

  100. produces code optimized for the local machine under the constraints

  101. of the selected instruction set.  

  102. </p>

  103. </dd>

  104. <dt>&lsquo;<samp>x86-64</samp>&rsquo;</dt>

  105. <dd><p>A generic CPU with 64-bit extensions.

  106. </p>

  107. </dd>

  108. <dt>&lsquo;<samp>i386</samp>&rsquo;</dt>

  109. <dd><p>Original Intel i386 CPU.

  110. </p>

  111. </dd>

  112. <dt>&lsquo;<samp>i486</samp>&rsquo;</dt>

  113. <dd><p>Intel i486 CPU.  (No scheduling is implemented for this chip.)

  114. </p>

  115. </dd>

  116. <dt>&lsquo;<samp>i586</samp>&rsquo;</dt>

  117. <dt>&lsquo;<samp>pentium</samp>&rsquo;</dt>

  118. <dd><p>Intel Pentium CPU with no MMX support.

  119. </p>

  120. </dd>

  121. <dt>&lsquo;<samp>lakemont</samp>&rsquo;</dt>

  122. <dd><p>Intel Lakemont MCU, based on Intel Pentium CPU.

  123. </p>

  124. </dd>

  125. <dt>&lsquo;<samp>pentium-mmx</samp>&rsquo;</dt>

  126. <dd><p>Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.

  127. </p>

  128. </dd>

  129. <dt>&lsquo;<samp>pentiumpro</samp>&rsquo;</dt>

  130. <dd><p>Intel Pentium Pro CPU.

  131. </p>

  132. </dd>

  133. <dt>&lsquo;<samp>i686</samp>&rsquo;</dt>

  134. <dd><p>When used with <samp>-march</samp>, the Pentium Pro

  135. instruction set is used, so the code runs on all i686 family chips.

  136. When used with <samp>-mtune</samp>, it has the same meaning as &lsquo;<samp>generic</samp>&rsquo;.

  137. </p>

  138. </dd>

  139. <dt>&lsquo;<samp>pentium2</samp>&rsquo;</dt>

  140. <dd><p>Intel Pentium II CPU, based on Pentium Pro core with MMX instruction set

  141. support.

  142. </p>

  143. </dd>

  144. <dt>&lsquo;<samp>pentium3</samp>&rsquo;</dt>

  145. <dt>&lsquo;<samp>pentium3m</samp>&rsquo;</dt>

  146. <dd><p>Intel Pentium III CPU, based on Pentium Pro core with MMX and SSE instruction

  147. set support.

  148. </p>

  149. </dd>

  150. <dt>&lsquo;<samp>pentium-m</samp>&rsquo;</dt>

  151. <dd><p>Intel Pentium M; low-power version of Intel Pentium III CPU

  152. with MMX, SSE and SSE2 instruction set support.  Used by Centrino notebooks.

  153. </p>

  154. </dd>

  155. <dt>&lsquo;<samp>pentium4</samp>&rsquo;</dt>

  156. <dt>&lsquo;<samp>pentium4m</samp>&rsquo;</dt>

  157. <dd><p>Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set support.

  158. </p>

  159. </dd>

  160. <dt>&lsquo;<samp>prescott</samp>&rsquo;</dt>

  161. <dd><p>Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2 and SSE3 instruction

  162. set support.

  163. </p>

  164. </dd>

  165. <dt>&lsquo;<samp>nocona</samp>&rsquo;</dt>

  166. <dd><p>Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE,

  167. SSE2 and SSE3 instruction set support.

  168. </p>

  169. </dd>

  170. <dt>&lsquo;<samp>core2</samp>&rsquo;</dt>

  171. <dd><p>Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3

  172. instruction set support.

  173. </p>

  174. </dd>

  175. <dt>&lsquo;<samp>nehalem</samp>&rsquo;</dt>

  176. <dd><p>Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,

  177. SSE4.1, SSE4.2 and POPCNT instruction set support.

  178. </p>

  179. </dd>

  180. <dt>&lsquo;<samp>westmere</samp>&rsquo;</dt>

  181. <dd><p>Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,

  182. SSE4.1, SSE4.2, POPCNT, AES and PCLMUL instruction set support.

  183. </p>

  184. </dd>

  185. <dt>&lsquo;<samp>sandybridge</samp>&rsquo;</dt>

  186. <dd><p>Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,

  187. SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.

  188. </p>

  189. </dd>

  190. <dt>&lsquo;<samp>ivybridge</samp>&rsquo;</dt>

  191. <dd><p>Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,

  192. SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C

  193. instruction set support.

  194. </p>

  195. </dd>

  196. <dt>&lsquo;<samp>haswell</samp>&rsquo;</dt>

  197. <dd><p>Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  198. SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,

  199. BMI, BMI2 and F16C instruction set support.

  200. </p>

  201. </dd>

  202. <dt>&lsquo;<samp>broadwell</samp>&rsquo;</dt>

  203. <dd><p>Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  204. SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,

  205. BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.

  206. </p>

  207. </dd>

  208. <dt>&lsquo;<samp>skylake</samp>&rsquo;</dt>

  209. <dd><p>Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  210. SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,

  211. BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and

  212. XSAVES instruction set support.

  213. </p>

  214. </dd>

  215. <dt>&lsquo;<samp>bonnell</samp>&rsquo;</dt>

  216. <dd><p>Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3

  217. instruction set support.

  218. </p>

  219. </dd>

  220. <dt>&lsquo;<samp>silvermont</samp>&rsquo;</dt>

  221. <dd><p>Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  222. SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.

  223. </p>

  224. </dd>

  225. <dt>&lsquo;<samp>goldmont</samp>&rsquo;</dt>

  226. <dd><p>Intel Goldmont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  227. SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT and FSGSBASE

  228. instruction set support.

  229. </p>

  230. </dd>

  231. <dt>&lsquo;<samp>goldmont-plus</samp>&rsquo;</dt>

  232. <dd><p>Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,

  233. SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE,

  234. PTWRITE, RDPID, SGX and UMIP instruction set support.

  235. </p>

  236. </dd>

  237. <dt>&lsquo;<samp>tremont</samp>&rsquo;</dt>

  238. <dd><p>Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  239. SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE,

  240. RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV instruction set support.

  241. </p>

  242. </dd>

  243. <dt>&lsquo;<samp>knl</samp>&rsquo;</dt>

  244. <dd><p>Intel Knight&rsquo;s Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,

  245. SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,

  246. BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and

  247. AVX512CD instruction set support.

  248. </p>

  249. </dd>

  250. <dt>&lsquo;<samp>knm</samp>&rsquo;</dt>

  251. <dd><p>Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,

  252. SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,

  253. BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER, AVX512CD,

  254. AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.

  255. </p>

  256. </dd>

  257. <dt>&lsquo;<samp>skylake-avx512</samp>&rsquo;</dt>

  258. <dd><p>Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,

  259. SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,

  260. BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,

  261. CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.

  262. </p>

  263. </dd>

  264. <dt>&lsquo;<samp>cannonlake</samp>&rsquo;</dt>

  265. <dd><p>Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,

  266. SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,

  267. RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,

  268. XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,

  269. AVX512IFMA, SHA and UMIP instruction set support.

  270. </p>

  271. </dd>

  272. <dt>&lsquo;<samp>icelake-client</samp>&rsquo;</dt>

  273. <dd><p>Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,

  274. SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,

  275. RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,

  276. XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,

  277. AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,

  278. AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.

  279. </p>

  280. </dd>

  281. <dt>&lsquo;<samp>icelake-server</samp>&rsquo;</dt>

  282. <dd><p>Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,

  283. SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,

  284. RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,

  285. XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,

  286. AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,

  287. AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction

  288. set support.

  289. </p>

  290. </dd>

  291. <dt>&lsquo;<samp>cascadelake</samp>&rsquo;</dt>

  292. <dd><p>Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  293. SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,

  294. BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,

  295. AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.

  296. </p>

  297. </dd>

  298. <dt>&lsquo;<samp>cooperlake</samp>&rsquo;</dt>

  299. <dd><p>Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  300. SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,

  301. BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,

  302. AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction

  303. set support.

  304. </p>

  305. </dd>

  306. <dt>&lsquo;<samp>tigerlake</samp>&rsquo;</dt>

  307. <dd><p>Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,

  308. SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,

  309. BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,

  310. AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,

  311. RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,

  312. VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and  AVX512VP2INTERSECT instruction

  313. set support.

  314. </p>

  315. </dd>

  316. <dt>&lsquo;<samp>k6</samp>&rsquo;</dt>

  317. <dd><p>AMD K6 CPU with MMX instruction set support.

  318. </p>

  319. </dd>

  320. <dt>&lsquo;<samp>k6-2</samp>&rsquo;</dt>

  321. <dt>&lsquo;<samp>k6-3</samp>&rsquo;</dt>

  322. <dd><p>Improved versions of AMD K6 CPU with MMX and 3DNow! instruction set support.

  323. </p>

  324. </dd>

  325. <dt>&lsquo;<samp>athlon</samp>&rsquo;</dt>

  326. <dt>&lsquo;<samp>athlon-tbird</samp>&rsquo;</dt>

  327. <dd><p>AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow! and SSE prefetch instructions

  328. support.

  329. </p>

  330. </dd>

  331. <dt>&lsquo;<samp>athlon-4</samp>&rsquo;</dt>

  332. <dt>&lsquo;<samp>athlon-xp</samp>&rsquo;</dt>

  333. <dt>&lsquo;<samp>athlon-mp</samp>&rsquo;</dt>

  334. <dd><p>Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow! and full SSE

  335. instruction set support.

  336. </p>

  337. </dd>

  338. <dt>&lsquo;<samp>k8</samp>&rsquo;</dt>

  339. <dt>&lsquo;<samp>opteron</samp>&rsquo;</dt>

  340. <dt>&lsquo;<samp>athlon64</samp>&rsquo;</dt>

  341. <dt>&lsquo;<samp>athlon-fx</samp>&rsquo;</dt>

  342. <dd><p>Processors based on the AMD K8 core with x86-64 instruction set support,

  343. including the AMD Opteron, Athlon 64, and Athlon 64 FX processors.

  344. (This supersets MMX, SSE, SSE2, 3DNow!, enhanced 3DNow! and 64-bit

  345. instruction set extensions.)

  346. </p>

  347. </dd>

  348. <dt>&lsquo;<samp>k8-sse3</samp>&rsquo;</dt>

  349. <dt>&lsquo;<samp>opteron-sse3</samp>&rsquo;</dt>

  350. <dt>&lsquo;<samp>athlon64-sse3</samp>&rsquo;</dt>

  351. <dd><p>Improved versions of AMD K8 cores with SSE3 instruction set support.

  352. </p>

  353. </dd>

  354. <dt>&lsquo;<samp>amdfam10</samp>&rsquo;</dt>

  355. <dt>&lsquo;<samp>barcelona</samp>&rsquo;</dt>

  356. <dd><p>CPUs based on AMD Family 10h cores with x86-64 instruction set support.  (This

  357. supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit

  358. instruction set extensions.)

  359. </p>

  360. </dd>

  361. <dt>&lsquo;<samp>bdver1</samp>&rsquo;</dt>

  362. <dd><p>CPUs based on AMD Family 15h cores with x86-64 instruction set support.  (This

  363. supersets FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,

  364. SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)

  365. </p>

  366. </dd>

  367. <dt>&lsquo;<samp>bdver2</samp>&rsquo;</dt>

  368. <dd><p>AMD Family 15h core based CPUs with x86-64 instruction set support.  (This

  369. supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCLMUL, CX16, MMX,

  370. SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set 

  371. extensions.)

  372. </p>

  373. </dd>

  374. <dt>&lsquo;<samp>bdver3</samp>&rsquo;</dt>

  375. <dd><p>AMD Family 15h core based CPUs with x86-64 instruction set support.  (This

  376. supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES, 

  377. PCLMUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and

  378. 64-bit instruction set extensions.)

  379. </p>

  380. </dd>

  381. <dt>&lsquo;<samp>bdver4</samp>&rsquo;</dt>

  382. <dd><p>AMD Family 15h core based CPUs with x86-64 instruction set support.  (This

  383. supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, 

  384. AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,

  385. SSE4.2, ABM and 64-bit instruction set extensions.)

  386. </p>

  387. </dd>

  388. <dt>&lsquo;<samp>znver1</samp>&rsquo;</dt>

  389. <dd><p>AMD Family 17h core based CPUs with x86-64 instruction set support.  (This

  390. supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX,

  391. SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3,

  392. SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit

  393. instruction set extensions.)

  394. </p>

  395. </dd>

  396. <dt>&lsquo;<samp>znver2</samp>&rsquo;</dt>

  397. <dd><p>AMD Family 17h core based CPUs with x86-64 instruction set support. (This

  398. supersets BMI, BMI2, CLWB, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED,

  399. MWAITX, SHA, CLZERO, AES, PCLMUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,

  400. SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, RDPID,

  401. WBNOINVD, and 64-bit instruction set extensions.)

  402. </p>

  403. </dd>

  404. <dt>&lsquo;<samp>btver1</samp>&rsquo;</dt>

  405. <dd><p>CPUs based on AMD Family 14h cores with x86-64 instruction set support.  (This

  406. supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit

  407. instruction set extensions.)

  408. </p>

  409. </dd>

  410. <dt>&lsquo;<samp>btver2</samp>&rsquo;</dt>

  411. <dd><p>CPUs based on AMD Family 16h cores with x86-64 instruction set support. This

  412. includes MOVBE, F16C, BMI, AVX, PCLMUL, AES, SSE4.2, SSE4.1, CX16, ABM,

  413. SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.

  414. </p>

  415. </dd>

  416. <dt>&lsquo;<samp>winchip-c6</samp>&rsquo;</dt>

  417. <dd><p>IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction

  418. set support.

  419. </p>

  420. </dd>

  421. <dt>&lsquo;<samp>winchip2</samp>&rsquo;</dt>

  422. <dd><p>IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow!

  423. instruction set support.

  424. </p>

  425. </dd>

  426. <dt>&lsquo;<samp>c3</samp>&rsquo;</dt>

  427. <dd><p>VIA C3 CPU with MMX and 3DNow! instruction set support.

  428. (No scheduling is implemented for this chip.)

  429. </p>

  430. </dd>

  431. <dt>&lsquo;<samp>c3-2</samp>&rsquo;</dt>

  432. <dd><p>VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support.

  433. (No scheduling is implemented for this chip.)

  434. </p>

  435. </dd>

  436. <dt>&lsquo;<samp>c7</samp>&rsquo;</dt>

  437. <dd><p>VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support.

  438. (No scheduling is implemented for this chip.)

  439. </p>

  440. </dd>

  441. <dt>&lsquo;<samp>samuel-2</samp>&rsquo;</dt>

  442. <dd><p>VIA Eden Samuel 2 CPU with MMX and 3DNow! instruction set support.

  443. (No scheduling is implemented for this chip.)

  444. </p>

  445. </dd>

  446. <dt>&lsquo;<samp>nehemiah</samp>&rsquo;</dt>

  447. <dd><p>VIA Eden Nehemiah CPU with MMX and SSE instruction set support.

  448. (No scheduling is implemented for this chip.)

  449. </p>

  450. </dd>

  451. <dt>&lsquo;<samp>esther</samp>&rsquo;</dt>

  452. <dd><p>VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support.

  453. (No scheduling is implemented for this chip.)

  454. </p>

  455. </dd>

  456. <dt>&lsquo;<samp>eden-x2</samp>&rsquo;</dt>

  457. <dd><p>VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support.

  458. (No scheduling is implemented for this chip.)

  459. </p>

  460. </dd>

  461. <dt>&lsquo;<samp>eden-x4</samp>&rsquo;</dt>

  462. <dd><p>VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,

  463. AVX and AVX2 instruction set support.

  464. (No scheduling is implemented for this chip.)

  465. </p>

  466. </dd>

  467. <dt>&lsquo;<samp>nano</samp>&rsquo;</dt>

  468. <dd><p>Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3

  469. instruction set support.

  470. (No scheduling is implemented for this chip.)

  471. </p>

  472. </dd>

  473. <dt>&lsquo;<samp>nano-1000</samp>&rsquo;</dt>

  474. <dd><p>VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3

  475. instruction set support.

  476. (No scheduling is implemented for this chip.)

  477. </p>

  478. </dd>

  479. <dt>&lsquo;<samp>nano-2000</samp>&rsquo;</dt>

  480. <dd><p>VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3

  481. instruction set support.

  482. (No scheduling is implemented for this chip.)

  483. </p>

  484. </dd>

  485. <dt>&lsquo;<samp>nano-3000</samp>&rsquo;</dt>

  486. <dd><p>VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1

  487. instruction set support.

  488. (No scheduling is implemented for this chip.)

  489. </p>

  490. </dd>

  491. <dt>&lsquo;<samp>nano-x2</samp>&rsquo;</dt>

  492. <dd><p>VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1

  493. instruction set support.

  494. (No scheduling is implemented for this chip.)

  495. </p>

  496. </dd>

  497. <dt>&lsquo;<samp>nano-x4</samp>&rsquo;</dt>

  498. <dd><p>VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1

  499. instruction set support.

  500. (No scheduling is implemented for this chip.)

  501. </p>

  502. </dd>

  503. <dt>&lsquo;<samp>geode</samp>&rsquo;</dt>

  504. <dd><p>AMD Geode embedded processor with MMX and 3DNow! instruction set support.

  505. </p></dd>

  506. </dl>

  507. 

  508. </dd>

  509. <dt><code>-mtune=<var>cpu-type</var></code></dt>

  510. <dd><a name="index-mtune-16"></a>

  511. <p>Tune to <var>cpu-type</var> everything applicable about the generated code, except

  512. for the ABI and the set of available instructions.  

  513. While picking a specific <var>cpu-type</var> schedules things appropriately

  514. for that particular chip, the compiler does not generate any code that

  515. cannot run on the default machine type unless you use a

  516. <samp>-march=<var>cpu-type</var></samp> option.

  517. For example, if GCC is configured for i686-pc-linux-gnu

  518. then <samp>-mtune=pentium4</samp> generates code that is tuned for Pentium 4

  519. but still runs on i686 machines.

  520. </p>

  521. <p>The choices for <var>cpu-type</var> are the same as for <samp>-march</samp>.

  522. In addition, <samp>-mtune</samp> supports 2 extra choices for <var>cpu-type</var>:

  523. </p>

  524. <dl compact="compact">

  525. <dt>&lsquo;<samp>generic</samp>&rsquo;</dt>

  526. <dd><p>Produce code optimized for the most common IA32/AMD64/EM64T processors.

  527. If you know the CPU on which your code will run, then you should use

  528. the corresponding <samp>-mtune</samp> or <samp>-march</samp> option instead of

  529. <samp>-mtune=generic</samp>.  But, if you do not know exactly what CPU users

  530. of your application will have, then you should use this option.

  531. </p>

  532. <p>As new processors are deployed in the marketplace, the behavior of this

  533. option will change.  Therefore, if you upgrade to a newer version of

  534. GCC, code generation controlled by this option will change to reflect

  535. the processors

  536. that are most common at the time that version of GCC is released.

  537. </p>

  538. <p>There is no <samp>-march=generic</samp> option because <samp>-march</samp>

  539. indicates the instruction set the compiler can use, and there is no

  540. generic instruction set applicable to all processors.  In contrast,

  541. <samp>-mtune</samp> indicates the processor (or, in this case, collection of

  542. processors) for which the code is optimized.

  543. </p>

  544. </dd>

  545. <dt>&lsquo;<samp>intel</samp>&rsquo;</dt>

  546. <dd><p>Produce code optimized for the most current Intel processors, which are

  547. Haswell and Silvermont for this version of GCC.  If you know the CPU

  548. on which your code will run, then you should use the corresponding

  549. <samp>-mtune</samp> or <samp>-march</samp> option instead of <samp>-mtune=intel</samp>.

  550. But, if you want your application performs better on both Haswell and

  551. Silvermont, then you should use this option.

  552. </p>

  553. <p>As new Intel processors are deployed in the marketplace, the behavior of

  554. this option will change.  Therefore, if you upgrade to a newer version of

  555. GCC, code generation controlled by this option will change to reflect

  556. the most current Intel processors at the time that version of GCC is

  557. released.

  558. </p>

  559. <p>There is no <samp>-march=intel</samp> option because <samp>-march</samp> indicates

  560. the instruction set the compiler can use, and there is no common

  561. instruction set applicable to all processors.  In contrast,

  562. <samp>-mtune</samp> indicates the processor (or, in this case, collection of

  563. processors) for which the code is optimized.

  564. </p></dd>

  565. </dl>

  566. 

  567. </dd>

  568. <dt><code>-mcpu=<var>cpu-type</var></code></dt>

  569. <dd><a name="index-mcpu-15"></a>

  570. <p>A deprecated synonym for <samp>-mtune</samp>.

  571. </p>

  572. </dd>

  573. <dt><code>-mfpmath=<var>unit</var></code></dt>

  574. <dd><a name="index-mfpmath-1"></a>

  575. <p>Generate floating-point arithmetic for selected unit <var>unit</var>.  The choices

  576. for <var>unit</var> are:

  577. </p>

  578. <dl compact="compact">

  579. <dt>&lsquo;<samp>387</samp>&rsquo;</dt>

  580. <dd><p>Use the standard 387 floating-point coprocessor present on the majority of chips and

  581. emulated otherwise.  Code compiled with this option runs almost everywhere.

  582. The temporary results are computed in 80-bit precision instead of the precision

  583. specified by the type, resulting in slightly different results compared to most

  584. of other chips.  See <samp>-ffloat-store</samp> for more detailed description.

  585. </p>

  586. <p>This is the default choice for non-Darwin x86-32 targets.

  587. </p>

  588. </dd>

  589. <dt>&lsquo;<samp>sse</samp>&rsquo;</dt>

  590. <dd><p>Use scalar floating-point instructions present in the SSE instruction set.

  591. This instruction set is supported by Pentium III and newer chips,

  592. and in the AMD line

  593. by Athlon-4, Athlon XP and Athlon MP chips.  The earlier version of the SSE

  594. instruction set supports only single-precision arithmetic, thus the double and

  595. extended-precision arithmetic are still done using 387.  A later version, present

  596. only in Pentium 4 and AMD x86-64 chips, supports double-precision

  597. arithmetic too.

  598. </p>

  599. <p>For the x86-32 compiler, you must use <samp>-march=<var>cpu-type</var></samp>, <samp>-msse</samp>

  600. or <samp>-msse2</samp> switches to enable SSE extensions and make this option

  601. effective.  For the x86-64 compiler, these extensions are enabled by default.

  602. </p>

  603. <p>The resulting code should be considerably faster in the majority of cases and avoid

  604. the numerical instability problems of 387 code, but may break some existing

  605. code that expects temporaries to be 80 bits.

  606. </p>

  607. <p>This is the default choice for the x86-64 compiler, Darwin x86-32 targets,

  608. and the default choice for x86-32 targets with the SSE2 instruction set

  609. when <samp>-ffast-math</samp> is enabled.

  610. </p>

  611. </dd>

  612. <dt>&lsquo;<samp>sse,387</samp>&rsquo;</dt>

  613. <dt>&lsquo;<samp>sse+387</samp>&rsquo;</dt>

  614. <dt>&lsquo;<samp>both</samp>&rsquo;</dt>

  615. <dd><p>Attempt to utilize both instruction sets at once.  This effectively doubles the

  616. amount of available registers, and on chips with separate execution units for

  617. 387 and SSE the execution resources too.  Use this option with care, as it is

  618. still experimental, because the GCC register allocator does not model separate

  619. functional units well, resulting in unstable performance.

  620. </p></dd>

  621. </dl>

  622. 

  623. </dd>

  624. <dt><code>-masm=<var>dialect</var></code></dt>

  625. <dd><a name="index-masm_003ddialect"></a>

  626. <p>Output assembly instructions using selected <var>dialect</var>.  Also affects

  627. which dialect is used for basic <code>asm</code> (see <a href="Basic-Asm.html#Basic-Asm">Basic Asm</a>) and

  628. extended <code>asm</code> (see <a href="Extended-Asm.html#Extended-Asm">Extended Asm</a>). Supported choices (in dialect

  629. order) are &lsquo;<samp>att</samp>&rsquo; or &lsquo;<samp>intel</samp>&rsquo;. The default is &lsquo;<samp>att</samp>&rsquo;. Darwin does

  630. not support &lsquo;<samp>intel</samp>&rsquo;.

  631. </p>

  632. </dd>

  633. <dt><code>-mieee-fp</code></dt>

  634. <dt><code>-mno-ieee-fp</code></dt>

  635. <dd><a name="index-mieee_002dfp"></a>

  636. <a name="index-mno_002dieee_002dfp"></a>

  637. <p>Control whether or not the compiler uses IEEE floating-point

  638. comparisons.  These correctly handle the case where the result of a

  639. comparison is unordered.

  640. </p>

  641. </dd>

  642. <dt><code>-m80387</code></dt>

  643. <dt><code>-mhard-float</code></dt>

  644. <dd><a name="index-80387"></a>

  645. <a name="index-mhard_002dfloat-11"></a>

  646. <p>Generate output containing 80387 instructions for floating point.

  647. </p>

  648. </dd>

  649. <dt><code>-mno-80387</code></dt>

  650. <dt><code>-msoft-float</code></dt>

  651. <dd><a name="index-no_002d80387"></a>

  652. <a name="index-msoft_002dfloat-15"></a>

  653. <p>Generate output containing library calls for floating point.

  654. </p>

  655. <p><strong>Warning:</strong> the requisite libraries are not part of GCC.

  656. Normally the facilities of the machine&rsquo;s usual C compiler are used, but

  657. this cannot be done directly in cross-compilation.  You must make your

  658. own arrangements to provide suitable library functions for

  659. cross-compilation.

  660. </p>

  661. <p>On machines where a function returns floating-point results in the 80387

  662. register stack, some floating-point opcodes may be emitted even if

  663. <samp>-msoft-float</samp> is used.

  664. </p>

  665. </dd>

  666. <dt><code>-mno-fp-ret-in-387</code></dt>

  667. <dd><a name="index-mno_002dfp_002dret_002din_002d387"></a>

  668. <a name="index-mfp_002dret_002din_002d387"></a>

  669. <p>Do not use the FPU registers for return values of functions.

  670. </p>

  671. <p>The usual calling convention has functions return values of types

  672. <code>float</code> and <code>double</code> in an FPU register, even if there

  673. is no FPU.  The idea is that the operating system should emulate

  674. an FPU.

  675. </p>

  676. <p>The option <samp>-mno-fp-ret-in-387</samp> causes such values to be returned

  677. in ordinary CPU registers instead.

  678. </p>

  679. </dd>

  680. <dt><code>-mno-fancy-math-387</code></dt>

  681. <dd><a name="index-mno_002dfancy_002dmath_002d387"></a>

  682. <a name="index-mfancy_002dmath_002d387"></a>

  683. <p>Some 387 emulators do not support the <code>sin</code>, <code>cos</code> and

  684. <code>sqrt</code> instructions for the 387.  Specify this option to avoid

  685. generating those instructions.

  686. This option is overridden when <samp>-march</samp>

  687. indicates that the target CPU always has an FPU and so the

  688. instruction does not need emulation.  These

  689. instructions are not generated unless you also use the

  690. <samp>-funsafe-math-optimizations</samp> switch.

  691. </p>

  692. </dd>

  693. <dt><code>-malign-double</code></dt>

  694. <dt><code>-mno-align-double</code></dt>

  695. <dd><a name="index-malign_002ddouble"></a>

  696. <a name="index-mno_002dalign_002ddouble"></a>

  697. <p>Control whether GCC aligns <code>double</code>, <code>long double</code>, and

  698. <code>long long</code> variables on a two-word boundary or a one-word

  699. boundary.  Aligning <code>double</code> variables on a two-word boundary

  700. produces code that runs somewhat faster on a Pentium at the

  701. expense of more memory.

  702. </p>

  703. <p>On x86-64, <samp>-malign-double</samp> is enabled by default.

  704. </p>

  705. <p><strong>Warning:</strong> if you use the <samp>-malign-double</samp> switch,

  706. structures containing the above types are aligned differently than

  707. the published application binary interface specifications for the x86-32

  708. and are not binary compatible with structures in code compiled

  709. without that switch.

  710. </p>

  711. </dd>

  712. <dt><code>-m96bit-long-double</code></dt>

  713. <dt><code>-m128bit-long-double</code></dt>

  714. <dd><a name="index-m96bit_002dlong_002ddouble"></a>

  715. <a name="index-m128bit_002dlong_002ddouble"></a>

  716. <p>These switches control the size of <code>long double</code> type.  The x86-32

  717. application binary interface specifies the size to be 96 bits,

  718. so <samp>-m96bit-long-double</samp> is the default in 32-bit mode.

  719. </p>

  720. <p>Modern architectures (Pentium and newer) prefer <code>long double</code>

  721. to be aligned to an 8- or 16-byte boundary.  In arrays or structures

  722. conforming to the ABI, this is not possible.  So specifying

  723. <samp>-m128bit-long-double</samp> aligns <code>long double</code>

  724. to a 16-byte boundary by padding the <code>long double</code> with an additional

  725. 32-bit zero.

  726. </p>

  727. <p>In the x86-64 compiler, <samp>-m128bit-long-double</samp> is the default choice as

  728. its ABI specifies that <code>long double</code> is aligned on 16-byte boundary.

  729. </p>

  730. <p>Notice that neither of these options enable any extra precision over the x87

  731. standard of 80 bits for a <code>long double</code>.

  732. </p>

  733. <p><strong>Warning:</strong> if you override the default value for your target ABI, this

  734. changes the size of 

  735. structures and arrays containing <code>long double</code> variables,

  736. as well as modifying the function calling convention for functions taking

  737. <code>long double</code>.  Hence they are not binary-compatible

  738. with code compiled without that switch.

  739. </p>

  740. </dd>

  741. <dt><code>-mlong-double-64</code></dt>

  742. <dt><code>-mlong-double-80</code></dt>

  743. <dt><code>-mlong-double-128</code></dt>

  744. <dd><a name="index-mlong_002ddouble_002d64-1"></a>

  745. <a name="index-mlong_002ddouble_002d80"></a>

  746. <a name="index-mlong_002ddouble_002d128-1"></a>

  747. <p>These switches control the size of <code>long double</code> type. A size

  748. of 64 bits makes the <code>long double</code> type equivalent to the <code>double</code>

  749. type. This is the default for 32-bit Bionic C library.  A size

  750. of 128 bits makes the <code>long double</code> type equivalent to the

  751. <code>__float128</code> type. This is the default for 64-bit Bionic C library.

  752. </p>

  753. <p><strong>Warning:</strong> if you override the default value for your target ABI, this

  754. changes the size of

  755. structures and arrays containing <code>long double</code> variables,

  756. as well as modifying the function calling convention for functions taking

  757. <code>long double</code>.  Hence they are not binary-compatible

  758. with code compiled without that switch.

  759. </p>

  760. </dd>

  761. <dt><code>-malign-data=<var>type</var></code></dt>

  762. <dd><a name="index-malign_002ddata-1"></a>

  763. <p>Control how GCC aligns variables.  Supported values for <var>type</var> are

  764. &lsquo;<samp>compat</samp>&rsquo; uses increased alignment value compatible uses GCC 4.8

  765. and earlier, &lsquo;<samp>abi</samp>&rsquo; uses alignment value as specified by the

  766. psABI, and &lsquo;<samp>cacheline</samp>&rsquo; uses increased alignment value to match

  767. the cache line size.  &lsquo;<samp>compat</samp>&rsquo; is the default.

  768. </p>

  769. </dd>

  770. <dt><code>-mlarge-data-threshold=<var>threshold</var></code></dt>

  771. <dd><a name="index-mlarge_002ddata_002dthreshold"></a>

  772. <p>When <samp>-mcmodel=medium</samp> is specified, data objects larger than

  773. <var>threshold</var> are placed in the large data section.  This value must be the

  774. same across all objects linked into the binary, and defaults to 65535.

  775. </p>

  776. </dd>

  777. <dt><code>-mrtd</code></dt>

  778. <dd><a name="index-mrtd-1"></a>

  779. <p>Use a different function-calling convention, in which functions that

  780. take a fixed number of arguments return with the <code>ret <var>num</var></code>

  781. instruction, which pops their arguments while returning.  This saves one

  782. instruction in the caller since there is no need to pop the arguments

  783. there.

  784. </p>

  785. <p>You can specify that an individual function is called with this calling

  786. sequence with the function attribute <code>stdcall</code>.  You can also

  787. override the <samp>-mrtd</samp> option by using the function attribute

  788. <code>cdecl</code>.  See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>.

  789. </p>

  790. <p><strong>Warning:</strong> this calling convention is incompatible with the one

  791. normally used on Unix, so you cannot use it if you need to call

  792. libraries compiled with the Unix compiler.

  793. </p>

  794. <p>Also, you must provide function prototypes for all functions that

  795. take variable numbers of arguments (including <code>printf</code>);

  796. otherwise incorrect code is generated for calls to those

  797. functions.

  798. </p>

  799. <p>In addition, seriously incorrect code results if you call a

  800. function with too many arguments.  (Normally, extra arguments are

  801. harmlessly ignored.)

  802. </p>

  803. </dd>

  804. <dt><code>-mregparm=<var>num</var></code></dt>

  805. <dd><a name="index-mregparm"></a>

  806. <p>Control how many registers are used to pass integer arguments.  By

  807. default, no registers are used to pass arguments, and at most 3

  808. registers can be used.  You can control this behavior for a specific

  809. function by using the function attribute <code>regparm</code>.

  810. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>.

  811. </p>

  812. <p><strong>Warning:</strong> if you use this switch, and

  813. <var>num</var> is nonzero, then you must build all modules with the same

  814. value, including any libraries.  This includes the system libraries and

  815. startup modules.

  816. </p>

  817. </dd>

  818. <dt><code>-msseregparm</code></dt>

  819. <dd><a name="index-msseregparm"></a>

  820. <p>Use SSE register passing conventions for float and double arguments

  821. and return values.  You can control this behavior for a specific

  822. function by using the function attribute <code>sseregparm</code>.

  823. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>.

  824. </p>

  825. <p><strong>Warning:</strong> if you use this switch then you must build all

  826. modules with the same value, including any libraries.  This includes

  827. the system libraries and startup modules.

  828. </p>

  829. </dd>

  830. <dt><code>-mvect8-ret-in-mem</code></dt>

  831. <dd><a name="index-mvect8_002dret_002din_002dmem"></a>

  832. <p>Return 8-byte vectors in memory instead of MMX registers.  This is the

  833. default on VxWorks to match the ABI of the Sun Studio compilers until

  834. version 12.  <em>Only</em> use this option if you need to remain

  835. compatible with existing code produced by those previous compiler

  836. versions or older versions of GCC.

  837. </p>

  838. </dd>

  839. <dt><code>-mpc32</code></dt>

  840. <dt><code>-mpc64</code></dt>

  841. <dt><code>-mpc80</code></dt>

  842. <dd><a name="index-mpc32"></a>

  843. <a name="index-mpc64"></a>

  844. <a name="index-mpc80"></a>

  845. 

  846. <p>Set 80387 floating-point precision to 32, 64 or 80 bits.  When <samp>-mpc32</samp>

  847. is specified, the significands of results of floating-point operations are

  848. rounded to 24 bits (single precision); <samp>-mpc64</samp> rounds the

  849. significands of results of floating-point operations to 53 bits (double

  850. precision) and <samp>-mpc80</samp> rounds the significands of results of

  851. floating-point operations to 64 bits (extended double precision), which is

  852. the default.  When this option is used, floating-point operations in higher

  853. precisions are not available to the programmer without setting the FPU

  854. control word explicitly.

  855. </p>

  856. <p>Setting the rounding of floating-point operations to less than the default

  857. 80 bits can speed some programs by 2% or more.  Note that some mathematical

  858. libraries assume that extended-precision (80-bit) floating-point operations

  859. are enabled by default; routines in such libraries could suffer significant

  860. loss of accuracy, typically through so-called &ldquo;catastrophic cancellation&rdquo;,

  861. when this option is used to set the precision to less than extended precision.

  862. </p>

  863. </dd>

  864. <dt><code>-mstackrealign</code></dt>

  865. <dd><a name="index-mstackrealign"></a>

  866. <p>Realign the stack at entry.  On the x86, the <samp>-mstackrealign</samp>

  867. option generates an alternate prologue and epilogue that realigns the

  868. run-time stack if necessary.  This supports mixing legacy codes that keep

  869. 4-byte stack alignment with modern codes that keep 16-byte stack alignment for

  870. SSE compatibility.  See also the attribute <code>force_align_arg_pointer</code>,

  871. applicable to individual functions.

  872. </p>

  873. </dd>

  874. <dt><code>-mpreferred-stack-boundary=<var>num</var></code></dt>

  875. <dd><a name="index-mpreferred_002dstack_002dboundary-1"></a>

  876. <p>Attempt to keep the stack boundary aligned to a 2 raised to <var>num</var>

  877. byte boundary.  If <samp>-mpreferred-stack-boundary</samp> is not specified,

  878. the default is 4 (16 bytes or 128 bits).

  879. </p>

  880. <p><strong>Warning:</strong> When generating code for the x86-64 architecture with

  881. SSE extensions disabled, <samp>-mpreferred-stack-boundary=3</samp> can be

  882. used to keep the stack boundary aligned to 8 byte boundary.  Since

  883. x86-64 ABI require 16 byte stack alignment, this is ABI incompatible and

  884. intended to be used in controlled environment where stack space is

  885. important limitation.  This option leads to wrong code when functions

  886. compiled with 16 byte stack alignment (such as functions from a standard

  887. library) are called with misaligned stack.  In this case, SSE

  888. instructions may lead to misaligned memory access traps.  In addition,

  889. variable arguments are handled incorrectly for 16 byte aligned

  890. objects (including x87 long double and __int128), leading to wrong

  891. results.  You must build all modules with

  892. <samp>-mpreferred-stack-boundary=3</samp>, including any libraries.  This

  893. includes the system libraries and startup modules.

  894. </p>

  895. </dd>

  896. <dt><code>-mincoming-stack-boundary=<var>num</var></code></dt>

  897. <dd><a name="index-mincoming_002dstack_002dboundary"></a>

  898. <p>Assume the incoming stack is aligned to a 2 raised to <var>num</var> byte

  899. boundary.  If <samp>-mincoming-stack-boundary</samp> is not specified,

  900. the one specified by <samp>-mpreferred-stack-boundary</samp> is used.

  901. </p>

  902. <p>On Pentium and Pentium Pro, <code>double</code> and <code>long double</code> values

  903. should be aligned to an 8-byte boundary (see <samp>-malign-double</samp>) or

  904. suffer significant run time performance penalties.  On Pentium III, the

  905. Streaming SIMD Extension (SSE) data type <code>__m128</code> may not work

  906. properly if it is not 16-byte aligned.

  907. </p>

  908. <p>To ensure proper alignment of this values on the stack, the stack boundary

  909. must be as aligned as that required by any value stored on the stack.

  910. Further, every function must be generated such that it keeps the stack

  911. aligned.  Thus calling a function compiled with a higher preferred

  912. stack boundary from a function compiled with a lower preferred stack

  913. boundary most likely misaligns the stack.  It is recommended that

  914. libraries that use callbacks always use the default setting.

  915. </p>

  916. <p>This extra alignment does consume extra stack space, and generally

  917. increases code size.  Code that is sensitive to stack space usage, such

  918. as embedded systems and operating system kernels, may want to reduce the

  919. preferred alignment to <samp>-mpreferred-stack-boundary=2</samp>.

  920. </p>

  921. </dd>

  922. <dt><code>-mmmx</code></dt>

  923. <dd><a name="index-mmmx"></a>

  924. </dd>

  925. <dt><code>-msse</code></dt>

  926. <dd><a name="index-msse"></a>

  927. </dd>

  928. <dt><code>-msse2</code></dt>

  929. <dd><a name="index-msse2"></a>

  930. </dd>

  931. <dt><code>-msse3</code></dt>

  932. <dd><a name="index-msse3"></a>

  933. </dd>

  934. <dt><code>-mssse3</code></dt>

  935. <dd><a name="index-mssse3"></a>

  936. </dd>

  937. <dt><code>-msse4</code></dt>

  938. <dd><a name="index-msse4"></a>

  939. </dd>

  940. <dt><code>-msse4a</code></dt>

  941. <dd><a name="index-msse4a"></a>

  942. </dd>

  943. <dt><code>-msse4.1</code></dt>

  944. <dd><a name="index-msse4_002e1"></a>

  945. </dd>

  946. <dt><code>-msse4.2</code></dt>

  947. <dd><a name="index-msse4_002e2"></a>

  948. </dd>

  949. <dt><code>-mavx</code></dt>

  950. <dd><a name="index-mavx"></a>

  951. </dd>

  952. <dt><code>-mavx2</code></dt>

  953. <dd><a name="index-mavx2"></a>

  954. </dd>

  955. <dt><code>-mavx512f</code></dt>

  956. <dd><a name="index-mavx512f"></a>

  957. </dd>

  958. <dt><code>-mavx512pf</code></dt>

  959. <dd><a name="index-mavx512pf"></a>

  960. </dd>

  961. <dt><code>-mavx512er</code></dt>

  962. <dd><a name="index-mavx512er"></a>

  963. </dd>

  964. <dt><code>-mavx512cd</code></dt>

  965. <dd><a name="index-mavx512cd"></a>

  966. </dd>

  967. <dt><code>-mavx512vl</code></dt>

  968. <dd><a name="index-mavx512vl"></a>

  969. </dd>

  970. <dt><code>-mavx512bw</code></dt>

  971. <dd><a name="index-mavx512bw"></a>

  972. </dd>

  973. <dt><code>-mavx512dq</code></dt>

  974. <dd><a name="index-mavx512dq"></a>

  975. </dd>

  976. <dt><code>-mavx512ifma</code></dt>

  977. <dd><a name="index-mavx512ifma"></a>

  978. </dd>

  979. <dt><code>-mavx512vbmi</code></dt>

  980. <dd><a name="index-mavx512vbmi"></a>

  981. </dd>

  982. <dt><code>-msha</code></dt>

  983. <dd><a name="index-msha"></a>

  984. </dd>

  985. <dt><code>-maes</code></dt>

  986. <dd><a name="index-maes"></a>

  987. </dd>

  988. <dt><code>-mpclmul</code></dt>

  989. <dd><a name="index-mpclmul"></a>

  990. </dd>

  991. <dt><code>-mclflushopt</code></dt>

  992. <dd><a name="index-mclflushopt"></a>

  993. </dd>

  994. <dt><code>-mclwb</code></dt>

  995. <dd><a name="index-mclwb"></a>

  996. </dd>

  997. <dt><code>-mfsgsbase</code></dt>

  998. <dd><a name="index-mfsgsbase"></a>

  999. </dd>

  1000. <dt><code>-mptwrite</code></dt>

  1001. <dd><a name="index-mptwrite"></a>

  1002. </dd>

  1003. <dt><code>-mrdrnd</code></dt>

  1004. <dd><a name="index-mrdrnd"></a>

  1005. </dd>

  1006. <dt><code>-mf16c</code></dt>

  1007. <dd><a name="index-mf16c"></a>

  1008. </dd>

  1009. <dt><code>-mfma</code></dt>

  1010. <dd><a name="index-mfma"></a>

  1011. </dd>

  1012. <dt><code>-mpconfig</code></dt>

  1013. <dd><a name="index-mpconfig"></a>

  1014. </dd>

  1015. <dt><code>-mwbnoinvd</code></dt>

  1016. <dd><a name="index-mwbnoinvd"></a>

  1017. </dd>

  1018. <dt><code>-mfma4</code></dt>

  1019. <dd><a name="index-mfma4"></a>

  1020. </dd>

  1021. <dt><code>-mprfchw</code></dt>

  1022. <dd><a name="index-mprfchw"></a>

  1023. </dd>

  1024. <dt><code>-mrdpid</code></dt>

  1025. <dd><a name="index-mrdpid"></a>

  1026. </dd>

  1027. <dt><code>-mprefetchwt1</code></dt>

  1028. <dd><a name="index-mprefetchwt1"></a>

  1029. </dd>

  1030. <dt><code>-mrdseed</code></dt>

  1031. <dd><a name="index-mrdseed"></a>

  1032. </dd>

  1033. <dt><code>-msgx</code></dt>

  1034. <dd><a name="index-msgx"></a>

  1035. </dd>

  1036. <dt><code>-mxop</code></dt>

  1037. <dd><a name="index-mxop"></a>

  1038. </dd>

  1039. <dt><code>-mlwp</code></dt>

  1040. <dd><a name="index-mlwp"></a>

  1041. </dd>

  1042. <dt><code>-m3dnow</code></dt>

  1043. <dd><a name="index-m3dnow"></a>

  1044. </dd>

  1045. <dt><code>-m3dnowa</code></dt>

  1046. <dd><a name="index-m3dnowa"></a>

  1047. </dd>

  1048. <dt><code>-mpopcnt</code></dt>

  1049. <dd><a name="index-mpopcnt"></a>

  1050. </dd>

  1051. <dt><code>-mabm</code></dt>

  1052. <dd><a name="index-mabm"></a>

  1053. </dd>

  1054. <dt><code>-madx</code></dt>

  1055. <dd><a name="index-madx"></a>

  1056. </dd>

  1057. <dt><code>-mbmi</code></dt>

  1058. <dd><a name="index-mbmi"></a>

  1059. </dd>

  1060. <dt><code>-mbmi2</code></dt>

  1061. <dd><a name="index-mbmi2"></a>

  1062. </dd>

  1063. <dt><code>-mlzcnt</code></dt>

  1064. <dd><a name="index-mlzcnt"></a>

  1065. </dd>

  1066. <dt><code>-mfxsr</code></dt>

  1067. <dd><a name="index-mfxsr"></a>

  1068. </dd>

  1069. <dt><code>-mxsave</code></dt>

  1070. <dd><a name="index-mxsave"></a>

  1071. </dd>

  1072. <dt><code>-mxsaveopt</code></dt>

  1073. <dd><a name="index-mxsaveopt"></a>

  1074. </dd>

  1075. <dt><code>-mxsavec</code></dt>

  1076. <dd><a name="index-mxsavec"></a>

  1077. </dd>

  1078. <dt><code>-mxsaves</code></dt>

  1079. <dd><a name="index-mxsaves"></a>

  1080. </dd>

  1081. <dt><code>-mrtm</code></dt>

  1082. <dd><a name="index-mrtm"></a>

  1083. </dd>

  1084. <dt><code>-mhle</code></dt>

  1085. <dd><a name="index-mhle"></a>

  1086. </dd>

  1087. <dt><code>-mtbm</code></dt>

  1088. <dd><a name="index-mtbm"></a>

  1089. </dd>

  1090. <dt><code>-mmwaitx</code></dt>

  1091. <dd><a name="index-mmwaitx"></a>

  1092. </dd>

  1093. <dt><code>-mclzero</code></dt>

  1094. <dd><a name="index-mclzero"></a>

  1095. </dd>

  1096. <dt><code>-mpku</code></dt>

  1097. <dd><a name="index-mpku"></a>

  1098. </dd>

  1099. <dt><code>-mavx512vbmi2</code></dt>

  1100. <dd><a name="index-mavx512vbmi2"></a>

  1101. </dd>

  1102. <dt><code>-mavx512bf16</code></dt>

  1103. <dd><a name="index-mavx512bf16"></a>

  1104. </dd>

  1105. <dt><code>-mgfni</code></dt>

  1106. <dd><a name="index-mgfni"></a>

  1107. </dd>

  1108. <dt><code>-mvaes</code></dt>

  1109. <dd><a name="index-mvaes"></a>

  1110. </dd>

  1111. <dt><code>-mwaitpkg</code></dt>

  1112. <dd><a name="index-mwaitpkg"></a>

  1113. </dd>

  1114. <dt><code>-mvpclmulqdq</code></dt>

  1115. <dd><a name="index-mvpclmulqdq"></a>

  1116. </dd>

  1117. <dt><code>-mavx512bitalg</code></dt>

  1118. <dd><a name="index-mavx512bitalg"></a>

  1119. </dd>

  1120. <dt><code>-mmovdiri</code></dt>

  1121. <dd><a name="index-mmovdiri"></a>

  1122. </dd>

  1123. <dt><code>-mmovdir64b</code></dt>

  1124. <dd><a name="index-mmovdir64b"></a>

  1125. </dd>

  1126. <dt><code>-menqcmd</code></dt>

  1127. <dd><a name="index-menqcmd"></a>

  1128. </dd>

  1129. <dt><code>-mavx512vpopcntdq</code></dt>

  1130. <dd><a name="index-mavx512vpopcntdq"></a>

  1131. </dd>

  1132. <dt><code>-mavx512vp2intersect</code></dt>

  1133. <dd><a name="index-mavx512vp2intersect"></a>

  1134. </dd>

  1135. <dt><code>-mavx5124fmaps</code></dt>

  1136. <dd><a name="index-mavx5124fmaps"></a>

  1137. </dd>

  1138. <dt><code>-mavx512vnni</code></dt>

  1139. <dd><a name="index-mavx512vnni"></a>

  1140. </dd>

  1141. <dt><code>-mavx5124vnniw</code></dt>

  1142. <dd><a name="index-mavx5124vnniw"></a>

  1143. </dd>

  1144. <dt><code>-mcldemote</code></dt>

  1145. <dd><a name="index-mcldemote"></a>

  1146. <p>These switches enable the use of instructions in the MMX, SSE,

  1147. SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,

  1148. AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,

  1149. AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,

  1150. WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,

  1151. 3DNow!, enhanced 3DNow!, POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE,

  1152. XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,

  1153. GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,

  1154. ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, or CLDEMOTE

  1155. extended instruction sets.  Each has a corresponding <samp>-mno-</samp> option to

  1156. disable use of these instructions.

  1157. </p>

  1158. <p>These extensions are also available as built-in functions: see

  1159. <a href="x86-Built_002din-Functions.html#x86-Built_002din-Functions">x86 Built-in Functions</a>, for details of the functions enabled and

  1160. disabled by these switches.

  1161. </p>

  1162. <p>To generate SSE/SSE2 instructions automatically from floating-point

  1163. code (as opposed to 387 instructions), see <samp>-mfpmath=sse</samp>.

  1164. </p>

  1165. <p>GCC depresses SSEx instructions when <samp>-mavx</samp> is used. Instead, it

  1166. generates new AVX instructions or AVX equivalence for all SSEx instructions

  1167. when needed.

  1168. </p>

  1169. <p>These options enable GCC to use these extended instructions in

  1170. generated code, even without <samp>-mfpmath=sse</samp>.  Applications that

  1171. perform run-time CPU detection must compile separate files for each

  1172. supported architecture, using the appropriate flags.  In particular,

  1173. the file containing the CPU detection code should be compiled without

  1174. these options.

  1175. </p>

  1176. </dd>

  1177. <dt><code>-mdump-tune-features</code></dt>

  1178. <dd><a name="index-mdump_002dtune_002dfeatures"></a>

  1179. <p>This option instructs GCC to dump the names of the x86 performance 

  1180. tuning features and default settings. The names can be used in 

  1181. <samp>-mtune-ctrl=<var>feature-list</var></samp>.

  1182. </p>

  1183. </dd>

  1184. <dt><code>-mtune-ctrl=<var>feature-list</var></code></dt>

  1185. <dd><a name="index-mtune_002dctrl_003dfeature_002dlist"></a>

  1186. <p>This option is used to do fine grain control of x86 code generation features.

  1187. <var>feature-list</var> is a comma separated list of <var>feature</var> names. See also

  1188. <samp>-mdump-tune-features</samp>. When specified, the <var>feature</var> is turned

  1189. on if it is not preceded with &lsquo;<samp>^</samp>&rsquo;, otherwise, it is turned off. 

  1190. <samp>-mtune-ctrl=<var>feature-list</var></samp> is intended to be used by GCC

  1191. developers. Using it may lead to code paths not covered by testing and can

  1192. potentially result in compiler ICEs or runtime errors.

  1193. </p>

  1194. </dd>

  1195. <dt><code>-mno-default</code></dt>

  1196. <dd><a name="index-mno_002ddefault"></a>

  1197. <p>This option instructs GCC to turn off all tunable features. See also 

  1198. <samp>-mtune-ctrl=<var>feature-list</var></samp> and <samp>-mdump-tune-features</samp>.

  1199. </p>

  1200. </dd>

  1201. <dt><code>-mcld</code></dt>

  1202. <dd><a name="index-mcld"></a>

  1203. <p>This option instructs GCC to emit a <code>cld</code> instruction in the prologue

  1204. of functions that use string instructions.  String instructions depend on

  1205. the DF flag to select between autoincrement or autodecrement mode.  While the

  1206. ABI specifies the DF flag to be cleared on function entry, some operating

  1207. systems violate this specification by not clearing the DF flag in their

  1208. exception dispatchers.  The exception handler can be invoked with the DF flag

  1209. set, which leads to wrong direction mode when string instructions are used.

  1210. This option can be enabled by default on 32-bit x86 targets by configuring

  1211. GCC with the <samp>--enable-cld</samp> configure option.  Generation of <code>cld</code>

  1212. instructions can be suppressed with the <samp>-mno-cld</samp> compiler option

  1213. in this case.

  1214. </p>

  1215. </dd>

  1216. <dt><code>-mvzeroupper</code></dt>

  1217. <dd><a name="index-mvzeroupper"></a>

  1218. <p>This option instructs GCC to emit a <code>vzeroupper</code> instruction

  1219. before a transfer of control flow out of the function to minimize

  1220. the AVX to SSE transition penalty as well as remove unnecessary <code>zeroupper</code>

  1221. intrinsics.

  1222. </p>

  1223. </dd>

  1224. <dt><code>-mprefer-avx128</code></dt>

  1225. <dd><a name="index-mprefer_002davx128"></a>

  1226. <p>This option instructs GCC to use 128-bit AVX instructions instead of

  1227. 256-bit AVX instructions in the auto-vectorizer.

  1228. </p>

  1229. </dd>

  1230. <dt><code>-mprefer-vector-width=<var>opt</var></code></dt>

  1231. <dd><a name="index-mprefer_002dvector_002dwidth"></a>

  1232. <p>This option instructs GCC to use <var>opt</var>-bit vector width in instructions

  1233. instead of default on the selected platform.

  1234. </p>

  1235. <dl compact="compact">

  1236. <dt>&lsquo;<samp>none</samp>&rsquo;</dt>

  1237. <dd><p>No extra limitations applied to GCC other than defined by the selected platform.

  1238. </p>

  1239. </dd>

  1240. <dt>&lsquo;<samp>128</samp>&rsquo;</dt>

  1241. <dd><p>Prefer 128-bit vector width for instructions.

  1242. </p>

  1243. </dd>

  1244. <dt>&lsquo;<samp>256</samp>&rsquo;</dt>

  1245. <dd><p>Prefer 256-bit vector width for instructions.

  1246. </p>

  1247. </dd>

  1248. <dt>&lsquo;<samp>512</samp>&rsquo;</dt>

  1249. <dd><p>Prefer 512-bit vector width for instructions.

  1250. </p></dd>

  1251. </dl>

  1252. 

  1253. </dd>

  1254. <dt><code>-mcx16</code></dt>

  1255. <dd><a name="index-mcx16"></a>

  1256. <p>This option enables GCC to generate <code>CMPXCHG16B</code> instructions in 64-bit

  1257. code to implement compare-and-exchange operations on 16-byte aligned 128-bit

  1258. objects.  This is useful for atomic updates of data structures exceeding one

  1259. machine word in size.  The compiler uses this instruction to implement

  1260. <a href="_005f_005fsync-Builtins.html#g_t_005f_005fsync-Builtins">__sync Builtins</a>.  However, for <a href="_005f_005fatomic-Builtins.html#g_t_005f_005fatomic-Builtins">__atomic Builtins</a> operating on

  1261. 128-bit integers, a library call is always used.

  1262. </p>

  1263. </dd>

  1264. <dt><code>-msahf</code></dt>

  1265. <dd><a name="index-msahf"></a>

  1266. <p>This option enables generation of <code>SAHF</code> instructions in 64-bit code.

  1267. Early Intel Pentium 4 CPUs with Intel 64 support,

  1268. prior to the introduction of Pentium 4 G1 step in December 2005,

  1269. lacked the <code>LAHF</code> and <code>SAHF</code> instructions

  1270. which are supported by AMD64.

  1271. These are load and store instructions, respectively, for certain status flags.

  1272. In 64-bit mode, the <code>SAHF</code> instruction is used to optimize <code>fmod</code>,

  1273. <code>drem</code>, and <code>remainder</code> built-in functions;

  1274. see <a href="Other-Builtins.html#Other-Builtins">Other Builtins</a> for details.

  1275. </p>

  1276. </dd>

  1277. <dt><code>-mmovbe</code></dt>

  1278. <dd><a name="index-mmovbe"></a>

  1279. <p>This option enables use of the <code>movbe</code> instruction to implement

  1280. <code>__builtin_bswap32</code> and <code>__builtin_bswap64</code>.

  1281. </p>

  1282. </dd>

  1283. <dt><code>-mshstk</code></dt>

  1284. <dd><a name="index-mshstk"></a>

  1285. <p>The <samp>-mshstk</samp> option enables shadow stack built-in functions

  1286. from x86 Control-flow Enforcement Technology (CET).

  1287. </p>

  1288. </dd>

  1289. <dt><code>-mcrc32</code></dt>

  1290. <dd><a name="index-mcrc32"></a>

  1291. <p>This option enables built-in functions <code>__builtin_ia32_crc32qi</code>,

  1292. <code>__builtin_ia32_crc32hi</code>, <code>__builtin_ia32_crc32si</code> and

  1293. <code>__builtin_ia32_crc32di</code> to generate the <code>crc32</code> machine instruction.

  1294. </p>

  1295. </dd>

  1296. <dt><code>-mrecip</code></dt>

  1297. <dd><a name="index-mrecip-1"></a>

  1298. <p>This option enables use of <code>RCPSS</code> and <code>RSQRTSS</code> instructions

  1299. (and their vectorized variants <code>RCPPS</code> and <code>RSQRTPS</code>)

  1300. with an additional Newton-Raphson step

  1301. to increase precision instead of <code>DIVSS</code> and <code>SQRTSS</code>

  1302. (and their vectorized

  1303. variants) for single-precision floating-point arguments.  These instructions

  1304. are generated only when <samp>-funsafe-math-optimizations</samp> is enabled

  1305. together with <samp>-ffinite-math-only</samp> and <samp>-fno-trapping-math</samp>.

  1306. Note that while the throughput of the sequence is higher than the throughput

  1307. of the non-reciprocal instruction, the precision of the sequence can be

  1308. decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).

  1309. </p>

  1310. <p>Note that GCC implements <code>1.0f/sqrtf(<var>x</var>)</code> in terms of <code>RSQRTSS</code>

  1311. (or <code>RSQRTPS</code>) already with <samp>-ffast-math</samp> (or the above option

  1312. combination), and doesn&rsquo;t need <samp>-mrecip</samp>.

  1313. </p>

  1314. <p>Also note that GCC emits the above sequence with additional Newton-Raphson step

  1315. for vectorized single-float division and vectorized <code>sqrtf(<var>x</var>)</code>

  1316. already with <samp>-ffast-math</samp> (or the above option combination), and

  1317. doesn&rsquo;t need <samp>-mrecip</samp>.

  1318. </p>

  1319. </dd>

  1320. <dt><code>-mrecip=<var>opt</var></code></dt>

  1321. <dd><a name="index-mrecip_003dopt-1"></a>

  1322. <p>This option controls which reciprocal estimate instructions

  1323. may be used.  <var>opt</var> is a comma-separated list of options, which may

  1324. be preceded by a &lsquo;<samp>!</samp>&rsquo; to invert the option:

  1325. </p>

  1326. <dl compact="compact">

  1327. <dt>&lsquo;<samp>all</samp>&rsquo;</dt>

  1328. <dd><p>Enable all estimate instructions.

  1329. </p>

  1330. </dd>

  1331. <dt>&lsquo;<samp>default</samp>&rsquo;</dt>

  1332. <dd><p>Enable the default instructions, equivalent to <samp>-mrecip</samp>.

  1333. </p>

  1334. </dd>

  1335. <dt>&lsquo;<samp>none</samp>&rsquo;</dt>

  1336. <dd><p>Disable all estimate instructions, equivalent to <samp>-mno-recip</samp>.

  1337. </p>

  1338. </dd>

  1339. <dt>&lsquo;<samp>div</samp>&rsquo;</dt>

  1340. <dd><p>Enable the approximation for scalar division.

  1341. </p>

  1342. </dd>

  1343. <dt>&lsquo;<samp>vec-div</samp>&rsquo;</dt>

  1344. <dd><p>Enable the approximation for vectorized division.

  1345. </p>

  1346. </dd>

  1347. <dt>&lsquo;<samp>sqrt</samp>&rsquo;</dt>

  1348. <dd><p>Enable the approximation for scalar square root.

  1349. </p>

  1350. </dd>

  1351. <dt>&lsquo;<samp>vec-sqrt</samp>&rsquo;</dt>

  1352. <dd><p>Enable the approximation for vectorized square root.

  1353. </p></dd>

  1354. </dl>

  1355. 

  1356. <p>So, for example, <samp>-mrecip=all,!sqrt</samp> enables

  1357. all of the reciprocal approximations, except for square root.

  1358. </p>

  1359. </dd>

  1360. <dt><code>-mveclibabi=<var>type</var></code></dt>

  1361. <dd><a name="index-mveclibabi-1"></a>

  1362. <p>Specifies the ABI type to use for vectorizing intrinsics using an

  1363. external library.  Supported values for <var>type</var> are &lsquo;<samp>svml</samp>&rsquo; 

  1364. for the Intel short

  1365. vector math library and &lsquo;<samp>acml</samp>&rsquo; for the AMD math core library.

  1366. To use this option, both <samp>-ftree-vectorize</samp> and

  1367. <samp>-funsafe-math-optimizations</samp> have to be enabled, and an SVML or ACML 

  1368. ABI-compatible library must be specified at link time.

  1369. </p>

  1370. <p>GCC currently emits calls to <code>vmldExp2</code>,

  1371. <code>vmldLn2</code>, <code>vmldLog102</code>, <code>vmldPow2</code>,

  1372. <code>vmldTanh2</code>, <code>vmldTan2</code>, <code>vmldAtan2</code>, <code>vmldAtanh2</code>,

  1373. <code>vmldCbrt2</code>, <code>vmldSinh2</code>, <code>vmldSin2</code>, <code>vmldAsinh2</code>,

  1374. <code>vmldAsin2</code>, <code>vmldCosh2</code>, <code>vmldCos2</code>, <code>vmldAcosh2</code>,

  1375. <code>vmldAcos2</code>, <code>vmlsExp4</code>, <code>vmlsLn4</code>,

  1376. <code>vmlsLog104</code>, <code>vmlsPow4</code>, <code>vmlsTanh4</code>, <code>vmlsTan4</code>,

  1377. <code>vmlsAtan4</code>, <code>vmlsAtanh4</code>, <code>vmlsCbrt4</code>, <code>vmlsSinh4</code>,

  1378. <code>vmlsSin4</code>, <code>vmlsAsinh4</code>, <code>vmlsAsin4</code>, <code>vmlsCosh4</code>,

  1379. <code>vmlsCos4</code>, <code>vmlsAcosh4</code> and <code>vmlsAcos4</code> for corresponding

  1380. function type when <samp>-mveclibabi=svml</samp> is used, and <code>__vrd2_sin</code>,

  1381. <code>__vrd2_cos</code>, <code>__vrd2_exp</code>, <code>__vrd2_log</code>, <code>__vrd2_log2</code>,

  1382. <code>__vrd2_log10</code>, <code>__vrs4_sinf</code>, <code>__vrs4_cosf</code>,

  1383. <code>__vrs4_expf</code>, <code>__vrs4_logf</code>, <code>__vrs4_log2f</code>,

  1384. <code>__vrs4_log10f</code> and <code>__vrs4_powf</code> for the corresponding function type

  1385. when <samp>-mveclibabi=acml</samp> is used.  

  1386. </p>

  1387. </dd>

  1388. <dt><code>-mabi=<var>name</var></code></dt>

  1389. <dd><a name="index-mabi-5"></a>

  1390. <p>Generate code for the specified calling convention.  Permissible values

  1391. are &lsquo;<samp>sysv</samp>&rsquo; for the ABI used on GNU/Linux and other systems, and

  1392. &lsquo;<samp>ms</samp>&rsquo; for the Microsoft ABI.  The default is to use the Microsoft

  1393. ABI when targeting Microsoft Windows and the SysV ABI on all other systems.

  1394. You can control this behavior for specific functions by

  1395. using the function attributes <code>ms_abi</code> and <code>sysv_abi</code>.

  1396. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>.

  1397. </p>

  1398. </dd>

  1399. <dt><code>-mforce-indirect-call</code></dt>

  1400. <dd><a name="index-mforce_002dindirect_002dcall"></a>

  1401. <p>Force all calls to functions to be indirect. This is useful

  1402. when using Intel Processor Trace where it generates more precise timing

  1403. information for function calls.

  1404. </p>

  1405. </dd>

  1406. <dt><code>-mmanual-endbr</code></dt>

  1407. <dd><a name="index-mmanual_002dendbr"></a>

  1408. <p>Insert ENDBR instruction at function entry only via the <code>cf_check</code>

  1409. function attribute. This is useful when used with the option

  1410. <samp>-fcf-protection=branch</samp> to control ENDBR insertion at the

  1411. function entry.

  1412. </p>

  1413. </dd>

  1414. <dt><code>-mcall-ms2sysv-xlogues</code></dt>

  1415. <dd><a name="index-mcall_002dms2sysv_002dxlogues"></a>

  1416. <a name="index-mno_002dcall_002dms2sysv_002dxlogues"></a>

  1417. <p>Due to differences in 64-bit ABIs, any Microsoft ABI function that calls a

  1418. System V ABI function must consider RSI, RDI and XMM6-15 as clobbered.  By

  1419. default, the code for saving and restoring these registers is emitted inline,

  1420. resulting in fairly lengthy prologues and epilogues.  Using

  1421. <samp>-mcall-ms2sysv-xlogues</samp> emits prologues and epilogues that

  1422. use stubs in the static portion of libgcc to perform these saves and restores,

  1423. thus reducing function size at the cost of a few extra instructions.

  1424. </p>

  1425. </dd>

  1426. <dt><code>-mtls-dialect=<var>type</var></code></dt>

  1427. <dd><a name="index-mtls_002ddialect-1"></a>

  1428. <p>Generate code to access thread-local storage using the &lsquo;<samp>gnu</samp>&rsquo; or

  1429. &lsquo;<samp>gnu2</samp>&rsquo; conventions.  &lsquo;<samp>gnu</samp>&rsquo; is the conservative default;

  1430. &lsquo;<samp>gnu2</samp>&rsquo; is more efficient, but it may add compile- and run-time

  1431. requirements that cannot be satisfied on all systems.

  1432. </p>

  1433. </dd>

  1434. <dt><code>-mpush-args</code></dt>

  1435. <dt><code>-mno-push-args</code></dt>

  1436. <dd><a name="index-mpush_002dargs"></a>

  1437. <a name="index-mno_002dpush_002dargs"></a>

  1438. <p>Use PUSH operations to store outgoing parameters.  This method is shorter

  1439. and usually equally fast as method using SUB/MOV operations and is enabled

  1440. by default.  In some cases disabling it may improve performance because of

  1441. improved scheduling and reduced dependencies.

  1442. </p>

  1443. </dd>

  1444. <dt><code>-maccumulate-outgoing-args</code></dt>

  1445. <dd><a name="index-maccumulate_002doutgoing_002dargs-1"></a>

  1446. <p>If enabled, the maximum amount of space required for outgoing arguments is

  1447. computed in the function prologue.  This is faster on most modern CPUs

  1448. because of reduced dependencies, improved scheduling and reduced stack usage

  1449. when the preferred stack boundary is not equal to 2.  The drawback is a notable

  1450. increase in code size.  This switch implies <samp>-mno-push-args</samp>.

  1451. </p>

  1452. </dd>

  1453. <dt><code>-mthreads</code></dt>

  1454. <dd><a name="index-mthreads"></a>

  1455. <p>Support thread-safe exception handling on MinGW.  Programs that rely

  1456. on thread-safe exception handling must compile and link all code with the

  1457. <samp>-mthreads</samp> option.  When compiling, <samp>-mthreads</samp> defines

  1458. <samp>-D_MT</samp>; when linking, it links in a special thread helper library

  1459. <samp>-lmingwthrd</samp> which cleans up per-thread exception-handling data.

  1460. </p>

  1461. </dd>

  1462. <dt><code>-mms-bitfields</code></dt>

  1463. <dt><code>-mno-ms-bitfields</code></dt>

  1464. <dd><a name="index-mms_002dbitfields"></a>

  1465. <a name="index-mno_002dms_002dbitfields"></a>

  1466. 

  1467. <p>Enable/disable bit-field layout compatible with the native Microsoft

  1468. Windows compiler.  

  1469. </p>

  1470. <p>If <code>packed</code> is used on a structure, or if bit-fields are used,

  1471. it may be that the Microsoft ABI lays out the structure differently

  1472. than the way GCC normally does.  Particularly when moving packed

  1473. data between functions compiled with GCC and the native Microsoft compiler

  1474. (either via function call or as data in a file), it may be necessary to access

  1475. either format.

  1476. </p>

  1477. <p>This option is enabled by default for Microsoft Windows

  1478. targets.  This behavior can also be controlled locally by use of variable

  1479. or type attributes.  For more information, see <a href="x86-Variable-Attributes.html#x86-Variable-Attributes">x86 Variable Attributes</a>

  1480. and <a href="x86-Type-Attributes.html#x86-Type-Attributes">x86 Type Attributes</a>.

  1481. </p>

  1482. <p>The Microsoft structure layout algorithm is fairly simple with the exception

  1483. of the bit-field packing.  

  1484. The padding and alignment of members of structures and whether a bit-field 

  1485. can straddle a storage-unit boundary are determine by these rules:

  1486. </p>

  1487. <ol>

  1488. <li> Structure members are stored sequentially in the order in which they are

  1489. declared: the first member has the lowest memory address and the last member

  1490. the highest.

  1491. 

  1492. </li><li> Every data object has an alignment requirement.  The alignment requirement

  1493. for all data except structures, unions, and arrays is either the size of the

  1494. object or the current packing size (specified with either the

  1495. <code>aligned</code> attribute or the <code>pack</code> pragma),

  1496. whichever is less.  For structures, unions, and arrays,

  1497. the alignment requirement is the largest alignment requirement of its members.

  1498. Every object is allocated an offset so that:

  1499. 

  1500. <div class="smallexample">

  1501. <pre class="smallexample">offset % alignment_requirement == 0

  1502. </pre></div>

  1503. 

  1504. </li><li> Adjacent bit-fields are packed into the same 1-, 2-, or 4-byte allocation

  1505. unit if the integral types are the same size and if the next bit-field fits

  1506. into the current allocation unit without crossing the boundary imposed by the

  1507. common alignment requirements of the bit-fields.

  1508. </li></ol>

  1509. 

  1510. <p>MSVC interprets zero-length bit-fields in the following ways:

  1511. </p>

  1512. <ol>

  1513. <li> If a zero-length bit-field is inserted between two bit-fields that

  1514. are normally coalesced, the bit-fields are not coalesced.

  1515. 

  1516. <p>For example:

  1517. </p>

  1518. <div class="smallexample">

  1519. <pre class="smallexample">struct

  1520.  {

  1521.    unsigned long bf_1 : 12;

  1522.    unsigned long : 0;

  1523.    unsigned long bf_2 : 12;

  1524.  } t1;

  1525. </pre></div>

  1526. 

  1527. <p>The size of <code>t1</code> is 8 bytes with the zero-length bit-field.  If the

  1528. zero-length bit-field were removed, <code>t1</code>&rsquo;s size would be 4 bytes.

  1529. </p>

  1530. </li><li> If a zero-length bit-field is inserted after a bit-field, <code>foo</code>, and the

  1531. alignment of the zero-length bit-field is greater than the member that follows it,

  1532. <code>bar</code>, <code>bar</code> is aligned as the type of the zero-length bit-field.

  1533. 

  1534. <p>For example:

  1535. </p>

  1536. <div class="smallexample">

  1537. <pre class="smallexample">struct

  1538.  {

  1539.    char foo : 4;

  1540.    short : 0;

  1541.    char bar;

  1542.  } t2;

  1543. 

  1544. struct

  1545.  {

  1546.    char foo : 4;

  1547.    short : 0;

  1548.    double bar;

  1549.  } t3;

  1550. </pre></div>

  1551. 

  1552. <p>For <code>t2</code>, <code>bar</code> is placed at offset 2, rather than offset 1.

  1553. Accordingly, the size of <code>t2</code> is 4.  For <code>t3</code>, the zero-length

  1554. bit-field does not affect the alignment of <code>bar</code> or, as a result, the size

  1555. of the structure.

  1556. </p>

  1557. <p>Taking this into account, it is important to note the following:

  1558. </p>

  1559. <ol>

  1560. <li> If a zero-length bit-field follows a normal bit-field, the type of the

  1561. zero-length bit-field may affect the alignment of the structure as whole. For

  1562. example, <code>t2</code> has a size of 4 bytes, since the zero-length bit-field follows a

  1563. normal bit-field, and is of type short.

  1564. 

  1565. </li><li> Even if a zero-length bit-field is not followed by a normal bit-field, it may

  1566. still affect the alignment of the structure:

  1567. 

  1568. <div class="smallexample">

  1569. <pre class="smallexample">struct

  1570.  {

  1571.    char foo : 6;

  1572.    long : 0;

  1573.  } t4;

  1574. </pre></div>

  1575. 

  1576. <p>Here, <code>t4</code> takes up 4 bytes.

  1577. </p></li></ol>

  1578. 

  1579. </li><li> Zero-length bit-fields following non-bit-field members are ignored:

  1580. 

  1581. <div class="smallexample">

  1582. <pre class="smallexample">struct

  1583.  {

  1584.    char foo;

  1585.    long : 0;

  1586.    char bar;

  1587.  } t5;

  1588. </pre></div>

  1589. 

  1590. <p>Here, <code>t5</code> takes up 2 bytes.

  1591. </p></li></ol>

  1592. 

  1593. 

  1594. </dd>

  1595. <dt><code>-mno-align-stringops</code></dt>

  1596. <dd><a name="index-mno_002dalign_002dstringops"></a>

  1597. <a name="index-malign_002dstringops"></a>

  1598. <p>Do not align the destination of inlined string operations.  This switch reduces

  1599. code size and improves performance in case the destination is already aligned,

  1600. but GCC doesn&rsquo;t know about it.

  1601. </p>

  1602. </dd>

  1603. <dt><code>-minline-all-stringops</code></dt>

  1604. <dd><a name="index-minline_002dall_002dstringops"></a>

  1605. <p>By default GCC inlines string operations only when the destination is 

  1606. known to be aligned to least a 4-byte boundary.  

  1607. This enables more inlining and increases code

  1608. size, but may improve performance of code that depends on fast

  1609. <code>memcpy</code> and <code>memset</code> for short lengths.

  1610. The option enables inline expansion of <code>strlen</code> for all

  1611. pointer alignments.

  1612. </p>

  1613. </dd>

  1614. <dt><code>-minline-stringops-dynamically</code></dt>

  1615. <dd><a name="index-minline_002dstringops_002ddynamically"></a>

  1616. <p>For string operations of unknown size, use run-time checks with

  1617. inline code for small blocks and a library call for large blocks.

  1618. </p>

  1619. </dd>

  1620. <dt><code>-mstringop-strategy=<var>alg</var></code></dt>

  1621. <dd><a name="index-mstringop_002dstrategy_003dalg"></a>

  1622. <p>Override the internal decision heuristic for the particular algorithm to use

  1623. for inlining string operations.  The allowed values for <var>alg</var> are:

  1624. </p>

  1625. <dl compact="compact">

  1626. <dt>&lsquo;<samp>rep_byte</samp>&rsquo;</dt>

  1627. <dt>&lsquo;<samp>rep_4byte</samp>&rsquo;</dt>

  1628. <dt>&lsquo;<samp>rep_8byte</samp>&rsquo;</dt>

  1629. <dd><p>Expand using i386 <code>rep</code> prefix of the specified size.

  1630. </p>

  1631. </dd>

  1632. <dt>&lsquo;<samp>byte_loop</samp>&rsquo;</dt>

  1633. <dt>&lsquo;<samp>loop</samp>&rsquo;</dt>

  1634. <dt>&lsquo;<samp>unrolled_loop</samp>&rsquo;</dt>

  1635. <dd><p>Expand into an inline loop.

  1636. </p>

  1637. </dd>

  1638. <dt>&lsquo;<samp>libcall</samp>&rsquo;</dt>

  1639. <dd><p>Always use a library call.

  1640. </p></dd>

  1641. </dl>

  1642. 

  1643. </dd>

  1644. <dt><code>-mmemcpy-strategy=<var>strategy</var></code></dt>

  1645. <dd><a name="index-mmemcpy_002dstrategy_003dstrategy"></a>

  1646. <p>Override the internal decision heuristic to decide if <code>__builtin_memcpy</code>

  1647. should be inlined and what inline algorithm to use when the expected size

  1648. of the copy operation is known. <var>strategy</var> 

  1649. is a comma-separated list of <var>alg</var>:<var>max_size</var>:<var>dest_align</var> triplets. 

  1650. <var>alg</var> is specified in <samp>-mstringop-strategy</samp>, <var>max_size</var> specifies

  1651. the max byte size with which inline algorithm <var>alg</var> is allowed.  For the last

  1652. triplet, the <var>max_size</var> must be <code>-1</code>. The <var>max_size</var> of the triplets

  1653. in the list must be specified in increasing order.  The minimal byte size for 

  1654. <var>alg</var> is <code>0</code> for the first triplet and <code><var>max_size</var> + 1</code> of the 

  1655. preceding range.

  1656. </p>

  1657. </dd>

  1658. <dt><code>-mmemset-strategy=<var>strategy</var></code></dt>

  1659. <dd><a name="index-mmemset_002dstrategy_003dstrategy"></a>

  1660. <p>The option is similar to <samp>-mmemcpy-strategy=</samp> except that it is to control

  1661. <code>__builtin_memset</code> expansion.

  1662. </p>

  1663. </dd>

  1664. <dt><code>-momit-leaf-frame-pointer</code></dt>

  1665. <dd><a name="index-momit_002dleaf_002dframe_002dpointer-2"></a>

  1666. <p>Don&rsquo;t keep the frame pointer in a register for leaf functions.  This

  1667. avoids the instructions to save, set up, and restore frame pointers and

  1668. makes an extra register available in leaf functions.  The option

  1669. <samp>-fomit-leaf-frame-pointer</samp> removes the frame pointer for leaf functions,

  1670. which might make debugging harder.

  1671. </p>

  1672. </dd>

  1673. <dt><code>-mtls-direct-seg-refs</code></dt>

  1674. <dt><code>-mno-tls-direct-seg-refs</code></dt>

  1675. <dd><a name="index-mtls_002ddirect_002dseg_002drefs"></a>

  1676. <p>Controls whether TLS variables may be accessed with offsets from the

  1677. TLS segment register (<code>%gs</code> for 32-bit, <code>%fs</code> for 64-bit),

  1678. or whether the thread base pointer must be added.  Whether or not this

  1679. is valid depends on the operating system, and whether it maps the

  1680. segment to cover the entire TLS area.

  1681. </p>

  1682. <p>For systems that use the GNU C Library, the default is on.

  1683. </p>

  1684. </dd>

  1685. <dt><code>-msse2avx</code></dt>

  1686. <dt><code>-mno-sse2avx</code></dt>

  1687. <dd><a name="index-msse2avx"></a>

  1688. <p>Specify that the assembler should encode SSE instructions with VEX

  1689. prefix.  The option <samp>-mavx</samp> turns this on by default.

  1690. </p>

  1691. </dd>

  1692. <dt><code>-mfentry</code></dt>

  1693. <dt><code>-mno-fentry</code></dt>

  1694. <dd><a name="index-mfentry"></a>

  1695. <p>If profiling is active (<samp>-pg</samp>), put the profiling

  1696. counter call before the prologue.

  1697. Note: On x86 architectures the attribute <code>ms_hook_prologue</code>

  1698. isn&rsquo;t possible at the moment for <samp>-mfentry</samp> and <samp>-pg</samp>.

  1699. </p>

  1700. </dd>

  1701. <dt><code>-mrecord-mcount</code></dt>

  1702. <dt><code>-mno-record-mcount</code></dt>

  1703. <dd><a name="index-mrecord_002dmcount"></a>

  1704. <p>If profiling is active (<samp>-pg</samp>), generate a __mcount_loc section

  1705. that contains pointers to each profiling call. This is useful for

  1706. automatically patching and out calls.

  1707. </p>

  1708. </dd>

  1709. <dt><code>-mnop-mcount</code></dt>

  1710. <dt><code>-mno-nop-mcount</code></dt>

  1711. <dd><a name="index-mnop_002dmcount"></a>

  1712. <p>If profiling is active (<samp>-pg</samp>), generate the calls to

  1713. the profiling functions as NOPs. This is useful when they

  1714. should be patched in later dynamically. This is likely only

  1715. useful together with <samp>-mrecord-mcount</samp>.

  1716. </p>

  1717. </dd>

  1718. <dt><code>-minstrument-return=<var>type</var></code></dt>

  1719. <dd><a name="index-minstrument_002dreturn"></a>

  1720. <p>Instrument function exit in -pg -mfentry instrumented functions with

  1721. call to specified function. This only instruments true returns ending

  1722. with ret, but not sibling calls ending with jump. Valid types

  1723. are <var>none</var> to not instrument, <var>call</var> to generate a call to __return__,

  1724. or <var>nop5</var> to generate a 5 byte nop.

  1725. </p>

  1726. </dd>

  1727. <dt><code>-mrecord-return</code></dt>

  1728. <dt><code>-mno-record-return</code></dt>

  1729. <dd><a name="index-mrecord_002dreturn"></a>

  1730. <p>Generate a __return_loc section pointing to all return instrumentation code.

  1731. </p>

  1732. </dd>

  1733. <dt><code>-mfentry-name=<var>name</var></code></dt>

  1734. <dd><a name="index-mfentry_002dname"></a>

  1735. <p>Set name of __fentry__ symbol called at function entry for -pg -mfentry functions.

  1736. </p>

  1737. </dd>

  1738. <dt><code>-mfentry-section=<var>name</var></code></dt>

  1739. <dd><a name="index-mfentry_002dsection"></a>

  1740. <p>Set name of section to record -mrecord-mcount calls (default __mcount_loc).

  1741. </p>

  1742. </dd>

  1743. <dt><code>-mskip-rax-setup</code></dt>

  1744. <dt><code>-mno-skip-rax-setup</code></dt>

  1745. <dd><a name="index-mskip_002drax_002dsetup"></a>

  1746. <p>When generating code for the x86-64 architecture with SSE extensions

  1747. disabled, <samp>-mskip-rax-setup</samp> can be used to skip setting up RAX

  1748. register when there are no variable arguments passed in vector registers.

  1749. </p>

  1750. <p><strong>Warning:</strong> Since RAX register is used to avoid unnecessarily

  1751. saving vector registers on stack when passing variable arguments, the

  1752. impacts of this option are callees may waste some stack space,

  1753. misbehave or jump to a random location.  GCC 4.4 or newer don&rsquo;t have

  1754. those issues, regardless the RAX register value.

  1755. </p>

  1756. </dd>

  1757. <dt><code>-m8bit-idiv</code></dt>

  1758. <dt><code>-mno-8bit-idiv</code></dt>

  1759. <dd><a name="index-m8bit_002didiv"></a>

  1760. <p>On some processors, like Intel Atom, 8-bit unsigned integer divide is

  1761. much faster than 32-bit/64-bit integer divide.  This option generates a

  1762. run-time check.  If both dividend and divisor are within range of 0

  1763. to 255, 8-bit unsigned integer divide is used instead of

  1764. 32-bit/64-bit integer divide.

  1765. </p>

  1766. </dd>

  1767. <dt><code>-mavx256-split-unaligned-load</code></dt>

  1768. <dt><code>-mavx256-split-unaligned-store</code></dt>

  1769. <dd><a name="index-mavx256_002dsplit_002dunaligned_002dload"></a>

  1770. <a name="index-mavx256_002dsplit_002dunaligned_002dstore"></a>

  1771. <p>Split 32-byte AVX unaligned load and store.

  1772. </p>

  1773. </dd>

  1774. <dt><code>-mstack-protector-guard=<var>guard</var></code></dt>

  1775. <dt><code>-mstack-protector-guard-reg=<var>reg</var></code></dt>

  1776. <dt><code>-mstack-protector-guard-offset=<var>offset</var></code></dt>

  1777. <dd><a name="index-mstack_002dprotector_002dguard-3"></a>

  1778. <a name="index-mstack_002dprotector_002dguard_002dreg-3"></a>

  1779. <a name="index-mstack_002dprotector_002dguard_002doffset-3"></a>

  1780. <p>Generate stack protection code using canary at <var>guard</var>.  Supported

  1781. locations are &lsquo;<samp>global</samp>&rsquo; for global canary or &lsquo;<samp>tls</samp>&rsquo; for per-thread

  1782. canary in the TLS block (the default).  This option has effect only when

  1783. <samp>-fstack-protector</samp> or <samp>-fstack-protector-all</samp> is specified.

  1784. </p>

  1785. <p>With the latter choice the options

  1786. <samp>-mstack-protector-guard-reg=<var>reg</var></samp> and

  1787. <samp>-mstack-protector-guard-offset=<var>offset</var></samp> furthermore specify

  1788. which segment register (<code>%fs</code> or <code>%gs</code>) to use as base register

  1789. for reading the canary, and from what offset from that base register.

  1790. The default for those is as specified in the relevant ABI.

  1791. </p>

  1792. </dd>

  1793. <dt><code>-mgeneral-regs-only</code></dt>

  1794. <dd><a name="index-mgeneral_002dregs_002donly-2"></a>

  1795. <p>Generate code that uses only the general-purpose registers.  This

  1796. prevents the compiler from using floating-point, vector, mask and bound

  1797. registers.

  1798. </p>

  1799. </dd>

  1800. <dt><code>-mindirect-branch=<var>choice</var></code></dt>

  1801. <dd><a name="index-mindirect_002dbranch"></a>

  1802. <p>Convert indirect call and jump with <var>choice</var>.  The default is

  1803. &lsquo;<samp>keep</samp>&rsquo;, which keeps indirect call and jump unmodified.

  1804. &lsquo;<samp>thunk</samp>&rsquo; converts indirect call and jump to call and return thunk.

  1805. &lsquo;<samp>thunk-inline</samp>&rsquo; converts indirect call and jump to inlined call

  1806. and return thunk.  &lsquo;<samp>thunk-extern</samp>&rsquo; converts indirect call and jump

  1807. to external call and return thunk provided in a separate object file.

  1808. You can control this behavior for a specific function by using the

  1809. function attribute <code>indirect_branch</code>.  See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>.

  1810. </p>

  1811. <p>Note that <samp>-mcmodel=large</samp> is incompatible with

  1812. <samp>-mindirect-branch=thunk</samp> and

  1813. <samp>-mindirect-branch=thunk-extern</samp> since the thunk function may

  1814. not be reachable in the large code model.

  1815. </p>

  1816. <p>Note that <samp>-mindirect-branch=thunk-extern</samp> is compatible with

  1817. <samp>-fcf-protection=branch</samp> since the external thunk can be made

  1818. to enable control-flow check.

  1819. </p>

  1820. </dd>

  1821. <dt><code>-mfunction-return=<var>choice</var></code></dt>

  1822. <dd><a name="index-mfunction_002dreturn"></a>

  1823. <p>Convert function return with <var>choice</var>.  The default is &lsquo;<samp>keep</samp>&rsquo;,

  1824. which keeps function return unmodified.  &lsquo;<samp>thunk</samp>&rsquo; converts function

  1825. return to call and return thunk.  &lsquo;<samp>thunk-inline</samp>&rsquo; converts function

  1826. return to inlined call and return thunk.  &lsquo;<samp>thunk-extern</samp>&rsquo; converts

  1827. function return to external call and return thunk provided in a separate

  1828. object file.  You can control this behavior for a specific function by

  1829. using the function attribute <code>function_return</code>.

  1830. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>.

  1831. </p>

  1832. <p>Note that <samp>-mindirect-return=thunk-extern</samp> is compatible with

  1833. <samp>-fcf-protection=branch</samp> since the external thunk can be made

  1834. to enable control-flow check.

  1835. </p>

  1836. <p>Note that <samp>-mcmodel=large</samp> is incompatible with

  1837. <samp>-mfunction-return=thunk</samp> and

  1838. <samp>-mfunction-return=thunk-extern</samp> since the thunk function may

  1839. not be reachable in the large code model.

  1840. </p>

  1841. 

  1842. </dd>

  1843. <dt><code>-mindirect-branch-register</code></dt>

  1844. <dd><a name="index-mindirect_002dbranch_002dregister"></a>

  1845. <p>Force indirect call and jump via register.

  1846. </p>

  1847. </dd>

  1848. </dl>

  1849. 

  1850. <p>These &lsquo;<samp>-m</samp>&rsquo; switches are supported in addition to the above

  1851. on x86-64 processors in 64-bit environments.

  1852. </p>

  1853. <dl compact="compact">

  1854. <dt><code>-m32</code></dt>

  1855. <dt><code>-m64</code></dt>

  1856. <dt><code>-mx32</code></dt>

  1857. <dt><code>-m16</code></dt>

  1858. <dt><code>-miamcu</code></dt>

  1859. <dd><a name="index-m32-5"></a>

  1860. <a name="index-m64-5"></a>

  1861. <a name="index-mx32"></a>

  1862. <a name="index-m16"></a>

  1863. <a name="index-miamcu"></a>

  1864. <p>Generate code for a 16-bit, 32-bit or 64-bit environment.

  1865. The <samp>-m32</samp> option sets <code>int</code>, <code>long</code>, and pointer types

  1866. to 32 bits, and

  1867. generates code that runs on any i386 system.

  1868. </p>

  1869. <p>The <samp>-m64</samp> option sets <code>int</code> to 32 bits and <code>long</code> and pointer

  1870. types to 64 bits, and generates code for the x86-64 architecture.

  1871. For Darwin only the <samp>-m64</samp> option also turns off the <samp>-fno-pic</samp>

  1872. and <samp>-mdynamic-no-pic</samp> options.

  1873. </p>

  1874. <p>The <samp>-mx32</samp> option sets <code>int</code>, <code>long</code>, and pointer types

  1875. to 32 bits, and

  1876. generates code for the x86-64 architecture.

  1877. </p>

  1878. <p>The <samp>-m16</samp> option is the same as <samp>-m32</samp>, except for that

  1879. it outputs the <code>.code16gcc</code> assembly directive at the beginning of

  1880. the assembly output so that the binary can run in 16-bit mode.

  1881. </p>

  1882. <p>The <samp>-miamcu</samp> option generates code which conforms to Intel MCU

  1883. psABI.  It requires the <samp>-m32</samp> option to be turned on.

  1884. </p>

  1885. </dd>

  1886. <dt><code>-mno-red-zone</code></dt>

  1887. <dd><a name="index-mno_002dred_002dzone"></a>

  1888. <a name="index-mred_002dzone"></a>

  1889. <p>Do not use a so-called &ldquo;red zone&rdquo; for x86-64 code.  The red zone is mandated

  1890. by the x86-64 ABI; it is a 128-byte area beyond the location of the

  1891. stack pointer that is not modified by signal or interrupt handlers

  1892. and therefore can be used for temporary data without adjusting the stack

  1893. pointer.  The flag <samp>-mno-red-zone</samp> disables this red zone.

  1894. </p>

  1895. </dd>

  1896. <dt><code>-mcmodel=small</code></dt>

  1897. <dd><a name="index-mcmodel_003dsmall-3"></a>

  1898. <p>Generate code for the small code model: the program and its symbols must

  1899. be linked in the lower 2 GB of the address space.  Pointers are 64 bits.

  1900. Programs can be statically or dynamically linked.  This is the default

  1901. code model.

  1902. </p>

  1903. </dd>

  1904. <dt><code>-mcmodel=kernel</code></dt>

  1905. <dd><a name="index-mcmodel_003dkernel"></a>

  1906. <p>Generate code for the kernel code model.  The kernel runs in the

  1907. negative 2 GB of the address space.

  1908. This model has to be used for Linux kernel code.

  1909. </p>

  1910. </dd>

  1911. <dt><code>-mcmodel=medium</code></dt>

  1912. <dd><a name="index-mcmodel_003dmedium-1"></a>

  1913. <p>Generate code for the medium model: the program is linked in the lower 2

  1914. GB of the address space.  Small symbols are also placed there.  Symbols

  1915. with sizes larger than <samp>-mlarge-data-threshold</samp> are put into

  1916. large data or BSS sections and can be located above 2GB.  Programs can

  1917. be statically or dynamically linked.

  1918. </p>

  1919. </dd>

  1920. <dt><code>-mcmodel=large</code></dt>

  1921. <dd><a name="index-mcmodel_003dlarge-3"></a>

  1922. <p>Generate code for the large model.  This model makes no assumptions

  1923. about addresses and sizes of sections.

  1924. </p>

  1925. </dd>

  1926. <dt><code>-maddress-mode=long</code></dt>

  1927. <dd><a name="index-maddress_002dmode_003dlong"></a>

  1928. <p>Generate code for long address mode.  This is only supported for 64-bit

  1929. and x32 environments.  It is the default address mode for 64-bit

  1930. environments.

  1931. </p>

  1932. </dd>

  1933. <dt><code>-maddress-mode=short</code></dt>

  1934. <dd><a name="index-maddress_002dmode_003dshort"></a>

  1935. <p>Generate code for short address mode.  This is only supported for 32-bit

  1936. and x32 environments.  It is the default address mode for 32-bit and

  1937. x32 environments.

  1938. </p></dd>

  1939. </dl>

  1940. 

  1941. <hr>

  1942. <div class="header">

  1943. <p>

  1944. Next: <a href="x86-Windows-Options.html#x86-Windows-Options" accesskey="n" rel="next">x86 Windows Options</a>, Previous: <a href="VxWorks-Options.html#VxWorks-Options" accesskey="p" rel="prev">VxWorks Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  1945. </div>

  1946. 

  1947. 

  1948. 

  1949. </body>

  1950. </html>