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  67. <a name="Interdependence-of-Patterns"></a>
  68. <h3 class="section">17.11 Interdependence of Patterns</h3>
  69. <a name="index-Dependent-Patterns"></a>
  70. <a name="index-Interdependence-of-Patterns"></a>
  71. <p>In some cases machines support instructions identical except for the
  72. machine mode of one or more operands. For example, there may be
  73. &ldquo;sign-extend halfword&rdquo; and &ldquo;sign-extend byte&rdquo; instructions whose
  74. patterns are
  75. </p>
  76. <div class="smallexample">
  77. <pre class="smallexample">(set (match_operand:SI 0 &hellip;)
  78. (extend:SI (match_operand:HI 1 &hellip;)))
  79. (set (match_operand:SI 0 &hellip;)
  80. (extend:SI (match_operand:QI 1 &hellip;)))
  81. </pre></div>
  82. <p>Constant integers do not specify a machine mode, so an instruction to
  83. extend a constant value could match either pattern. The pattern it
  84. actually will match is the one that appears first in the file. For correct
  85. results, this must be the one for the widest possible mode (<code>HImode</code>,
  86. here). If the pattern matches the <code>QImode</code> instruction, the results
  87. will be incorrect if the constant value does not actually fit that mode.
  88. </p>
  89. <p>Such instructions to extend constants are rarely generated because they are
  90. optimized away, but they do occasionally happen in nonoptimized
  91. compilations.
  92. </p>
  93. <p>If a constraint in a pattern allows a constant, the reload pass may
  94. replace a register with a constant permitted by the constraint in some
  95. cases. Similarly for memory references. Because of this substitution,
  96. you should not provide separate patterns for increment and decrement
  97. instructions. Instead, they should be generated from the same pattern
  98. that supports register-register add insns by examining the operands and
  99. generating the appropriate machine instruction.
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