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  70. <a name="Processor-pipeline-description"></a>

  71. <div class="header">

  72. <p>

  73. Previous: <a href="Delay-Slots.html#Delay-Slots" accesskey="p" rel="prev">Delay Slots</a>, Up: <a href="Insn-Attributes.html#Insn-Attributes" accesskey="u" rel="up">Insn Attributes</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  74. </div>

  75. <hr>

  76. <a name="Specifying-processor-pipeline-description"></a>

  77. <h4 class="subsection">17.19.9 Specifying processor pipeline description</h4>

  78. <a name="index-processor-pipeline-description"></a>

  79. <a name="index-processor-functional-units"></a>

  80. <a name="index-instruction-latency-time"></a>

  81. <a name="index-interlock-delays"></a>

  82. <a name="index-data-dependence-delays"></a>

  83. <a name="index-reservation-delays"></a>

  84. <a name="index-pipeline-hazard-recognizer"></a>

  85. <a name="index-automaton-based-pipeline-description"></a>

  86. <a name="index-regular-expressions"></a>

  87. <a name="index-deterministic-finite-state-automaton"></a>

  88. <a name="index-automaton-based-scheduler"></a>

  89. <a name="index-RISC"></a>

  90. <a name="index-VLIW"></a>

  91. 

  92. <p>To achieve better performance, most modern processors

  93. (super-pipelined, superscalar <acronym>RISC</acronym>, and <acronym>VLIW</acronym>

  94. processors) have many <em>functional units</em> on which several

  95. instructions can be executed simultaneously.  An instruction starts

  96. execution if its issue conditions are satisfied.  If not, the

  97. instruction is stalled until its conditions are satisfied.  Such

  98. <em>interlock (pipeline) delay</em> causes interruption of the fetching

  99. of successor instructions (or demands nop instructions, e.g. for some

  100. MIPS processors).

  101. </p>

  102. <p>There are two major kinds of interlock delays in modern processors.

  103. The first one is a data dependence delay determining <em>instruction

  104. latency time</em>.  The instruction execution is not started until all

  105. source data have been evaluated by prior instructions (there are more

  106. complex cases when the instruction execution starts even when the data

  107. are not available but will be ready in given time after the

  108. instruction execution start).  Taking the data dependence delays into

  109. account is simple.  The data dependence (true, output, and

  110. anti-dependence) delay between two instructions is given by a

  111. constant.  In most cases this approach is adequate.  The second kind

  112. of interlock delays is a reservation delay.  The reservation delay

  113. means that two instructions under execution will be in need of shared

  114. processors resources, i.e. buses, internal registers, and/or

  115. functional units, which are reserved for some time.  Taking this kind

  116. of delay into account is complex especially for modern <acronym>RISC</acronym>

  117. processors.

  118. </p>

  119. <p>The task of exploiting more processor parallelism is solved by an

  120. instruction scheduler.  For a better solution to this problem, the

  121. instruction scheduler has to have an adequate description of the

  122. processor parallelism (or <em>pipeline description</em>).  GCC

  123. machine descriptions describe processor parallelism and functional

  124. unit reservations for groups of instructions with the aid of

  125. <em>regular expressions</em>.

  126. </p>

  127. <p>The GCC instruction scheduler uses a <em>pipeline hazard recognizer</em> to

  128. figure out the possibility of the instruction issue by the processor

  129. on a given simulated processor cycle.  The pipeline hazard recognizer is

  130. automatically generated from the processor pipeline description.  The

  131. pipeline hazard recognizer generated from the machine description

  132. is based on a deterministic finite state automaton (<acronym>DFA</acronym>):

  133. the instruction issue is possible if there is a transition from one

  134. automaton state to another one.  This algorithm is very fast, and

  135. furthermore, its speed is not dependent on processor

  136. complexity<a name="DOCF5" href="#FOOT5"><sup>5</sup></a>.

  137. </p>

  138. <a name="index-automaton-based-pipeline-description-1"></a>

  139. <p>The rest of this section describes the directives that constitute

  140. an automaton-based processor pipeline description.  The order of

  141. these constructions within the machine description file is not

  142. important.

  143. </p>

  144. <a name="index-define_005fautomaton"></a>

  145. <a name="index-pipeline-hazard-recognizer-1"></a>

  146. <p>The following optional construction describes names of automata

  147. generated and used for the pipeline hazards recognition.  Sometimes

  148. the generated finite state automaton used by the pipeline hazard

  149. recognizer is large.  If we use more than one automaton and bind functional

  150. units to the automata, the total size of the automata is usually

  151. less than the size of the single automaton.  If there is no one such

  152. construction, only one finite state automaton is generated.

  153. </p>

  154. <div class="smallexample">

  155. <pre class="smallexample">(define_automaton <var>automata-names</var>)

  156. </pre></div>

  157. 

  158. <p><var>automata-names</var> is a string giving names of the automata.  The

  159. names are separated by commas.  All the automata should have unique names.

  160. The automaton name is used in the constructions <code>define_cpu_unit</code> and

  161. <code>define_query_cpu_unit</code>.

  162. </p>

  163. <a name="index-define_005fcpu_005funit"></a>

  164. <a name="index-processor-functional-units-1"></a>

  165. <p>Each processor functional unit used in the description of instruction

  166. reservations should be described by the following construction.

  167. </p>

  168. <div class="smallexample">

  169. <pre class="smallexample">(define_cpu_unit <var>unit-names</var> [<var>automaton-name</var>])

  170. </pre></div>

  171. 

  172. <p><var>unit-names</var> is a string giving the names of the functional units

  173. separated by commas.  Don&rsquo;t use name &lsquo;<samp>nothing</samp>&rsquo;, it is reserved

  174. for other goals.

  175. </p>

  176. <p><var>automaton-name</var> is a string giving the name of the automaton with

  177. which the unit is bound.  The automaton should be described in

  178. construction <code>define_automaton</code>.  You should give

  179. <em>automaton-name</em>, if there is a defined automaton.

  180. </p>

  181. <p>The assignment of units to automata are constrained by the uses of the

  182. units in insn reservations.  The most important constraint is: if a

  183. unit reservation is present on a particular cycle of an alternative

  184. for an insn reservation, then some unit from the same automaton must

  185. be present on the same cycle for the other alternatives of the insn

  186. reservation.  The rest of the constraints are mentioned in the

  187. description of the subsequent constructions.

  188. </p>

  189. <a name="index-define_005fquery_005fcpu_005funit"></a>

  190. <a name="index-querying-function-unit-reservations"></a>

  191. <p>The following construction describes CPU functional units analogously

  192. to <code>define_cpu_unit</code>.  The reservation of such units can be

  193. queried for an automaton state.  The instruction scheduler never

  194. queries reservation of functional units for given automaton state.  So

  195. as a rule, you don&rsquo;t need this construction.  This construction could

  196. be used for future code generation goals (e.g. to generate

  197. <acronym>VLIW</acronym> insn templates).

  198. </p>

  199. <div class="smallexample">

  200. <pre class="smallexample">(define_query_cpu_unit <var>unit-names</var> [<var>automaton-name</var>])

  201. </pre></div>

  202. 

  203. <p><var>unit-names</var> is a string giving names of the functional units

  204. separated by commas.

  205. </p>

  206. <p><var>automaton-name</var> is a string giving the name of the automaton with

  207. which the unit is bound.

  208. </p>

  209. <a name="index-define_005finsn_005freservation"></a>

  210. <a name="index-instruction-latency-time-1"></a>

  211. <a name="index-regular-expressions-1"></a>

  212. <a name="index-data-bypass"></a>

  213. <p>The following construction is the major one to describe pipeline

  214. characteristics of an instruction.

  215. </p>

  216. <div class="smallexample">

  217. <pre class="smallexample">(define_insn_reservation <var>insn-name</var> <var>default_latency</var>

  218.                          <var>condition</var> <var>regexp</var>)

  219. </pre></div>

  220. 

  221. <p><var>default_latency</var> is a number giving latency time of the

  222. instruction.  There is an important difference between the old

  223. description and the automaton based pipeline description.  The latency

  224. time is used for all dependencies when we use the old description.  In

  225. the automaton based pipeline description, the given latency time is only

  226. used for true dependencies.  The cost of anti-dependencies is always

  227. zero and the cost of output dependencies is the difference between

  228. latency times of the producing and consuming insns (if the difference

  229. is negative, the cost is considered to be zero).  You can always

  230. change the default costs for any description by using the target hook

  231. <code>TARGET_SCHED_ADJUST_COST</code> (see <a href="Scheduling.html#Scheduling">Scheduling</a>).

  232. </p>

  233. <p><var>insn-name</var> is a string giving the internal name of the insn.  The

  234. internal names are used in constructions <code>define_bypass</code> and in

  235. the automaton description file generated for debugging.  The internal

  236. name has nothing in common with the names in <code>define_insn</code>.  It is a

  237. good practice to use insn classes described in the processor manual.

  238. </p>

  239. <p><var>condition</var> defines what RTL insns are described by this

  240. construction.  You should remember that you will be in trouble if

  241. <var>condition</var> for two or more different

  242. <code>define_insn_reservation</code> constructions is TRUE for an insn.  In

  243. this case what reservation will be used for the insn is not defined.

  244. Such cases are not checked during generation of the pipeline hazards

  245. recognizer because in general recognizing that two conditions may have

  246. the same value is quite difficult (especially if the conditions

  247. contain <code>symbol_ref</code>).  It is also not checked during the

  248. pipeline hazard recognizer work because it would slow down the

  249. recognizer considerably.

  250. </p>

  251. <p><var>regexp</var> is a string describing the reservation of the cpu&rsquo;s functional

  252. units by the instruction.  The reservations are described by a regular

  253. expression according to the following syntax:

  254. </p>

  255. <div class="smallexample">

  256. <pre class="smallexample">       regexp = regexp &quot;,&quot; oneof

  257.               | oneof

  258. 

  259.        oneof = oneof &quot;|&quot; allof

  260.              | allof

  261. 

  262.        allof = allof &quot;+&quot; repeat

  263.              | repeat

  264. 

  265.        repeat = element &quot;*&quot; number

  266.               | element

  267. 

  268.        element = cpu_function_unit_name

  269.                | reservation_name

  270.                | result_name

  271.                | &quot;nothing&quot;

  272.                | &quot;(&quot; regexp &quot;)&quot;

  273. </pre></div>

  274. 

  275. <ul>

  276. <li> &lsquo;<samp>,</samp>&rsquo; is used for describing the start of the next cycle in

  277. the reservation.

  278. 

  279. </li><li> &lsquo;<samp>|</samp>&rsquo; is used for describing a reservation described by the first

  280. regular expression <strong>or</strong> a reservation described by the second

  281. regular expression <strong>or</strong> etc.

  282. 

  283. </li><li> &lsquo;<samp>+</samp>&rsquo; is used for describing a reservation described by the first

  284. regular expression <strong>and</strong> a reservation described by the

  285. second regular expression <strong>and</strong> etc.

  286. 

  287. </li><li> &lsquo;<samp>*</samp>&rsquo; is used for convenience and simply means a sequence in which

  288. the regular expression are repeated <var>number</var> times with cycle

  289. advancing (see &lsquo;<samp>,</samp>&rsquo;).

  290. 

  291. </li><li> &lsquo;<samp>cpu_function_unit_name</samp>&rsquo; denotes reservation of the named

  292. functional unit.

  293. 

  294. </li><li> &lsquo;<samp>reservation_name</samp>&rsquo; &mdash; see description of construction

  295. &lsquo;<samp>define_reservation</samp>&rsquo;.

  296. 

  297. </li><li> &lsquo;<samp>nothing</samp>&rsquo; denotes no unit reservations.

  298. </li></ul>

  299. 

  300. <a name="index-define_005freservation"></a>

  301. <p>Sometimes unit reservations for different insns contain common parts.

  302. In such case, you can simplify the pipeline description by describing

  303. the common part by the following construction

  304. </p>

  305. <div class="smallexample">

  306. <pre class="smallexample">(define_reservation <var>reservation-name</var> <var>regexp</var>)

  307. </pre></div>

  308. 

  309. <p><var>reservation-name</var> is a string giving name of <var>regexp</var>.

  310. Functional unit names and reservation names are in the same name

  311. space.  So the reservation names should be different from the

  312. functional unit names and cannot be the reserved name &lsquo;<samp>nothing</samp>&rsquo;.

  313. </p>

  314. <a name="index-define_005fbypass"></a>

  315. <a name="index-instruction-latency-time-2"></a>

  316. <a name="index-data-bypass-1"></a>

  317. <p>The following construction is used to describe exceptions in the

  318. latency time for given instruction pair.  This is so called bypasses.

  319. </p>

  320. <div class="smallexample">

  321. <pre class="smallexample">(define_bypass <var>number</var> <var>out_insn_names</var> <var>in_insn_names</var>

  322.                [<var>guard</var>])

  323. </pre></div>

  324. 

  325. <p><var>number</var> defines when the result generated by the instructions

  326. given in string <var>out_insn_names</var> will be ready for the

  327. instructions given in string <var>in_insn_names</var>.  Each of these

  328. strings is a comma-separated list of filename-style globs and

  329. they refer to the names of <code>define_insn_reservation</code>s.

  330. For example:

  331. </p><div class="smallexample">

  332. <pre class="smallexample">(define_bypass 1 &quot;cpu1_load_*, cpu1_store_*&quot; &quot;cpu1_load_*&quot;)

  333. </pre></div>

  334. <p>defines a bypass between instructions that start with

  335. &lsquo;<samp>cpu1_load_</samp>&rsquo; or &lsquo;<samp>cpu1_store_</samp>&rsquo; and those that start with

  336. &lsquo;<samp>cpu1_load_</samp>&rsquo;.

  337. </p>

  338. <p><var>guard</var> is an optional string giving the name of a C function which

  339. defines an additional guard for the bypass.  The function will get the

  340. two insns as parameters.  If the function returns zero the bypass will

  341. be ignored for this case.  The additional guard is necessary to

  342. recognize complicated bypasses, e.g. when the consumer is only an address

  343. of insn &lsquo;<samp>store</samp>&rsquo; (not a stored value).

  344. </p>

  345. <p>If there are more one bypass with the same output and input insns, the

  346. chosen bypass is the first bypass with a guard in description whose

  347. guard function returns nonzero.  If there is no such bypass, then

  348. bypass without the guard function is chosen.

  349. </p>

  350. <a name="index-exclusion_005fset"></a>

  351. <a name="index-presence_005fset"></a>

  352. <a name="index-final_005fpresence_005fset"></a>

  353. <a name="index-absence_005fset"></a>

  354. <a name="index-final_005fabsence_005fset"></a>

  355. <a name="index-VLIW-1"></a>

  356. <a name="index-RISC-1"></a>

  357. <p>The following five constructions are usually used to describe

  358. <acronym>VLIW</acronym> processors, or more precisely, to describe a placement

  359. of small instructions into <acronym>VLIW</acronym> instruction slots.  They

  360. can be used for <acronym>RISC</acronym> processors, too.

  361. </p>

  362. <div class="smallexample">

  363. <pre class="smallexample">(exclusion_set <var>unit-names</var> <var>unit-names</var>)

  364. (presence_set <var>unit-names</var> <var>patterns</var>)

  365. (final_presence_set <var>unit-names</var> <var>patterns</var>)

  366. (absence_set <var>unit-names</var> <var>patterns</var>)

  367. (final_absence_set <var>unit-names</var> <var>patterns</var>)

  368. </pre></div>

  369. 

  370. <p><var>unit-names</var> is a string giving names of functional units

  371. separated by commas.

  372. </p>

  373. <p><var>patterns</var> is a string giving patterns of functional units

  374. separated by comma.  Currently pattern is one unit or units

  375. separated by white-spaces.

  376. </p>

  377. <p>The first construction (&lsquo;<samp>exclusion_set</samp>&rsquo;) means that each

  378. functional unit in the first string cannot be reserved simultaneously

  379. with a unit whose name is in the second string and vice versa.  For

  380. example, the construction is useful for describing processors

  381. (e.g. some SPARC processors) with a fully pipelined floating point

  382. functional unit which can execute simultaneously only single floating

  383. point insns or only double floating point insns.

  384. </p>

  385. <p>The second construction (&lsquo;<samp>presence_set</samp>&rsquo;) means that each

  386. functional unit in the first string cannot be reserved unless at

  387. least one of pattern of units whose names are in the second string is

  388. reserved.  This is an asymmetric relation.  For example, it is useful

  389. for description that <acronym>VLIW</acronym> &lsquo;<samp>slot1</samp>&rsquo; is reserved after

  390. &lsquo;<samp>slot0</samp>&rsquo; reservation.  We could describe it by the following

  391. construction

  392. </p>

  393. <div class="smallexample">

  394. <pre class="smallexample">(presence_set &quot;slot1&quot; &quot;slot0&quot;)

  395. </pre></div>

  396. 

  397. <p>Or &lsquo;<samp>slot1</samp>&rsquo; is reserved only after &lsquo;<samp>slot0</samp>&rsquo; and unit &lsquo;<samp>b0</samp>&rsquo;

  398. reservation.  In this case we could write

  399. </p>

  400. <div class="smallexample">

  401. <pre class="smallexample">(presence_set &quot;slot1&quot; &quot;slot0 b0&quot;)

  402. </pre></div>

  403. 

  404. <p>The third construction (&lsquo;<samp>final_presence_set</samp>&rsquo;) is analogous to

  405. &lsquo;<samp>presence_set</samp>&rsquo;.  The difference between them is when checking is

  406. done.  When an instruction is issued in given automaton state

  407. reflecting all current and planned unit reservations, the automaton

  408. state is changed.  The first state is a source state, the second one

  409. is a result state.  Checking for &lsquo;<samp>presence_set</samp>&rsquo; is done on the

  410. source state reservation, checking for &lsquo;<samp>final_presence_set</samp>&rsquo; is

  411. done on the result reservation.  This construction is useful to

  412. describe a reservation which is actually two subsequent reservations.

  413. For example, if we use

  414. </p>

  415. <div class="smallexample">

  416. <pre class="smallexample">(presence_set &quot;slot1&quot; &quot;slot0&quot;)

  417. </pre></div>

  418. 

  419. <p>the following insn will be never issued (because &lsquo;<samp>slot1</samp>&rsquo; requires

  420. &lsquo;<samp>slot0</samp>&rsquo; which is absent in the source state).

  421. </p>

  422. <div class="smallexample">

  423. <pre class="smallexample">(define_reservation &quot;insn_and_nop&quot; &quot;slot0 + slot1&quot;)

  424. </pre></div>

  425. 

  426. <p>but it can be issued if we use analogous &lsquo;<samp>final_presence_set</samp>&rsquo;.

  427. </p>

  428. <p>The forth construction (&lsquo;<samp>absence_set</samp>&rsquo;) means that each functional

  429. unit in the first string can be reserved only if each pattern of units

  430. whose names are in the second string is not reserved.  This is an

  431. asymmetric relation (actually &lsquo;<samp>exclusion_set</samp>&rsquo; is analogous to

  432. this one but it is symmetric).  For example it might be useful in a

  433. <acronym>VLIW</acronym> description to say that &lsquo;<samp>slot0</samp>&rsquo; cannot be reserved

  434. after either &lsquo;<samp>slot1</samp>&rsquo; or &lsquo;<samp>slot2</samp>&rsquo; have been reserved.  This

  435. can be described as:

  436. </p>

  437. <div class="smallexample">

  438. <pre class="smallexample">(absence_set &quot;slot0&quot; &quot;slot1, slot2&quot;)

  439. </pre></div>

  440. 

  441. <p>Or &lsquo;<samp>slot2</samp>&rsquo; cannot be reserved if &lsquo;<samp>slot0</samp>&rsquo; and unit &lsquo;<samp>b0</samp>&rsquo;

  442. are reserved or &lsquo;<samp>slot1</samp>&rsquo; and unit &lsquo;<samp>b1</samp>&rsquo; are reserved.  In

  443. this case we could write

  444. </p>

  445. <div class="smallexample">

  446. <pre class="smallexample">(absence_set &quot;slot2&quot; &quot;slot0 b0, slot1 b1&quot;)

  447. </pre></div>

  448. 

  449. <p>All functional units mentioned in a set should belong to the same

  450. automaton.

  451. </p>

  452. <p>The last construction (&lsquo;<samp>final_absence_set</samp>&rsquo;) is analogous to

  453. &lsquo;<samp>absence_set</samp>&rsquo; but checking is done on the result (state)

  454. reservation.  See comments for &lsquo;<samp>final_presence_set</samp>&rsquo;.

  455. </p>

  456. <a name="index-automata_005foption"></a>

  457. <a name="index-deterministic-finite-state-automaton-1"></a>

  458. <a name="index-nondeterministic-finite-state-automaton"></a>

  459. <a name="index-finite-state-automaton-minimization"></a>

  460. <p>You can control the generator of the pipeline hazard recognizer with

  461. the following construction.

  462. </p>

  463. <div class="smallexample">

  464. <pre class="smallexample">(automata_option <var>options</var>)

  465. </pre></div>

  466. 

  467. <p><var>options</var> is a string giving options which affect the generated

  468. code.  Currently there are the following options:

  469. </p>

  470. <ul>

  471. <li> <em>no-minimization</em> makes no minimization of the automaton.  This is

  472. only worth to do when we are debugging the description and need to

  473. look more accurately at reservations of states.

  474. 

  475. </li><li> <em>time</em> means printing time statistics about the generation of

  476. automata.

  477. 

  478. </li><li> <em>stats</em> means printing statistics about the generated automata

  479. such as the number of DFA states, NDFA states and arcs.

  480. 

  481. </li><li> <em>v</em> means a generation of the file describing the result automata.

  482. The file has suffix &lsquo;<samp>.dfa</samp>&rsquo; and can be used for the description

  483. verification and debugging.

  484. 

  485. </li><li> <em>w</em> means a generation of warning instead of error for

  486. non-critical errors.

  487. 

  488. </li><li> <em>no-comb-vect</em> prevents the automaton generator from generating

  489. two data structures and comparing them for space efficiency.  Using

  490. a comb vector to represent transitions may be better, but it can be

  491. very expensive to construct.  This option is useful if the build

  492. process spends an unacceptably long time in genautomata.

  493. 

  494. </li><li> <em>ndfa</em> makes nondeterministic finite state automata.  This affects

  495. the treatment of operator &lsquo;<samp>|</samp>&rsquo; in the regular expressions.  The

  496. usual treatment of the operator is to try the first alternative and,

  497. if the reservation is not possible, the second alternative.  The

  498. nondeterministic treatment means trying all alternatives, some of them

  499. may be rejected by reservations in the subsequent insns.

  500. 

  501. </li><li> <em>collapse-ndfa</em> modifies the behavior of the generator when

  502. producing an automaton.  An additional state transition to collapse a

  503. nondeterministic <acronym>NDFA</acronym> state to a deterministic <acronym>DFA</acronym>

  504. state is generated.  It can be triggered by passing <code>const0_rtx</code> to

  505. state_transition.  In such an automaton, cycle advance transitions are

  506. available only for these collapsed states.  This option is useful for

  507. ports that want to use the <code>ndfa</code> option, but also want to use

  508. <code>define_query_cpu_unit</code> to assign units to insns issued in a cycle.

  509. 

  510. </li><li> <em>progress</em> means output of a progress bar showing how many states

  511. were generated so far for automaton being processed.  This is useful

  512. during debugging a <acronym>DFA</acronym> description.  If you see too many

  513. generated states, you could interrupt the generator of the pipeline

  514. hazard recognizer and try to figure out a reason for generation of the

  515. huge automaton.

  516. </li></ul>

  517. 

  518. <p>As an example, consider a superscalar <acronym>RISC</acronym> machine which can

  519. issue three insns (two integer insns and one floating point insn) on

  520. the cycle but can finish only two insns.  To describe this, we define

  521. the following functional units.

  522. </p>

  523. <div class="smallexample">

  524. <pre class="smallexample">(define_cpu_unit &quot;i0_pipeline, i1_pipeline, f_pipeline&quot;)

  525. (define_cpu_unit &quot;port0, port1&quot;)

  526. </pre></div>

  527. 

  528. <p>All simple integer insns can be executed in any integer pipeline and

  529. their result is ready in two cycles.  The simple integer insns are

  530. issued into the first pipeline unless it is reserved, otherwise they

  531. are issued into the second pipeline.  Integer division and

  532. multiplication insns can be executed only in the second integer

  533. pipeline and their results are ready correspondingly in 9 and 4

  534. cycles.  The integer division is not pipelined, i.e. the subsequent

  535. integer division insn cannot be issued until the current division

  536. insn finished.  Floating point insns are fully pipelined and their

  537. results are ready in 3 cycles.  Where the result of a floating point

  538. insn is used by an integer insn, an additional delay of one cycle is

  539. incurred.  To describe all of this we could specify

  540. </p>

  541. <div class="smallexample">

  542. <pre class="smallexample">(define_cpu_unit &quot;div&quot;)

  543. 

  544. (define_insn_reservation &quot;simple&quot; 2 (eq_attr &quot;type&quot; &quot;int&quot;)

  545.                          &quot;(i0_pipeline | i1_pipeline), (port0 | port1)&quot;)

  546. 

  547. (define_insn_reservation &quot;mult&quot; 4 (eq_attr &quot;type&quot; &quot;mult&quot;)

  548.                          &quot;i1_pipeline, nothing*2, (port0 | port1)&quot;)

  549. 

  550. (define_insn_reservation &quot;div&quot; 9 (eq_attr &quot;type&quot; &quot;div&quot;)

  551.                          &quot;i1_pipeline, div*7, div + (port0 | port1)&quot;)

  552. 

  553. (define_insn_reservation &quot;float&quot; 3 (eq_attr &quot;type&quot; &quot;float&quot;)

  554.                          &quot;f_pipeline, nothing, (port0 | port1))

  555. 

  556. (define_bypass 4 &quot;float&quot; &quot;simple,mult,div&quot;)

  557. </pre></div>

  558. 

  559. <p>To simplify the description we could describe the following reservation

  560. </p>

  561. <div class="smallexample">

  562. <pre class="smallexample">(define_reservation &quot;finish&quot; &quot;port0|port1&quot;)

  563. </pre></div>

  564. 

  565. <p>and use it in all <code>define_insn_reservation</code> as in the following

  566. construction

  567. </p>

  568. <div class="smallexample">

  569. <pre class="smallexample">(define_insn_reservation &quot;simple&quot; 2 (eq_attr &quot;type&quot; &quot;int&quot;)

  570.                          &quot;(i0_pipeline | i1_pipeline), finish&quot;)

  571. </pre></div>

  572. 

  573. 

  574. <div class="footnote">

  575. <hr>

  576. <h4 class="footnotes-heading">Footnotes</h4>

  577. 

  578. <h3><a name="FOOT5" href="#DOCF5">(5)</a></h3>

  579. <p>However, the size of the automaton depends on

  580. processor complexity.  To limit this effect, machine descriptions

  581. can split orthogonal parts of the machine description among several

  582. automata: but then, since each of these must be stepped independently,

  583. this does cause a small decrease in the algorithm&rsquo;s performance.</p>

  584. </div>

  585. <hr>

  586. <div class="header">

  587. <p>

  588. Previous: <a href="Delay-Slots.html#Delay-Slots" accesskey="p" rel="prev">Delay Slots</a>, Up: <a href="Insn-Attributes.html#Insn-Attributes" accesskey="u" rel="up">Insn Attributes</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>

  589. </div>

  590. 

  591. 

  592. 

  593. </body>

  594. </html>