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- <a name="define_005fpeephole2"></a>
- <div class="header">
- <p>
- Previous: <a href="define_005fpeephole.html#define_005fpeephole" accesskey="p" rel="prev">define_peephole</a>, Up: <a href="Peephole-Definitions.html#Peephole-Definitions" accesskey="u" rel="up">Peephole Definitions</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
- </div>
- <hr>
- <a name="RTL-to-RTL-Peephole-Optimizers"></a>
- <h4 class="subsection">17.18.2 RTL to RTL Peephole Optimizers</h4>
- <a name="index-define_005fpeephole2"></a>
-
- <p>The <code>define_peephole2</code> definition tells the compiler how to
- substitute one sequence of instructions for another sequence,
- what additional scratch registers may be needed and what their
- lifetimes must be.
- </p>
- <div class="smallexample">
- <pre class="smallexample">(define_peephole2
- [<var>insn-pattern-1</var>
- <var>insn-pattern-2</var>
- …]
- "<var>condition</var>"
- [<var>new-insn-pattern-1</var>
- <var>new-insn-pattern-2</var>
- …]
- "<var>preparation-statements</var>")
- </pre></div>
-
- <p>The definition is almost identical to <code>define_split</code>
- (see <a href="Insn-Splitting.html#Insn-Splitting">Insn Splitting</a>) except that the pattern to match is not a
- single instruction, but a sequence of instructions.
- </p>
- <p>It is possible to request additional scratch registers for use in the
- output template. If appropriate registers are not free, the pattern
- will simply not match.
- </p>
- <a name="index-match_005fscratch-1"></a>
- <a name="index-match_005fdup-1"></a>
- <p>Scratch registers are requested with a <code>match_scratch</code> pattern at
- the top level of the input pattern. The allocated register (initially) will
- be dead at the point requested within the original sequence. If the scratch
- is used at more than a single point, a <code>match_dup</code> pattern at the
- top level of the input pattern marks the last position in the input sequence
- at which the register must be available.
- </p>
- <p>Here is an example from the IA-32 machine description:
- </p>
- <div class="smallexample">
- <pre class="smallexample">(define_peephole2
- [(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "register_operand" "")
- (match_operator:SI 3 "arith_or_logical_operator"
- [(match_dup 0)
- (match_operand:SI 1 "memory_operand" "")]))
- (clobber (reg:CC 17))])]
- "! optimize_size && ! TARGET_READ_MODIFY"
- [(set (match_dup 2) (match_dup 1))
- (parallel [(set (match_dup 0)
- (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
- (clobber (reg:CC 17))])]
- "")
- </pre></div>
-
- <p>This pattern tries to split a load from its use in the hopes that we’ll be
- able to schedule around the memory load latency. It allocates a single
- <code>SImode</code> register of class <code>GENERAL_REGS</code> (<code>"r"</code>) that needs
- to be live only at the point just before the arithmetic.
- </p>
- <p>A real example requiring extended scratch lifetimes is harder to come by,
- so here’s a silly made-up example:
- </p>
- <div class="smallexample">
- <pre class="smallexample">(define_peephole2
- [(match_scratch:SI 4 "r")
- (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
- (set (match_operand:SI 2 "" "") (match_dup 1))
- (match_dup 4)
- (set (match_operand:SI 3 "" "") (match_dup 1))]
- "/* <span class="roman">determine 1 does not overlap 0 and 2</span> */"
- [(set (match_dup 4) (match_dup 1))
- (set (match_dup 0) (match_dup 4))
- (set (match_dup 2) (match_dup 4))
- (set (match_dup 3) (match_dup 4))]
- "")
- </pre></div>
-
- <p>There are two special macros defined for use in the preparation statements:
- <code>DONE</code> and <code>FAIL</code>. Use them with a following semicolon,
- as a statement.
- </p>
- <dl compact="compact">
- <dd>
- <a name="index-DONE-2"></a>
- </dd>
- <dt><code>DONE</code></dt>
- <dd><p>Use the <code>DONE</code> macro to end RTL generation for the peephole. The
- only RTL insns generated as replacement for the matched input insn will
- be those already emitted by explicit calls to <code>emit_insn</code> within
- the preparation statements; the replacement pattern is not used.
- </p>
- <a name="index-FAIL-2"></a>
- </dd>
- <dt><code>FAIL</code></dt>
- <dd><p>Make the <code>define_peephole2</code> fail on this occasion. When a <code>define_peephole2</code>
- fails, it means that the replacement was not truly available for the
- particular inputs it was given. In that case, GCC may still apply a
- later <code>define_peephole2</code> that also matches the given insn pattern.
- (Note that this is different from <code>define_split</code>, where <code>FAIL</code>
- prevents the input insn from being split at all.)
- </p></dd>
- </dl>
-
- <p>If the preparation falls through (invokes neither <code>DONE</code> nor
- <code>FAIL</code>), then the <code>define_peephole2</code> uses the replacement
- template.
- </p>
- <p>If we had not added the <code>(match_dup 4)</code> in the middle of the input
- sequence, it might have been the case that the register we chose at the
- beginning of the sequence is killed by the first or second <code>set</code>.
- </p>
- <hr>
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- <p>
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