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- <h4 class="subsection">G.5.8 NDS32 Features</h4>
- <a name="index-target-descriptions_002c-NDS32-features"></a>
-
- <p>The ‘<samp>org.gnu.gdb.nds32.core</samp>’ feature is required for NDS32
- targets. It should contain at least registers ‘<samp>r0</samp>’ through
- ‘<samp>r10</samp>’, ‘<samp>r15</samp>’, ‘<samp>fp</samp>’, ‘<samp>gp</samp>’, ‘<samp>lp</samp>’, ‘<samp>sp</samp>’,
- and ‘<samp>pc</samp>’.
- </p>
- <p>The ‘<samp>org.gnu.gdb.nds32.fpu</samp>’ feature is optional. If present,
- it should contain 64-bit double-precision floating-point registers
- ‘<samp>fd0</samp>’ through <em>fdN</em>, which should be ‘<samp>fd3</samp>’, ‘<samp>fd7</samp>’,
- ‘<samp>fd15</samp>’, or ‘<samp>fd31</samp>’ based on the FPU configuration implemented.
- </p>
- <p><em>Note:</em> The first sixteen 64-bit double-precision floating-point
- registers are overlapped with the thirty-two 32-bit single-precision
- floating-point registers. The 32-bit single-precision registers, if
- not being listed explicitly, will be synthesized from halves of the
- overlapping 64-bit double-precision registers. Listing 32-bit
- single-precision registers explicitly is deprecated, and the
- support to it could be totally removed some day.
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