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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

  2. <html>

  3. <!-- This file documents the GNU linker LD

  4. (GNU Arm Embedded Toolchain 10-2020-q4-major)

  5. version 2.35.1.

  6. 

  7. Copyright (C) 1991-2020 Free Software Foundation, Inc.

  8. 

  9. Permission is granted to copy, distribute and/or modify this document

  10. under the terms of the GNU Free Documentation License, Version 1.3

  11. or any later version published by the Free Software Foundation;

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  16. <head>

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  18. <title>ARM (LD)</title>

  19. 

  20. <meta name="description" content="ARM (LD)">

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  25. <link href="index.html#Top" rel="start" title="Top">

  26. <link href="LD-Index.html#LD-Index" rel="index" title="LD Index">

  27. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  28. <link href="Machine-Dependent.html#Machine-Dependent" rel="up" title="Machine Dependent">

  29. <link href="HPPA-ELF32.html#HPPA-ELF32" rel="next" title="HPPA ELF32">

  30. <link href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" rel="prev" title="M68HC11/68HC12">

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  58. 

  59. 

  60. </head>

  61. 

  62. <body lang="en">

  63. <a name="ARM"></a>

  64. <div class="header">

  65. <p>

  66. Next: <a href="HPPA-ELF32.html#HPPA-ELF32" accesskey="n" rel="next">HPPA ELF32</a>, Previous: <a href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" accesskey="p" rel="prev">M68HC11/68HC12</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p>

  67. </div>

  68. <hr>

  69. <a name="ld-and-the-ARM-family"></a>

  70. <h3 class="section">4.3 <code>ld</code> and the ARM family</h3>

  71. 

  72. <a name="index-ARM-interworking-support"></a>

  73. <a name="index-_002d_002dsupport_002dold_002dcode"></a>

  74. <p>For the ARM, <code>ld</code> will generate code stubs to allow functions calls

  75. between ARM and Thumb code.  These stubs only work with code that has

  76. been compiled and assembled with the &lsquo;<samp>-mthumb-interwork</samp>&rsquo; command

  77. line option.  If it is necessary to link with old ARM object files or

  78. libraries, which have not been compiled with the -mthumb-interwork

  79. option then the &lsquo;<samp>--support-old-code</samp>&rsquo; command-line switch should be

  80. given to the linker.  This will make it generate larger stub functions

  81. which will work with non-interworking aware ARM code.  Note, however,

  82. the linker does not support generating stubs for function calls to

  83. non-interworking aware Thumb code.

  84. </p>

  85. <a name="index-thumb-entry-point"></a>

  86. <a name="index-entry-point_002c-thumb"></a>

  87. <a name="index-_002d_002dthumb_002dentry_003dentry"></a>

  88. <p>The &lsquo;<samp>--thumb-entry</samp>&rsquo; switch is a duplicate of the generic

  89. &lsquo;<samp>--entry</samp>&rsquo; switch, in that it sets the program&rsquo;s starting address.

  90. But it also sets the bottom bit of the address, so that it can be

  91. branched to using a BX instruction, and the program will start

  92. executing in Thumb mode straight away.

  93. </p>

  94. <a name="index-PE-import-table-prefixing"></a>

  95. <a name="index-_002d_002duse_002dnul_002dprefixed_002dimport_002dtables"></a>

  96. <p>The &lsquo;<samp>--use-nul-prefixed-import-tables</samp>&rsquo; switch is specifying, that

  97. the import tables idata4 and idata5 have to be generated with a zero

  98. element prefix for import libraries. This is the old style to generate

  99. import tables. By default this option is turned off.

  100. </p>

  101. <a name="index-BE8"></a>

  102. <a name="index-_002d_002dbe8"></a>

  103. <p>The &lsquo;<samp>--be8</samp>&rsquo; switch instructs <code>ld</code> to generate BE8 format

  104. executables.  This option is only valid when linking big-endian

  105. objects - ie ones which have been assembled with the <samp>-EB</samp>

  106. option.  The resulting image will contain big-endian data and

  107. little-endian code.

  108. </p>

  109. <a name="index-TARGET1"></a>

  110. <a name="index-_002d_002dtarget1_002drel"></a>

  111. <a name="index-_002d_002dtarget1_002dabs"></a>

  112. <p>The &lsquo;<samp>R_ARM_TARGET1</samp>&rsquo; relocation is typically used for entries in the

  113. &lsquo;<samp>.init_array</samp>&rsquo; section.  It is interpreted as either &lsquo;<samp>R_ARM_REL32</samp>&rsquo;

  114. or &lsquo;<samp>R_ARM_ABS32</samp>&rsquo;, depending on the target.  The &lsquo;<samp>--target1-rel</samp>&rsquo;

  115. and &lsquo;<samp>--target1-abs</samp>&rsquo; switches override the default.

  116. </p>

  117. <a name="index-TARGET2"></a>

  118. <a name="index-_002d_002dtarget2_003dtype"></a>

  119. <p>The &lsquo;<samp>--target2=type</samp>&rsquo; switch overrides the default definition of the

  120. &lsquo;<samp>R_ARM_TARGET2</samp>&rsquo; relocation.  Valid values for &lsquo;<samp>type</samp>&rsquo;, their

  121. meanings, and target defaults are as follows:

  122. </p><dl compact="compact">

  123. <dt>&lsquo;<samp>rel</samp>&rsquo;</dt>

  124. <dd><p>&lsquo;<samp>R_ARM_REL32</samp>&rsquo; (arm*-*-elf, arm*-*-eabi)

  125. </p></dd>

  126. <dt>&lsquo;<samp>abs</samp>&rsquo;</dt>

  127. <dd><p>&lsquo;<samp>R_ARM_ABS32</samp>&rsquo; (arm*-*-symbianelf)

  128. </p></dd>

  129. <dt>&lsquo;<samp>got-rel</samp>&rsquo;</dt>

  130. <dd><p>&lsquo;<samp>R_ARM_GOT_PREL</samp>&rsquo; (arm*-*-linux, arm*-*-*bsd)

  131. </p></dd>

  132. </dl>

  133. 

  134. <a name="index-FIX_005fV4BX"></a>

  135. <a name="index-_002d_002dfix_002dv4bx"></a>

  136. <p>The &lsquo;<samp>R_ARM_V4BX</samp>&rsquo; relocation (defined by the ARM AAELF

  137. specification) enables objects compiled for the ARMv4 architecture to be

  138. interworking-safe when linked with other objects compiled for ARMv4t, but

  139. also allows pure ARMv4 binaries to be built from the same ARMv4 objects.

  140. </p>

  141. <p>In the latter case, the switch <samp>--fix-v4bx</samp> must be passed to the

  142. linker, which causes v4t <code>BX rM</code> instructions to be rewritten as

  143. <code>MOV PC,rM</code>, since v4 processors do not have a <code>BX</code> instruction.

  144. </p>

  145. <p>In the former case, the switch should not be used, and &lsquo;<samp>R_ARM_V4BX</samp>&rsquo;

  146. relocations are ignored.

  147. </p>

  148. <a name="index-FIX_005fV4BX_005fINTERWORKING"></a>

  149. <a name="index-_002d_002dfix_002dv4bx_002dinterworking"></a>

  150. <p>Replace <code>BX rM</code> instructions identified by &lsquo;<samp>R_ARM_V4BX</samp>&rsquo;

  151. relocations with a branch to the following veneer:

  152. </p>

  153. <div class="smallexample">

  154. <pre class="smallexample">TST rM, #1

  155. MOVEQ PC, rM

  156. BX Rn

  157. </pre></div>

  158. 

  159. <p>This allows generation of libraries/applications that work on ARMv4 cores

  160. and are still interworking safe.  Note that the above veneer clobbers the

  161. condition flags, so may cause incorrect program behavior in rare cases.

  162. </p>

  163. <a name="index-USE_005fBLX"></a>

  164. <a name="index-_002d_002duse_002dblx"></a>

  165. <p>The &lsquo;<samp>--use-blx</samp>&rsquo; switch enables the linker to use ARM/Thumb

  166. BLX instructions (available on ARMv5t and above) in various

  167. situations. Currently it is used to perform calls via the PLT from Thumb

  168. code using BLX rather than using BX and a mode-switching stub before

  169. each PLT entry. This should lead to such calls executing slightly faster.

  170. </p>

  171. <p>This option is enabled implicitly for SymbianOS, so there is no need to

  172. specify it if you are using that target.

  173. </p>

  174. <a name="index-VFP11_005fDENORM_005fFIX"></a>

  175. <a name="index-_002d_002dvfp11_002ddenorm_002dfix"></a>

  176. <p>The &lsquo;<samp>--vfp11-denorm-fix</samp>&rsquo; switch enables a link-time workaround for a

  177. bug in certain VFP11 coprocessor hardware, which sometimes allows

  178. instructions with denorm operands (which must be handled by support code)

  179. to have those operands overwritten by subsequent instructions before

  180. the support code can read the intended values.

  181. </p>

  182. <p>The bug may be avoided in scalar mode if you allow at least one

  183. intervening instruction between a VFP11 instruction which uses a register

  184. and another instruction which writes to the same register, or at least two

  185. intervening instructions if vector mode is in use. The bug only affects

  186. full-compliance floating-point mode: you do not need this workaround if

  187. you are using &quot;runfast&quot; mode. Please contact ARM for further details.

  188. </p>

  189. <p>If you know you are using buggy VFP11 hardware, you can

  190. enable this workaround by specifying the linker option

  191. &lsquo;<samp>--vfp-denorm-fix=scalar</samp>&rsquo; if you are using the VFP11 scalar

  192. mode only, or &lsquo;<samp>--vfp-denorm-fix=vector</samp>&rsquo; if you are using

  193. vector mode (the latter also works for scalar code). The default is

  194. &lsquo;<samp>--vfp-denorm-fix=none</samp>&rsquo;.

  195. </p>

  196. <p>If the workaround is enabled, instructions are scanned for

  197. potentially-troublesome sequences, and a veneer is created for each

  198. such sequence which may trigger the erratum. The veneer consists of the

  199. first instruction of the sequence and a branch back to the subsequent

  200. instruction. The original instruction is then replaced with a branch to

  201. the veneer. The extra cycles required to call and return from the veneer

  202. are sufficient to avoid the erratum in both the scalar and vector cases.

  203. </p>

  204. <a name="index-ARM1176-erratum-workaround"></a>

  205. <a name="index-_002d_002dfix_002darm1176"></a>

  206. <a name="index-_002d_002dno_002dfix_002darm1176"></a>

  207. <p>The &lsquo;<samp>--fix-arm1176</samp>&rsquo; switch enables a link-time workaround for an erratum

  208. in certain ARM1176 processors.  The workaround is enabled by default if you

  209. are targeting ARM v6 (excluding ARM v6T2) or earlier.  It can be disabled

  210. unconditionally by specifying &lsquo;<samp>--no-fix-arm1176</samp>&rsquo;.

  211. </p>

  212. <p>Further information is available in the &ldquo;ARM1176JZ-S and ARM1176JZF-S

  213. Programmer Advice Notice&rdquo; available on the ARM documentation website at:

  214. http://infocenter.arm.com/.

  215. </p>

  216. <a name="index-STM32L4xx-erratum-workaround"></a>

  217. <a name="index-_002d_002dfix_002dstm32l4xx_002d629360"></a>

  218. 

  219. <p>The &lsquo;<samp>--fix-stm32l4xx-629360</samp>&rsquo; switch enables a link-time

  220. workaround for a bug in the bus matrix / memory controller for some of

  221. the STM32 Cortex-M4 based products (STM32L4xx).  When accessing

  222. off-chip memory via the affected bus for bus reads of 9 words or more,

  223. the bus can generate corrupt data and/or abort.  These are only

  224. core-initiated accesses (not DMA), and might affect any access:

  225. integer loads such as LDM, POP and floating-point loads such as VLDM,

  226. VPOP.  Stores are not affected.

  227. </p>

  228. <p>The bug can be avoided by splitting memory accesses into the

  229. necessary chunks to keep bus reads below 8 words.

  230. </p>

  231. <p>The workaround is not enabled by default, this is equivalent to use

  232. &lsquo;<samp>--fix-stm32l4xx-629360=none</samp>&rsquo;.  If you know you are using buggy

  233. STM32L4xx hardware, you can enable the workaround by specifying the

  234. linker option &lsquo;<samp>--fix-stm32l4xx-629360</samp>&rsquo;, or the equivalent

  235. &lsquo;<samp>--fix-stm32l4xx-629360=default</samp>&rsquo;.

  236. </p>

  237. <p>If the workaround is enabled, instructions are scanned for

  238. potentially-troublesome sequences, and a veneer is created for each

  239. such sequence which may trigger the erratum.  The veneer consists in a

  240. replacement sequence emulating the behaviour of the original one and a

  241. branch back to the subsequent instruction.  The original instruction is

  242. then replaced with a branch to the veneer.

  243. </p>

  244. <p>The workaround does not always preserve the memory access order for

  245. the LDMDB instruction, when the instruction loads the PC.

  246. </p>

  247. <p>The workaround is not able to handle problematic instructions when

  248. they are in the middle of an IT block, since a branch is not allowed

  249. there.  In that case, the linker reports a warning and no replacement

  250. occurs.

  251. </p>

  252. <p>The workaround is not able to replace problematic instructions with a

  253. PC-relative branch instruction if the &lsquo;<samp>.text</samp>&rsquo; section is too

  254. large.  In that case, when the branch that replaces the original code

  255. cannot be encoded, the linker reports a warning and no replacement

  256. occurs.

  257. </p>

  258. <a name="index-NO_005fENUM_005fSIZE_005fWARNING"></a>

  259. <a name="index-_002d_002dno_002denum_002dsize_002dwarning"></a>

  260. <p>The <samp>--no-enum-size-warning</samp> switch prevents the linker from

  261. warning when linking object files that specify incompatible EABI

  262. enumeration size attributes.  For example, with this switch enabled,

  263. linking of an object file using 32-bit enumeration values with another

  264. using enumeration values fitted into the smallest possible space will

  265. not be diagnosed.

  266. </p>

  267. <a name="index-NO_005fWCHAR_005fSIZE_005fWARNING"></a>

  268. <a name="index-_002d_002dno_002dwchar_002dsize_002dwarning"></a>

  269. <p>The <samp>--no-wchar-size-warning</samp> switch prevents the linker from

  270. warning when linking object files that specify incompatible EABI

  271. <code>wchar_t</code> size attributes.  For example, with this switch enabled,

  272. linking of an object file using 32-bit <code>wchar_t</code> values with another

  273. using 16-bit <code>wchar_t</code> values will not be diagnosed.

  274. </p>

  275. <a name="index-PIC_005fVENEER"></a>

  276. <a name="index-_002d_002dpic_002dveneer"></a>

  277. <p>The &lsquo;<samp>--pic-veneer</samp>&rsquo; switch makes the linker use PIC sequences for

  278. ARM/Thumb interworking veneers, even if the rest of the binary

  279. is not PIC.  This avoids problems on uClinux targets where

  280. &lsquo;<samp>--emit-relocs</samp>&rsquo; is used to generate relocatable binaries.

  281. </p>

  282. <a name="index-STUB_005fGROUP_005fSIZE"></a>

  283. <a name="index-_002d_002dstub_002dgroup_002dsize_003dN"></a>

  284. <p>The linker will automatically generate and insert small sequences of

  285. code into a linked ARM ELF executable whenever an attempt is made to

  286. perform a function call to a symbol that is too far away.  The

  287. placement of these sequences of instructions - called stubs - is

  288. controlled by the command-line option <samp>--stub-group-size=N</samp>.

  289. The placement is important because a poor choice can create a need for

  290. duplicate stubs, increasing the code size.  The linker will try to

  291. group stubs together in order to reduce interruptions to the flow of

  292. code, but it needs guidance as to how big these groups should be and

  293. where they should be placed.

  294. </p>

  295. <p>The value of &lsquo;<samp>N</samp>&rsquo;, the parameter to the

  296. <samp>--stub-group-size=</samp> option controls where the stub groups are

  297. placed.  If it is negative then all stubs are placed after the first

  298. branch that needs them.  If it is positive then the stubs can be

  299. placed either before or after the branches that need them.  If the

  300. value of &lsquo;<samp>N</samp>&rsquo; is 1 (either +1 or -1) then the linker will choose

  301. exactly where to place groups of stubs, using its built in heuristics.

  302. A value of &lsquo;<samp>N</samp>&rsquo; greater than 1 (or smaller than -1) tells the

  303. linker that a single group of stubs can service at most &lsquo;<samp>N</samp>&rsquo; bytes

  304. from the input sections.

  305. </p>

  306. <p>The default, if <samp>--stub-group-size=</samp> is not specified, is

  307. &lsquo;<samp>N = +1</samp>&rsquo;.

  308. </p>

  309. <p>Farcalls stubs insertion is fully supported for the ARM-EABI target

  310. only, because it relies on object files properties not present

  311. otherwise.

  312. </p>

  313. <a name="index-Cortex_002dA8-erratum-workaround"></a>

  314. <a name="index-_002d_002dfix_002dcortex_002da8"></a>

  315. <a name="index-_002d_002dno_002dfix_002dcortex_002da8"></a>

  316. <p>The &lsquo;<samp>--fix-cortex-a8</samp>&rsquo; switch enables a link-time workaround for an erratum in certain Cortex-A8 processors.  The workaround is enabled by default if you are targeting the ARM v7-A architecture profile.  It can be enabled otherwise by specifying &lsquo;<samp>--fix-cortex-a8</samp>&rsquo;, or disabled unconditionally by specifying &lsquo;<samp>--no-fix-cortex-a8</samp>&rsquo;.

  317. </p>

  318. <p>The erratum only affects Thumb-2 code.  Please contact ARM for further details.

  319. </p>

  320. <a name="index-Cortex_002dA53-erratum-835769-workaround"></a>

  321. <a name="index-_002d_002dfix_002dcortex_002da53_002d835769"></a>

  322. <a name="index-_002d_002dno_002dfix_002dcortex_002da53_002d835769"></a>

  323. <p>The &lsquo;<samp>--fix-cortex-a53-835769</samp>&rsquo; switch enables a link-time workaround for erratum 835769 present on certain early revisions of Cortex-A53 processors.  The workaround is disabled by default.  It can be enabled by specifying &lsquo;<samp>--fix-cortex-a53-835769</samp>&rsquo;, or disabled unconditionally by specifying &lsquo;<samp>--no-fix-cortex-a53-835769</samp>&rsquo;.

  324. </p>

  325. <p>Please contact ARM for further details.

  326. </p>

  327. <a name="index-_002d_002dmerge_002dexidx_002dentries"></a>

  328. <a name="index-_002d_002dno_002dmerge_002dexidx_002dentries-1"></a>

  329. <a name="index-Merging-exidx-entries"></a>

  330. <p>The &lsquo;<samp>--no-merge-exidx-entries</samp>&rsquo; switch disables the merging of adjacent exidx entries in debuginfo.

  331. </p>

  332. <a name="index-_002d_002dlong_002dplt"></a>

  333. <a name="index-32_002dbit-PLT-entries"></a>

  334. <p>The &lsquo;<samp>--long-plt</samp>&rsquo; option enables the use of 16 byte PLT entries

  335. which support up to 4Gb of code.  The default is to use 12 byte PLT

  336. entries which only support 512Mb of code.

  337. </p>

  338. <a name="index-_002d_002dno_002dapply_002ddynamic_002drelocs"></a>

  339. <a name="index-AArch64-rela-addend"></a>

  340. <p>The &lsquo;<samp>--no-apply-dynamic-relocs</samp>&rsquo; option makes AArch64 linker do not apply

  341. link-time values for dynamic relocations.

  342. </p>

  343. <a name="index-Placement-of-SG-veneers"></a>

  344. <p>All SG veneers are placed in the special output section <code>.gnu.sgstubs</code>.

  345. Its start address must be set, either with the command-line option

  346. &lsquo;<samp>--section-start</samp>&rsquo; or in a linker script, to indicate where to place these

  347. veneers in memory.

  348. </p>

  349. <a name="index-_002d_002dcmse_002dimplib"></a>

  350. <a name="index-Secure-gateway-import-library"></a>

  351. <p>The &lsquo;<samp>--cmse-implib</samp>&rsquo; option requests that the import libraries

  352. specified by the &lsquo;<samp>--out-implib</samp>&rsquo; and &lsquo;<samp>--in-implib</samp>&rsquo; options are

  353. secure gateway import libraries, suitable for linking a non-secure

  354. executable against secure code as per ARMv8-M Security Extensions.

  355. </p>

  356. <a name="index-_002d_002din_002dimplib_003dfile"></a>

  357. <a name="index-Input-import-library"></a>

  358. <p>The &lsquo;<samp>--in-implib=file</samp>&rsquo; specifies an input import library whose symbols

  359. must keep the same address in the executable being produced.  A warning is

  360. given if no &lsquo;<samp>--out-implib</samp>&rsquo; is given but new symbols have been introduced

  361. in the executable that should be listed in its import library.  Otherwise, if

  362. &lsquo;<samp>--out-implib</samp>&rsquo; is specified, the symbols are added to the output import

  363. library.  A warning is also given if some symbols present in the input import

  364. library have disappeared from the executable.  This option is only effective

  365. for Secure Gateway import libraries, ie. when &lsquo;<samp>--cmse-implib</samp>&rsquo; is

  366. specified.

  367. </p>

  368. 

  369. 

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