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toolchain-gcc-arm-embedded/lib/gcc/arm-none-eabi/10.2.1/plugin/include/genrtl.h

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  1. /* Generated automatically by gengenrtl from rtl.def.  */

  2. 

  3. #ifndef GCC_GENRTL_H

  4. #define GCC_GENRTL_H

  5. 

  6. #include "statistics.h"

  7. 

  8. static inline rtx

  9. init_rtx_fmt_0 (rtx rt, machine_mode mode)

  10. {

  11.   PUT_MODE_RAW (rt, mode);

  12.   X0EXP (rt, 0) = NULL_RTX;

  13.   return rt;

  14. }

  15. 

  16. static inline rtx

  17. gen_rtx_fmt_0_stat (RTX_CODE code, machine_mode mode MEM_STAT_DECL)

  18. {

  19.   rtx rt;

  20. 

  21.   rt = rtx_alloc (code PASS_MEM_STAT);

  22.   return init_rtx_fmt_0 (rt, mode);

  23. }

  24. 

  25. #define gen_rtx_fmt_0(c, m) \

  26.   gen_rtx_fmt_0_stat ((c), (m) MEM_STAT_INFO)

  27. 

  28. #define alloca_rtx_fmt_0(c, m) \

  29.   init_rtx_fmt_0 (rtx_alloca ((c)), (m))

  30. 

  31. static inline rtx

  32. init_rtx_fmt_ee (rtx rt, machine_mode mode,

  33. 	rtx arg0,

  34. 	rtx arg1)

  35. {

  36.   PUT_MODE_RAW (rt, mode);

  37.   XEXP (rt, 0) = arg0;

  38.   XEXP (rt, 1) = arg1;

  39.   return rt;

  40. }

  41. 

  42. static inline rtx

  43. gen_rtx_fmt_ee_stat (RTX_CODE code, machine_mode mode,

  44. 	rtx arg0,

  45. 	rtx arg1 MEM_STAT_DECL)

  46. {

  47.   rtx rt;

  48. 

  49.   rt = rtx_alloc (code PASS_MEM_STAT);

  50.   return init_rtx_fmt_ee (rt, mode, arg0, arg1);

  51. }

  52. 

  53. #define gen_rtx_fmt_ee(c, m, arg0, arg1) \

  54.   gen_rtx_fmt_ee_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  55. 

  56. #define alloca_rtx_fmt_ee(c, m, arg0, arg1) \

  57.   init_rtx_fmt_ee (rtx_alloca ((c)), (m), (arg0), (arg1))

  58. 

  59. static inline rtx

  60. init_rtx_fmt_ue (rtx rt, machine_mode mode,

  61. 	rtx arg0,

  62. 	rtx arg1)

  63. {

  64.   PUT_MODE_RAW (rt, mode);

  65.   XEXP (rt, 0) = arg0;

  66.   XEXP (rt, 1) = arg1;

  67.   return rt;

  68. }

  69. 

  70. static inline rtx

  71. gen_rtx_fmt_ue_stat (RTX_CODE code, machine_mode mode,

  72. 	rtx arg0,

  73. 	rtx arg1 MEM_STAT_DECL)

  74. {

  75.   rtx rt;

  76. 

  77.   rt = rtx_alloc (code PASS_MEM_STAT);

  78.   return init_rtx_fmt_ue (rt, mode, arg0, arg1);

  79. }

  80. 

  81. #define gen_rtx_fmt_ue(c, m, arg0, arg1) \

  82.   gen_rtx_fmt_ue_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  83. 

  84. #define alloca_rtx_fmt_ue(c, m, arg0, arg1) \

  85.   init_rtx_fmt_ue (rtx_alloca ((c)), (m), (arg0), (arg1))

  86. 

  87. static inline rtx

  88. init_rtx_fmt_ie (rtx rt, machine_mode mode,

  89. 	int arg0,

  90. 	rtx arg1)

  91. {

  92.   PUT_MODE_RAW (rt, mode);

  93.   XINT (rt, 0) = arg0;

  94.   XEXP (rt, 1) = arg1;

  95.   return rt;

  96. }

  97. 

  98. static inline rtx

  99. gen_rtx_fmt_ie_stat (RTX_CODE code, machine_mode mode,

  100. 	int arg0,

  101. 	rtx arg1 MEM_STAT_DECL)

  102. {

  103.   rtx rt;

  104. 

  105.   rt = rtx_alloc (code PASS_MEM_STAT);

  106.   return init_rtx_fmt_ie (rt, mode, arg0, arg1);

  107. }

  108. 

  109. #define gen_rtx_fmt_ie(c, m, arg0, arg1) \

  110.   gen_rtx_fmt_ie_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  111. 

  112. #define alloca_rtx_fmt_ie(c, m, arg0, arg1) \

  113.   init_rtx_fmt_ie (rtx_alloca ((c)), (m), (arg0), (arg1))

  114. 

  115. static inline rtx

  116. init_rtx_fmt_E (rtx rt, machine_mode mode,

  117. 	rtvec arg0)

  118. {

  119.   PUT_MODE_RAW (rt, mode);

  120.   XVEC (rt, 0) = arg0;

  121.   return rt;

  122. }

  123. 

  124. static inline rtx

  125. gen_rtx_fmt_E_stat (RTX_CODE code, machine_mode mode,

  126. 	rtvec arg0 MEM_STAT_DECL)

  127. {

  128.   rtx rt;

  129. 

  130.   rt = rtx_alloc (code PASS_MEM_STAT);

  131.   return init_rtx_fmt_E (rt, mode, arg0);

  132. }

  133. 

  134. #define gen_rtx_fmt_E(c, m, arg0) \

  135.   gen_rtx_fmt_E_stat ((c), (m), (arg0) MEM_STAT_INFO)

  136. 

  137. #define alloca_rtx_fmt_E(c, m, arg0) \

  138.   init_rtx_fmt_E (rtx_alloca ((c)), (m), (arg0))

  139. 

  140. static inline rtx

  141. init_rtx_fmt_i (rtx rt, machine_mode mode,

  142. 	int arg0)

  143. {

  144.   PUT_MODE_RAW (rt, mode);

  145.   XINT (rt, 0) = arg0;

  146.   return rt;

  147. }

  148. 

  149. static inline rtx

  150. gen_rtx_fmt_i_stat (RTX_CODE code, machine_mode mode,

  151. 	int arg0 MEM_STAT_DECL)

  152. {

  153.   rtx rt;

  154. 

  155.   rt = rtx_alloc (code PASS_MEM_STAT);

  156.   return init_rtx_fmt_i (rt, mode, arg0);

  157. }

  158. 

  159. #define gen_rtx_fmt_i(c, m, arg0) \

  160.   gen_rtx_fmt_i_stat ((c), (m), (arg0) MEM_STAT_INFO)

  161. 

  162. #define alloca_rtx_fmt_i(c, m, arg0) \

  163.   init_rtx_fmt_i (rtx_alloca ((c)), (m), (arg0))

  164. 

  165. static inline rtx

  166. init_rtx_fmt_uuBeiie (rtx rt, machine_mode mode,

  167. 	rtx arg0,

  168. 	rtx arg1,

  169. 	basic_block arg2,

  170. 	rtx arg3,

  171. 	int arg4,

  172. 	int arg5,

  173. 	rtx arg6)

  174. {

  175.   PUT_MODE_RAW (rt, mode);

  176.   XEXP (rt, 0) = arg0;

  177.   XEXP (rt, 1) = arg1;

  178.   XBBDEF (rt, 2) = arg2;

  179.   XEXP (rt, 3) = arg3;

  180.   XINT (rt, 4) = arg4;

  181.   XINT (rt, 5) = arg5;

  182.   XEXP (rt, 6) = arg6;

  183.   return rt;

  184. }

  185. 

  186. static inline rtx

  187. gen_rtx_fmt_uuBeiie_stat (RTX_CODE code, machine_mode mode,

  188. 	rtx arg0,

  189. 	rtx arg1,

  190. 	basic_block arg2,

  191. 	rtx arg3,

  192. 	int arg4,

  193. 	int arg5,

  194. 	rtx arg6 MEM_STAT_DECL)

  195. {

  196.   rtx rt;

  197. 

  198.   rt = rtx_alloc (code PASS_MEM_STAT);

  199.   return init_rtx_fmt_uuBeiie (rt, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6);

  200. }

  201. 

  202. #define gen_rtx_fmt_uuBeiie(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \

  203.   gen_rtx_fmt_uuBeiie_stat ((c), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6) MEM_STAT_INFO)

  204. 

  205. #define alloca_rtx_fmt_uuBeiie(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \

  206.   init_rtx_fmt_uuBeiie (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6))

  207. 

  208. static inline rtx

  209. init_rtx_fmt_uuBeiie0 (rtx rt, machine_mode mode,

  210. 	rtx arg0,

  211. 	rtx arg1,

  212. 	basic_block arg2,

  213. 	rtx arg3,

  214. 	int arg4,

  215. 	int arg5,

  216. 	rtx arg6)

  217. {

  218.   PUT_MODE_RAW (rt, mode);

  219.   XEXP (rt, 0) = arg0;

  220.   XEXP (rt, 1) = arg1;

  221.   XBBDEF (rt, 2) = arg2;

  222.   XEXP (rt, 3) = arg3;

  223.   XINT (rt, 4) = arg4;

  224.   XINT (rt, 5) = arg5;

  225.   XEXP (rt, 6) = arg6;

  226.   X0EXP (rt, 7) = NULL_RTX;

  227.   return rt;

  228. }

  229. 

  230. static inline rtx

  231. gen_rtx_fmt_uuBeiie0_stat (RTX_CODE code, machine_mode mode,

  232. 	rtx arg0,

  233. 	rtx arg1,

  234. 	basic_block arg2,

  235. 	rtx arg3,

  236. 	int arg4,

  237. 	int arg5,

  238. 	rtx arg6 MEM_STAT_DECL)

  239. {

  240.   rtx rt;

  241. 

  242.   rt = rtx_alloc (code PASS_MEM_STAT);

  243.   return init_rtx_fmt_uuBeiie0 (rt, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6);

  244. }

  245. 

  246. #define gen_rtx_fmt_uuBeiie0(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \

  247.   gen_rtx_fmt_uuBeiie0_stat ((c), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6) MEM_STAT_INFO)

  248. 

  249. #define alloca_rtx_fmt_uuBeiie0(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \

  250.   init_rtx_fmt_uuBeiie0 (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6))

  251. 

  252. static inline rtx

  253. init_rtx_fmt_uuBeiiee (rtx rt, machine_mode mode,

  254. 	rtx arg0,

  255. 	rtx arg1,

  256. 	basic_block arg2,

  257. 	rtx arg3,

  258. 	int arg4,

  259. 	int arg5,

  260. 	rtx arg6,

  261. 	rtx arg7)

  262. {

  263.   PUT_MODE_RAW (rt, mode);

  264.   XEXP (rt, 0) = arg0;

  265.   XEXP (rt, 1) = arg1;

  266.   XBBDEF (rt, 2) = arg2;

  267.   XEXP (rt, 3) = arg3;

  268.   XINT (rt, 4) = arg4;

  269.   XINT (rt, 5) = arg5;

  270.   XEXP (rt, 6) = arg6;

  271.   XEXP (rt, 7) = arg7;

  272.   return rt;

  273. }

  274. 

  275. static inline rtx

  276. gen_rtx_fmt_uuBeiiee_stat (RTX_CODE code, machine_mode mode,

  277. 	rtx arg0,

  278. 	rtx arg1,

  279. 	basic_block arg2,

  280. 	rtx arg3,

  281. 	int arg4,

  282. 	int arg5,

  283. 	rtx arg6,

  284. 	rtx arg7 MEM_STAT_DECL)

  285. {

  286.   rtx rt;

  287. 

  288.   rt = rtx_alloc (code PASS_MEM_STAT);

  289.   return init_rtx_fmt_uuBeiiee (rt, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7);

  290. }

  291. 

  292. #define gen_rtx_fmt_uuBeiiee(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) \

  293.   gen_rtx_fmt_uuBeiiee_stat ((c), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6), (arg7) MEM_STAT_INFO)

  294. 

  295. #define alloca_rtx_fmt_uuBeiiee(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) \

  296.   init_rtx_fmt_uuBeiiee (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6), (arg7))

  297. 

  298. static inline rtx

  299. init_rtx_fmt_uuBe0000 (rtx rt, machine_mode mode,

  300. 	rtx arg0,

  301. 	rtx arg1,

  302. 	basic_block arg2,

  303. 	rtx arg3)

  304. {

  305.   PUT_MODE_RAW (rt, mode);

  306.   XEXP (rt, 0) = arg0;

  307.   XEXP (rt, 1) = arg1;

  308.   XBBDEF (rt, 2) = arg2;

  309.   XEXP (rt, 3) = arg3;

  310.   X0EXP (rt, 4) = NULL_RTX;

  311.   X0EXP (rt, 5) = NULL_RTX;

  312.   X0EXP (rt, 6) = NULL_RTX;

  313.   X0EXP (rt, 7) = NULL_RTX;

  314.   return rt;

  315. }

  316. 

  317. static inline rtx

  318. gen_rtx_fmt_uuBe0000_stat (RTX_CODE code, machine_mode mode,

  319. 	rtx arg0,

  320. 	rtx arg1,

  321. 	basic_block arg2,

  322. 	rtx arg3 MEM_STAT_DECL)

  323. {

  324.   rtx rt;

  325. 

  326.   rt = rtx_alloc (code PASS_MEM_STAT);

  327.   return init_rtx_fmt_uuBe0000 (rt, mode, arg0, arg1, arg2, arg3);

  328. }

  329. 

  330. #define gen_rtx_fmt_uuBe0000(c, m, arg0, arg1, arg2, arg3) \

  331.   gen_rtx_fmt_uuBe0000_stat ((c), (m), (arg0), (arg1), (arg2), (arg3) MEM_STAT_INFO)

  332. 

  333. #define alloca_rtx_fmt_uuBe0000(c, m, arg0, arg1, arg2, arg3) \

  334.   init_rtx_fmt_uuBe0000 (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3))

  335. 

  336. static inline rtx

  337. init_rtx_fmt_uu00000 (rtx rt, machine_mode mode,

  338. 	rtx arg0,

  339. 	rtx arg1)

  340. {

  341.   PUT_MODE_RAW (rt, mode);

  342.   XEXP (rt, 0) = arg0;

  343.   XEXP (rt, 1) = arg1;

  344.   X0EXP (rt, 2) = NULL_RTX;

  345.   X0EXP (rt, 3) = NULL_RTX;

  346.   X0EXP (rt, 4) = NULL_RTX;

  347.   X0EXP (rt, 5) = NULL_RTX;

  348.   X0EXP (rt, 6) = NULL_RTX;

  349.   return rt;

  350. }

  351. 

  352. static inline rtx

  353. gen_rtx_fmt_uu00000_stat (RTX_CODE code, machine_mode mode,

  354. 	rtx arg0,

  355. 	rtx arg1 MEM_STAT_DECL)

  356. {

  357.   rtx rt;

  358. 

  359.   rt = rtx_alloc (code PASS_MEM_STAT);

  360.   return init_rtx_fmt_uu00000 (rt, mode, arg0, arg1);

  361. }

  362. 

  363. #define gen_rtx_fmt_uu00000(c, m, arg0, arg1) \

  364.   gen_rtx_fmt_uu00000_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  365. 

  366. #define alloca_rtx_fmt_uu00000(c, m, arg0, arg1) \

  367.   init_rtx_fmt_uu00000 (rtx_alloca ((c)), (m), (arg0), (arg1))

  368. 

  369. static inline rtx

  370. init_rtx_fmt_uuB00is (rtx rt, machine_mode mode,

  371. 	rtx arg0,

  372. 	rtx arg1,

  373. 	basic_block arg2,

  374. 	int arg3,

  375. 	const char *arg4)

  376. {

  377.   PUT_MODE_RAW (rt, mode);

  378.   XEXP (rt, 0) = arg0;

  379.   XEXP (rt, 1) = arg1;

  380.   XBBDEF (rt, 2) = arg2;

  381.   X0EXP (rt, 3) = NULL_RTX;

  382.   X0EXP (rt, 4) = NULL_RTX;

  383.   XINT (rt, 5) = arg3;

  384.   XSTR (rt, 6) = arg4;

  385.   return rt;

  386. }

  387. 

  388. static inline rtx

  389. gen_rtx_fmt_uuB00is_stat (RTX_CODE code, machine_mode mode,

  390. 	rtx arg0,

  391. 	rtx arg1,

  392. 	basic_block arg2,

  393. 	int arg3,

  394. 	const char *arg4 MEM_STAT_DECL)

  395. {

  396.   rtx rt;

  397. 

  398.   rt = rtx_alloc (code PASS_MEM_STAT);

  399.   return init_rtx_fmt_uuB00is (rt, mode, arg0, arg1, arg2, arg3, arg4);

  400. }

  401. 

  402. #define gen_rtx_fmt_uuB00is(c, m, arg0, arg1, arg2, arg3, arg4) \

  403.   gen_rtx_fmt_uuB00is_stat ((c), (m), (arg0), (arg1), (arg2), (arg3), (arg4) MEM_STAT_INFO)

  404. 

  405. #define alloca_rtx_fmt_uuB00is(c, m, arg0, arg1, arg2, arg3, arg4) \

  406.   init_rtx_fmt_uuB00is (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3), (arg4))

  407. 

  408. static inline rtx

  409. init_rtx_fmt_si (rtx rt, machine_mode mode,

  410. 	const char *arg0,

  411. 	int arg1)

  412. {

  413.   PUT_MODE_RAW (rt, mode);

  414.   XSTR (rt, 0) = arg0;

  415.   XINT (rt, 1) = arg1;

  416.   return rt;

  417. }

  418. 

  419. static inline rtx

  420. gen_rtx_fmt_si_stat (RTX_CODE code, machine_mode mode,

  421. 	const char *arg0,

  422. 	int arg1 MEM_STAT_DECL)

  423. {

  424.   rtx rt;

  425. 

  426.   rt = rtx_alloc (code PASS_MEM_STAT);

  427.   return init_rtx_fmt_si (rt, mode, arg0, arg1);

  428. }

  429. 

  430. #define gen_rtx_fmt_si(c, m, arg0, arg1) \

  431.   gen_rtx_fmt_si_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  432. 

  433. #define alloca_rtx_fmt_si(c, m, arg0, arg1) \

  434.   init_rtx_fmt_si (rtx_alloca ((c)), (m), (arg0), (arg1))

  435. 

  436. static inline rtx

  437. init_rtx_fmt_ssiEEEi (rtx rt, machine_mode mode,

  438. 	const char *arg0,

  439. 	const char *arg1,

  440. 	int arg2,

  441. 	rtvec arg3,

  442. 	rtvec arg4,

  443. 	rtvec arg5,

  444. 	int arg6)

  445. {

  446.   PUT_MODE_RAW (rt, mode);

  447.   XSTR (rt, 0) = arg0;

  448.   XSTR (rt, 1) = arg1;

  449.   XINT (rt, 2) = arg2;

  450.   XVEC (rt, 3) = arg3;

  451.   XVEC (rt, 4) = arg4;

  452.   XVEC (rt, 5) = arg5;

  453.   XINT (rt, 6) = arg6;

  454.   return rt;

  455. }

  456. 

  457. static inline rtx

  458. gen_rtx_fmt_ssiEEEi_stat (RTX_CODE code, machine_mode mode,

  459. 	const char *arg0,

  460. 	const char *arg1,

  461. 	int arg2,

  462. 	rtvec arg3,

  463. 	rtvec arg4,

  464. 	rtvec arg5,

  465. 	int arg6 MEM_STAT_DECL)

  466. {

  467.   rtx rt;

  468. 

  469.   rt = rtx_alloc (code PASS_MEM_STAT);

  470.   return init_rtx_fmt_ssiEEEi (rt, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6);

  471. }

  472. 

  473. #define gen_rtx_fmt_ssiEEEi(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \

  474.   gen_rtx_fmt_ssiEEEi_stat ((c), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6) MEM_STAT_INFO)

  475. 

  476. #define alloca_rtx_fmt_ssiEEEi(c, m, arg0, arg1, arg2, arg3, arg4, arg5, arg6) \

  477.   init_rtx_fmt_ssiEEEi (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5), (arg6))

  478. 

  479. static inline rtx

  480. init_rtx_fmt_Ei (rtx rt, machine_mode mode,

  481. 	rtvec arg0,

  482. 	int arg1)

  483. {

  484.   PUT_MODE_RAW (rt, mode);

  485.   XVEC (rt, 0) = arg0;

  486.   XINT (rt, 1) = arg1;

  487.   return rt;

  488. }

  489. 

  490. static inline rtx

  491. gen_rtx_fmt_Ei_stat (RTX_CODE code, machine_mode mode,

  492. 	rtvec arg0,

  493. 	int arg1 MEM_STAT_DECL)

  494. {

  495.   rtx rt;

  496. 

  497.   rt = rtx_alloc (code PASS_MEM_STAT);

  498.   return init_rtx_fmt_Ei (rt, mode, arg0, arg1);

  499. }

  500. 

  501. #define gen_rtx_fmt_Ei(c, m, arg0, arg1) \

  502.   gen_rtx_fmt_Ei_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  503. 

  504. #define alloca_rtx_fmt_Ei(c, m, arg0, arg1) \

  505.   init_rtx_fmt_Ei (rtx_alloca ((c)), (m), (arg0), (arg1))

  506. 

  507. static inline rtx

  508. init_rtx_fmt_eEee0 (rtx rt, machine_mode mode,

  509. 	rtx arg0,

  510. 	rtvec arg1,

  511. 	rtx arg2,

  512. 	rtx arg3)

  513. {

  514.   PUT_MODE_RAW (rt, mode);

  515.   XEXP (rt, 0) = arg0;

  516.   XVEC (rt, 1) = arg1;

  517.   XEXP (rt, 2) = arg2;

  518.   XEXP (rt, 3) = arg3;

  519.   X0EXP (rt, 4) = NULL_RTX;

  520.   return rt;

  521. }

  522. 

  523. static inline rtx

  524. gen_rtx_fmt_eEee0_stat (RTX_CODE code, machine_mode mode,

  525. 	rtx arg0,

  526. 	rtvec arg1,

  527. 	rtx arg2,

  528. 	rtx arg3 MEM_STAT_DECL)

  529. {

  530.   rtx rt;

  531. 

  532.   rt = rtx_alloc (code PASS_MEM_STAT);

  533.   return init_rtx_fmt_eEee0 (rt, mode, arg0, arg1, arg2, arg3);

  534. }

  535. 

  536. #define gen_rtx_fmt_eEee0(c, m, arg0, arg1, arg2, arg3) \

  537.   gen_rtx_fmt_eEee0_stat ((c), (m), (arg0), (arg1), (arg2), (arg3) MEM_STAT_INFO)

  538. 

  539. #define alloca_rtx_fmt_eEee0(c, m, arg0, arg1, arg2, arg3) \

  540.   init_rtx_fmt_eEee0 (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3))

  541. 

  542. static inline rtx

  543. init_rtx_fmt_eee (rtx rt, machine_mode mode,

  544. 	rtx arg0,

  545. 	rtx arg1,

  546. 	rtx arg2)

  547. {

  548.   PUT_MODE_RAW (rt, mode);

  549.   XEXP (rt, 0) = arg0;

  550.   XEXP (rt, 1) = arg1;

  551.   XEXP (rt, 2) = arg2;

  552.   return rt;

  553. }

  554. 

  555. static inline rtx

  556. gen_rtx_fmt_eee_stat (RTX_CODE code, machine_mode mode,

  557. 	rtx arg0,

  558. 	rtx arg1,

  559. 	rtx arg2 MEM_STAT_DECL)

  560. {

  561.   rtx rt;

  562. 

  563.   rt = rtx_alloc (code PASS_MEM_STAT);

  564.   return init_rtx_fmt_eee (rt, mode, arg0, arg1, arg2);

  565. }

  566. 

  567. #define gen_rtx_fmt_eee(c, m, arg0, arg1, arg2) \

  568.   gen_rtx_fmt_eee_stat ((c), (m), (arg0), (arg1), (arg2) MEM_STAT_INFO)

  569. 

  570. #define alloca_rtx_fmt_eee(c, m, arg0, arg1, arg2) \

  571.   init_rtx_fmt_eee (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2))

  572. 

  573. static inline rtx

  574. init_rtx_fmt_e (rtx rt, machine_mode mode,

  575. 	rtx arg0)

  576. {

  577.   PUT_MODE_RAW (rt, mode);

  578.   XEXP (rt, 0) = arg0;

  579.   return rt;

  580. }

  581. 

  582. static inline rtx

  583. gen_rtx_fmt_e_stat (RTX_CODE code, machine_mode mode,

  584. 	rtx arg0 MEM_STAT_DECL)

  585. {

  586.   rtx rt;

  587. 

  588.   rt = rtx_alloc (code PASS_MEM_STAT);

  589.   return init_rtx_fmt_e (rt, mode, arg0);

  590. }

  591. 

  592. #define gen_rtx_fmt_e(c, m, arg0) \

  593.   gen_rtx_fmt_e_stat ((c), (m), (arg0) MEM_STAT_INFO)

  594. 

  595. #define alloca_rtx_fmt_e(c, m, arg0) \

  596.   init_rtx_fmt_e (rtx_alloca ((c)), (m), (arg0))

  597. 

  598. static inline rtx

  599. init_rtx_fmt_ (rtx rt, machine_mode mode)

  600. {

  601.   PUT_MODE_RAW (rt, mode);

  602.   return rt;

  603. }

  604. 

  605. static inline rtx

  606. gen_rtx_fmt__stat (RTX_CODE code, machine_mode mode MEM_STAT_DECL)

  607. {

  608.   rtx rt;

  609. 

  610.   rt = rtx_alloc (code PASS_MEM_STAT);

  611.   return init_rtx_fmt_ (rt, mode);

  612. }

  613. 

  614. #define gen_rtx_fmt_(c, m) \

  615.   gen_rtx_fmt__stat ((c), (m) MEM_STAT_INFO)

  616. 

  617. #define alloca_rtx_fmt_(c, m) \

  618.   init_rtx_fmt_ (rtx_alloca ((c)), (m))

  619. 

  620. static inline rtx

  621. init_rtx_fmt_w (rtx rt, machine_mode mode,

  622. 	HOST_WIDE_INT arg0)

  623. {

  624.   PUT_MODE_RAW (rt, mode);

  625.   XWINT (rt, 0) = arg0;

  626.   return rt;

  627. }

  628. 

  629. static inline rtx

  630. gen_rtx_fmt_w_stat (RTX_CODE code, machine_mode mode,

  631. 	HOST_WIDE_INT arg0 MEM_STAT_DECL)

  632. {

  633.   rtx rt;

  634. 

  635.   rt = rtx_alloc (code PASS_MEM_STAT);

  636.   return init_rtx_fmt_w (rt, mode, arg0);

  637. }

  638. 

  639. #define gen_rtx_fmt_w(c, m, arg0) \

  640.   gen_rtx_fmt_w_stat ((c), (m), (arg0) MEM_STAT_INFO)

  641. 

  642. #define alloca_rtx_fmt_w(c, m, arg0) \

  643.   init_rtx_fmt_w (rtx_alloca ((c)), (m), (arg0))

  644. 

  645. static inline rtx

  646. init_rtx_fmt_www (rtx rt, machine_mode mode,

  647. 	HOST_WIDE_INT arg0,

  648. 	HOST_WIDE_INT arg1,

  649. 	HOST_WIDE_INT arg2)

  650. {

  651.   PUT_MODE_RAW (rt, mode);

  652.   XWINT (rt, 0) = arg0;

  653.   XWINT (rt, 1) = arg1;

  654.   XWINT (rt, 2) = arg2;

  655.   return rt;

  656. }

  657. 

  658. static inline rtx

  659. gen_rtx_fmt_www_stat (RTX_CODE code, machine_mode mode,

  660. 	HOST_WIDE_INT arg0,

  661. 	HOST_WIDE_INT arg1,

  662. 	HOST_WIDE_INT arg2 MEM_STAT_DECL)

  663. {

  664.   rtx rt;

  665. 

  666.   rt = rtx_alloc (code PASS_MEM_STAT);

  667.   return init_rtx_fmt_www (rt, mode, arg0, arg1, arg2);

  668. }

  669. 

  670. #define gen_rtx_fmt_www(c, m, arg0, arg1, arg2) \

  671.   gen_rtx_fmt_www_stat ((c), (m), (arg0), (arg1), (arg2) MEM_STAT_INFO)

  672. 

  673. #define alloca_rtx_fmt_www(c, m, arg0, arg1, arg2) \

  674.   init_rtx_fmt_www (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2))

  675. 

  676. static inline rtx

  677. init_rtx_fmt_s (rtx rt, machine_mode mode,

  678. 	const char *arg0)

  679. {

  680.   PUT_MODE_RAW (rt, mode);

  681.   XSTR (rt, 0) = arg0;

  682.   return rt;

  683. }

  684. 

  685. static inline rtx

  686. gen_rtx_fmt_s_stat (RTX_CODE code, machine_mode mode,

  687. 	const char *arg0 MEM_STAT_DECL)

  688. {

  689.   rtx rt;

  690. 

  691.   rt = rtx_alloc (code PASS_MEM_STAT);

  692.   return init_rtx_fmt_s (rt, mode, arg0);

  693. }

  694. 

  695. #define gen_rtx_fmt_s(c, m, arg0) \

  696.   gen_rtx_fmt_s_stat ((c), (m), (arg0) MEM_STAT_INFO)

  697. 

  698. #define alloca_rtx_fmt_s(c, m, arg0) \

  699.   init_rtx_fmt_s (rtx_alloca ((c)), (m), (arg0))

  700. 

  701. static inline rtx

  702. init_rtx_fmt_ep (rtx rt, machine_mode mode,

  703. 	rtx arg0,

  704. 	poly_uint16 arg1)

  705. {

  706.   PUT_MODE_RAW (rt, mode);

  707.   XEXP (rt, 0) = arg0;

  708.   SUBREG_BYTE (rt) = arg1;

  709.   return rt;

  710. }

  711. 

  712. static inline rtx

  713. gen_rtx_fmt_ep_stat (RTX_CODE code, machine_mode mode,

  714. 	rtx arg0,

  715. 	poly_uint16 arg1 MEM_STAT_DECL)

  716. {

  717.   rtx rt;

  718. 

  719.   rt = rtx_alloc (code PASS_MEM_STAT);

  720.   return init_rtx_fmt_ep (rt, mode, arg0, arg1);

  721. }

  722. 

  723. #define gen_rtx_fmt_ep(c, m, arg0, arg1) \

  724.   gen_rtx_fmt_ep_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  725. 

  726. #define alloca_rtx_fmt_ep(c, m, arg0, arg1) \

  727.   init_rtx_fmt_ep (rtx_alloca ((c)), (m), (arg0), (arg1))

  728. 

  729. static inline rtx

  730. init_rtx_fmt_e0 (rtx rt, machine_mode mode,

  731. 	rtx arg0)

  732. {

  733.   PUT_MODE_RAW (rt, mode);

  734.   XEXP (rt, 0) = arg0;

  735.   X0EXP (rt, 1) = NULL_RTX;

  736.   return rt;

  737. }

  738. 

  739. static inline rtx

  740. gen_rtx_fmt_e0_stat (RTX_CODE code, machine_mode mode,

  741. 	rtx arg0 MEM_STAT_DECL)

  742. {

  743.   rtx rt;

  744. 

  745.   rt = rtx_alloc (code PASS_MEM_STAT);

  746.   return init_rtx_fmt_e0 (rt, mode, arg0);

  747. }

  748. 

  749. #define gen_rtx_fmt_e0(c, m, arg0) \

  750.   gen_rtx_fmt_e0_stat ((c), (m), (arg0) MEM_STAT_INFO)

  751. 

  752. #define alloca_rtx_fmt_e0(c, m, arg0) \

  753.   init_rtx_fmt_e0 (rtx_alloca ((c)), (m), (arg0))

  754. 

  755. static inline rtx

  756. init_rtx_fmt_u (rtx rt, machine_mode mode,

  757. 	rtx arg0)

  758. {

  759.   PUT_MODE_RAW (rt, mode);

  760.   XEXP (rt, 0) = arg0;

  761.   return rt;

  762. }

  763. 

  764. static inline rtx

  765. gen_rtx_fmt_u_stat (RTX_CODE code, machine_mode mode,

  766. 	rtx arg0 MEM_STAT_DECL)

  767. {

  768.   rtx rt;

  769. 

  770.   rt = rtx_alloc (code PASS_MEM_STAT);

  771.   return init_rtx_fmt_u (rt, mode, arg0);

  772. }

  773. 

  774. #define gen_rtx_fmt_u(c, m, arg0) \

  775.   gen_rtx_fmt_u_stat ((c), (m), (arg0) MEM_STAT_INFO)

  776. 

  777. #define alloca_rtx_fmt_u(c, m, arg0) \

  778.   init_rtx_fmt_u (rtx_alloca ((c)), (m), (arg0))

  779. 

  780. static inline rtx

  781. init_rtx_fmt_s0 (rtx rt, machine_mode mode,

  782. 	const char *arg0)

  783. {

  784.   PUT_MODE_RAW (rt, mode);

  785.   XSTR (rt, 0) = arg0;

  786.   X0EXP (rt, 1) = NULL_RTX;

  787.   return rt;

  788. }

  789. 

  790. static inline rtx

  791. gen_rtx_fmt_s0_stat (RTX_CODE code, machine_mode mode,

  792. 	const char *arg0 MEM_STAT_DECL)

  793. {

  794.   rtx rt;

  795. 

  796.   rt = rtx_alloc (code PASS_MEM_STAT);

  797.   return init_rtx_fmt_s0 (rt, mode, arg0);

  798. }

  799. 

  800. #define gen_rtx_fmt_s0(c, m, arg0) \

  801.   gen_rtx_fmt_s0_stat ((c), (m), (arg0) MEM_STAT_INFO)

  802. 

  803. #define alloca_rtx_fmt_s0(c, m, arg0) \

  804.   init_rtx_fmt_s0 (rtx_alloca ((c)), (m), (arg0))

  805. 

  806. static inline rtx

  807. init_rtx_fmt_te (rtx rt, machine_mode mode,

  808. 	tree arg0,

  809. 	rtx arg1)

  810. {

  811.   PUT_MODE_RAW (rt, mode);

  812.   XTREE (rt, 0) = arg0;

  813.   XEXP (rt, 1) = arg1;

  814.   return rt;

  815. }

  816. 

  817. static inline rtx

  818. gen_rtx_fmt_te_stat (RTX_CODE code, machine_mode mode,

  819. 	tree arg0,

  820. 	rtx arg1 MEM_STAT_DECL)

  821. {

  822.   rtx rt;

  823. 

  824.   rt = rtx_alloc (code PASS_MEM_STAT);

  825.   return init_rtx_fmt_te (rt, mode, arg0, arg1);

  826. }

  827. 

  828. #define gen_rtx_fmt_te(c, m, arg0, arg1) \

  829.   gen_rtx_fmt_te_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  830. 

  831. #define alloca_rtx_fmt_te(c, m, arg0, arg1) \

  832.   init_rtx_fmt_te (rtx_alloca ((c)), (m), (arg0), (arg1))

  833. 

  834. static inline rtx

  835. init_rtx_fmt_t (rtx rt, machine_mode mode,

  836. 	tree arg0)

  837. {

  838.   PUT_MODE_RAW (rt, mode);

  839.   XTREE (rt, 0) = arg0;

  840.   return rt;

  841. }

  842. 

  843. static inline rtx

  844. gen_rtx_fmt_t_stat (RTX_CODE code, machine_mode mode,

  845. 	tree arg0 MEM_STAT_DECL)

  846. {

  847.   rtx rt;

  848. 

  849.   rt = rtx_alloc (code PASS_MEM_STAT);

  850.   return init_rtx_fmt_t (rt, mode, arg0);

  851. }

  852. 

  853. #define gen_rtx_fmt_t(c, m, arg0) \

  854.   gen_rtx_fmt_t_stat ((c), (m), (arg0) MEM_STAT_INFO)

  855. 

  856. #define alloca_rtx_fmt_t(c, m, arg0) \

  857.   init_rtx_fmt_t (rtx_alloca ((c)), (m), (arg0))

  858. 

  859. static inline rtx

  860. init_rtx_fmt_iss (rtx rt, machine_mode mode,

  861. 	int arg0,

  862. 	const char *arg1,

  863. 	const char *arg2)

  864. {

  865.   PUT_MODE_RAW (rt, mode);

  866.   XINT (rt, 0) = arg0;

  867.   XSTR (rt, 1) = arg1;

  868.   XSTR (rt, 2) = arg2;

  869.   return rt;

  870. }

  871. 

  872. static inline rtx

  873. gen_rtx_fmt_iss_stat (RTX_CODE code, machine_mode mode,

  874. 	int arg0,

  875. 	const char *arg1,

  876. 	const char *arg2 MEM_STAT_DECL)

  877. {

  878.   rtx rt;

  879. 

  880.   rt = rtx_alloc (code PASS_MEM_STAT);

  881.   return init_rtx_fmt_iss (rt, mode, arg0, arg1, arg2);

  882. }

  883. 

  884. #define gen_rtx_fmt_iss(c, m, arg0, arg1, arg2) \

  885.   gen_rtx_fmt_iss_stat ((c), (m), (arg0), (arg1), (arg2) MEM_STAT_INFO)

  886. 

  887. #define alloca_rtx_fmt_iss(c, m, arg0, arg1, arg2) \

  888.   init_rtx_fmt_iss (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2))

  889. 

  890. static inline rtx

  891. init_rtx_fmt_is (rtx rt, machine_mode mode,

  892. 	int arg0,

  893. 	const char *arg1)

  894. {

  895.   PUT_MODE_RAW (rt, mode);

  896.   XINT (rt, 0) = arg0;

  897.   XSTR (rt, 1) = arg1;

  898.   return rt;

  899. }

  900. 

  901. static inline rtx

  902. gen_rtx_fmt_is_stat (RTX_CODE code, machine_mode mode,

  903. 	int arg0,

  904. 	const char *arg1 MEM_STAT_DECL)

  905. {

  906.   rtx rt;

  907. 

  908.   rt = rtx_alloc (code PASS_MEM_STAT);

  909.   return init_rtx_fmt_is (rt, mode, arg0, arg1);

  910. }

  911. 

  912. #define gen_rtx_fmt_is(c, m, arg0, arg1) \

  913.   gen_rtx_fmt_is_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  914. 

  915. #define alloca_rtx_fmt_is(c, m, arg0, arg1) \

  916.   init_rtx_fmt_is (rtx_alloca ((c)), (m), (arg0), (arg1))

  917. 

  918. static inline rtx

  919. init_rtx_fmt_isE (rtx rt, machine_mode mode,

  920. 	int arg0,

  921. 	const char *arg1,

  922. 	rtvec arg2)

  923. {

  924.   PUT_MODE_RAW (rt, mode);

  925.   XINT (rt, 0) = arg0;

  926.   XSTR (rt, 1) = arg1;

  927.   XVEC (rt, 2) = arg2;

  928.   return rt;

  929. }

  930. 

  931. static inline rtx

  932. gen_rtx_fmt_isE_stat (RTX_CODE code, machine_mode mode,

  933. 	int arg0,

  934. 	const char *arg1,

  935. 	rtvec arg2 MEM_STAT_DECL)

  936. {

  937.   rtx rt;

  938. 

  939.   rt = rtx_alloc (code PASS_MEM_STAT);

  940.   return init_rtx_fmt_isE (rt, mode, arg0, arg1, arg2);

  941. }

  942. 

  943. #define gen_rtx_fmt_isE(c, m, arg0, arg1, arg2) \

  944.   gen_rtx_fmt_isE_stat ((c), (m), (arg0), (arg1), (arg2) MEM_STAT_INFO)

  945. 

  946. #define alloca_rtx_fmt_isE(c, m, arg0, arg1, arg2) \

  947.   init_rtx_fmt_isE (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2))

  948. 

  949. static inline rtx

  950. init_rtx_fmt_iE (rtx rt, machine_mode mode,

  951. 	int arg0,

  952. 	rtvec arg1)

  953. {

  954.   PUT_MODE_RAW (rt, mode);

  955.   XINT (rt, 0) = arg0;

  956.   XVEC (rt, 1) = arg1;

  957.   return rt;

  958. }

  959. 

  960. static inline rtx

  961. gen_rtx_fmt_iE_stat (RTX_CODE code, machine_mode mode,

  962. 	int arg0,

  963. 	rtvec arg1 MEM_STAT_DECL)

  964. {

  965.   rtx rt;

  966. 

  967.   rt = rtx_alloc (code PASS_MEM_STAT);

  968.   return init_rtx_fmt_iE (rt, mode, arg0, arg1);

  969. }

  970. 

  971. #define gen_rtx_fmt_iE(c, m, arg0, arg1) \

  972.   gen_rtx_fmt_iE_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  973. 

  974. #define alloca_rtx_fmt_iE(c, m, arg0, arg1) \

  975.   init_rtx_fmt_iE (rtx_alloca ((c)), (m), (arg0), (arg1))

  976. 

  977. static inline rtx

  978. init_rtx_fmt_ss (rtx rt, machine_mode mode,

  979. 	const char *arg0,

  980. 	const char *arg1)

  981. {

  982.   PUT_MODE_RAW (rt, mode);

  983.   XSTR (rt, 0) = arg0;

  984.   XSTR (rt, 1) = arg1;

  985.   return rt;

  986. }

  987. 

  988. static inline rtx

  989. gen_rtx_fmt_ss_stat (RTX_CODE code, machine_mode mode,

  990. 	const char *arg0,

  991. 	const char *arg1 MEM_STAT_DECL)

  992. {

  993.   rtx rt;

  994. 

  995.   rt = rtx_alloc (code PASS_MEM_STAT);

  996.   return init_rtx_fmt_ss (rt, mode, arg0, arg1);

  997. }

  998. 

  999. #define gen_rtx_fmt_ss(c, m, arg0, arg1) \

  1000.   gen_rtx_fmt_ss_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  1001. 

  1002. #define alloca_rtx_fmt_ss(c, m, arg0, arg1) \

  1003.   init_rtx_fmt_ss (rtx_alloca ((c)), (m), (arg0), (arg1))

  1004. 

  1005. static inline rtx

  1006. init_rtx_fmt_eE (rtx rt, machine_mode mode,

  1007. 	rtx arg0,

  1008. 	rtvec arg1)

  1009. {

  1010.   PUT_MODE_RAW (rt, mode);

  1011.   XEXP (rt, 0) = arg0;

  1012.   XVEC (rt, 1) = arg1;

  1013.   return rt;

  1014. }

  1015. 

  1016. static inline rtx

  1017. gen_rtx_fmt_eE_stat (RTX_CODE code, machine_mode mode,

  1018. 	rtx arg0,

  1019. 	rtvec arg1 MEM_STAT_DECL)

  1020. {

  1021.   rtx rt;

  1022. 

  1023.   rt = rtx_alloc (code PASS_MEM_STAT);

  1024.   return init_rtx_fmt_eE (rt, mode, arg0, arg1);

  1025. }

  1026. 

  1027. #define gen_rtx_fmt_eE(c, m, arg0, arg1) \

  1028.   gen_rtx_fmt_eE_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  1029. 

  1030. #define alloca_rtx_fmt_eE(c, m, arg0, arg1) \

  1031.   init_rtx_fmt_eE (rtx_alloca ((c)), (m), (arg0), (arg1))

  1032. 

  1033. static inline rtx

  1034. init_rtx_fmt_ses (rtx rt, machine_mode mode,

  1035. 	const char *arg0,

  1036. 	rtx arg1,

  1037. 	const char *arg2)

  1038. {

  1039.   PUT_MODE_RAW (rt, mode);

  1040.   XSTR (rt, 0) = arg0;

  1041.   XEXP (rt, 1) = arg1;

  1042.   XSTR (rt, 2) = arg2;

  1043.   return rt;

  1044. }

  1045. 

  1046. static inline rtx

  1047. gen_rtx_fmt_ses_stat (RTX_CODE code, machine_mode mode,

  1048. 	const char *arg0,

  1049. 	rtx arg1,

  1050. 	const char *arg2 MEM_STAT_DECL)

  1051. {

  1052.   rtx rt;

  1053. 

  1054.   rt = rtx_alloc (code PASS_MEM_STAT);

  1055.   return init_rtx_fmt_ses (rt, mode, arg0, arg1, arg2);

  1056. }

  1057. 

  1058. #define gen_rtx_fmt_ses(c, m, arg0, arg1, arg2) \

  1059.   gen_rtx_fmt_ses_stat ((c), (m), (arg0), (arg1), (arg2) MEM_STAT_INFO)

  1060. 

  1061. #define alloca_rtx_fmt_ses(c, m, arg0, arg1, arg2) \

  1062.   init_rtx_fmt_ses (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2))

  1063. 

  1064. static inline rtx

  1065. init_rtx_fmt_sss (rtx rt, machine_mode mode,

  1066. 	const char *arg0,

  1067. 	const char *arg1,

  1068. 	const char *arg2)

  1069. {

  1070.   PUT_MODE_RAW (rt, mode);

  1071.   XSTR (rt, 0) = arg0;

  1072.   XSTR (rt, 1) = arg1;

  1073.   XSTR (rt, 2) = arg2;

  1074.   return rt;

  1075. }

  1076. 

  1077. static inline rtx

  1078. gen_rtx_fmt_sss_stat (RTX_CODE code, machine_mode mode,

  1079. 	const char *arg0,

  1080. 	const char *arg1,

  1081. 	const char *arg2 MEM_STAT_DECL)

  1082. {

  1083.   rtx rt;

  1084. 

  1085.   rt = rtx_alloc (code PASS_MEM_STAT);

  1086.   return init_rtx_fmt_sss (rt, mode, arg0, arg1, arg2);

  1087. }

  1088. 

  1089. #define gen_rtx_fmt_sss(c, m, arg0, arg1, arg2) \

  1090.   gen_rtx_fmt_sss_stat ((c), (m), (arg0), (arg1), (arg2) MEM_STAT_INFO)

  1091. 

  1092. #define alloca_rtx_fmt_sss(c, m, arg0, arg1, arg2) \

  1093.   init_rtx_fmt_sss (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2))

  1094. 

  1095. static inline rtx

  1096. init_rtx_fmt_sse (rtx rt, machine_mode mode,

  1097. 	const char *arg0,

  1098. 	const char *arg1,

  1099. 	rtx arg2)

  1100. {

  1101.   PUT_MODE_RAW (rt, mode);

  1102.   XSTR (rt, 0) = arg0;

  1103.   XSTR (rt, 1) = arg1;

  1104.   XEXP (rt, 2) = arg2;

  1105.   return rt;

  1106. }

  1107. 

  1108. static inline rtx

  1109. gen_rtx_fmt_sse_stat (RTX_CODE code, machine_mode mode,

  1110. 	const char *arg0,

  1111. 	const char *arg1,

  1112. 	rtx arg2 MEM_STAT_DECL)

  1113. {

  1114.   rtx rt;

  1115. 

  1116.   rt = rtx_alloc (code PASS_MEM_STAT);

  1117.   return init_rtx_fmt_sse (rt, mode, arg0, arg1, arg2);

  1118. }

  1119. 

  1120. #define gen_rtx_fmt_sse(c, m, arg0, arg1, arg2) \

  1121.   gen_rtx_fmt_sse_stat ((c), (m), (arg0), (arg1), (arg2) MEM_STAT_INFO)

  1122. 

  1123. #define alloca_rtx_fmt_sse(c, m, arg0, arg1, arg2) \

  1124.   init_rtx_fmt_sse (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2))

  1125. 

  1126. static inline rtx

  1127. init_rtx_fmt_sies (rtx rt, machine_mode mode,

  1128. 	const char *arg0,

  1129. 	int arg1,

  1130. 	rtx arg2,

  1131. 	const char *arg3)

  1132. {

  1133.   PUT_MODE_RAW (rt, mode);

  1134.   XSTR (rt, 0) = arg0;

  1135.   XINT (rt, 1) = arg1;

  1136.   XEXP (rt, 2) = arg2;

  1137.   XSTR (rt, 3) = arg3;

  1138.   return rt;

  1139. }

  1140. 

  1141. static inline rtx

  1142. gen_rtx_fmt_sies_stat (RTX_CODE code, machine_mode mode,

  1143. 	const char *arg0,

  1144. 	int arg1,

  1145. 	rtx arg2,

  1146. 	const char *arg3 MEM_STAT_DECL)

  1147. {

  1148.   rtx rt;

  1149. 

  1150.   rt = rtx_alloc (code PASS_MEM_STAT);

  1151.   return init_rtx_fmt_sies (rt, mode, arg0, arg1, arg2, arg3);

  1152. }

  1153. 

  1154. #define gen_rtx_fmt_sies(c, m, arg0, arg1, arg2, arg3) \

  1155.   gen_rtx_fmt_sies_stat ((c), (m), (arg0), (arg1), (arg2), (arg3) MEM_STAT_INFO)

  1156. 

  1157. #define alloca_rtx_fmt_sies(c, m, arg0, arg1, arg2, arg3) \

  1158.   init_rtx_fmt_sies (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3))

  1159. 

  1160. static inline rtx

  1161. init_rtx_fmt_sE (rtx rt, machine_mode mode,

  1162. 	const char *arg0,

  1163. 	rtvec arg1)

  1164. {

  1165.   PUT_MODE_RAW (rt, mode);

  1166.   XSTR (rt, 0) = arg0;

  1167.   XVEC (rt, 1) = arg1;

  1168.   return rt;

  1169. }

  1170. 

  1171. static inline rtx

  1172. gen_rtx_fmt_sE_stat (RTX_CODE code, machine_mode mode,

  1173. 	const char *arg0,

  1174. 	rtvec arg1 MEM_STAT_DECL)

  1175. {

  1176.   rtx rt;

  1177. 

  1178.   rt = rtx_alloc (code PASS_MEM_STAT);

  1179.   return init_rtx_fmt_sE (rt, mode, arg0, arg1);

  1180. }

  1181. 

  1182. #define gen_rtx_fmt_sE(c, m, arg0, arg1) \

  1183.   gen_rtx_fmt_sE_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  1184. 

  1185. #define alloca_rtx_fmt_sE(c, m, arg0, arg1) \

  1186.   init_rtx_fmt_sE (rtx_alloca ((c)), (m), (arg0), (arg1))

  1187. 

  1188. static inline rtx

  1189. init_rtx_fmt_ww (rtx rt, machine_mode mode,

  1190. 	HOST_WIDE_INT arg0,

  1191. 	HOST_WIDE_INT arg1)

  1192. {

  1193.   PUT_MODE_RAW (rt, mode);

  1194.   XWINT (rt, 0) = arg0;

  1195.   XWINT (rt, 1) = arg1;

  1196.   return rt;

  1197. }

  1198. 

  1199. static inline rtx

  1200. gen_rtx_fmt_ww_stat (RTX_CODE code, machine_mode mode,

  1201. 	HOST_WIDE_INT arg0,

  1202. 	HOST_WIDE_INT arg1 MEM_STAT_DECL)

  1203. {

  1204.   rtx rt;

  1205. 

  1206.   rt = rtx_alloc (code PASS_MEM_STAT);

  1207.   return init_rtx_fmt_ww (rt, mode, arg0, arg1);

  1208. }

  1209. 

  1210. #define gen_rtx_fmt_ww(c, m, arg0, arg1) \

  1211.   gen_rtx_fmt_ww_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  1212. 

  1213. #define alloca_rtx_fmt_ww(c, m, arg0, arg1) \

  1214.   init_rtx_fmt_ww (rtx_alloca ((c)), (m), (arg0), (arg1))

  1215. 

  1216. static inline rtx

  1217. init_rtx_fmt_Ee (rtx rt, machine_mode mode,

  1218. 	rtvec arg0,

  1219. 	rtx arg1)

  1220. {

  1221.   PUT_MODE_RAW (rt, mode);

  1222.   XVEC (rt, 0) = arg0;

  1223.   XEXP (rt, 1) = arg1;

  1224.   return rt;

  1225. }

  1226. 

  1227. static inline rtx

  1228. gen_rtx_fmt_Ee_stat (RTX_CODE code, machine_mode mode,

  1229. 	rtvec arg0,

  1230. 	rtx arg1 MEM_STAT_DECL)

  1231. {

  1232.   rtx rt;

  1233. 

  1234.   rt = rtx_alloc (code PASS_MEM_STAT);

  1235.   return init_rtx_fmt_Ee (rt, mode, arg0, arg1);

  1236. }

  1237. 

  1238. #define gen_rtx_fmt_Ee(c, m, arg0, arg1) \

  1239.   gen_rtx_fmt_Ee_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO)

  1240. 

  1241. #define alloca_rtx_fmt_Ee(c, m, arg0, arg1) \

  1242.   init_rtx_fmt_Ee (rtx_alloca ((c)), (m), (arg0), (arg1))

  1243. 

  1244. static inline rtx

  1245. init_rtx_fmt_sEsE (rtx rt, machine_mode mode,

  1246. 	const char *arg0,

  1247. 	rtvec arg1,

  1248. 	const char *arg2,

  1249. 	rtvec arg3)

  1250. {

  1251.   PUT_MODE_RAW (rt, mode);

  1252.   XSTR (rt, 0) = arg0;

  1253.   XVEC (rt, 1) = arg1;

  1254.   XSTR (rt, 2) = arg2;

  1255.   XVEC (rt, 3) = arg3;

  1256.   return rt;

  1257. }

  1258. 

  1259. static inline rtx

  1260. gen_rtx_fmt_sEsE_stat (RTX_CODE code, machine_mode mode,

  1261. 	const char *arg0,

  1262. 	rtvec arg1,

  1263. 	const char *arg2,

  1264. 	rtvec arg3 MEM_STAT_DECL)

  1265. {

  1266.   rtx rt;

  1267. 

  1268.   rt = rtx_alloc (code PASS_MEM_STAT);

  1269.   return init_rtx_fmt_sEsE (rt, mode, arg0, arg1, arg2, arg3);

  1270. }

  1271. 

  1272. #define gen_rtx_fmt_sEsE(c, m, arg0, arg1, arg2, arg3) \

  1273.   gen_rtx_fmt_sEsE_stat ((c), (m), (arg0), (arg1), (arg2), (arg3) MEM_STAT_INFO)

  1274. 

  1275. #define alloca_rtx_fmt_sEsE(c, m, arg0, arg1, arg2, arg3) \

  1276.   init_rtx_fmt_sEsE (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3))

  1277. 

  1278. static inline rtx

  1279. init_rtx_fmt_ssss (rtx rt, machine_mode mode,

  1280. 	const char *arg0,

  1281. 	const char *arg1,

  1282. 	const char *arg2,

  1283. 	const char *arg3)

  1284. {

  1285.   PUT_MODE_RAW (rt, mode);

  1286.   XSTR (rt, 0) = arg0;

  1287.   XSTR (rt, 1) = arg1;

  1288.   XSTR (rt, 2) = arg2;

  1289.   XSTR (rt, 3) = arg3;

  1290.   return rt;

  1291. }

  1292. 

  1293. static inline rtx

  1294. gen_rtx_fmt_ssss_stat (RTX_CODE code, machine_mode mode,

  1295. 	const char *arg0,

  1296. 	const char *arg1,

  1297. 	const char *arg2,

  1298. 	const char *arg3 MEM_STAT_DECL)

  1299. {

  1300.   rtx rt;

  1301. 

  1302.   rt = rtx_alloc (code PASS_MEM_STAT);

  1303.   return init_rtx_fmt_ssss (rt, mode, arg0, arg1, arg2, arg3);

  1304. }

  1305. 

  1306. #define gen_rtx_fmt_ssss(c, m, arg0, arg1, arg2, arg3) \

  1307.   gen_rtx_fmt_ssss_stat ((c), (m), (arg0), (arg1), (arg2), (arg3) MEM_STAT_INFO)

  1308. 

  1309. #define alloca_rtx_fmt_ssss(c, m, arg0, arg1, arg2, arg3) \

  1310.   init_rtx_fmt_ssss (rtx_alloca ((c)), (m), (arg0), (arg1), (arg2), (arg3))

  1311. 

  1312. 

  1313. #define gen_rtx_VALUE(MODE) \

  1314.   gen_rtx_fmt_0 (VALUE, (MODE))

  1315. #define gen_rtx_DEBUG_EXPR(MODE) \

  1316.   gen_rtx_fmt_0 (DEBUG_EXPR, (MODE))

  1317. #define gen_rtx_raw_EXPR_LIST(MODE, ARG0, ARG1) \

  1318.   gen_rtx_fmt_ee (EXPR_LIST, (MODE), (ARG0), (ARG1))

  1319. #define gen_rtx_raw_INSN_LIST(MODE, ARG0, ARG1) \

  1320.   gen_rtx_fmt_ue (INSN_LIST, (MODE), (ARG0), (ARG1))

  1321. #define gen_rtx_INT_LIST(MODE, ARG0, ARG1) \

  1322.   gen_rtx_fmt_ie (INT_LIST, (MODE), (ARG0), (ARG1))

  1323. #define gen_rtx_SEQUENCE(MODE, ARG0) \

  1324.   gen_rtx_fmt_E (SEQUENCE, (MODE), (ARG0))

  1325. #define gen_rtx_ADDRESS(MODE, ARG0) \

  1326.   gen_rtx_fmt_i (ADDRESS, (MODE), (ARG0))

  1327. #define gen_rtx_DEBUG_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \

  1328.   gen_rtx_fmt_uuBeiie (DEBUG_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6))

  1329. #define gen_rtx_raw_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \

  1330.   gen_rtx_fmt_uuBeiie (INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6))

  1331. #define gen_rtx_JUMP_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \

  1332.   gen_rtx_fmt_uuBeiie0 (JUMP_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6))

  1333. #define gen_rtx_CALL_INSN(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6, ARG7) \

  1334.   gen_rtx_fmt_uuBeiiee (CALL_INSN, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6), (ARG7))

  1335. #define gen_rtx_JUMP_TABLE_DATA(MODE, ARG0, ARG1, ARG2, ARG3) \

  1336.   gen_rtx_fmt_uuBe0000 (JUMP_TABLE_DATA, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))

  1337. #define gen_rtx_BARRIER(MODE, ARG0, ARG1) \

  1338.   gen_rtx_fmt_uu00000 (BARRIER, (MODE), (ARG0), (ARG1))

  1339. #define gen_rtx_CODE_LABEL(MODE, ARG0, ARG1, ARG2, ARG3, ARG4) \

  1340.   gen_rtx_fmt_uuB00is (CODE_LABEL, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4))

  1341. #define gen_rtx_COND_EXEC(MODE, ARG0, ARG1) \

  1342.   gen_rtx_fmt_ee (COND_EXEC, (MODE), (ARG0), (ARG1))

  1343. #define gen_rtx_PARALLEL(MODE, ARG0) \

  1344.   gen_rtx_fmt_E (PARALLEL, (MODE), (ARG0))

  1345. #define gen_rtx_ASM_INPUT(MODE, ARG0, ARG1) \

  1346.   gen_rtx_fmt_si (ASM_INPUT, (MODE), (ARG0), (ARG1))

  1347. #define gen_rtx_ASM_OPERANDS(MODE, ARG0, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \

  1348.   gen_rtx_fmt_ssiEEEi (ASM_OPERANDS, (MODE), (ARG0), (ARG1), (ARG2), (ARG3), (ARG4), (ARG5), (ARG6))

  1349. #define gen_rtx_UNSPEC(MODE, ARG0, ARG1) \

  1350.   gen_rtx_fmt_Ei (UNSPEC, (MODE), (ARG0), (ARG1))

  1351. #define gen_rtx_UNSPEC_VOLATILE(MODE, ARG0, ARG1) \

  1352.   gen_rtx_fmt_Ei (UNSPEC_VOLATILE, (MODE), (ARG0), (ARG1))

  1353. #define gen_rtx_ADDR_VEC(MODE, ARG0) \

  1354.   gen_rtx_fmt_E (ADDR_VEC, (MODE), (ARG0))

  1355. #define gen_rtx_ADDR_DIFF_VEC(MODE, ARG0, ARG1, ARG2, ARG3) \

  1356.   gen_rtx_fmt_eEee0 (ADDR_DIFF_VEC, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))

  1357. #define gen_rtx_PREFETCH(MODE, ARG0, ARG1, ARG2) \

  1358.   gen_rtx_fmt_eee (PREFETCH, (MODE), (ARG0), (ARG1), (ARG2))

  1359. #define gen_rtx_SET(ARG0, ARG1) \

  1360.   gen_rtx_fmt_ee (SET, VOIDmode, (ARG0), (ARG1))

  1361. #define gen_rtx_USE(MODE, ARG0) \

  1362.   gen_rtx_fmt_e (USE, (MODE), (ARG0))

  1363. #define gen_rtx_CLOBBER(MODE, ARG0) \

  1364.   gen_rtx_fmt_e (CLOBBER, (MODE), (ARG0))

  1365. #define gen_rtx_CALL(MODE, ARG0, ARG1) \

  1366.   gen_rtx_fmt_ee (CALL, (MODE), (ARG0), (ARG1))

  1367. #define gen_rtx_raw_RETURN(MODE) \

  1368.   gen_rtx_fmt_ (RETURN, (MODE))

  1369. #define gen_rtx_raw_SIMPLE_RETURN(MODE) \

  1370.   gen_rtx_fmt_ (SIMPLE_RETURN, (MODE))

  1371. #define gen_rtx_EH_RETURN(MODE) \

  1372.   gen_rtx_fmt_ (EH_RETURN, (MODE))

  1373. #define gen_rtx_TRAP_IF(MODE, ARG0, ARG1) \

  1374.   gen_rtx_fmt_ee (TRAP_IF, (MODE), (ARG0), (ARG1))

  1375. #define gen_rtx_raw_CONST_INT(MODE, ARG0) \

  1376.   gen_rtx_fmt_w (CONST_INT, (MODE), (ARG0))

  1377. #define gen_rtx_raw_CONST_VECTOR(MODE, ARG0) \

  1378.   gen_rtx_fmt_E (CONST_VECTOR, (MODE), (ARG0))

  1379. #define gen_rtx_CONST_STRING(MODE, ARG0) \

  1380.   gen_rtx_fmt_s (CONST_STRING, (MODE), (ARG0))

  1381. #define gen_rtx_CONST(MODE, ARG0) \

  1382.   gen_rtx_fmt_e (CONST, (MODE), (ARG0))

  1383. #define gen_rtx_raw_PC(MODE) \

  1384.   gen_rtx_fmt_ (PC, (MODE))

  1385. #define gen_rtx_SCRATCH(MODE) \

  1386.   gen_rtx_fmt_ (SCRATCH, (MODE))

  1387. #define gen_rtx_raw_SUBREG(MODE, ARG0, ARG1) \

  1388.   gen_rtx_fmt_ep (SUBREG, (MODE), (ARG0), (ARG1))

  1389. #define gen_rtx_STRICT_LOW_PART(MODE, ARG0) \

  1390.   gen_rtx_fmt_e (STRICT_LOW_PART, (MODE), (ARG0))

  1391. #define gen_rtx_CONCAT(MODE, ARG0, ARG1) \

  1392.   gen_rtx_fmt_ee (CONCAT, (MODE), (ARG0), (ARG1))

  1393. #define gen_rtx_CONCATN(MODE, ARG0) \

  1394.   gen_rtx_fmt_E (CONCATN, (MODE), (ARG0))

  1395. #define gen_rtx_raw_MEM(MODE, ARG0) \

  1396.   gen_rtx_fmt_e0 (MEM, (MODE), (ARG0))

  1397. #define gen_rtx_LABEL_REF(MODE, ARG0) \

  1398.   gen_rtx_fmt_u (LABEL_REF, (MODE), (ARG0))

  1399. #define gen_rtx_SYMBOL_REF(MODE, ARG0) \

  1400.   gen_rtx_fmt_s0 (SYMBOL_REF, (MODE), (ARG0))

  1401. #define gen_rtx_raw_CC0(MODE) \

  1402.   gen_rtx_fmt_ (CC0, (MODE))

  1403. #define gen_rtx_IF_THEN_ELSE(MODE, ARG0, ARG1, ARG2) \

  1404.   gen_rtx_fmt_eee (IF_THEN_ELSE, (MODE), (ARG0), (ARG1), (ARG2))

  1405. #define gen_rtx_COMPARE(MODE, ARG0, ARG1) \

  1406.   gen_rtx_fmt_ee (COMPARE, (MODE), (ARG0), (ARG1))

  1407. #define gen_rtx_PLUS(MODE, ARG0, ARG1) \

  1408.   gen_rtx_fmt_ee (PLUS, (MODE), (ARG0), (ARG1))

  1409. #define gen_rtx_MINUS(MODE, ARG0, ARG1) \

  1410.   gen_rtx_fmt_ee (MINUS, (MODE), (ARG0), (ARG1))

  1411. #define gen_rtx_NEG(MODE, ARG0) \

  1412.   gen_rtx_fmt_e (NEG, (MODE), (ARG0))

  1413. #define gen_rtx_MULT(MODE, ARG0, ARG1) \

  1414.   gen_rtx_fmt_ee (MULT, (MODE), (ARG0), (ARG1))

  1415. #define gen_rtx_SS_MULT(MODE, ARG0, ARG1) \

  1416.   gen_rtx_fmt_ee (SS_MULT, (MODE), (ARG0), (ARG1))

  1417. #define gen_rtx_US_MULT(MODE, ARG0, ARG1) \

  1418.   gen_rtx_fmt_ee (US_MULT, (MODE), (ARG0), (ARG1))

  1419. #define gen_rtx_DIV(MODE, ARG0, ARG1) \

  1420.   gen_rtx_fmt_ee (DIV, (MODE), (ARG0), (ARG1))

  1421. #define gen_rtx_SS_DIV(MODE, ARG0, ARG1) \

  1422.   gen_rtx_fmt_ee (SS_DIV, (MODE), (ARG0), (ARG1))

  1423. #define gen_rtx_US_DIV(MODE, ARG0, ARG1) \

  1424.   gen_rtx_fmt_ee (US_DIV, (MODE), (ARG0), (ARG1))

  1425. #define gen_rtx_MOD(MODE, ARG0, ARG1) \

  1426.   gen_rtx_fmt_ee (MOD, (MODE), (ARG0), (ARG1))

  1427. #define gen_rtx_UDIV(MODE, ARG0, ARG1) \

  1428.   gen_rtx_fmt_ee (UDIV, (MODE), (ARG0), (ARG1))

  1429. #define gen_rtx_UMOD(MODE, ARG0, ARG1) \

  1430.   gen_rtx_fmt_ee (UMOD, (MODE), (ARG0), (ARG1))

  1431. #define gen_rtx_AND(MODE, ARG0, ARG1) \

  1432.   gen_rtx_fmt_ee (AND, (MODE), (ARG0), (ARG1))

  1433. #define gen_rtx_IOR(MODE, ARG0, ARG1) \

  1434.   gen_rtx_fmt_ee (IOR, (MODE), (ARG0), (ARG1))

  1435. #define gen_rtx_XOR(MODE, ARG0, ARG1) \

  1436.   gen_rtx_fmt_ee (XOR, (MODE), (ARG0), (ARG1))

  1437. #define gen_rtx_NOT(MODE, ARG0) \

  1438.   gen_rtx_fmt_e (NOT, (MODE), (ARG0))

  1439. #define gen_rtx_ASHIFT(MODE, ARG0, ARG1) \

  1440.   gen_rtx_fmt_ee (ASHIFT, (MODE), (ARG0), (ARG1))

  1441. #define gen_rtx_ROTATE(MODE, ARG0, ARG1) \

  1442.   gen_rtx_fmt_ee (ROTATE, (MODE), (ARG0), (ARG1))

  1443. #define gen_rtx_ASHIFTRT(MODE, ARG0, ARG1) \

  1444.   gen_rtx_fmt_ee (ASHIFTRT, (MODE), (ARG0), (ARG1))

  1445. #define gen_rtx_LSHIFTRT(MODE, ARG0, ARG1) \

  1446.   gen_rtx_fmt_ee (LSHIFTRT, (MODE), (ARG0), (ARG1))

  1447. #define gen_rtx_ROTATERT(MODE, ARG0, ARG1) \

  1448.   gen_rtx_fmt_ee (ROTATERT, (MODE), (ARG0), (ARG1))

  1449. #define gen_rtx_SMIN(MODE, ARG0, ARG1) \

  1450.   gen_rtx_fmt_ee (SMIN, (MODE), (ARG0), (ARG1))

  1451. #define gen_rtx_SMAX(MODE, ARG0, ARG1) \

  1452.   gen_rtx_fmt_ee (SMAX, (MODE), (ARG0), (ARG1))

  1453. #define gen_rtx_UMIN(MODE, ARG0, ARG1) \

  1454.   gen_rtx_fmt_ee (UMIN, (MODE), (ARG0), (ARG1))

  1455. #define gen_rtx_UMAX(MODE, ARG0, ARG1) \

  1456.   gen_rtx_fmt_ee (UMAX, (MODE), (ARG0), (ARG1))

  1457. #define gen_rtx_PRE_DEC(MODE, ARG0) \

  1458.   gen_rtx_fmt_e (PRE_DEC, (MODE), (ARG0))

  1459. #define gen_rtx_PRE_INC(MODE, ARG0) \

  1460.   gen_rtx_fmt_e (PRE_INC, (MODE), (ARG0))

  1461. #define gen_rtx_POST_DEC(MODE, ARG0) \

  1462.   gen_rtx_fmt_e (POST_DEC, (MODE), (ARG0))

  1463. #define gen_rtx_POST_INC(MODE, ARG0) \

  1464.   gen_rtx_fmt_e (POST_INC, (MODE), (ARG0))

  1465. #define gen_rtx_PRE_MODIFY(MODE, ARG0, ARG1) \

  1466.   gen_rtx_fmt_ee (PRE_MODIFY, (MODE), (ARG0), (ARG1))

  1467. #define gen_rtx_POST_MODIFY(MODE, ARG0, ARG1) \

  1468.   gen_rtx_fmt_ee (POST_MODIFY, (MODE), (ARG0), (ARG1))

  1469. #define gen_rtx_NE(MODE, ARG0, ARG1) \

  1470.   gen_rtx_fmt_ee (NE, (MODE), (ARG0), (ARG1))

  1471. #define gen_rtx_EQ(MODE, ARG0, ARG1) \

  1472.   gen_rtx_fmt_ee (EQ, (MODE), (ARG0), (ARG1))

  1473. #define gen_rtx_GE(MODE, ARG0, ARG1) \

  1474.   gen_rtx_fmt_ee (GE, (MODE), (ARG0), (ARG1))

  1475. #define gen_rtx_GT(MODE, ARG0, ARG1) \

  1476.   gen_rtx_fmt_ee (GT, (MODE), (ARG0), (ARG1))

  1477. #define gen_rtx_LE(MODE, ARG0, ARG1) \

  1478.   gen_rtx_fmt_ee (LE, (MODE), (ARG0), (ARG1))

  1479. #define gen_rtx_LT(MODE, ARG0, ARG1) \

  1480.   gen_rtx_fmt_ee (LT, (MODE), (ARG0), (ARG1))

  1481. #define gen_rtx_LTGT(MODE, ARG0, ARG1) \

  1482.   gen_rtx_fmt_ee (LTGT, (MODE), (ARG0), (ARG1))

  1483. #define gen_rtx_GEU(MODE, ARG0, ARG1) \

  1484.   gen_rtx_fmt_ee (GEU, (MODE), (ARG0), (ARG1))

  1485. #define gen_rtx_GTU(MODE, ARG0, ARG1) \

  1486.   gen_rtx_fmt_ee (GTU, (MODE), (ARG0), (ARG1))

  1487. #define gen_rtx_LEU(MODE, ARG0, ARG1) \

  1488.   gen_rtx_fmt_ee (LEU, (MODE), (ARG0), (ARG1))

  1489. #define gen_rtx_LTU(MODE, ARG0, ARG1) \

  1490.   gen_rtx_fmt_ee (LTU, (MODE), (ARG0), (ARG1))

  1491. #define gen_rtx_UNORDERED(MODE, ARG0, ARG1) \

  1492.   gen_rtx_fmt_ee (UNORDERED, (MODE), (ARG0), (ARG1))

  1493. #define gen_rtx_ORDERED(MODE, ARG0, ARG1) \

  1494.   gen_rtx_fmt_ee (ORDERED, (MODE), (ARG0), (ARG1))

  1495. #define gen_rtx_UNEQ(MODE, ARG0, ARG1) \

  1496.   gen_rtx_fmt_ee (UNEQ, (MODE), (ARG0), (ARG1))

  1497. #define gen_rtx_UNGE(MODE, ARG0, ARG1) \

  1498.   gen_rtx_fmt_ee (UNGE, (MODE), (ARG0), (ARG1))

  1499. #define gen_rtx_UNGT(MODE, ARG0, ARG1) \

  1500.   gen_rtx_fmt_ee (UNGT, (MODE), (ARG0), (ARG1))

  1501. #define gen_rtx_UNLE(MODE, ARG0, ARG1) \

  1502.   gen_rtx_fmt_ee (UNLE, (MODE), (ARG0), (ARG1))

  1503. #define gen_rtx_UNLT(MODE, ARG0, ARG1) \

  1504.   gen_rtx_fmt_ee (UNLT, (MODE), (ARG0), (ARG1))

  1505. #define gen_rtx_SIGN_EXTEND(MODE, ARG0) \

  1506.   gen_rtx_fmt_e (SIGN_EXTEND, (MODE), (ARG0))

  1507. #define gen_rtx_ZERO_EXTEND(MODE, ARG0) \

  1508.   gen_rtx_fmt_e (ZERO_EXTEND, (MODE), (ARG0))

  1509. #define gen_rtx_TRUNCATE(MODE, ARG0) \

  1510.   gen_rtx_fmt_e (TRUNCATE, (MODE), (ARG0))

  1511. #define gen_rtx_FLOAT_EXTEND(MODE, ARG0) \

  1512.   gen_rtx_fmt_e (FLOAT_EXTEND, (MODE), (ARG0))

  1513. #define gen_rtx_FLOAT_TRUNCATE(MODE, ARG0) \

  1514.   gen_rtx_fmt_e (FLOAT_TRUNCATE, (MODE), (ARG0))

  1515. #define gen_rtx_FLOAT(MODE, ARG0) \

  1516.   gen_rtx_fmt_e (FLOAT, (MODE), (ARG0))

  1517. #define gen_rtx_FIX(MODE, ARG0) \

  1518.   gen_rtx_fmt_e (FIX, (MODE), (ARG0))

  1519. #define gen_rtx_UNSIGNED_FLOAT(MODE, ARG0) \

  1520.   gen_rtx_fmt_e (UNSIGNED_FLOAT, (MODE), (ARG0))

  1521. #define gen_rtx_UNSIGNED_FIX(MODE, ARG0) \

  1522.   gen_rtx_fmt_e (UNSIGNED_FIX, (MODE), (ARG0))

  1523. #define gen_rtx_FRACT_CONVERT(MODE, ARG0) \

  1524.   gen_rtx_fmt_e (FRACT_CONVERT, (MODE), (ARG0))

  1525. #define gen_rtx_UNSIGNED_FRACT_CONVERT(MODE, ARG0) \

  1526.   gen_rtx_fmt_e (UNSIGNED_FRACT_CONVERT, (MODE), (ARG0))

  1527. #define gen_rtx_SAT_FRACT(MODE, ARG0) \

  1528.   gen_rtx_fmt_e (SAT_FRACT, (MODE), (ARG0))

  1529. #define gen_rtx_UNSIGNED_SAT_FRACT(MODE, ARG0) \

  1530.   gen_rtx_fmt_e (UNSIGNED_SAT_FRACT, (MODE), (ARG0))

  1531. #define gen_rtx_ABS(MODE, ARG0) \

  1532.   gen_rtx_fmt_e (ABS, (MODE), (ARG0))

  1533. #define gen_rtx_SQRT(MODE, ARG0) \

  1534.   gen_rtx_fmt_e (SQRT, (MODE), (ARG0))

  1535. #define gen_rtx_BSWAP(MODE, ARG0) \

  1536.   gen_rtx_fmt_e (BSWAP, (MODE), (ARG0))

  1537. #define gen_rtx_FFS(MODE, ARG0) \

  1538.   gen_rtx_fmt_e (FFS, (MODE), (ARG0))

  1539. #define gen_rtx_CLRSB(MODE, ARG0) \

  1540.   gen_rtx_fmt_e (CLRSB, (MODE), (ARG0))

  1541. #define gen_rtx_CLZ(MODE, ARG0) \

  1542.   gen_rtx_fmt_e (CLZ, (MODE), (ARG0))

  1543. #define gen_rtx_CTZ(MODE, ARG0) \

  1544.   gen_rtx_fmt_e (CTZ, (MODE), (ARG0))

  1545. #define gen_rtx_POPCOUNT(MODE, ARG0) \

  1546.   gen_rtx_fmt_e (POPCOUNT, (MODE), (ARG0))

  1547. #define gen_rtx_PARITY(MODE, ARG0) \

  1548.   gen_rtx_fmt_e (PARITY, (MODE), (ARG0))

  1549. #define gen_rtx_SIGN_EXTRACT(MODE, ARG0, ARG1, ARG2) \

  1550.   gen_rtx_fmt_eee (SIGN_EXTRACT, (MODE), (ARG0), (ARG1), (ARG2))

  1551. #define gen_rtx_ZERO_EXTRACT(MODE, ARG0, ARG1, ARG2) \

  1552.   gen_rtx_fmt_eee (ZERO_EXTRACT, (MODE), (ARG0), (ARG1), (ARG2))

  1553. #define gen_rtx_HIGH(MODE, ARG0) \

  1554.   gen_rtx_fmt_e (HIGH, (MODE), (ARG0))

  1555. #define gen_rtx_LO_SUM(MODE, ARG0, ARG1) \

  1556.   gen_rtx_fmt_ee (LO_SUM, (MODE), (ARG0), (ARG1))

  1557. #define gen_rtx_VEC_MERGE(MODE, ARG0, ARG1, ARG2) \

  1558.   gen_rtx_fmt_eee (VEC_MERGE, (MODE), (ARG0), (ARG1), (ARG2))

  1559. #define gen_rtx_VEC_SELECT(MODE, ARG0, ARG1) \

  1560.   gen_rtx_fmt_ee (VEC_SELECT, (MODE), (ARG0), (ARG1))

  1561. #define gen_rtx_VEC_CONCAT(MODE, ARG0, ARG1) \

  1562.   gen_rtx_fmt_ee (VEC_CONCAT, (MODE), (ARG0), (ARG1))

  1563. #define gen_rtx_VEC_DUPLICATE(MODE, ARG0) \

  1564.   gen_rtx_fmt_e (VEC_DUPLICATE, (MODE), (ARG0))

  1565. #define gen_rtx_VEC_SERIES(MODE, ARG0, ARG1) \

  1566.   gen_rtx_fmt_ee (VEC_SERIES, (MODE), (ARG0), (ARG1))

  1567. #define gen_rtx_SS_PLUS(MODE, ARG0, ARG1) \

  1568.   gen_rtx_fmt_ee (SS_PLUS, (MODE), (ARG0), (ARG1))

  1569. #define gen_rtx_US_PLUS(MODE, ARG0, ARG1) \

  1570.   gen_rtx_fmt_ee (US_PLUS, (MODE), (ARG0), (ARG1))

  1571. #define gen_rtx_SS_MINUS(MODE, ARG0, ARG1) \

  1572.   gen_rtx_fmt_ee (SS_MINUS, (MODE), (ARG0), (ARG1))

  1573. #define gen_rtx_SS_NEG(MODE, ARG0) \

  1574.   gen_rtx_fmt_e (SS_NEG, (MODE), (ARG0))

  1575. #define gen_rtx_US_NEG(MODE, ARG0) \

  1576.   gen_rtx_fmt_e (US_NEG, (MODE), (ARG0))

  1577. #define gen_rtx_SS_ABS(MODE, ARG0) \

  1578.   gen_rtx_fmt_e (SS_ABS, (MODE), (ARG0))

  1579. #define gen_rtx_SS_ASHIFT(MODE, ARG0, ARG1) \

  1580.   gen_rtx_fmt_ee (SS_ASHIFT, (MODE), (ARG0), (ARG1))

  1581. #define gen_rtx_US_ASHIFT(MODE, ARG0, ARG1) \

  1582.   gen_rtx_fmt_ee (US_ASHIFT, (MODE), (ARG0), (ARG1))

  1583. #define gen_rtx_US_MINUS(MODE, ARG0, ARG1) \

  1584.   gen_rtx_fmt_ee (US_MINUS, (MODE), (ARG0), (ARG1))

  1585. #define gen_rtx_SS_TRUNCATE(MODE, ARG0) \

  1586.   gen_rtx_fmt_e (SS_TRUNCATE, (MODE), (ARG0))

  1587. #define gen_rtx_US_TRUNCATE(MODE, ARG0) \

  1588.   gen_rtx_fmt_e (US_TRUNCATE, (MODE), (ARG0))

  1589. #define gen_rtx_FMA(MODE, ARG0, ARG1, ARG2) \

  1590.   gen_rtx_fmt_eee (FMA, (MODE), (ARG0), (ARG1), (ARG2))

  1591. #define gen_rtx_DEBUG_IMPLICIT_PTR(MODE, ARG0) \

  1592.   gen_rtx_fmt_t (DEBUG_IMPLICIT_PTR, (MODE), (ARG0))

  1593. #define gen_rtx_ENTRY_VALUE(MODE) \

  1594.   gen_rtx_fmt_0 (ENTRY_VALUE, (MODE))

  1595. #define gen_rtx_DEBUG_PARAMETER_REF(MODE, ARG0) \

  1596.   gen_rtx_fmt_t (DEBUG_PARAMETER_REF, (MODE), (ARG0))

  1597. #define gen_rtx_DEBUG_MARKER(MODE) \

  1598.   gen_rtx_fmt_ (DEBUG_MARKER, (MODE))

  1599. #define gen_rtx_MATCH_OPERAND(MODE, ARG0, ARG1, ARG2) \

  1600.   gen_rtx_fmt_iss (MATCH_OPERAND, (MODE), (ARG0), (ARG1), (ARG2))

  1601. #define gen_rtx_MATCH_SCRATCH(MODE, ARG0, ARG1) \

  1602.   gen_rtx_fmt_is (MATCH_SCRATCH, (MODE), (ARG0), (ARG1))

  1603. #define gen_rtx_MATCH_OPERATOR(MODE, ARG0, ARG1, ARG2) \

  1604.   gen_rtx_fmt_isE (MATCH_OPERATOR, (MODE), (ARG0), (ARG1), (ARG2))

  1605. #define gen_rtx_MATCH_PARALLEL(MODE, ARG0, ARG1, ARG2) \

  1606.   gen_rtx_fmt_isE (MATCH_PARALLEL, (MODE), (ARG0), (ARG1), (ARG2))

  1607. #define gen_rtx_MATCH_DUP(MODE, ARG0) \

  1608.   gen_rtx_fmt_i (MATCH_DUP, (MODE), (ARG0))

  1609. #define gen_rtx_MATCH_OP_DUP(MODE, ARG0, ARG1) \

  1610.   gen_rtx_fmt_iE (MATCH_OP_DUP, (MODE), (ARG0), (ARG1))

  1611. #define gen_rtx_MATCH_PAR_DUP(MODE, ARG0, ARG1) \

  1612.   gen_rtx_fmt_iE (MATCH_PAR_DUP, (MODE), (ARG0), (ARG1))

  1613. #define gen_rtx_MATCH_CODE(MODE, ARG0, ARG1) \

  1614.   gen_rtx_fmt_ss (MATCH_CODE, (MODE), (ARG0), (ARG1))

  1615. #define gen_rtx_MATCH_TEST(MODE, ARG0) \

  1616.   gen_rtx_fmt_s (MATCH_TEST, (MODE), (ARG0))

  1617. #define gen_rtx_DEFINE_DELAY(MODE, ARG0, ARG1) \

  1618.   gen_rtx_fmt_eE (DEFINE_DELAY, (MODE), (ARG0), (ARG1))

  1619. #define gen_rtx_DEFINE_PREDICATE(MODE, ARG0, ARG1, ARG2) \

  1620.   gen_rtx_fmt_ses (DEFINE_PREDICATE, (MODE), (ARG0), (ARG1), (ARG2))

  1621. #define gen_rtx_DEFINE_SPECIAL_PREDICATE(MODE, ARG0, ARG1, ARG2) \

  1622.   gen_rtx_fmt_ses (DEFINE_SPECIAL_PREDICATE, (MODE), (ARG0), (ARG1), (ARG2))

  1623. #define gen_rtx_DEFINE_REGISTER_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \

  1624.   gen_rtx_fmt_sss (DEFINE_REGISTER_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))

  1625. #define gen_rtx_DEFINE_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \

  1626.   gen_rtx_fmt_sse (DEFINE_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))

  1627. #define gen_rtx_DEFINE_MEMORY_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \

  1628.   gen_rtx_fmt_sse (DEFINE_MEMORY_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))

  1629. #define gen_rtx_DEFINE_SPECIAL_MEMORY_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \

  1630.   gen_rtx_fmt_sse (DEFINE_SPECIAL_MEMORY_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))

  1631. #define gen_rtx_DEFINE_ADDRESS_CONSTRAINT(MODE, ARG0, ARG1, ARG2) \

  1632.   gen_rtx_fmt_sse (DEFINE_ADDRESS_CONSTRAINT, (MODE), (ARG0), (ARG1), (ARG2))

  1633. #define gen_rtx_EXCLUSION_SET(MODE, ARG0, ARG1) \

  1634.   gen_rtx_fmt_ss (EXCLUSION_SET, (MODE), (ARG0), (ARG1))

  1635. #define gen_rtx_PRESENCE_SET(MODE, ARG0, ARG1) \

  1636.   gen_rtx_fmt_ss (PRESENCE_SET, (MODE), (ARG0), (ARG1))

  1637. #define gen_rtx_FINAL_PRESENCE_SET(MODE, ARG0, ARG1) \

  1638.   gen_rtx_fmt_ss (FINAL_PRESENCE_SET, (MODE), (ARG0), (ARG1))

  1639. #define gen_rtx_ABSENCE_SET(MODE, ARG0, ARG1) \

  1640.   gen_rtx_fmt_ss (ABSENCE_SET, (MODE), (ARG0), (ARG1))

  1641. #define gen_rtx_FINAL_ABSENCE_SET(MODE, ARG0, ARG1) \

  1642.   gen_rtx_fmt_ss (FINAL_ABSENCE_SET, (MODE), (ARG0), (ARG1))

  1643. #define gen_rtx_DEFINE_AUTOMATON(MODE, ARG0) \

  1644.   gen_rtx_fmt_s (DEFINE_AUTOMATON, (MODE), (ARG0))

  1645. #define gen_rtx_AUTOMATA_OPTION(MODE, ARG0) \

  1646.   gen_rtx_fmt_s (AUTOMATA_OPTION, (MODE), (ARG0))

  1647. #define gen_rtx_DEFINE_RESERVATION(MODE, ARG0, ARG1) \

  1648.   gen_rtx_fmt_ss (DEFINE_RESERVATION, (MODE), (ARG0), (ARG1))

  1649. #define gen_rtx_DEFINE_INSN_RESERVATION(MODE, ARG0, ARG1, ARG2, ARG3) \

  1650.   gen_rtx_fmt_sies (DEFINE_INSN_RESERVATION, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))

  1651. #define gen_rtx_DEFINE_ATTR(MODE, ARG0, ARG1, ARG2) \

  1652.   gen_rtx_fmt_sse (DEFINE_ATTR, (MODE), (ARG0), (ARG1), (ARG2))

  1653. #define gen_rtx_DEFINE_ENUM_ATTR(MODE, ARG0, ARG1, ARG2) \

  1654.   gen_rtx_fmt_sse (DEFINE_ENUM_ATTR, (MODE), (ARG0), (ARG1), (ARG2))

  1655. #define gen_rtx_ATTR(MODE, ARG0) \

  1656.   gen_rtx_fmt_s (ATTR, (MODE), (ARG0))

  1657. #define gen_rtx_SET_ATTR(MODE, ARG0, ARG1) \

  1658.   gen_rtx_fmt_ss (SET_ATTR, (MODE), (ARG0), (ARG1))

  1659. #define gen_rtx_SET_ATTR_ALTERNATIVE(MODE, ARG0, ARG1) \

  1660.   gen_rtx_fmt_sE (SET_ATTR_ALTERNATIVE, (MODE), (ARG0), (ARG1))

  1661. #define gen_rtx_EQ_ATTR(MODE, ARG0, ARG1) \

  1662.   gen_rtx_fmt_ss (EQ_ATTR, (MODE), (ARG0), (ARG1))

  1663. #define gen_rtx_EQ_ATTR_ALT(MODE, ARG0, ARG1) \

  1664.   gen_rtx_fmt_ww (EQ_ATTR_ALT, (MODE), (ARG0), (ARG1))

  1665. #define gen_rtx_ATTR_FLAG(MODE, ARG0) \

  1666.   gen_rtx_fmt_s (ATTR_FLAG, (MODE), (ARG0))

  1667. #define gen_rtx_COND(MODE, ARG0, ARG1) \

  1668.   gen_rtx_fmt_Ee (COND, (MODE), (ARG0), (ARG1))

  1669. #define gen_rtx_DEFINE_SUBST(MODE, ARG0, ARG1, ARG2, ARG3) \

  1670.   gen_rtx_fmt_sEsE (DEFINE_SUBST, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))

  1671. #define gen_rtx_DEFINE_SUBST_ATTR(MODE, ARG0, ARG1, ARG2, ARG3) \

  1672.   gen_rtx_fmt_ssss (DEFINE_SUBST_ATTR, (MODE), (ARG0), (ARG1), (ARG2), (ARG3))

  1673. 

  1674. #endif /* GCC_GENRTL_H */