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<a name="AArch64-Opcodes"></a>
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Next: <a href="AArch64-Mapping-Symbols.html#AArch64-Mapping-Symbols" accesskey="n" rel="next">AArch64 Mapping Symbols</a>, Previous: <a href="AArch64-Directives.html#AArch64-Directives" accesskey="p" rel="prev">AArch64 Directives</a>, Up: <a href="AArch64_002dDependent.html#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<a name="Opcodes"></a>
<h4 class="subsection">9.1.6 Opcodes</h4>

<a name="index-AArch64-opcodes"></a>
<a name="index-opcodes-for-AArch64"></a>
<p>GAS implements all the standard AArch64 opcodes.  It also
implements several pseudo opcodes, including several synthetic load
instructions.
</p>
<dl compact="compact">
<dd>
<a name="index-LDR-reg_002c_003d_003cexpr_003e-pseudo-op_002c-AArch64"></a>
</dd>
<dt><code>LDR =</code></dt>
<dd><div class="smallexample">
<pre class="smallexample">  ldr &lt;register&gt; , =&lt;expression&gt;
</pre></div>

<p>The constant expression will be placed into the nearest literal pool (if it not
already there) and a PC-relative LDR instruction will be generated.
</p>
</dd>
</dl>

<p>For more information on the AArch64 instruction set and assembly language
notation, see &lsquo;<samp>ARMv8 Instruction Set Overview</samp>&rsquo; available at
<a href="http://infocenter.arm.com">http://infocenter.arm.com</a>.
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