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<title>ARC Options (Using as)</title>

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<a name="ARC-Options"></a>
<div class="header">
<p>
Next: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="n" rel="next">ARC Syntax</a>, Up: <a href="ARC_002dDependent.html#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="Options-2"></a>
<h4 class="subsection">9.3.1 Options</h4>
<a name="index-ARC-options"></a>
<a name="index-options-for-ARC"></a>

<p>The following options control the type of CPU for which code is
assembled, and generic constraints on the code generated:
</p>
<dl compact="compact">
<dt><code>-mcpu=<var>cpu</var></code></dt>
<dd><a name="index-_002dmcpu_003dcpu-command_002dline-option_002c-ARC"></a>
<p>Set architecture type and register usage for <var>cpu</var>.  There are
also shortcut alias options available for backward compatibility and
convenience.  Supported values for <var>cpu</var> are
</p>
<dl compact="compact">
<dd><a name="index-mA6-command_002dline-option_002c-ARC"></a>
<a name="index-marc600-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>arc600</code></dt>
<dd><p>Assemble for ARC 600.  Aliases: <code>-mA6</code>, <code>-mARC600</code>.
</p>
</dd>
<dt><code>arc600_norm</code></dt>
<dd><p>Assemble for ARC 600 with norm instructions.
</p>
</dd>
<dt><code>arc600_mul64</code></dt>
<dd><p>Assemble for ARC 600 with mul64 instructions.
</p>
</dd>
<dt><code>arc600_mul32x16</code></dt>
<dd><p>Assemble for ARC 600 with mul32x16 instructions.
</p>
</dd>
<dt><code>arc601</code></dt>
<dd><a name="index-mARC601-command_002dline-option_002c-ARC"></a>
<p>Assemble for ARC 601.  Alias: <code>-mARC601</code>.
</p>
</dd>
<dt><code>arc601_norm</code></dt>
<dd><p>Assemble for ARC 601 with norm instructions.
</p>
</dd>
<dt><code>arc601_mul64</code></dt>
<dd><p>Assemble for ARC 601 with mul64 instructions.
</p>
</dd>
<dt><code>arc601_mul32x16</code></dt>
<dd><p>Assemble for ARC 601 with mul32x16 instructions.
</p>
</dd>
<dt><code>arc700</code></dt>
<dd><a name="index-mA7-command_002dline-option_002c-ARC"></a>
<a name="index-mARC700-command_002dline-option_002c-ARC"></a>
<p>Assemble for ARC 700.  Aliases: <code>-mA7</code>, <code>-mARC700</code>.
</p>
</dd>
<dt><code>arcem</code></dt>
<dd><a name="index-mEM-command_002dline-option_002c-ARC"></a>
<p>Assemble for ARC EM.  Aliases: <code>-mEM</code>
</p>
</dd>
<dt><code>em</code></dt>
<dd><p>Assemble for ARC EM, identical as arcem variant.
</p>
</dd>
<dt><code>em4</code></dt>
<dd><p>Assemble for ARC EM with code-density instructions.
</p>
</dd>
<dt><code>em4_dmips</code></dt>
<dd><p>Assemble for ARC EM with code-density instructions.
</p>
</dd>
<dt><code>em4_fpus</code></dt>
<dd><p>Assemble for ARC EM with code-density instructions.
</p>
</dd>
<dt><code>em4_fpuda</code></dt>
<dd><p>Assemble for ARC EM with code-density, and double-precision assist
instructions.
</p>
</dd>
<dt><code>quarkse_em</code></dt>
<dd><p>Assemble for QuarkSE-EM cpu.
</p>
</dd>
<dt><code>archs</code></dt>
<dd><a name="index-mHS-command_002dline-option_002c-ARC"></a>
<p>Assemble for ARC HS.  Aliases: <code>-mHS</code>, <code>-mav2hs</code>.
</p>
</dd>
<dt><code>hs</code></dt>
<dd><p>Assemble for ARC HS.
</p>
</dd>
<dt><code>hs34</code></dt>
<dd><p>Assemble for ARC HS34.
</p>
</dd>
<dt><code>hs38</code></dt>
<dd><p>Assemble for ARC HS38.
</p>
</dd>
<dt><code>hs38_linux</code></dt>
<dd><p>Assemble for ARC HS38 with floating point support on.
</p>
</dd>
<dt><code>nps400</code></dt>
<dd><a name="index-mnps400-command_002dline-option_002c-ARC"></a>
<p>Assemble for ARC 700 with NPS-400 extended instructions.
</p>
</dd>
</dl>

<p>Note: the <code>.cpu</code> directive (see <a href="ARC-Directives.html#ARC-Directives">ARC Directives</a>) can
to be used to select a core variant from within assembly code.
</p>
<a name="index-_002dEB-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-EB</code></dt>
<dd><p>This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
</p>
<a name="index-_002dEL-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-EL</code></dt>
<dd><p>This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor - this is the
default.
</p>
<a name="index-_002dmcode_002ddensity-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-mcode-density</code></dt>
<dd><p>This option turns on Code Density instructions.  Only valid for ARC EM
processors.
</p>
<a name="index-_002dmrelax-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-mrelax</code></dt>
<dd><p>Enable support for assembly-time relaxation.  The assembler will
replace a longer version of an instruction with a shorter one,
whenever it is possible.
</p>
<a name="index-_002dmnps400-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-mnps400</code></dt>
<dd><p>Enable support for NPS-400 extended instructions.
</p>
<a name="index-_002dmspfp-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-mspfp</code></dt>
<dd><p>Enable support for single-precision floating point instructions.
</p>
<a name="index-_002dmdpfp-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-mdpfp</code></dt>
<dd><p>Enable support for double-precision floating point instructions.
</p>
<a name="index-_002dmfpuda-command_002dline-option_002c-ARC"></a>
</dd>
<dt><code>-mfpuda</code></dt>
<dd><p>Enable support for double-precision assist floating point instructions.
Only valid for ARC EM processors.
</p>
</dd>
</dl>

<hr>
<div class="header">
<p>
Next: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="n" rel="next">ARC Syntax</a>, Up: <a href="ARC_002dDependent.html#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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