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<a name="M32R_002dWarnings"></a>
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<hr>
<a name="M32R-Warnings"></a>
<h4 class="subsection">9.21.3 M32R Warnings</h4>

<a name="index-warnings_002c-M32R"></a>
<a name="index-M32R-warnings"></a>

<p>There are several warning and error messages that can be produced by
<code>as</code> which are specific to the M32R:
</p>
<dl compact="compact">
<dt><code>output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?</code></dt>
<dd><p>This message is only produced if warnings for explicit parallel
conflicts have been enabled.  It indicates that the assembler has
encountered a parallel instruction in which the destination register of
the left hand instruction is used as an input register in the right hand
instruction.  For example in this code fragment
&lsquo;<samp>mv r1, r2 || neg r3, r1</samp>&rsquo; register r1 is the destination of the
move instruction and the input to the neg instruction.
</p>
</dd>
<dt><code>output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?</code></dt>
<dd><p>This message is only produced if warnings for explicit parallel
conflicts have been enabled.  It indicates that the assembler has
encountered a parallel instruction in which the destination register of
the right hand instruction is used as an input register in the left hand
instruction.  For example in this code fragment
&lsquo;<samp>mv r1, r2 || neg r2, r3</samp>&rsquo; register r2 is the destination of the
neg instruction and the input to the move instruction.
</p>
</dd>
<dt><code>instruction &lsquo;<samp>...</samp>&rsquo; is for the M32RX only</code></dt>
<dd><p>This message is produced when the assembler encounters an instruction
which is only supported by the M32Rx processor, and the &lsquo;<samp>-m32rx</samp>&rsquo;
command-line flag has not been specified to allow assembly of such
instructions.
</p>
</dd>
<dt><code>unknown instruction &lsquo;<samp>...</samp>&rsquo;</code></dt>
<dd><p>This message is produced when the assembler encounters an instruction
which it does not recognize.
</p>
</dd>
<dt><code>only the NOP instruction can be issued in parallel on the m32r</code></dt>
<dd><p>This message is produced when the assembler encounters a parallel
instruction which does not involve a NOP instruction and the
&lsquo;<samp>-m32rx</samp>&rsquo; command-line flag has not been specified.  Only the M32Rx
processor is able to execute two instructions in parallel.
</p>
</dd>
<dt><code>instruction &lsquo;<samp>...</samp>&rsquo; cannot be executed in parallel.</code></dt>
<dd><p>This message is produced when the assembler encounters a parallel
instruction which is made up of one or two instructions which cannot be
executed in parallel.
</p>
</dd>
<dt><code>Instructions share the same execution pipeline</code></dt>
<dd><p>This message is produced when the assembler encounters a parallel
instruction whose components both use the same execution pipeline.
</p>
</dd>
<dt><code>Instructions write to the same destination register.</code></dt>
<dd><p>This message is produced when the assembler encounters a parallel
instruction where both components attempt to modify the same register.
For example these code fragments will produce this message:
&lsquo;<samp>mv r1, r2 || neg r1, r3</samp>&rsquo;
&lsquo;<samp>jl r0 || mv r14, r1</samp>&rsquo;
&lsquo;<samp>st r2, @-r1 || mv r1, r3</samp>&rsquo;
&lsquo;<samp>mv r1, r2 || ld r0, @r1+</samp>&rsquo;
&lsquo;<samp>cmp r1, r2 || addx r3, r4</samp>&rsquo; (Both write to the condition bit)
</p>
</dd>
</dl>

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