visus
/
toolchain-gcc-arm-embedded
Obserwuj 1
Polub 0
Forkuj 0
Kod Zgłoszenia 0 Oczekujące zmiany 0 Wydania 0 Wiki Aktywność
Nie możesz wybrać więcej, niż 25 tematów Tematy muszą się zaczynać od litery lub cyfry, mogą zawierać myślniki ('-') i mogą mieć do 35 znaków.
2 Commity
1 Gałąź
Drzewo: 898a39b5ab
Gałęzie Tagi
${ item.name }
Utwórz gałąź ${ searchTerm }
z '898a39b5ab'
${ noResults }
toolchain-gcc-arm-embedded/share/doc/gcc-arm-none-eabi/html/as.html/MIPS-Options.html

707 lines
28KB
Czysty Wina Historia 

  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

  2. <html>

  3. <!-- This file documents the GNU Assembler "as".

  4. 

  5. Copyright (C) 1991-2020 Free Software Foundation, Inc.

  6. 

  7. Permission is granted to copy, distribute and/or modify this document

  8. under the terms of the GNU Free Documentation License, Version 1.3

  9. or any later version published by the Free Software Foundation;

  10. with no Invariant Sections, with no Front-Cover Texts, and with no

  11. Back-Cover Texts.  A copy of the license is included in the

  12. section entitled "GNU Free Documentation License".

  13.  -->

  14. <!-- Created by GNU Texinfo 6.5, http://www.gnu.org/software/texinfo/ -->

  15. <head>

  16. <meta http-equiv="Content-Type" content="text/html; charset=utf-8">

  17. <title>MIPS Options (Using as)</title>

  18. 

  19. <meta name="description" content="MIPS Options (Using as)">

  20. <meta name="keywords" content="MIPS Options (Using as)">

  21. <meta name="resource-type" content="document">

  22. <meta name="distribution" content="global">

  23. <meta name="Generator" content="makeinfo">

  24. <link href="index.html#Top" rel="start" title="Top">

  25. <link href="AS-Index.html#AS-Index" rel="index" title="AS Index">

  26. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">

  27. <link href="MIPS_002dDependent.html#MIPS_002dDependent" rel="up" title="MIPS-Dependent">

  28. <link href="MIPS-Macros.html#MIPS-Macros" rel="next" title="MIPS Macros">

  29. <link href="MIPS_002dDependent.html#MIPS_002dDependent" rel="prev" title="MIPS-Dependent">

  30. <style type="text/css">

  31. <!--

  32. a.summary-letter {text-decoration: none}

  33. blockquote.indentedblock {margin-right: 0em}

  34. blockquote.smallindentedblock {margin-right: 0em; font-size: smaller}

  35. blockquote.smallquotation {font-size: smaller}

  36. div.display {margin-left: 3.2em}

  37. div.example {margin-left: 3.2em}

  38. div.lisp {margin-left: 3.2em}

  39. div.smalldisplay {margin-left: 3.2em}

  40. div.smallexample {margin-left: 3.2em}

  41. div.smalllisp {margin-left: 3.2em}

  42. kbd {font-style: oblique}

  43. pre.display {font-family: inherit}

  44. pre.format {font-family: inherit}

  45. pre.menu-comment {font-family: serif}

  46. pre.menu-preformatted {font-family: serif}

  47. pre.smalldisplay {font-family: inherit; font-size: smaller}

  48. pre.smallexample {font-size: smaller}

  49. pre.smallformat {font-family: inherit; font-size: smaller}

  50. pre.smalllisp {font-size: smaller}

  51. span.nolinebreak {white-space: nowrap}

  52. span.roman {font-family: initial; font-weight: normal}

  53. span.sansserif {font-family: sans-serif; font-weight: normal}

  54. ul.no-bullet {list-style: none}

  55. -->

  56. </style>

  57. 

  58. 

  59. </head>

  60. 

  61. <body lang="en">

  62. <a name="MIPS-Options"></a>

  63. <div class="header">

  64. <p>

  65. Next: <a href="MIPS-Macros.html#MIPS-Macros" accesskey="n" rel="next">MIPS Macros</a>, Up: <a href="MIPS_002dDependent.html#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  66. </div>

  67. <hr>

  68. <a name="Assembler-options"></a>

  69. <h4 class="subsection">9.27.1 Assembler options</h4>

  70. 

  71. <p>The MIPS configurations of <small>GNU</small> <code>as</code> support these

  72. special options:

  73. </p>

  74. <dl compact="compact">

  75. <dd><a name="index-_002dG-option-_0028MIPS_0029"></a>

  76. </dd>

  77. <dt><code>-G <var>num</var></code></dt>

  78. <dd><p>Set the &ldquo;small data&rdquo; limit to <var>n</var> bytes.  The default limit is 8 bytes.

  79. See <a href="MIPS-Small-Data.html#MIPS-Small-Data">Controlling the use of small data accesses</a>.

  80. </p>

  81. <a name="index-_002dEB-option-_0028MIPS_0029"></a>

  82. <a name="index-_002dEL-option-_0028MIPS_0029"></a>

  83. <a name="index-MIPS-big_002dendian-output"></a>

  84. <a name="index-MIPS-little_002dendian-output"></a>

  85. <a name="index-big_002dendian-output_002c-MIPS"></a>

  86. <a name="index-little_002dendian-output_002c-MIPS"></a>

  87. </dd>

  88. <dt><code>-EB</code></dt>

  89. <dt><code>-EL</code></dt>

  90. <dd><p>Any MIPS configuration of <code>as</code> can select big-endian or

  91. little-endian output at run time (unlike the other <small>GNU</small> development

  92. tools, which must be configured for one or the other).  Use &lsquo;<samp>-EB</samp>&rsquo;

  93. to select big-endian output, and &lsquo;<samp>-EL</samp>&rsquo; for little-endian.

  94. </p>

  95. </dd>

  96. <dt><code>-KPIC</code></dt>

  97. <dd><a name="index-PIC-selection_002c-MIPS"></a>

  98. <a name="index-_002dKPIC-option_002c-MIPS"></a>

  99. <p>Generate SVR4-style PIC.  This option tells the assembler to generate

  100. SVR4-style position-independent macro expansions.  It also tells the

  101. assembler to mark the output file as PIC.

  102. </p>

  103. </dd>

  104. <dt><code>-mvxworks-pic</code></dt>

  105. <dd><a name="index-_002dmvxworks_002dpic-option_002c-MIPS"></a>

  106. <p>Generate VxWorks PIC.  This option tells the assembler to generate

  107. VxWorks-style position-independent macro expansions.

  108. </p>

  109. <a name="index-MIPS-architecture-options"></a>

  110. </dd>

  111. <dt><code>-mips1</code></dt>

  112. <dt><code>-mips2</code></dt>

  113. <dt><code>-mips3</code></dt>

  114. <dt><code>-mips4</code></dt>

  115. <dt><code>-mips5</code></dt>

  116. <dt><code>-mips32</code></dt>

  117. <dt><code>-mips32r2</code></dt>

  118. <dt><code>-mips32r3</code></dt>

  119. <dt><code>-mips32r5</code></dt>

  120. <dt><code>-mips32r6</code></dt>

  121. <dt><code>-mips64</code></dt>

  122. <dt><code>-mips64r2</code></dt>

  123. <dt><code>-mips64r3</code></dt>

  124. <dt><code>-mips64r5</code></dt>

  125. <dt><code>-mips64r6</code></dt>

  126. <dd><p>Generate code for a particular MIPS Instruction Set Architecture level.

  127. &lsquo;<samp>-mips1</samp>&rsquo; corresponds to the R2000 and R3000 processors,

  128. &lsquo;<samp>-mips2</samp>&rsquo; to the R6000 processor, &lsquo;<samp>-mips3</samp>&rsquo; to the

  129. R4000 processor, and &lsquo;<samp>-mips4</samp>&rsquo; to the R8000 and R10000 processors.

  130. &lsquo;<samp>-mips5</samp>&rsquo;, &lsquo;<samp>-mips32</samp>&rsquo;, &lsquo;<samp>-mips32r2</samp>&rsquo;, &lsquo;<samp>-mips32r3</samp>&rsquo;,

  131. &lsquo;<samp>-mips32r5</samp>&rsquo;, &lsquo;<samp>-mips32r6</samp>&rsquo;, &lsquo;<samp>-mips64</samp>&rsquo;, &lsquo;<samp>-mips64r2</samp>&rsquo;,

  132. &lsquo;<samp>-mips64r3</samp>&rsquo;, &lsquo;<samp>-mips64r5</samp>&rsquo;, and &lsquo;<samp>-mips64r6</samp>&rsquo; correspond to

  133. generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32

  134. Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64

  135. Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors,

  136. respectively.  You can also switch instruction sets during the assembly;

  137. see <a href="MIPS-ISA.html#MIPS-ISA">Directives to override the ISA level</a>.

  138. </p>

  139. </dd>

  140. <dt><code>-mgp32</code></dt>

  141. <dt><code>-mfp32</code></dt>

  142. <dd><p>Some macros have different expansions for 32-bit and 64-bit registers.

  143. The register sizes are normally inferred from the ISA and ABI, but these

  144. flags force a certain group of registers to be treated as 32 bits wide at

  145. all times.  &lsquo;<samp>-mgp32</samp>&rsquo; controls the size of general-purpose registers

  146. and &lsquo;<samp>-mfp32</samp>&rsquo; controls the size of floating-point registers.

  147. </p>

  148. <p>The <code>.set gp=32</code> and <code>.set fp=32</code> directives allow the size

  149. of registers to be changed for parts of an object. The default value is

  150. restored by <code>.set gp=default</code> and <code>.set fp=default</code>.

  151. </p>

  152. <p>On some MIPS variants there is a 32-bit mode flag; when this flag is

  153. set, 64-bit instructions generate a trap.  Also, some 32-bit OSes only

  154. save the 32-bit registers on a context switch, so it is essential never

  155. to use the 64-bit registers.

  156. </p>

  157. </dd>

  158. <dt><code>-mgp64</code></dt>

  159. <dt><code>-mfp64</code></dt>

  160. <dd><p>Assume that 64-bit registers are available.  This is provided in the

  161. interests of symmetry with &lsquo;<samp>-mgp32</samp>&rsquo; and &lsquo;<samp>-mfp32</samp>&rsquo;.

  162. </p>

  163. <p>The <code>.set gp=64</code> and <code>.set fp=64</code> directives allow the size

  164. of registers to be changed for parts of an object. The default value is

  165. restored by <code>.set gp=default</code> and <code>.set fp=default</code>.

  166. </p>

  167. </dd>

  168. <dt><code>-mfpxx</code></dt>

  169. <dd><p>Make no assumptions about whether 32-bit or 64-bit floating-point

  170. registers are available. This is provided to support having modules

  171. compatible with either &lsquo;<samp>-mfp32</samp>&rsquo; or &lsquo;<samp>-mfp64</samp>&rsquo;. This option can

  172. only be used with MIPS II and above.

  173. </p>

  174. <p>The <code>.set fp=xx</code> directive allows a part of an object to be marked

  175. as not making assumptions about 32-bit or 64-bit FP registers.  The

  176. default value is restored by <code>.set fp=default</code>.

  177. </p>

  178. </dd>

  179. <dt><code>-modd-spreg</code></dt>

  180. <dt><code>-mno-odd-spreg</code></dt>

  181. <dd><p>Enable use of floating-point operations on odd-numbered single-precision

  182. registers when supported by the ISA.  &lsquo;<samp>-mfpxx</samp>&rsquo; implies

  183. &lsquo;<samp>-mno-odd-spreg</samp>&rsquo;, otherwise the default is &lsquo;<samp>-modd-spreg</samp>&rsquo;

  184. </p>

  185. </dd>

  186. <dt><code>-mips16</code></dt>

  187. <dt><code>-no-mips16</code></dt>

  188. <dd><p>Generate code for the MIPS 16 processor.  This is equivalent to putting

  189. <code>.module mips16</code> at the start of the assembly file.  &lsquo;<samp>-no-mips16</samp>&rsquo;

  190. turns off this option.

  191. </p>

  192. </dd>

  193. <dt><code>-mmips16e2</code></dt>

  194. <dt><code>-mno-mips16e2</code></dt>

  195. <dd><p>Enable the use of MIPS16e2 instructions in MIPS16 mode.  This is equivalent

  196. to putting <code>.module mips16e2</code> at the start of the assembly file.

  197. &lsquo;<samp>-mno-mips16e2</samp>&rsquo; turns off this option.

  198. </p>

  199. </dd>

  200. <dt><code>-mmicromips</code></dt>

  201. <dt><code>-mno-micromips</code></dt>

  202. <dd><p>Generate code for the microMIPS processor.  This is equivalent to putting

  203. <code>.module micromips</code> at the start of the assembly file.

  204. &lsquo;<samp>-mno-micromips</samp>&rsquo; turns off this option.  This is equivalent to putting

  205. <code>.module nomicromips</code> at the start of the assembly file.

  206. </p>

  207. </dd>

  208. <dt><code>-msmartmips</code></dt>

  209. <dt><code>-mno-smartmips</code></dt>

  210. <dd><p>Enables the SmartMIPS extensions to the MIPS32 instruction set, which

  211. provides a number of new instructions which target smartcard and

  212. cryptographic applications.  This is equivalent to putting

  213. <code>.module smartmips</code> at the start of the assembly file.

  214. &lsquo;<samp>-mno-smartmips</samp>&rsquo; turns off this option.

  215. </p>

  216. </dd>

  217. <dt><code>-mips3d</code></dt>

  218. <dt><code>-no-mips3d</code></dt>

  219. <dd><p>Generate code for the MIPS-3D Application Specific Extension.

  220. This tells the assembler to accept MIPS-3D instructions.

  221. &lsquo;<samp>-no-mips3d</samp>&rsquo; turns off this option.

  222. </p>

  223. </dd>

  224. <dt><code>-mdmx</code></dt>

  225. <dt><code>-no-mdmx</code></dt>

  226. <dd><p>Generate code for the MDMX Application Specific Extension.

  227. This tells the assembler to accept MDMX instructions.

  228. &lsquo;<samp>-no-mdmx</samp>&rsquo; turns off this option.

  229. </p>

  230. </dd>

  231. <dt><code>-mdsp</code></dt>

  232. <dt><code>-mno-dsp</code></dt>

  233. <dd><p>Generate code for the DSP Release 1 Application Specific Extension.

  234. This tells the assembler to accept DSP Release 1 instructions.

  235. &lsquo;<samp>-mno-dsp</samp>&rsquo; turns off this option.

  236. </p>

  237. </dd>

  238. <dt><code>-mdspr2</code></dt>

  239. <dt><code>-mno-dspr2</code></dt>

  240. <dd><p>Generate code for the DSP Release 2 Application Specific Extension.

  241. This option implies &lsquo;<samp>-mdsp</samp>&rsquo;.

  242. This tells the assembler to accept DSP Release 2 instructions.

  243. &lsquo;<samp>-mno-dspr2</samp>&rsquo; turns off this option.

  244. </p>

  245. </dd>

  246. <dt><code>-mdspr3</code></dt>

  247. <dt><code>-mno-dspr3</code></dt>

  248. <dd><p>Generate code for the DSP Release 3 Application Specific Extension.

  249. This option implies &lsquo;<samp>-mdsp</samp>&rsquo; and &lsquo;<samp>-mdspr2</samp>&rsquo;.

  250. This tells the assembler to accept DSP Release 3 instructions.

  251. &lsquo;<samp>-mno-dspr3</samp>&rsquo; turns off this option.

  252. </p>

  253. </dd>

  254. <dt><code>-mmt</code></dt>

  255. <dt><code>-mno-mt</code></dt>

  256. <dd><p>Generate code for the MT Application Specific Extension.

  257. This tells the assembler to accept MT instructions.

  258. &lsquo;<samp>-mno-mt</samp>&rsquo; turns off this option.

  259. </p>

  260. </dd>

  261. <dt><code>-mmcu</code></dt>

  262. <dt><code>-mno-mcu</code></dt>

  263. <dd><p>Generate code for the MCU Application Specific Extension.

  264. This tells the assembler to accept MCU instructions.

  265. &lsquo;<samp>-mno-mcu</samp>&rsquo; turns off this option.

  266. </p>

  267. </dd>

  268. <dt><code>-mmsa</code></dt>

  269. <dt><code>-mno-msa</code></dt>

  270. <dd><p>Generate code for the MIPS SIMD Architecture Extension.

  271. This tells the assembler to accept MSA instructions.

  272. &lsquo;<samp>-mno-msa</samp>&rsquo; turns off this option.

  273. </p>

  274. </dd>

  275. <dt><code>-mxpa</code></dt>

  276. <dt><code>-mno-xpa</code></dt>

  277. <dd><p>Generate code for the MIPS eXtended Physical Address (XPA) Extension.

  278. This tells the assembler to accept XPA instructions.

  279. &lsquo;<samp>-mno-xpa</samp>&rsquo; turns off this option.

  280. </p>

  281. </dd>

  282. <dt><code>-mvirt</code></dt>

  283. <dt><code>-mno-virt</code></dt>

  284. <dd><p>Generate code for the Virtualization Application Specific Extension.

  285. This tells the assembler to accept Virtualization instructions.

  286. &lsquo;<samp>-mno-virt</samp>&rsquo; turns off this option.

  287. </p>

  288. </dd>

  289. <dt><code>-mcrc</code></dt>

  290. <dt><code>-mno-crc</code></dt>

  291. <dd><p>Generate code for the cyclic redundancy check (CRC) Application Specific

  292. Extension.  This tells the assembler to accept CRC instructions.

  293. &lsquo;<samp>-mno-crc</samp>&rsquo; turns off this option.

  294. </p>

  295. </dd>

  296. <dt><code>-mginv</code></dt>

  297. <dt><code>-mno-ginv</code></dt>

  298. <dd><p>Generate code for the Global INValidate (GINV) Application Specific

  299. Extension.  This tells the assembler to accept GINV instructions.

  300. &lsquo;<samp>-mno-ginv</samp>&rsquo; turns off this option.

  301. </p>

  302. </dd>

  303. <dt><code>-mloongson-mmi</code></dt>

  304. <dt><code>-mno-loongson-mmi</code></dt>

  305. <dd><p>Generate code for the Loongson MultiMedia extensions Instructions (MMI)

  306. Application Specific Extension.  This tells the assembler to accept MMI

  307. instructions.

  308. &lsquo;<samp>-mno-loongson-mmi</samp>&rsquo; turns off this option.

  309. </p>

  310. </dd>

  311. <dt><code>-mloongson-cam</code></dt>

  312. <dt><code>-mno-loongson-cam</code></dt>

  313. <dd><p>Generate code for the Loongson Content Address Memory (CAM)

  314. Application Specific Extension.  This tells the assembler to accept CAM

  315. instructions.

  316. &lsquo;<samp>-mno-loongson-cam</samp>&rsquo; turns off this option.

  317. </p>

  318. </dd>

  319. <dt><code>-mloongson-ext</code></dt>

  320. <dt><code>-mno-loongson-ext</code></dt>

  321. <dd><p>Generate code for the Loongson EXTensions (EXT) instructions

  322. Application Specific Extension.  This tells the assembler to accept EXT

  323. instructions.

  324. &lsquo;<samp>-mno-loongson-ext</samp>&rsquo; turns off this option.

  325. </p>

  326. </dd>

  327. <dt><code>-mloongson-ext2</code></dt>

  328. <dt><code>-mno-loongson-ext2</code></dt>

  329. <dd><p>Generate code for the Loongson EXTensions R2 (EXT2) instructions

  330. Application Specific Extension.  This tells the assembler to accept EXT2

  331. instructions.

  332. &lsquo;<samp>-mno-loongson-ext2</samp>&rsquo; turns off this option.

  333. </p>

  334. </dd>

  335. <dt><code>-minsn32</code></dt>

  336. <dt><code>-mno-insn32</code></dt>

  337. <dd><p>Only use 32-bit instruction encodings when generating code for the

  338. microMIPS processor.  This option inhibits the use of any 16-bit

  339. instructions.  This is equivalent to putting <code>.set insn32</code> at

  340. the start of the assembly file.  &lsquo;<samp>-mno-insn32</samp>&rsquo; turns off this

  341. option.  This is equivalent to putting <code>.set noinsn32</code> at the

  342. start of the assembly file.  By default &lsquo;<samp>-mno-insn32</samp>&rsquo; is

  343. selected, allowing all instructions to be used.

  344. </p>

  345. </dd>

  346. <dt><code>-mfix7000</code></dt>

  347. <dt><code>-mno-fix7000</code></dt>

  348. <dd><p>Cause nops to be inserted if the read of the destination register

  349. of an mfhi or mflo instruction occurs in the following two instructions.

  350. </p>

  351. </dd>

  352. <dt><code>-mfix-rm7000</code></dt>

  353. <dt><code>-mno-fix-rm7000</code></dt>

  354. <dd><p>Cause nops to be inserted if a dmult or dmultu instruction is

  355. followed by a load instruction.

  356. </p>

  357. </dd>

  358. <dt><code>-mfix-loongson2f-jump</code></dt>

  359. <dt><code>-mno-fix-loongson2f-jump</code></dt>

  360. <dd><p>Eliminate instruction fetch from outside 256M region to work around the

  361. Loongson2F &lsquo;<samp>jump</samp>&rsquo; instructions.  Without it, under extreme cases,

  362. the kernel may crash.  The issue has been solved in latest processor

  363. batches, but this fix has no side effect to them.

  364. </p>

  365. </dd>

  366. <dt><code>-mfix-loongson2f-nop</code></dt>

  367. <dt><code>-mno-fix-loongson2f-nop</code></dt>

  368. <dd><p>Replace nops by <code>or at,at,zero</code> to work around the Loongson2F

  369. &lsquo;<samp>nop</samp>&rsquo; errata.  Without it, under extreme cases, the CPU might

  370. deadlock.  The issue has been solved in later Loongson2F batches, but

  371. this fix has no side effect to them.

  372. </p>

  373. </dd>

  374. <dt><code>-mfix-loongson3-llsc</code></dt>

  375. <dt><code>-mno-fix-loongson3-llsc</code></dt>

  376. <dd><p>Insert &lsquo;<samp>sync</samp>&rsquo; before &lsquo;<samp>ll</samp>&rsquo; and &lsquo;<samp>lld</samp>&rsquo; to work around

  377. Loongson3 LLSC errata.  Without it, under extrame cases, the CPU might

  378. deadlock. The default can be controlled by the

  379. <samp>--enable-mips-fix-loongson3-llsc=[yes|no]</samp> configure option.

  380. </p>

  381. </dd>

  382. <dt><code>-mfix-vr4120</code></dt>

  383. <dt><code>-mno-fix-vr4120</code></dt>

  384. <dd><p>Insert nops to work around certain VR4120 errata.  This option is

  385. intended to be used on GCC-generated code: it is not designed to catch

  386. all problems in hand-written assembler code.

  387. </p>

  388. </dd>

  389. <dt><code>-mfix-vr4130</code></dt>

  390. <dt><code>-mno-fix-vr4130</code></dt>

  391. <dd><p>Insert nops to work around the VR4130 &lsquo;<samp>mflo</samp>&rsquo;/&lsquo;<samp>mfhi</samp>&rsquo; errata.

  392. </p>

  393. </dd>

  394. <dt><code>-mfix-24k</code></dt>

  395. <dt><code>-mno-fix-24k</code></dt>

  396. <dd><p>Insert nops to work around the 24K &lsquo;<samp>eret</samp>&rsquo;/&lsquo;<samp>deret</samp>&rsquo; errata.

  397. </p>

  398. </dd>

  399. <dt><code>-mfix-cn63xxp1</code></dt>

  400. <dt><code>-mno-fix-cn63xxp1</code></dt>

  401. <dd><p>Replace <code>pref</code> hints 0 - 4 and 6 - 24 with hint 28 to work around

  402. certain CN63XXP1 errata.

  403. </p>

  404. </dd>

  405. <dt><code>-mfix-r5900</code></dt>

  406. <dt><code>-mno-fix-r5900</code></dt>

  407. <dd><p>Do not attempt to schedule the preceding instruction into the delay slot

  408. of a branch instruction placed at the end of a short loop of six

  409. instructions or fewer and always schedule a <code>nop</code> instruction there

  410. instead.  The short loop bug under certain conditions causes loops to

  411. execute only once or twice, due to a hardware bug in the R5900 chip.

  412. </p>

  413. </dd>

  414. <dt><code>-m4010</code></dt>

  415. <dt><code>-no-m4010</code></dt>

  416. <dd><p>Generate code for the LSI R4010 chip.  This tells the assembler to

  417. accept the R4010-specific instructions (&lsquo;<samp>addciu</samp>&rsquo;, &lsquo;<samp>ffc</samp>&rsquo;,

  418. etc.), and to not schedule &lsquo;<samp>nop</samp>&rsquo; instructions around accesses to

  419. the &lsquo;<samp>HI</samp>&rsquo; and &lsquo;<samp>LO</samp>&rsquo; registers.  &lsquo;<samp>-no-m4010</samp>&rsquo; turns off this

  420. option.

  421. </p>

  422. </dd>

  423. <dt><code>-m4650</code></dt>

  424. <dt><code>-no-m4650</code></dt>

  425. <dd><p>Generate code for the MIPS R4650 chip.  This tells the assembler to accept

  426. the &lsquo;<samp>mad</samp>&rsquo; and &lsquo;<samp>madu</samp>&rsquo; instruction, and to not schedule &lsquo;<samp>nop</samp>&rsquo;

  427. instructions around accesses to the &lsquo;<samp>HI</samp>&rsquo; and &lsquo;<samp>LO</samp>&rsquo; registers.

  428. &lsquo;<samp>-no-m4650</samp>&rsquo; turns off this option.

  429. </p>

  430. </dd>

  431. <dt><code>-m3900</code></dt>

  432. <dt><code>-no-m3900</code></dt>

  433. <dt><code>-m4100</code></dt>

  434. <dt><code>-no-m4100</code></dt>

  435. <dd><p>For each option &lsquo;<samp>-m<var>nnnn</var></samp>&rsquo;, generate code for the MIPS

  436. R<var>nnnn</var> chip.  This tells the assembler to accept instructions

  437. specific to that chip, and to schedule for that chip&rsquo;s hazards.

  438. </p>

  439. </dd>

  440. <dt><code>-march=<var>cpu</var></code></dt>

  441. <dd><p>Generate code for a particular MIPS CPU.  It is exactly equivalent to

  442. &lsquo;<samp>-m<var>cpu</var></samp>&rsquo;, except that there are more value of <var>cpu</var>

  443. understood.  Valid <var>cpu</var> value are:

  444. </p>

  445. <blockquote>

  446. <p>2000,

  447. 3000,

  448. 3900,

  449. 4000,

  450. 4010,

  451. 4100,

  452. 4111,

  453. vr4120,

  454. vr4130,

  455. vr4181,

  456. 4300,

  457. 4400,

  458. 4600,

  459. 4650,

  460. 5000,

  461. rm5200,

  462. rm5230,

  463. rm5231,

  464. rm5261,

  465. rm5721,

  466. vr5400,

  467. vr5500,

  468. 6000,

  469. rm7000,

  470. 8000,

  471. rm9000,

  472. 10000,

  473. 12000,

  474. 14000,

  475. 16000,

  476. 4kc,

  477. 4km,

  478. 4kp,

  479. 4ksc,

  480. 4kec,

  481. 4kem,

  482. 4kep,

  483. 4ksd,

  484. m4k,

  485. m4kp,

  486. m14k,

  487. m14kc,

  488. m14ke,

  489. m14kec,

  490. 24kc,

  491. 24kf2_1,

  492. 24kf,

  493. 24kf1_1,

  494. 24kec,

  495. 24kef2_1,

  496. 24kef,

  497. 24kef1_1,

  498. 34kc,

  499. 34kf2_1,

  500. 34kf,

  501. 34kf1_1,

  502. 34kn,

  503. 74kc,

  504. 74kf2_1,

  505. 74kf,

  506. 74kf1_1,

  507. 74kf3_2,

  508. 1004kc,

  509. 1004kf2_1,

  510. 1004kf,

  511. 1004kf1_1,

  512. interaptiv,

  513. interaptiv-mr2,

  514. m5100,

  515. m5101,

  516. p5600,

  517. 5kc,

  518. 5kf,

  519. 20kc,

  520. 25kf,

  521. sb1,

  522. sb1a,

  523. i6400,

  524. i6500,

  525. p6600,

  526. loongson2e,

  527. loongson2f,

  528. gs464,

  529. gs464e,

  530. gs264e,

  531. octeon,

  532. octeon+,

  533. octeon2,

  534. octeon3,

  535. xlr,

  536. xlp

  537. </p></blockquote>

  538. 

  539. <p>For compatibility reasons, &lsquo;<samp><var>n</var>x</samp>&rsquo; and &lsquo;<samp><var>b</var>fx</samp>&rsquo; are

  540. accepted as synonyms for &lsquo;<samp><var>n</var>f1_1</samp>&rsquo;.  These values are

  541. deprecated.

  542. </p>

  543. </dd>

  544. <dt><code>-mtune=<var>cpu</var></code></dt>

  545. <dd><p>Schedule and tune for a particular MIPS CPU.  Valid <var>cpu</var> values are

  546. identical to &lsquo;<samp>-march=<var>cpu</var></samp>&rsquo;.

  547. </p>

  548. </dd>

  549. <dt><code>-mabi=<var>abi</var></code></dt>

  550. <dd><p>Record which ABI the source code uses.  The recognized arguments

  551. are: &lsquo;<samp>32</samp>&rsquo;, &lsquo;<samp>n32</samp>&rsquo;, &lsquo;<samp>o64</samp>&rsquo;, &lsquo;<samp>64</samp>&rsquo; and &lsquo;<samp>eabi</samp>&rsquo;.

  552. </p>

  553. </dd>

  554. <dt><code>-msym32</code></dt>

  555. <dt><code>-mno-sym32</code></dt>

  556. <dd><a name="index-_002dmsym32"></a>

  557. <a name="index-_002dmno_002dsym32"></a>

  558. <p>Equivalent to adding <code>.set sym32</code> or <code>.set nosym32</code> to

  559. the beginning of the assembler input.  See <a href="MIPS-Symbol-Sizes.html#MIPS-Symbol-Sizes">MIPS Symbol Sizes</a>.

  560. </p>

  561. <a name="index-_002dnocpp-ignored-_0028MIPS_0029"></a>

  562. </dd>

  563. <dt><code>-nocpp</code></dt>

  564. <dd><p>This option is ignored.  It is accepted for command-line compatibility with

  565. other assemblers, which use it to turn off C style preprocessing.  With

  566. <small>GNU</small> <code>as</code>, there is no need for &lsquo;<samp>-nocpp</samp>&rsquo;, because the

  567. <small>GNU</small> assembler itself never runs the C preprocessor.

  568. </p>

  569. </dd>

  570. <dt><code>-msoft-float</code></dt>

  571. <dt><code>-mhard-float</code></dt>

  572. <dd><p>Disable or enable floating-point instructions.  Note that by default

  573. floating-point instructions are always allowed even with CPU targets

  574. that don&rsquo;t have support for these instructions.

  575. </p>

  576. </dd>

  577. <dt><code>-msingle-float</code></dt>

  578. <dt><code>-mdouble-float</code></dt>

  579. <dd><p>Disable or enable double-precision floating-point operations.  Note

  580. that by default double-precision floating-point operations are always

  581. allowed even with CPU targets that don&rsquo;t have support for these

  582. operations.

  583. </p>

  584. </dd>

  585. <dt><code>--construct-floats</code></dt>

  586. <dt><code>--no-construct-floats</code></dt>

  587. <dd><p>The <code>--no-construct-floats</code> option disables the construction of

  588. double width floating point constants by loading the two halves of the

  589. value into the two single width floating point registers that make up

  590. the double width register.  This feature is useful if the processor

  591. support the FR bit in its status  register, and this bit is known (by

  592. the programmer) to be set.  This bit prevents the aliasing of the double

  593. width register by the single width registers.

  594. </p>

  595. <p>By default <code>--construct-floats</code> is selected, allowing construction

  596. of these floating point constants.

  597. </p>

  598. </dd>

  599. <dt><code>--relax-branch</code></dt>

  600. <dt><code>--no-relax-branch</code></dt>

  601. <dd><p>The &lsquo;<samp>--relax-branch</samp>&rsquo; option enables the relaxation of out-of-range

  602. branches.  Any branches whose target cannot be reached directly are

  603. converted to a small instruction sequence including an inverse-condition

  604. branch to the physically next instruction, and a jump to the original

  605. target is inserted between the two instructions.  In PIC code the jump

  606. will involve further instructions for address calculation.

  607. </p>

  608. <p>The <code>BC1ANY2F</code>, <code>BC1ANY2T</code>, <code>BC1ANY4F</code>, <code>BC1ANY4T</code>,

  609. <code>BPOSGE32</code> and <code>BPOSGE64</code> instructions are excluded from

  610. relaxation, because they have no complementing counterparts.  They could

  611. be relaxed with the use of a longer sequence involving another branch,

  612. however this has not been implemented and if their target turns out of

  613. reach, they produce an error even if branch relaxation is enabled.

  614. </p>

  615. <p>Also no MIPS16 branches are ever relaxed.

  616. </p>

  617. <p>By default &lsquo;<samp>--no-relax-branch</samp>&rsquo; is selected, causing any out-of-range

  618. branches to produce an error.

  619. </p>

  620. </dd>

  621. <dt><code>-mignore-branch-isa</code></dt>

  622. <dt><code>-mno-ignore-branch-isa</code></dt>

  623. <dd><p>Ignore branch checks for invalid transitions between ISA modes.

  624. </p>

  625. <p>The semantics of branches does not provide for an ISA mode switch, so in

  626. most cases the ISA mode a branch has been encoded for has to be the same

  627. as the ISA mode of the branch&rsquo;s target label.  If the ISA modes do not

  628. match, then such a branch, if taken, will cause the ISA mode to remain

  629. unchanged and instructions that follow will be executed in the wrong ISA

  630. mode causing the program to misbehave or crash.

  631. </p>

  632. <p>In the case of the <code>BAL</code> instruction it may be possible to relax

  633. it to an equivalent <code>JALX</code> instruction so that the ISA mode is

  634. switched at the run time as required.  For other branches no relaxation

  635. is possible and therefore GAS has checks implemented that verify in

  636. branch assembly that the two ISA modes match, and report an error

  637. otherwise so that the problem with code can be diagnosed at the assembly

  638. time rather than at the run time.

  639. </p>

  640. <p>However some assembly code, including generated code produced by some

  641. versions of GCC, may incorrectly include branches to data labels, which

  642. appear to require a mode switch but are either dead or immediately

  643. followed by valid instructions encoded for the same ISA the branch has

  644. been encoded for.  While not strictly correct at the source level such

  645. code will execute as intended, so to help with these cases

  646. &lsquo;<samp>-mignore-branch-isa</samp>&rsquo; is supported which disables ISA mode checks

  647. for branches.

  648. </p>

  649. <p>By default &lsquo;<samp>-mno-ignore-branch-isa</samp>&rsquo; is selected, causing any invalid

  650. branch requiring a transition between ISA modes to produce an error.

  651. </p>

  652. <a name="index-_002dmnan_003d-command_002dline-option_002c-MIPS"></a>

  653. </dd>

  654. <dt><code>-mnan=<var>encoding</var></code></dt>

  655. <dd><p>This option indicates whether the source code uses the IEEE 2008

  656. NaN encoding (<samp>-mnan=2008</samp>) or the original MIPS encoding

  657. (<samp>-mnan=legacy</samp>).  It is equivalent to adding a <code>.nan</code>

  658. directive to the beginning of the source file.  See <a href="MIPS-NaN-Encodings.html#MIPS-NaN-Encodings">MIPS NaN Encodings</a>.

  659. </p>

  660. <p><samp>-mnan=legacy</samp> is the default if no <samp>-mnan</samp> option or

  661. <code>.nan</code> directive is used.

  662. </p>

  663. </dd>

  664. <dt><code>--trap</code></dt>

  665. <dt><code>--no-break</code></dt>

  666. <dd><p><code>as</code> automatically macro expands certain division and

  667. multiplication instructions to check for overflow and division by zero.  This

  668. option causes <code>as</code> to generate code to take a trap exception

  669. rather than a break exception when an error is detected.  The trap instructions

  670. are only supported at Instruction Set Architecture level 2 and higher.

  671. </p>

  672. </dd>

  673. <dt><code>--break</code></dt>

  674. <dt><code>--no-trap</code></dt>

  675. <dd><p>Generate code to take a break exception rather than a trap exception when an

  676. error is detected.  This is the default.

  677. </p>

  678. </dd>

  679. <dt><code>-mpdr</code></dt>

  680. <dt><code>-mno-pdr</code></dt>

  681. <dd><p>Control generation of <code>.pdr</code> sections.  Off by default on IRIX, on

  682. elsewhere.

  683. </p>

  684. </dd>

  685. <dt><code>-mshared</code></dt>

  686. <dt><code>-mno-shared</code></dt>

  687. <dd><p>When generating code using the Unix calling conventions (selected by

  688. &lsquo;<samp>-KPIC</samp>&rsquo; or &lsquo;<samp>-mcall_shared</samp>&rsquo;), gas will normally generate code

  689. which can go into a shared library.  The &lsquo;<samp>-mno-shared</samp>&rsquo; option

  690. tells gas to generate code which uses the calling convention, but can

  691. not go into a shared library.  The resulting code is slightly more

  692. efficient.  This option only affects the handling of the

  693. &lsquo;<samp>.cpload</samp>&rsquo; and &lsquo;<samp>.cpsetup</samp>&rsquo; pseudo-ops.

  694. </p></dd>

  695. </dl>

  696. 

  697. <hr>

  698. <div class="header">

  699. <p>

  700. Next: <a href="MIPS-Macros.html#MIPS-Macros" accesskey="n" rel="next">MIPS Macros</a>, Up: <a href="MIPS_002dDependent.html#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  701. </div>

  702. 

  703. 

  704. 

  705. </body>

  706. </html>