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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

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  17. <title>NDS32-Ops (Using as)</title>

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  62. <a name="NDS32_002dOps"></a>

  63. <div class="header">

  64. <p>

  65. Previous: <a href="NDS32_002dRegs.html#NDS32_002dRegs" accesskey="p" rel="prev">NDS32-Regs</a>, Up: <a href="NDS32-Syntax.html#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  66. </div>

  67. <hr>

  68. <a name="Pseudo-Instructions-1"></a>

  69. <h4 class="subsubsection">9.30.2.3 Pseudo Instructions</h4>

  70. <dl compact="compact">

  71. <dt><code>li rt5,imm32</code></dt>

  72. <dd><p>load 32-bit integer into register rt5.  &lsquo;<samp>sethi rt5,hi20(imm32)</samp>&rsquo; and then

  73. &lsquo;<samp>ori rt5,reg,lo12(imm32)</samp>&rsquo;.

  74. </p>

  75. </dd>

  76. <dt><code>la rt5,var</code></dt>

  77. <dd><p>Load 32-bit address of var into register rt5.  &lsquo;<samp>sethi rt5,hi20(var)</samp>&rsquo; and

  78. then &lsquo;<samp>ori reg,rt5,lo12(var)</samp>&rsquo;

  79. </p>

  80. </dd>

  81. <dt><code>l.[bhw] rt5,var</code></dt>

  82. <dd><p>Load value of var into register rt5.  &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then

  83. &lsquo;<samp>l[bhw]i rt5,[$ta+lo12(var)]</samp>&rsquo;

  84. </p>

  85. </dd>

  86. <dt><code>l.[bh]s rt5,var</code></dt>

  87. <dd><p>Load value of var into register rt5.  &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then

  88. &lsquo;<samp>l[bh]si rt5,[$ta+lo12(var)]</samp>&rsquo;

  89. </p>

  90. </dd>

  91. <dt><code>l.[bhw]p rt5,var,inc</code></dt>

  92. <dd><p>Load value of var into register rt5 and increment $ta by amount inc.

  93. &lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>l[bhw]i.bi rt5,[$ta],inc</samp>&rsquo;

  94. </p>

  95. </dd>

  96. <dt><code>l.[bhw]pc rt5,inc</code></dt>

  97. <dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc.

  98. &lsquo;<samp>l[bhw]i.bi rt5,[$ta],inc.</samp>&rsquo;

  99. </p>

  100. </dd>

  101. <dt><code>l.[bh]sp rt5,var,inc</code></dt>

  102. <dd><p>Load value of var into register rt5 and increment $ta by amount inc.

  103. &lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>l[bh]si.bi rt5,[$ta],inc</samp>&rsquo;

  104. </p>

  105. </dd>

  106. <dt><code>l.[bh]spc rt5,inc</code></dt>

  107. <dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc.

  108. &lsquo;<samp>l[bh]si.bi rt5,[$ta],inc.</samp>&rsquo;

  109. </p>

  110. </dd>

  111. <dt><code>s.[bhw] rt5,var</code></dt>

  112. <dd><p>Store register rt5 to var.

  113. &lsquo;<samp>sethi $ta,hi20(var)</samp>&rsquo; and then &lsquo;<samp>s[bhw]i rt5,[$ta+lo12(var)]</samp>&rsquo;

  114. </p>

  115. </dd>

  116. <dt><code>s.[bhw]p rt5,var,inc</code></dt>

  117. <dd><p>Store register rt5 to var and increment $ta by amount inc.

  118. &lsquo;<samp>la $ta,var</samp>&rsquo; and then &lsquo;<samp>s[bhw]i.bi rt5,[$ta],inc</samp>&rsquo;

  119. </p>

  120. </dd>

  121. <dt><code>s.[bhw]pc rt5,inc</code></dt>

  122. <dd><p>Continue storing register rt5 to var and increment $ta by amount inc.

  123. &lsquo;<samp>s[bhw]i.bi rt5,[$ta],inc.</samp>&rsquo;

  124. </p>

  125. </dd>

  126. <dt><code>not rt5,ra5</code></dt>

  127. <dd><p>Alias of &lsquo;<samp>nor rt5,ra5,ra5</samp>&rsquo;.

  128. </p>

  129. </dd>

  130. <dt><code>neg rt5,ra5</code></dt>

  131. <dd><p>Alias of &lsquo;<samp>subri rt5,ra5,0</samp>&rsquo;.

  132. </p>

  133. </dd>

  134. <dt><code>br rb5</code></dt>

  135. <dd><p>Depending on how it is assembled, it is translated into &lsquo;<samp>r5 rb5</samp>&rsquo;

  136. or &lsquo;<samp>jr rb5</samp>&rsquo;.

  137. </p>

  138. </dd>

  139. <dt><code>b label</code></dt>

  140. <dd><p>Branch to label depending on how it is assembled, it is translated into

  141. &lsquo;<samp>j8 label</samp>&rsquo;, &lsquo;<samp>j label</samp>&rsquo;, or &quot;&lsquo;<samp>la $ta,label</samp>&rsquo; &lsquo;<samp>br $ta</samp>&rsquo;&quot;.

  142. </p>

  143. </dd>

  144. <dt><code>bral rb5</code></dt>

  145. <dd><p>Alias of jral br5 depending on how it is assembled, it is translated

  146. into &lsquo;<samp>jral5 rb5</samp>&rsquo; or &lsquo;<samp>jral rb5</samp>&rsquo;.

  147. </p>

  148. </dd>

  149. <dt><code>bal fname</code></dt>

  150. <dd><p>Alias of jal fname depending on how it is assembled, it is translated into

  151. &lsquo;<samp>jal fname</samp>&rsquo; or &quot;&lsquo;<samp>la $ta,fname</samp>&rsquo; &lsquo;<samp>bral $ta</samp>&rsquo;&quot;.

  152. </p>

  153. </dd>

  154. <dt><code>call fname</code></dt>

  155. <dd><p>Call function fname same as &lsquo;<samp>jal fname</samp>&rsquo;.

  156. </p>

  157. </dd>

  158. <dt><code>move rt5,ra5</code></dt>

  159. <dd><p>For 16-bit, this is &lsquo;<samp>mov55 rt5,ra5</samp>&rsquo;.

  160. For no 16-bit, this is &lsquo;<samp>ori rt5,ra5,0</samp>&rsquo;.

  161. </p>

  162. </dd>

  163. <dt><code>move rt5,var</code></dt>

  164. <dd><p>This is the same as &lsquo;<samp>l.w rt5,var</samp>&rsquo;.

  165. </p>

  166. </dd>

  167. <dt><code>move rt5,imm32</code></dt>

  168. <dd><p>This is the same as &lsquo;<samp>li rt5,imm32</samp>&rsquo;.

  169. </p>

  170. </dd>

  171. <dt><code>pushm ra5,rb5</code></dt>

  172. <dd><p>Push contents of registers from ra5 to rb5 into stack.

  173. </p>

  174. </dd>

  175. <dt><code>push ra5</code></dt>

  176. <dd><p>Push content of register ra5 into stack. (same &lsquo;<samp>pushm ra5,ra5</samp>&rsquo;).

  177. </p>

  178. </dd>

  179. <dt><code>push.d var</code></dt>

  180. <dd><p>Push value of double-word variable var into stack.

  181. </p>

  182. </dd>

  183. <dt><code>push.w var</code></dt>

  184. <dd><p>Push value of word variable var into stack.

  185. </p>

  186. </dd>

  187. <dt><code>push.h var</code></dt>

  188. <dd><p>Push value of half-word variable var into stack.

  189. </p>

  190. </dd>

  191. <dt><code>push.b var</code></dt>

  192. <dd><p>Push value of byte variable var into stack.

  193. </p>

  194. </dd>

  195. <dt><code>pusha var</code></dt>

  196. <dd><p>Push 32-bit address of variable var into stack.

  197. </p>

  198. </dd>

  199. <dt><code>pushi imm32</code></dt>

  200. <dd><p>Push 32-bit immediate value into stack.

  201. </p>

  202. </dd>

  203. <dt><code>popm ra5,rb5</code></dt>

  204. <dd><p>Pop top of stack values into registers ra5 to rb5.

  205. </p>

  206. </dd>

  207. <dt><code>pop rt5</code></dt>

  208. <dd><p>Pop top of stack value into register. (same as &lsquo;<samp>popm rt5,rt5</samp>&rsquo;.)

  209. </p>

  210. </dd>

  211. <dt><code>pop.d var,ra5</code></dt>

  212. <dd><p>Pop value of double-word variable var from stack using register ra5

  213. as 2nd scratch register. (1st is $ta)

  214. </p>

  215. </dd>

  216. <dt><code>pop.w var,ra5</code></dt>

  217. <dd><p>Pop value of word variable var from stack using register ra5.

  218. </p>

  219. </dd>

  220. <dt><code>pop.h var,ra5</code></dt>

  221. <dd><p>Pop value of half-word variable var from stack using register ra5.

  222. </p>

  223. </dd>

  224. <dt><code>pop.b var,ra5</code></dt>

  225. <dd><p>Pop value of byte variable var from stack using register ra5.

  226. </p>

  227. </dd>

  228. </dl>

  229. 

  230. <hr>

  231. <div class="header">

  232. <p>

  233. Previous: <a href="NDS32_002dRegs.html#NDS32_002dRegs" accesskey="p" rel="prev">NDS32-Regs</a>, Up: <a href="NDS32-Syntax.html#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  234. </div>

  235. 

  236. 

  237. 

  238. </body>

  239. </html>