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  62. <a name="RISC_002dV_002dFormats"></a>

  63. <div class="header">

  64. <p>

  65. Next: <a href="RISC_002dV_002dATTRIBUTE.html#RISC_002dV_002dATTRIBUTE" accesskey="n" rel="next">RISC-V-ATTRIBUTE</a>, Previous: <a href="RISC_002dV_002dModifiers.html#RISC_002dV_002dModifiers" accesskey="p" rel="prev">RISC-V-Modifiers</a>, Up: <a href="RISC_002dV_002dDependent.html#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  66. </div>

  67. <hr>

  68. <a name="RISC_002dV-Instruction-Formats"></a>

  69. <h4 class="subsection">9.38.4 RISC-V Instruction Formats</h4>

  70. <a name="index-instruction-formats_002c-risc_002dv"></a>

  71. <a name="index-RISC_002dV-instruction-formats"></a>

  72. 

  73. <p>The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12

  74. instruction formats where some of the formats have multiple variants.

  75. For the &lsquo;<samp>.insn</samp>&rsquo; pseudo directive the assembler recognizes some

  76. of the formats.

  77. Typically, the most general variant of the instruction format is used

  78. by the &lsquo;<samp>.insn</samp>&rsquo; directive.

  79. </p>

  80. <p>The following table lists the abbreviations used in the table of

  81. instruction formats:

  82. </p>

  83. <div class="display">

  84. <table>

  85. <tr><td width="15%"><pre class="display">opcode</pre></td><td width="40%"><pre class="display">Unsigned immediate or opcode name for 7-bits opcode.</pre></td></tr>

  86. <tr><td width="15%"><pre class="display">opcode2</pre></td><td width="40%"><pre class="display">Unsigned immediate or opcode name for 2-bits opcode.</pre></td></tr>

  87. <tr><td width="15%"><pre class="display">func7</pre></td><td width="40%"><pre class="display">Unsigned immediate for 7-bits function code.</pre></td></tr>

  88. <tr><td width="15%"><pre class="display">func6</pre></td><td width="40%"><pre class="display">Unsigned immediate for 6-bits function code.</pre></td></tr>

  89. <tr><td width="15%"><pre class="display">func4</pre></td><td width="40%"><pre class="display">Unsigned immediate for 4-bits function code.</pre></td></tr>

  90. <tr><td width="15%"><pre class="display">func3</pre></td><td width="40%"><pre class="display">Unsigned immediate for 3-bits function code.</pre></td></tr>

  91. <tr><td width="15%"><pre class="display">func2</pre></td><td width="40%"><pre class="display">Unsigned immediate for 2-bits function code.</pre></td></tr>

  92. <tr><td width="15%"><pre class="display">rd</pre></td><td width="40%"><pre class="display">Destination register number for operand x, can be GPR or FPR.</pre></td></tr>

  93. <tr><td width="15%"><pre class="display">rd&rsquo;</pre></td><td width="40%"><pre class="display">Destination register number for operand x,

  94. only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr>

  95. <tr><td width="15%"><pre class="display">rs1</pre></td><td width="40%"><pre class="display">First source register number for operand x, can be GPR or FPR.</pre></td></tr>

  96. <tr><td width="15%"><pre class="display">rs1&rsquo;</pre></td><td width="40%"><pre class="display">First source register number for operand x,

  97. only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr>

  98. <tr><td width="15%"><pre class="display">rs2</pre></td><td width="40%"><pre class="display">Second source register number for operand x, can be GPR or FPR.</pre></td></tr>

  99. <tr><td width="15%"><pre class="display">rs2&rsquo;</pre></td><td width="40%"><pre class="display">Second source register number for operand x,

  100. only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.</pre></td></tr>

  101. <tr><td width="15%"><pre class="display">simm12</pre></td><td width="40%"><pre class="display">Sign-extended 12-bit immediate for operand x.</pre></td></tr>

  102. <tr><td width="15%"><pre class="display">simm20</pre></td><td width="40%"><pre class="display">Sign-extended 20-bit immediate for operand x.</pre></td></tr>

  103. <tr><td width="15%"><pre class="display">simm6</pre></td><td width="40%"><pre class="display">Sign-extended 6-bit immediate for operand x.</pre></td></tr>

  104. <tr><td width="15%"><pre class="display">uimm8</pre></td><td width="40%"><pre class="display">Unsigned 8-bit immediate for operand x.</pre></td></tr>

  105. <tr><td width="15%"><pre class="display">symbol</pre></td><td width="40%"><pre class="display">Symbol or lable reference for operand x.</pre></td></tr>

  106. </table>

  107. </div>

  108. 

  109. <p>The following table lists all available opcode name:

  110. </p>

  111. <dl compact="compact">

  112. <dt><code>C0</code></dt>

  113. <dt><code>C1</code></dt>

  114. <dt><code>C2</code></dt>

  115. <dd><p>Opcode space for compressed instructions.

  116. </p>

  117. </dd>

  118. <dt><code>LOAD</code></dt>

  119. <dd><p>Opcode space for load instructions.

  120. </p>

  121. </dd>

  122. <dt><code>LOAD_FP</code></dt>

  123. <dd><p>Opcode space for floating-point load instructions.

  124. </p>

  125. </dd>

  126. <dt><code>STORE</code></dt>

  127. <dd><p>Opcode space for store instructions.

  128. </p>

  129. </dd>

  130. <dt><code>STORE_FP</code></dt>

  131. <dd><p>Opcode space for floating-point store instructions.

  132. </p>

  133. </dd>

  134. <dt><code>AUIPC</code></dt>

  135. <dd><p>Opcode space for auipc instruction.

  136. </p>

  137. </dd>

  138. <dt><code>LUI</code></dt>

  139. <dd><p>Opcode space for lui instruction.

  140. </p>

  141. </dd>

  142. <dt><code>BRANCH</code></dt>

  143. <dd><p>Opcode space for branch instructions.

  144. </p>

  145. </dd>

  146. <dt><code>JAL</code></dt>

  147. <dd><p>Opcode space for jal instruction.

  148. </p>

  149. </dd>

  150. <dt><code>JALR</code></dt>

  151. <dd><p>Opcode space for jalr instruction.

  152. </p>

  153. </dd>

  154. <dt><code>OP</code></dt>

  155. <dd><p>Opcode space for ALU instructions.

  156. </p>

  157. </dd>

  158. <dt><code>OP_32</code></dt>

  159. <dd><p>Opcode space for 32-bits ALU instructions.

  160. </p>

  161. </dd>

  162. <dt><code>OP_IMM</code></dt>

  163. <dd><p>Opcode space for ALU with immediate instructions.

  164. </p>

  165. </dd>

  166. <dt><code>OP_IMM_32</code></dt>

  167. <dd><p>Opcode space for 32-bits ALU with immediate instructions.

  168. </p>

  169. </dd>

  170. <dt><code>OP_FP</code></dt>

  171. <dd><p>Opcode space for floating-point operation instructions.

  172. </p>

  173. </dd>

  174. <dt><code>MADD</code></dt>

  175. <dd><p>Opcode space for madd instruction.

  176. </p>

  177. </dd>

  178. <dt><code>MSUB</code></dt>

  179. <dd><p>Opcode space for msub instruction.

  180. </p>

  181. </dd>

  182. <dt><code>NMADD</code></dt>

  183. <dd><p>Opcode space for nmadd instruction.

  184. </p>

  185. </dd>

  186. <dt><code>NMSUB</code></dt>

  187. <dd><p>Opcode space for msub instruction.

  188. </p>

  189. </dd>

  190. <dt><code>AMO</code></dt>

  191. <dd><p>Opcode space for atomic memory operation instructions.

  192. </p>

  193. </dd>

  194. <dt><code>MISC_MEM</code></dt>

  195. <dd><p>Opcode space for misc instructions.

  196. </p>

  197. </dd>

  198. <dt><code>SYSTEM</code></dt>

  199. <dd><p>Opcode space for system instructions.

  200. </p>

  201. </dd>

  202. <dt><code>CUSTOM_0</code></dt>

  203. <dt><code>CUSTOM_1</code></dt>

  204. <dt><code>CUSTOM_2</code></dt>

  205. <dt><code>CUSTOM_3</code></dt>

  206. <dd><p>Opcode space for customize instructions.

  207. </p>

  208. </dd>

  209. </dl>

  210. 

  211. <p>An instruction is two or four bytes in length and must be aligned

  212. on a 2 byte boundary. The first two bits of the instruction specify the

  213. length of the instruction, 00, 01 and 10 indicates a two byte instruction,

  214. 11 indicates a four byte instruction.

  215. </p>

  216. <p>The following table lists the RISC-V instruction formats that are available

  217. with the &lsquo;<samp>.insn</samp>&rsquo; pseudo directive:

  218. </p>

  219. <dl compact="compact">

  220. <dt><code>R type: .insn r opcode, func3, func7, rd, rs1, rs2</code></dt>

  221. <dd><pre class="verbatim">+-------+-----+-----+-------+----+-------------+

  222. | func7 | rs2 | rs1 | func3 | rd |      opcode |

  223. +-------+-----+-----+-------+----+-------------+

  224. 31      25    20    15      12   7             0

  225. </pre>

  226. </dd>

  227. <dt><code>R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3</code></dt>

  228. <dt><code>R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3</code></dt>

  229. <dd><pre class="verbatim">+-----+-------+-----+-----+-------+----+-------------+

  230. | rs3 | func2 | rs2 | rs1 | func3 | rd |      opcode |

  231. +-----+-------+-----+-----+-------+----+-------------+

  232. 31    27      25    20    15      12   7             0

  233. </pre>

  234. </dd>

  235. <dt><code>I type: .insn i opcode, func3, rd, rs1, simm12</code></dt>

  236. <dt><code>I type: .insn i opcode, func3, rd, simm12(rs1)</code></dt>

  237. <dd><pre class="verbatim">+-------------+-----+-------+----+-------------+

  238. |      simm12 | rs1 | func3 | rd |      opcode |

  239. +-------------+-----+-------+----+-------------+

  240. 31            20    15      12   7             0

  241. </pre>

  242. </dd>

  243. <dt><code>S type: .insn s opcode, func3, rs2, simm12(rs1)</code></dt>

  244. <dd><pre class="verbatim">+--------------+-----+-----+-------+-------------+-------------+

  245. | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] |      opcode |

  246. +--------------+-----+-----+-------+-------------+-------------+

  247. 31             25    20    15      12            7             0

  248. </pre>

  249. </dd>

  250. <dt><code>B type: .insn s opcode, func3, rs1, rs2, symbol</code></dt>

  251. <dt><code>SB type: .insn sb opcode, func3, rs1, rs2, symbol</code></dt>

  252. <dd><pre class="verbatim">+------------+--------------+-----+-----+-------+-------------+-------------+--------+

  253. | simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |

  254. +------------+--------------+-----+-----+-------+-------------+-------------+--------+

  255. 31          30            25    20    15      12           7            0

  256. </pre>

  257. </dd>

  258. <dt><code>U type: .insn u opcode, rd, simm20</code></dt>

  259. <dd><pre class="verbatim">+---------------------------+----+-------------+

  260. |                    simm20 | rd |      opcode |

  261. +---------------------------+----+-------------+

  262. 31                          12   7             0

  263. </pre>

  264. </dd>

  265. <dt><code>J type: .insn j opcode, rd, symbol</code></dt>

  266. <dt><code>UJ type: .insn uj opcode, rd, symbol</code></dt>

  267. <dd><pre class="verbatim">+------------+--------------+------------+---------------+----+-------------+

  268. | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd |      opcode |

  269. +------------+--------------+------------+---------------+----+-------------+

  270. 31           30             21           20              12   7             0

  271. </pre>

  272. </dd>

  273. <dt><code>CR type: .insn cr opcode2, func4, rd, rs2</code></dt>

  274. <dd><pre class="verbatim">+---------+--------+-----+---------+

  275. |   func4 | rd/rs1 | rs2 | opcode2 |

  276. +---------+--------+-----+---------+

  277. 15        12       7     2        0

  278. </pre>

  279. </dd>

  280. <dt><code>CI type: .insn ci opcode2, func3, rd, simm6</code></dt>

  281. <dd><pre class="verbatim">+---------+-----+--------+-----+---------+

  282. |   func3 | imm | rd/rs1 | imm | opcode2 |

  283. +---------+-----+--------+-----+---------+

  284. 15        13    12       7     2         0

  285. </pre>

  286. </dd>

  287. <dt><code>CIW type: .insn ciw opcode2, func3, rd, uimm8</code></dt>

  288. <dd><pre class="verbatim">+---------+--------------+-----+---------+

  289. |   func3 |          imm | rd' | opcode2 |

  290. +---------+--------------+-----+---------+

  291. 15        13             7     2         0

  292. </pre>

  293. </dd>

  294. <dt><code>CA type: .insn ca opcode2, func6, func2, rd, rs2</code></dt>

  295. <dd><pre class="verbatim">+---------+----------+-------+------+--------+

  296. |   func6 | rd'/rs1' | func2 | rs2' | opcode |

  297. +---------+----------+-------+------+--------+

  298. 15        10         7       5      2        0

  299. </pre>

  300. </dd>

  301. <dt><code>CB type: .insn cb opcode2, func3, rs1, symbol</code></dt>

  302. <dd><pre class="verbatim">+---------+--------+------+--------+---------+

  303. |   func3 | offset | rs1' | offset | opcode2 |

  304. +---------+--------+------+--------+---------+

  305. 15        13       10     7        2         0

  306. </pre>

  307. </dd>

  308. <dt><code>CJ type: .insn cj opcode2, symbol</code></dt>

  309. <dd><pre class="verbatim">+---------+--------------------+---------+

  310. |   func3 |        jump target | opcode2 |

  311. +---------+--------------------+---------+

  312. 15        13             7     2         0

  313. </pre>

  314. 

  315. </dd>

  316. </dl>

  317. 

  318. <p>For the complete list of all instruction format variants see

  319. The RISC-V Instruction Set Manual Volume I: User-Level ISA.

  320. </p>

  321. <hr>

  322. <div class="header">

  323. <p>

  324. Next: <a href="RISC_002dV_002dATTRIBUTE.html#RISC_002dV_002dATTRIBUTE" accesskey="n" rel="next">RISC-V-ATTRIBUTE</a>, Previous: <a href="RISC_002dV_002dModifiers.html#RISC_002dV_002dModifiers" accesskey="p" rel="prev">RISC-V-Modifiers</a>, Up: <a href="RISC_002dV_002dDependent.html#RISC_002dV_002dDependent" accesskey="u" rel="up">RISC-V-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  325. </div>

  326. 

  327. 

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