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  15. <title>S12Z Addressing Modes (Using as)</title>
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  56. <a name="S12Z-Addressing-Modes"></a>
  57. <div class="header">
  58. <p>
  59. Next: <a href="S12Z-Register-Notation.html#S12Z-Register-Notation" accesskey="n" rel="next">S12Z Register Notation</a>, Previous: <a href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview" accesskey="p" rel="prev">S12Z Syntax Overview</a>, Up: <a href="S12Z-Syntax.html#S12Z-Syntax" accesskey="u" rel="up">S12Z Syntax</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
  60. </div>
  61. <hr>
  62. <a name="Addressing-Modes-3"></a>
  63. <h4 class="subsubsection">9.24.2.2 Addressing Modes</h4>
  64. <a name="index-S12Z-addressing-modes"></a>
  65. <a name="index-addressing-modes_002c-S12Z"></a>
  66. <p>The following addressing modes are understood for the S12Z.
  67. </p><dl compact="compact">
  68. <dt><em>Immediate</em></dt>
  69. <dd><p>&lsquo;<samp>#<var>number</var></samp>&rsquo;
  70. </p>
  71. </dd>
  72. <dt><em>Immediate Bit Field</em></dt>
  73. <dd><p>&lsquo;<samp>#<var>width</var>:<var>offset</var></samp>&rsquo;
  74. </p>
  75. <p>Bit field instructions in the immediate mode require the width and offset to
  76. be specified.
  77. The <var>width</var> parameter specifies the number of bits in the field.
  78. It should be a number in the range [1,32].
  79. <var>Offset</var> determines the position within the field where the operation
  80. should start.
  81. It should be a number in the range [0,31].
  82. </p>
  83. </dd>
  84. <dt><em>Relative</em></dt>
  85. <dd><p>&lsquo;<samp>*<var>symbol</var></samp>&rsquo;, or &lsquo;<samp>*[+-]<var>digits</var></samp>&rsquo;
  86. </p>
  87. <p>Program counter relative addresses have a width of 15 bits.
  88. Thus, they must be within the range [-32768, 32767].
  89. </p>
  90. </dd>
  91. <dt><em>Register</em></dt>
  92. <dd><p>&lsquo;<samp><var>reg</var></samp>&rsquo;
  93. </p>
  94. <a name="index-register-names_002c-S12Z"></a>
  95. <p>Some instructions accept a register as an operand.
  96. In general, <var>reg</var> may be a
  97. data register (&lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip; &lsquo;<samp>D7</samp>&rsquo;),
  98. the &lsquo;<samp>X</samp>&rsquo; register or the &lsquo;<samp>Y</samp>&rsquo; register.
  99. </p>
  100. <p>A few instructions accept as an argument the stack pointer
  101. register (&lsquo;<samp>S</samp>&rsquo;), and/or the program counter (&lsquo;<samp>P</samp>&rsquo;).
  102. </p>
  103. <p>Some very special instructions accept arguments which refer to the
  104. condition code register. For these arguments the syntax is
  105. &lsquo;<samp>CCR</samp>&rsquo;, &lsquo;<samp>CCH</samp>&rsquo; or &lsquo;<samp>CCL</samp>&rsquo; which refer to the complete
  106. condition code register, the condition code register high byte
  107. and the condition code register low byte respectively.
  108. </p>
  109. </dd>
  110. <dt><em>Absolute Direct</em></dt>
  111. <dd><p>&lsquo;<samp><var>symbol</var></samp>&rsquo;, or &lsquo;<samp><var>digits</var></samp>&rsquo;
  112. </p>
  113. </dd>
  114. <dt><em>Absolute Indirect</em></dt>
  115. <dd><p>&lsquo;<samp>[<var>symbol</var></samp>&rsquo;, or &lsquo;<samp><var>digits</var>]</samp>&rsquo;
  116. </p>
  117. </dd>
  118. <dt><em>Constant Offset Indexed</em></dt>
  119. <dd><p>&lsquo;<samp>(<var>number</var>,<var>reg</var>)</samp>&rsquo;
  120. </p>
  121. <p><var>Reg</var> may be either &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, &lsquo;<samp>S</samp>&rsquo; or
  122. &lsquo;<samp>P</samp>&rsquo; or one of the data registers &lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip;
  123. &lsquo;<samp>D7</samp>&rsquo;.
  124. If any of the registers &lsquo;<samp>D2</samp>&rsquo; &hellip; &lsquo;<samp>D5</samp>&rsquo; are specified, then the
  125. register value is treated as a signed value.
  126. Otherwise it is treated as unsigned.
  127. <var>Number</var> may be any integer in the range [-8388608,8388607].
  128. </p>
  129. </dd>
  130. <dt><em>Offset Indexed Indirect</em></dt>
  131. <dd><p>&lsquo;<samp>[<var>number</var>,<var>reg</var>]</samp>&rsquo;
  132. </p>
  133. <p><var>Reg</var> may be either &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, &lsquo;<samp>S</samp>&rsquo; or
  134. &lsquo;<samp>P</samp>&rsquo;.
  135. <var>Number</var> may be any integer in the range [-8388608,8388607].
  136. </p>
  137. </dd>
  138. <dt><em>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</em></dt>
  139. <dd><p>&lsquo;<samp>-<var>reg</var></samp>&rsquo;,
  140. &lsquo;<samp>+<var>reg</var></samp>&rsquo;,
  141. &lsquo;<samp><var>reg</var>-</samp>&rsquo; or
  142. &lsquo;<samp><var>reg</var>+</samp>&rsquo;
  143. </p>
  144. <p>This addressing mode is typically used to access a value at an address,
  145. and simultaneously to increment/decrement the register pointing to that
  146. address.
  147. Thus <var>reg</var> may be any of the 24 bit registers &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, or
  148. &lsquo;<samp>S</samp>&rsquo;.
  149. Pre-increment and post-decrement are not available for
  150. register &lsquo;<samp>S</samp>&rsquo; (only post-increment and pre-decrement are available).
  151. </p>
  152. </dd>
  153. <dt><em>Register Offset Direct</em></dt>
  154. <dd><p>&lsquo;<samp>(<var>data-reg</var>,<var>reg</var>)</samp>&rsquo;
  155. </p>
  156. <p><var>Reg</var> can be either &lsquo;<samp>X</samp>&rsquo;, &lsquo;<samp>Y</samp>&rsquo;, or &lsquo;<samp>S</samp>&rsquo;.
  157. <var>Data-reg</var>
  158. must be one of the data registers &lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip; &lsquo;<samp>D7</samp>&rsquo;.
  159. If any of the registers &lsquo;<samp>D2</samp>&rsquo; &hellip; &lsquo;<samp>D5</samp>&rsquo; are specified, then
  160. the register value is treated as a signed value.
  161. Otherwise it is treated as unsigned.
  162. </p>
  163. </dd>
  164. <dt><em>Register Offset Indirect</em></dt>
  165. <dd><p>&lsquo;<samp>[<var>data-reg</var>,<var>reg</var>]</samp>&rsquo;
  166. </p>
  167. <p><var>Reg</var> can be either &lsquo;<samp>X</samp>&rsquo; or &lsquo;<samp>Y</samp>&rsquo;.
  168. <var>Data-reg</var>
  169. must be one of the data registers &lsquo;<samp>D0</samp>&rsquo;, &lsquo;<samp>D1</samp>&rsquo; &hellip; &lsquo;<samp>D7</samp>&rsquo;.
  170. If any of the registers &lsquo;<samp>D2</samp>&rsquo; &hellip; &lsquo;<samp>D5</samp>&rsquo; are specified, then
  171. the register value is treated as a signed value.
  172. Otherwise it is treated as unsigned.
  173. </p></dd>
  174. </dl>
  175. <p>For example:
  176. </p>
  177. <div class="smallexample">
  178. <pre class="smallexample"> trap #197 ;; Immediate mode
  179. bra *+49 ;; Relative mode
  180. bra .L0 ;; ditto
  181. jmp 0xFE0034 ;; Absolute direct mode
  182. jmp [0xFD0012] ;; Absolute indirect mode
  183. inc.b (4,x) ;; Constant offset indexed mode
  184. jsr (45, d0) ;; ditto
  185. dec.w [4,y] ;; Constant offset indexed indirect mode
  186. clr.p (-s) ;; Pre-decrement mode
  187. neg.l (d0, s) ;; Register offset direct mode
  188. com.b [d1, x] ;; Register offset indirect mode
  189. psh cch ;; Register mode
  190. </pre></div>
  191. <hr>
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