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  62. <a name="Sparc_002dConstants"></a>

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  66. </div>

  67. <hr>

  68. <a name="Constants-2"></a>

  69. <h4 class="subsubsection">9.44.3.3 Constants</h4>

  70. <a name="index-Sparc-constants"></a>

  71. <a name="index-constants_002c-Sparc"></a>

  72. 

  73. <p>Several Sparc instructions take an immediate operand field for

  74. which mnemonic names exist.  Two such examples are &lsquo;<samp>membar</samp>&rsquo;

  75. and &lsquo;<samp>prefetch</samp>&rsquo;.  Another example are the set of V9

  76. memory access instruction that allow specification of an

  77. address space identifier.

  78. </p>

  79. <p>The &lsquo;<samp>membar</samp>&rsquo; instruction specifies a memory barrier that is

  80. the defined by the operand which is a bitmask.  The supported

  81. mask mnemonics are:

  82. </p>

  83. <ul>

  84. <li> &lsquo;<samp>#Sync</samp>&rsquo; requests that all operations (including nonmemory

  85. reference operations) appearing prior to the <code>membar</code> must have

  86. been performed and the effects of any exceptions become visible before

  87. any instructions after the <code>membar</code> may be initiated.  This

  88. corresponds to <code>membar</code> cmask field bit 2.

  89. 

  90. </li><li> &lsquo;<samp>#MemIssue</samp>&rsquo; requests that all memory reference operations

  91. appearing prior to the <code>membar</code> must have been performed before

  92. any memory operation after the <code>membar</code> may be initiated.  This

  93. corresponds to <code>membar</code> cmask field bit 1.

  94. 

  95. </li><li> &lsquo;<samp>#Lookaside</samp>&rsquo; requests that a store appearing prior to the

  96. <code>membar</code> must complete before any load following the

  97. <code>membar</code> referencing the same address can be initiated.  This

  98. corresponds to <code>membar</code> cmask field bit 0.

  99. 

  100. </li><li> &lsquo;<samp>#StoreStore</samp>&rsquo; defines that the effects of all stores appearing

  101. prior to the <code>membar</code> instruction must be visible to all

  102. processors before the effect of any stores following the

  103. <code>membar</code>.  Equivalent to the deprecated <code>stbar</code> instruction.

  104. This corresponds to <code>membar</code> mmask field bit 3.

  105. 

  106. </li><li> &lsquo;<samp>#LoadStore</samp>&rsquo; defines all loads appearing prior to the

  107. <code>membar</code> instruction must have been performed before the effect

  108. of any stores following the <code>membar</code> is visible to any other

  109. processor.  This corresponds to <code>membar</code> mmask field bit 2.

  110. 

  111. </li><li> &lsquo;<samp>#StoreLoad</samp>&rsquo; defines that the effects of all stores appearing

  112. prior to the <code>membar</code> instruction must be visible to all

  113. processors before loads following the <code>membar</code> may be performed.

  114. This corresponds to <code>membar</code> mmask field bit 1.

  115. 

  116. </li><li> &lsquo;<samp>#LoadLoad</samp>&rsquo; defines that all loads appearing prior to the

  117. <code>membar</code> instruction must have been performed before any loads

  118. following the <code>membar</code> may be performed.  This corresponds to

  119. <code>membar</code> mmask field bit 0.

  120. 

  121. </li></ul>

  122. 

  123. <p>These values can be ored together, for example:

  124. </p>

  125. <div class="example">

  126. <pre class="example">membar #Sync

  127. membar #StoreLoad | #LoadLoad

  128. membar #StoreLoad | #StoreStore

  129. </pre></div>

  130. 

  131. <p>The <code>prefetch</code> and <code>prefetcha</code> instructions take a prefetch

  132. function code.  The following prefetch function code constant

  133. mnemonics are available:

  134. </p>

  135. <ul>

  136. <li> &lsquo;<samp>#n_reads</samp>&rsquo; requests a prefetch for several reads, and corresponds

  137. to a prefetch function code of 0.

  138. 

  139. <p>&lsquo;<samp>#one_read</samp>&rsquo; requests a prefetch for one read, and corresponds

  140. to a prefetch function code of 1.

  141. </p>

  142. <p>&lsquo;<samp>#n_writes</samp>&rsquo; requests a prefetch for several writes (and possibly

  143. reads), and corresponds to a prefetch function code of 2.

  144. </p>

  145. <p>&lsquo;<samp>#one_write</samp>&rsquo; requests a prefetch for one write, and corresponds

  146. to a prefetch function code of 3.

  147. </p>

  148. <p>&lsquo;<samp>#page</samp>&rsquo; requests a prefetch page, and corresponds to a prefetch

  149. function code of 4.

  150. </p>

  151. <p>&lsquo;<samp>#invalidate</samp>&rsquo; requests a prefetch invalidate, and corresponds to

  152. a prefetch function code of 16.

  153. </p>

  154. <p>&lsquo;<samp>#unified</samp>&rsquo; requests a prefetch to the nearest unified cache, and

  155. corresponds to a prefetch function code of 17.

  156. </p>

  157. <p>&lsquo;<samp>#n_reads_strong</samp>&rsquo; requests a strong prefetch for several reads,

  158. and corresponds to a prefetch function code of 20.

  159. </p>

  160. <p>&lsquo;<samp>#one_read_strong</samp>&rsquo; requests a strong prefetch for one read,

  161. and corresponds to a prefetch function code of 21.

  162. </p>

  163. <p>&lsquo;<samp>#n_writes_strong</samp>&rsquo; requests a strong prefetch for several writes,

  164. and corresponds to a prefetch function code of 22.

  165. </p>

  166. <p>&lsquo;<samp>#one_write_strong</samp>&rsquo; requests a strong prefetch for one write,

  167. and corresponds to a prefetch function code of 23.

  168. </p>

  169. <p>Onle one prefetch code may be specified.  Here are some examples:

  170. </p>

  171. <div class="example">

  172. <pre class="example">prefetch  [%l0 + %l2], #one_read

  173. prefetch  [%g2 + 8], #n_writes

  174. prefetcha [%g1] 0x8, #unified

  175. prefetcha [%o0 + 0x10] %asi, #n_reads

  176. </pre></div>

  177. 

  178. <p>The actual behavior of a given prefetch function code is processor

  179. specific.  If a processor does not implement a given prefetch

  180. function code, it will treat the prefetch instruction as a nop.

  181. </p>

  182. <p>For instructions that accept an immediate address space identifier,

  183. <code>as</code> provides many mnemonics corresponding to

  184. V9 defined as well as UltraSPARC and Niagara extended values.

  185. For example, &lsquo;<samp>#ASI_P</samp>&rsquo; and &lsquo;<samp>#ASI_BLK_INIT_QUAD_LDD_AIUS</samp>&rsquo;.

  186. See the V9 and processor specific manuals for details.

  187. </p>

  188. </li></ul>

  189. 

  190. <hr>

  191. <div class="header">

  192. <p>

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  194. </div>

  195. 

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