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  62. <a name="Memory-References"></a>
  63. <h4 class="subsection">9.16.7 Memory References</h4>
  64. <a name="index-i386-memory-references"></a>
  65. <a name="index-memory-references_002c-i386"></a>
  66. <a name="index-x86_002d64-memory-references"></a>
  67. <a name="index-memory-references_002c-x86_002d64"></a>
  68. <p>An Intel syntax indirect memory reference of the form
  69. </p>
  70. <div class="smallexample">
  71. <pre class="smallexample"><var>section</var>:[<var>base</var> + <var>index</var>*<var>scale</var> + <var>disp</var>]
  72. </pre></div>
  73. <p>is translated into the AT&amp;T syntax
  74. </p>
  75. <div class="smallexample">
  76. <pre class="smallexample"><var>section</var>:<var>disp</var>(<var>base</var>, <var>index</var>, <var>scale</var>)
  77. </pre></div>
  78. <p>where <var>base</var> and <var>index</var> are the optional 32-bit base and
  79. index registers, <var>disp</var> is the optional displacement, and
  80. <var>scale</var>, taking the values 1, 2, 4, and 8, multiplies <var>index</var>
  81. to calculate the address of the operand. If no <var>scale</var> is
  82. specified, <var>scale</var> is taken to be 1. <var>section</var> specifies the
  83. optional section register for the memory operand, and may override the
  84. default section register (see a 80386 manual for section register
  85. defaults). Note that section overrides in AT&amp;T syntax <em>must</em>
  86. be preceded by a &lsquo;<samp>%</samp>&rsquo;. If you specify a section override which
  87. coincides with the default section register, <code>as</code> does <em>not</em>
  88. output any section register override prefixes to assemble the given
  89. instruction. Thus, section overrides can be specified to emphasize which
  90. section register is used for a given memory operand.
  91. </p>
  92. <p>Here are some examples of Intel and AT&amp;T style memory references:
  93. </p>
  94. <dl compact="compact">
  95. <dt>AT&amp;T: &lsquo;<samp>-4(%ebp)</samp>&rsquo;, Intel: &lsquo;<samp>[ebp - 4]</samp>&rsquo;</dt>
  96. <dd><p><var>base</var> is &lsquo;<samp>%ebp</samp>&rsquo;; <var>disp</var> is &lsquo;<samp>-4</samp>&rsquo;. <var>section</var> is
  97. missing, and the default section is used (&lsquo;<samp>%ss</samp>&rsquo; for addressing with
  98. &lsquo;<samp>%ebp</samp>&rsquo; as the base register). <var>index</var>, <var>scale</var> are both missing.
  99. </p>
  100. </dd>
  101. <dt>AT&amp;T: &lsquo;<samp>foo(,%eax,4)</samp>&rsquo;, Intel: &lsquo;<samp>[foo + eax*4]</samp>&rsquo;</dt>
  102. <dd><p><var>index</var> is &lsquo;<samp>%eax</samp>&rsquo; (scaled by a <var>scale</var> 4); <var>disp</var> is
  103. &lsquo;<samp>foo</samp>&rsquo;. All other fields are missing. The section register here
  104. defaults to &lsquo;<samp>%ds</samp>&rsquo;.
  105. </p>
  106. </dd>
  107. <dt>AT&amp;T: &lsquo;<samp>foo(,1)</samp>&rsquo;; Intel &lsquo;<samp>[foo]</samp>&rsquo;</dt>
  108. <dd><p>This uses the value pointed to by &lsquo;<samp>foo</samp>&rsquo; as a memory operand.
  109. Note that <var>base</var> and <var>index</var> are both missing, but there is only
  110. <em>one</em> &lsquo;<samp>,</samp>&rsquo;. This is a syntactic exception.
  111. </p>
  112. </dd>
  113. <dt>AT&amp;T: &lsquo;<samp>%gs:foo</samp>&rsquo;; Intel &lsquo;<samp>gs:foo</samp>&rsquo;</dt>
  114. <dd><p>This selects the contents of the variable &lsquo;<samp>foo</samp>&rsquo; with section
  115. register <var>section</var> being &lsquo;<samp>%gs</samp>&rsquo;.
  116. </p></dd>
  117. </dl>
  118. <p>Absolute (as opposed to PC relative) call and jump operands must be
  119. prefixed with &lsquo;<samp>*</samp>&rsquo;. If no &lsquo;<samp>*</samp>&rsquo; is specified, <code>as</code>
  120. always chooses PC relative addressing for jump/call labels.
  121. </p>
  122. <p>Any instruction that has a memory operand, but no register operand,
  123. <em>must</em> specify its size (byte, word, long, or quadruple) with an
  124. instruction mnemonic suffix (&lsquo;<samp>b</samp>&rsquo;, &lsquo;<samp>w</samp>&rsquo;, &lsquo;<samp>l</samp>&rsquo; or &lsquo;<samp>q</samp>&rsquo;,
  125. respectively).
  126. </p>
  127. <p>The x86-64 architecture adds an RIP (instruction pointer relative)
  128. addressing. This addressing mode is specified by using &lsquo;<samp>rip</samp>&rsquo; as a
  129. base register. Only constant offsets are valid. For example:
  130. </p>
  131. <dl compact="compact">
  132. <dt>AT&amp;T: &lsquo;<samp>1234(%rip)</samp>&rsquo;, Intel: &lsquo;<samp>[rip + 1234]</samp>&rsquo;</dt>
  133. <dd><p>Points to the address 1234 bytes past the end of the current
  134. instruction.
  135. </p>
  136. </dd>
  137. <dt>AT&amp;T: &lsquo;<samp>symbol(%rip)</samp>&rsquo;, Intel: &lsquo;<samp>[rip + symbol]</samp>&rsquo;</dt>
  138. <dd><p>Points to the <code>symbol</code> in RIP relative way, this is shorter than
  139. the default absolute addressing.
  140. </p></dd>
  141. </dl>
  142. <p>Other addressing modes remain unchanged in x86-64 architecture, except
  143. registers used are 64-bit instead of 32-bit.
  144. </p>
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