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  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">

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  17. <title>i386-Regs (Using as)</title>

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  61. <body lang="en">

  62. <a name="i386_002dRegs"></a>

  63. <div class="header">

  64. <p>

  65. Next: <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="n" rel="next">i386-Prefixes</a>, Previous: <a href="i386_002dMnemonics.html#i386_002dMnemonics" accesskey="p" rel="prev">i386-Mnemonics</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  66. </div>

  67. <hr>

  68. <a name="Register-Naming"></a>

  69. <h4 class="subsection">9.16.5 Register Naming</h4>

  70. 

  71. <a name="index-i386-registers"></a>

  72. <a name="index-registers_002c-i386"></a>

  73. <a name="index-x86_002d64-registers"></a>

  74. <a name="index-registers_002c-x86_002d64"></a>

  75. <p>Register operands are always prefixed with &lsquo;<samp>%</samp>&rsquo;.  The 80386 registers

  76. consist of

  77. </p>

  78. <ul>

  79. <li> the 8 32-bit registers &lsquo;<samp>%eax</samp>&rsquo; (the accumulator), &lsquo;<samp>%ebx</samp>&rsquo;,

  80. &lsquo;<samp>%ecx</samp>&rsquo;, &lsquo;<samp>%edx</samp>&rsquo;, &lsquo;<samp>%edi</samp>&rsquo;, &lsquo;<samp>%esi</samp>&rsquo;, &lsquo;<samp>%ebp</samp>&rsquo; (the

  81. frame pointer), and &lsquo;<samp>%esp</samp>&rsquo; (the stack pointer).

  82. 

  83. </li><li> the 8 16-bit low-ends of these: &lsquo;<samp>%ax</samp>&rsquo;, &lsquo;<samp>%bx</samp>&rsquo;, &lsquo;<samp>%cx</samp>&rsquo;,

  84. &lsquo;<samp>%dx</samp>&rsquo;, &lsquo;<samp>%di</samp>&rsquo;, &lsquo;<samp>%si</samp>&rsquo;, &lsquo;<samp>%bp</samp>&rsquo;, and &lsquo;<samp>%sp</samp>&rsquo;.

  85. 

  86. </li><li> the 8 8-bit registers: &lsquo;<samp>%ah</samp>&rsquo;, &lsquo;<samp>%al</samp>&rsquo;, &lsquo;<samp>%bh</samp>&rsquo;,

  87. &lsquo;<samp>%bl</samp>&rsquo;, &lsquo;<samp>%ch</samp>&rsquo;, &lsquo;<samp>%cl</samp>&rsquo;, &lsquo;<samp>%dh</samp>&rsquo;, and &lsquo;<samp>%dl</samp>&rsquo; (These

  88. are the high-bytes and low-bytes of &lsquo;<samp>%ax</samp>&rsquo;, &lsquo;<samp>%bx</samp>&rsquo;,

  89. &lsquo;<samp>%cx</samp>&rsquo;, and &lsquo;<samp>%dx</samp>&rsquo;)

  90. 

  91. </li><li> the 6 section registers &lsquo;<samp>%cs</samp>&rsquo; (code section), &lsquo;<samp>%ds</samp>&rsquo;

  92. (data section), &lsquo;<samp>%ss</samp>&rsquo; (stack section), &lsquo;<samp>%es</samp>&rsquo;, &lsquo;<samp>%fs</samp>&rsquo;,

  93. and &lsquo;<samp>%gs</samp>&rsquo;.

  94. 

  95. </li><li> the 5 processor control registers &lsquo;<samp>%cr0</samp>&rsquo;, &lsquo;<samp>%cr2</samp>&rsquo;,

  96. &lsquo;<samp>%cr3</samp>&rsquo;, &lsquo;<samp>%cr4</samp>&rsquo;, and &lsquo;<samp>%cr8</samp>&rsquo;.

  97. 

  98. </li><li> the 6 debug registers &lsquo;<samp>%db0</samp>&rsquo;, &lsquo;<samp>%db1</samp>&rsquo;, &lsquo;<samp>%db2</samp>&rsquo;,

  99. &lsquo;<samp>%db3</samp>&rsquo;, &lsquo;<samp>%db6</samp>&rsquo;, and &lsquo;<samp>%db7</samp>&rsquo;.

  100. 

  101. </li><li> the 2 test registers &lsquo;<samp>%tr6</samp>&rsquo; and &lsquo;<samp>%tr7</samp>&rsquo;.

  102. 

  103. </li><li> the 8 floating point register stack &lsquo;<samp>%st</samp>&rsquo; or equivalently

  104. &lsquo;<samp>%st(0)</samp>&rsquo;, &lsquo;<samp>%st(1)</samp>&rsquo;, &lsquo;<samp>%st(2)</samp>&rsquo;, &lsquo;<samp>%st(3)</samp>&rsquo;,

  105. &lsquo;<samp>%st(4)</samp>&rsquo;, &lsquo;<samp>%st(5)</samp>&rsquo;, &lsquo;<samp>%st(6)</samp>&rsquo;, and &lsquo;<samp>%st(7)</samp>&rsquo;.

  106. These registers are overloaded by 8 MMX registers &lsquo;<samp>%mm0</samp>&rsquo;,

  107. &lsquo;<samp>%mm1</samp>&rsquo;, &lsquo;<samp>%mm2</samp>&rsquo;, &lsquo;<samp>%mm3</samp>&rsquo;, &lsquo;<samp>%mm4</samp>&rsquo;, &lsquo;<samp>%mm5</samp>&rsquo;,

  108. &lsquo;<samp>%mm6</samp>&rsquo; and &lsquo;<samp>%mm7</samp>&rsquo;.

  109. 

  110. </li><li> the 8 128-bit SSE registers registers &lsquo;<samp>%xmm0</samp>&rsquo;, &lsquo;<samp>%xmm1</samp>&rsquo;, &lsquo;<samp>%xmm2</samp>&rsquo;,

  111. &lsquo;<samp>%xmm3</samp>&rsquo;, &lsquo;<samp>%xmm4</samp>&rsquo;, &lsquo;<samp>%xmm5</samp>&rsquo;, &lsquo;<samp>%xmm6</samp>&rsquo; and &lsquo;<samp>%xmm7</samp>&rsquo;.

  112. </li></ul>

  113. 

  114. <p>The AMD x86-64 architecture extends the register set by:

  115. </p>

  116. <ul>

  117. <li> enhancing the 8 32-bit registers to 64-bit: &lsquo;<samp>%rax</samp>&rsquo; (the

  118. accumulator), &lsquo;<samp>%rbx</samp>&rsquo;, &lsquo;<samp>%rcx</samp>&rsquo;, &lsquo;<samp>%rdx</samp>&rsquo;, &lsquo;<samp>%rdi</samp>&rsquo;,

  119. &lsquo;<samp>%rsi</samp>&rsquo;, &lsquo;<samp>%rbp</samp>&rsquo; (the frame pointer), &lsquo;<samp>%rsp</samp>&rsquo; (the stack

  120. pointer)

  121. 

  122. </li><li> the 8 extended registers &lsquo;<samp>%r8</samp>&rsquo;&ndash;&lsquo;<samp>%r15</samp>&rsquo;.

  123. 

  124. </li><li> the 8 32-bit low ends of the extended registers: &lsquo;<samp>%r8d</samp>&rsquo;&ndash;&lsquo;<samp>%r15d</samp>&rsquo;.

  125. 

  126. </li><li> the 8 16-bit low ends of the extended registers: &lsquo;<samp>%r8w</samp>&rsquo;&ndash;&lsquo;<samp>%r15w</samp>&rsquo;.

  127. 

  128. </li><li> the 8 8-bit low ends of the extended registers: &lsquo;<samp>%r8b</samp>&rsquo;&ndash;&lsquo;<samp>%r15b</samp>&rsquo;.

  129. 

  130. </li><li> the 4 8-bit registers: &lsquo;<samp>%sil</samp>&rsquo;, &lsquo;<samp>%dil</samp>&rsquo;, &lsquo;<samp>%bpl</samp>&rsquo;, &lsquo;<samp>%spl</samp>&rsquo;.

  131. 

  132. </li><li> the 8 debug registers: &lsquo;<samp>%db8</samp>&rsquo;&ndash;&lsquo;<samp>%db15</samp>&rsquo;.

  133. 

  134. </li><li> the 8 128-bit SSE registers: &lsquo;<samp>%xmm8</samp>&rsquo;&ndash;&lsquo;<samp>%xmm15</samp>&rsquo;.

  135. </li></ul>

  136. 

  137. <p>With the AVX extensions more registers were made available:

  138. </p>

  139. <ul>

  140. <li> the 16 256-bit SSE &lsquo;<samp>%ymm0</samp>&rsquo;&ndash;&lsquo;<samp>%ymm15</samp>&rsquo; (only the first 8

  141. available in 32-bit mode).  The bottom 128 bits are overlaid with the

  142. &lsquo;<samp>xmm0</samp>&rsquo;&ndash;&lsquo;<samp>xmm15</samp>&rsquo; registers.

  143. 

  144. </li></ul>

  145. 

  146. <p>The AVX512 extensions added the following registers:

  147. </p>

  148. <ul>

  149. <li> the 32 512-bit registers &lsquo;<samp>%zmm0</samp>&rsquo;&ndash;&lsquo;<samp>%zmm31</samp>&rsquo; (only the first 8

  150. available in 32-bit mode).  The bottom 128 bits are overlaid with the

  151. &lsquo;<samp>%xmm0</samp>&rsquo;&ndash;&lsquo;<samp>%xmm31</samp>&rsquo; registers and the first 256 bits are

  152. overlaid with the &lsquo;<samp>%ymm0</samp>&rsquo;&ndash;&lsquo;<samp>%ymm31</samp>&rsquo; registers.

  153. 

  154. </li><li> the 8 mask registers &lsquo;<samp>%k0</samp>&rsquo;&ndash;&lsquo;<samp>%k7</samp>&rsquo;.

  155. 

  156. </li></ul>

  157. 

  158. <hr>

  159. <div class="header">

  160. <p>

  161. Next: <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="n" rel="next">i386-Prefixes</a>, Previous: <a href="i386_002dMnemonics.html#i386_002dMnemonics" accesskey="p" rel="prev">i386-Mnemonics</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>

  162. </div>

  163. 

  164. 

  165. 

  166. </body>

  167. </html>